Innovative Memory workshop, June 29, 2011, Grenoble, France

Recent Progress inResistive Switching Memories

Yoshio NishiStanford UniversityStanford, California

U.S.A.

Motivations for New Nonvolatile Memories

• Scalability beyond 15nm nodes of existing memory in question both volatile memory and nonvolatile memory

• Increasing needs for less power consumption on chip

• Increasing demands for embedded memory size for memory access band width

• “Nano” materials evolution/revolutions have stimulated exploration of new memory opportunities

• Logic coupled with memory

Memory area will increase

Per

cen

tag

e o

f ar

ea in

So

C [

%]

2001 2004 2007 2010 2013 20160

20

40

60

80

100

Year

Memory

Logic

Due to design productivity, yield, and power

ITRS’ 2000

Traditional Memory Hierarchy

On CPU Embedded Off Package Memory Storage (HDD) Memory (SRAM cache) (DRAM)

Latency = 1x Latency ~= 100,000x

Normalized CPU Performance Normalized Media Access Time for 20K Read

20

180

160 Multicore CPU

140 CPU

120 Disk

100

80

60

More cores per chip will slow some 40 programs [red] unless there’s a big 20 boost in memory bandwidth [yellow]. 0

Source: Intel measurements

3 Source: “Multicore Is Bad News For Supercomputers”, IEEE Spectrum November 2008

3D Cross-point Memory

• Goal: Design a stackable cross-point memory array

(without switches or diodes).

• Must ensure that peripheral circuitry can fit to

accommodate a single bit line pitch

Memory elements

Word lines

Bit lines

Bit lines

With N-layer stack, can achieve effective cell size of 4F2/N

2011 ISSCCA 4Mb Embedded SLC Resistive-RAM Macro with

7.2ns Read-Write Random-Access Time and 160ns MLC-Access Capability

ITRI

2011 ISSCCA 4Mb Conductive-Bridge Resistive Memory with

2.3GB/s Read-Throughput and 216MB/s Program-ThroughputSony

May 18 2011

Resistive random-access memory (RRAM) is something various

electronics companies have been working on for years, but now

Panasonic seems to be ready to be the first to start mass-producing

the next-generation memory chips, according to a report in Japan’s

biggest business daily The Nikkei.

The new memory type can retain stored data over time even when it’s

not powered, it’s much faster and more eco-friendly than flash memory

chips, for example (using up to 90% less power). Panasonic says that

the energy consumed by TVs operating in standby, for example, could

be cut by 66% or more when using RRAMs.

The company plans to ship samples of 2Mbit RRAMs for use in TVs

and Blu-ray players by the end of this year, followed by mass

production in 2012.

Materials for Resistive Switching

Binary Metal Oxide TiO2,Al2O3, NiO, CuxO, ZrO2, MnO2, HfO2, WO3, Ta2O5, Nb2O5, VO2, Fe3O4…

Perovskite PCMO(Pr0.7Ca0.3MnO3), LCMO(La1-xCaxMnO3)BSCFO(Ba0.5Sr0.5Co0.8Fe0.2O3-δ), YBCO(YBa2Cu3O7-x)

(Ba,Sr)TiO3(Cr, Nb-doped), SrZrO3(Cr,V-doped), (La, Sr)MnO3Sr1-xLaxTiO3, La1-xSrxFeO3, La1-xSrxCoO3,

SrFeO2.7, LaCoO3, RuSr2GdCu2O3, YBa2Cu3O7…

Metal sulfide GexSe1-x(Ag,Cu,Te-doped), Ag2S, Cu2S, CdS, ZnS, CeO2,,

Others C(sp2-sp3)

What is the conduction mechanism for the “on” state?

• Metallic filament?

• Vacancy chain?

• Local density of states arising from

vacancy distribution or metallic behavior?

• Transport, electronic or ionic?

• Formation energy of conductive path?

• Macroscopic model vs atomic scale

model?

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En

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DO

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arb

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nit

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E - EF (eV)

Spin up Spin down

• Even though we have more vacancies, lowering resistance is not so big as long as vacancies are randomly distributed.

Randomly Distributed Vacancies

[110]

Ti

Ti

0.1e/Å3

On –state

[001]

-8 -6 -4 -2 0 2 4 6-150

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E - EF (eV)

• Filament type conductive channel which is composed of Ti atoms can be formed in either [001] or [110] direction.

S.G. Park et al., EDL, 32, 197 (2011)

Ordering of Vacancies

Ti

0.1e/Å3

Stability of Vacancy Ordering

0.30

0.32

0.34

0.36

0.38

0.40

FR3R2

Evf (

eV/f

orm

ula

un

it.)

Vacancy configurationR 1

R1 : random config.

R2, R3 : random on (110)

F : Filament on (110)

S.G. Park et al., EDL, 32, 197 (2011)

Evf = E(TiO2-x) – E(TiO2) +n/2E(O2)

E(TiO2-x) : The total energy of a supercell containing oxygen vacancies

E(TiO2) : The total energy of a perfect TiO2 in the same size of supercell

E(O2) : The energy of oxygen molecule

n : The number of oxygen vacancy

Ti3+ - Ti3+ pair chain(missing two oxygen chains)

Ti3+

Ordering of bipolaron chains

Rutile (TiO2)

High Vo concentration

Vo ordering

The formation of Bipolaron (Ti3+ - Ti3+)

Magnéli phase (Ti4O7)

Rutile (TiO2) ���� Magnéli (Ti4O7)

Vacancy Ordering in Magnéli Phase

• High Vo concentration in rutile TiO2 results in the transition to Magneliphase by forming bipolaron chains.

• Bipolaron chain composed of successive Ti3+ atoms in one direction���� associated with vacancy ordering in TiO2

• “ON”-state conduction is related to vacancy ordering.

Vo chain

Ti

O

Vo

-8 -6 -4 -2 0 2 4 6-150

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Vo2+ chain

Vo2+

• Even though electrons are removed from vacancies, many defect levels are still in the band gap with strong interactions.

Charged Vacancy (Vo2+)

Vo

Vo2+

Partial charge densityELF

0.1e/Å3

0.1e/Å3

• The ordering of positively charged vacancies can also make a conductive channel as neutral vacancies.

Charged Vacancy (Vo2+)

Ti

O

Vo

0.1e/Å3

Ti

0.1e/Å3

S.G. Park et al., VLSI (2011) (accepted)

Rupture of Conductive Channel

2Vo off[001] chain

Vo

• The conductive channel is disconnected by the diffusion of oxygen into the channel.

Vo chain Vo + H chain

Ti

O

Vo

Vo+H

• Substitutional Hydrogen atoms remove some of defect states which were induced by oxygen vacancies.

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Hydrogen in Conductive Channel

Vo chain Vo + H complex chain

Ti

H+Vo

0.1e/Å3 0.1e/Å3

Ti

Vo

H

Vo

S.G. Park et al., VLSI (2011) (accepted)

Hydrogen in Conductive Channel

• Hydrogen segregated to the vacancy sites - results in the rupture of the conductive channel by localizing electrons in those sites.

Initial (Insulator) On (LRS) Off (HRS)

Electro

forming

Vacancies in random Vo ordered domains Disruption of Vo ordering

Reset

Set

• Vo concentration Increases locally ���� Vo are ordered. (LRS)• Thermal heating by high current density ���� Vo diffuse out (HRS)• The resistance of each state might be determined by the amount of

vacancy ordered domains. (It doesn’t have to be Magneli phase.)

Vo

Switching Modeling

Understandings from ab-initio study of conduction mechanism

• The multi-oxygen vacancy configuration is linked to the formation of a metallic filament

• The chain like vacancy configurations may account for the higher conductivity observed in oxygen deficient TiO2 and NiO

• Filament rapture can take place by oxygen or hydrogen at substitutional sites

• Electron transport and interface effects also contribute to the formation of vacancy configurations –future directions.

Possible Elimination of “Forming”

• Adequately designed “vacancy pool” built

in device structure

• In-situ processing to avoid Schottky junction formation

• Demonstrated possibility for reduced

switching power consumption and multi-

state bit

Feasibility Demonstration for Scalability

• LRS would scale beyond certain geometry

• On/off ratio sustainable

• Variability decrease with geometry scaling,

partly helped by bit/word line resistance

Status Quo for ReRAM

• In-depth understanding of resistive switching mechanism, formation energy for nano-conductive filament: Good progress made

• On-state and off-state conduction mechanisms: Progress for on-state, but still a lot of room for off-state

• Effects of electrode and additional element doping: active electrode vsinert electrode, but less systematic work for doping

• Variability of switching characteristics: better in smaller device area• Programming power vs data retention: subject for filament formation

energy

• Effort toward scalability: geometry driven vs MLC and/or MLS• Demonstration of cross point memory: selection device becoming a

focal point

• Product introduction: Productization has started with small scale integration

Ending CommentFuture of Resistive Switching

Memory?• Replacement of Flash

• Nonvolatile RAM, given that programming speed

and set/reset endurance are enough for applications

• Embedded memory with least area penalty, particularly coupled with 3D stacking

• Controllability and reproducibility with additional doping

• Materials compatibility with Si based CMOS