MDLC21USN j1

M S RAMAIAH INSTITUTE OF TECHNOLOGY(AUTONOMOUS INSTITUTE, AFFILIATED TO VTU)

BANGALORE - 560 054SEMESTER END EXAMINATIONS - JUNE 2010

Course & Branch : M.Tech ( Digital Electronics andCommunication)

Semester II

Subject : Real Time Embedded System Max. Marks : 100

Subject Code : MDLC21 Du ration : 3 Hrs

Instructions to the Candidates:Answer any Five Full questions.

L a) Comparei)ii)iii)

Hard and Soft Real Time SystemsRAM and EPROM featuresHarvard and Princeton Architectures

b) Explain the following terms with an example.i) Single purpose processorii) Deterministic systemiii) Embedded systemiv) Immediate addressing mode

(12)

(08)

2. a) Describe (12)

i) DMA ii) UART

with block diagrams and timing diagrams.b) A processor has an onchip WDT and ADC. A 16 bit register operating (08)

at a clock frequency of 40 MHz is used for the WDT design.Determine its resolution and also the terminal count value forgenerating a delay of 1 msec. If the overflow interrupt is generatedafter the last count FFFFH, what is the delay generated? The ADChas 8 bits for the digital output and operates in the range - 5V to+5V. Determine the digital output when analog input is -3V. What isthe analog input for generating an output of 40H and also itsresolution?

3. a) Explain the differences between hardware and software interrupts (12)with examples. What are the actions taken by the processor when aninterrupt occurs? How the shared data problem can be solved usinginterrupt instructions? Illustrate with an example.

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MDLC21

b) Explain the terms interrupt latency and context switching. There are (08)3 processes with low, medium and high priorities. The execution timeof these processes are 250µsec, 180µsec and 100µsec respectively.The deadline of the low priority process is 700µsec and the minimuminterrupt latency for starting any ISR is 150µsec. Is it possible tocomplete the execution for the low priority process well within thedeadline, if all the three processes interrupt the system together.Context switching time is negligible. What is the worst case latencyfor the low priority process?

4. a) Describei) Function queue scheduling and (12)ii) RTOS architectures, with algorithms.

b) Explain the algorithm for a simple bridge using RR with interrupts (08)architecture.

5. a) Explain (12)i) Polled loop systemii) Interrupt driven systemiii) Foreground - background systems.

b) Explain Kernel hierarchy and different types of kernel with a (08)diagram.

6. a) Explain scheduling and dispatching mechanisms. Describe rate (12)monotonic scheduling and also priority based preemptive schedulingschemes.

b) Describe the function of the various states and the switching (08)operation using a Task control block structure and state transitiondiagram, in a multitasking system.

7. a) Explain the terms :

b)

(12)

i)ii)iii)

SemaphoresMailboxes for interprocess communicationPOSIX features

Mention the fifteen point strategies for synchronization. (08)

Compare (12)

i)ii)

MFT and MVT memory management techniquesVxWorks and µcos RTOS

Describe automatic chocolate vending machine design with a block (08)diagram.

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