Razavi Solution Book Design of Analog CMOS Integrated Circuits
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refer-ust be
rigi-W”hange
n. To
-
_____
CORRECTIONS TO SOLUTIONS MANUAL
In the new edition, some chapter problems have been reordered and equations and figure ences have changed. The solutions manual is based on the preview edition and therefore mcorrected to apply to the new edition. Below is a list reflecting those changes.
The “NEW” column contains the problem numbers in the new edition. If that problem was onally under another number in the preview edition, that number will be listed in the “PREVIEcolumn on the same line. In addition, if a reference used in that problem has changed, that cwill be noted under the problem number in quotes. Chapters and problems not listed areunchanged.
For example:
NEW PREVIEW----- ---------4.18 4.5 “Fig. 4.38” “Fig. 4.35” “Fig. 4.39” “Fig. 4.36”
The above means that problem 4.18 in the new edition was problem 4.5 in the preview editiofind its solution, look up problem 4.5 in the solutions manual. Also, the problem 4.5 solutionreferred to “Fig. 4.35” and “Fig. 4.36” and should now be “Fig. 4.38” and “Fig. 4.39,” respectively.________________________________________________________________________
CHAPTER 3
NEW PREVIEW----- ---------3.1 3.83.2 3.93.3 3.113.4 3.123.5 3.133.6 3.143.7 3.15 “From 3.6” “From 3.14”3.8 3.163.9 3.173.10 3.183.11 3.193.12 3.203.13 3.213.14 3.223.15 3.1
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3.16 3.23.17 3.2’3.18 3.33.19 3.43.20 3.53.21 3.63.22 3.73.23 3.103.24 3.233.25 3.243.26 3.253.27 3.263.28 3.273.29 3.28
CHAPTER 4
NEW PREVIEW----- ---------4.1 4.124.2 4.134.3 4.144.4 4.154.5 4.164.6 4.174.7 4.18 “p. 4.6” “p. 4.17”4.8 4.194.9 4.204.10 4.214.11 4.224.12 4.234.13 4.24 “p. 4.9” “p. 4.20”4.14 4.1 “(4.52)” “(4.51)” “(4.53)” “(4.52)”4.15 4.24.16 4.34.17 4.44.18 4.5 “Fig. 4.38” “Fig. 4.35” “Fig. 4.39” “Fig. 4.36”4.19 4.6 “Fig 4.39(c)” “Fig 4.36(c)”
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4.20 4.74.21 4.84.22 4.94.23 4.104.24 4.114.25 4.254.26 4.26 “p. 4.9” “p. 4.20”
CHAPTER 5
NEW PREVIEW----- ---------5.1 5.165.2 5.175.3 5.185.4 5.195.5 5.205.6 5.215.7 5.225.8 5.235.9 5.15.10 5.25.11 5.35.12 5.45.13 5.55.14 5.65.15 5.75.16 5.85.17 5.95.18 5.10 “Similar to 5.18(a)” “Similar to 5.10(a)”5.19 5.115.20 5.125.21 5.135.22 5.145.23 5.15
CHAPTER 6
NEW PREVIEW----- ---------6.1 6.76.2 6.8
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6.3 6.9 “from eq(6.23)” “from eq(6.20)”6.4 6.106.5 6.11 “eq (6.52)” “eq (6.49)”6.6 6.16.7 6.26.8 6.36.9 6.46.10 6.56.11 6.66.13 6.13 “eq (6.56)” “eq (6.53)” “problem 3” “problem 9”6.16 6.16 “to (6.23) & (6.80)” “to (6.20) & (6.76)”6.17 6.17 “equation (6.23)” “equation (6.20)”
CHAPTER 7
NEW PREVIEW----- ---------7.2 7.2 “eqn. (7.59)” “eqn. (7.57)”7.17 7.17 “eqn. (7.59)” “eqn. (7.57)7.19 7.19 “eqns 7.66 and 7.67” “eqns 7.60 and 7.61”7.21 7.21 “eqn. 7.66” “eqn. 7.60”7.22 7.22 “eqns 7.70 and 7.71” “eqns. 7.64 and 7.65”7.23 7.23 “eqn. 7.71” “eqn. 7.65”7.24 7.24 “eqn 7.79” “eqn 7.73”
CHAPTER 8
NEW PREVIEW----- ---------8.1 8.58.2 8.6
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8.3 8.78.4 8.88.5 8.98.6 8.108.7 8.118.8 8.18.9 8.28.10 8.38.11 8.48.13 8.13 “problem 8.5” “problem 8.9”
CHAPTER 13
NEW PREVIEW----- ---------3.17 3.17 “Eq. (3.123)” “Eq. (3.119)”
CHAPTER 14 - New Chapter, “Oscillators”
CHAPTER 15 - New Chapter, “Phase-Locked Loops”
CHAPTER 16 - Was Chapter 14 in Preview Ed.
Change all chapter references in solutions manual from 14 to 16.
CHAPTER 17 - Was Chapter 15 in Preview Ed.
Change all chapter references in solutions manual from 15 to 17.
CHAPTER 18 - Was Chapter 16 in Preview Ed.
NEW PREVIEW----- ---------18.3 16.3 “Fig. 18.12(c)” “Fig. 16.13(c)”18.8 16.8 “Fig. 18.33(a,b,c,d)” “Fig. 16.34(a,b,c,d)”
Also, change all chapter references from 16 to 18.
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Design of Analog CMOS Integrated Circuits
Behzad Razavi
Errata in Problem Sets
Chapter 2� In Eq. (2.44), �n must be in the numerator.Chapter 3� Call the third problem 3.2’.� In Problem 3.2, Fig. 3.68(d), change the gate voltage ofM2
to Vb2.� In Problem 3.4, Fig. 3.71(a), change the gate voltage ofM=
1 to Vb1.� In Fig. 3.72(e), Vb1 must be changed to Vin.� In Fig. 3.73(h), the output is at the source of M2.� In Problem 3.10(c), the question must be phrased as: Whichdevice enters the triode region first as Vout falls?� In Problem 3.13, first sentence should read: ... withW=L =50=0:5 ...� In Problem 3.16(a), do not neglect channel-length modula-tion in the triode region.Chapter 4� In Problem 4.2, assume ISS = 1 mA and change part (a) to:Determine the voltage gain.� In Problem 4.6, assume � = 0.� In Problem 4.9, assume � = = 0.� In Problem 4.11, assume ID5 = 20 �A.� In Problem 4.13, change the figure number to 4.8(a).Chapter 5� In Problem 5.16(d), assume VTH does not vary with tem-perature.Chapter 6� In Problem 6.4(b) and (d), assume � 6= 0.Chapter 7� The second sentence of Problem 7.2 should read: Assume(W=L)1 = 50=0:5; ID1 = ID2 = 0:1 mA ...
� In Problem 7.20, change ID1 and ID2 to 0.05 mA.� In Problem 7.24, change the bias current to 0.1 mA.Chapter 8� In Problem 8.10, change the tolerable gain error to 5%.� In Problem 8.15, Fig. 8.55(b), call label the top Gm blockGm2. The output is at the output nodes of Gm2.Chapter 10� In Problem 10.11, change ISS to 0.25 mA and (W=L)5;6 to60/0.5.� In Problem 10.12, add: Maximize VGS14 = VGS15 whileleaving at least 0.5 V across I1. Also, in part (b), change M2
to M1.� Problem 10.17 should read: ... between the gate and thedrain of M2 or M3.� In Fig. 10.42, change the gate voltage of M3;4 to Vb1.� In Problem 10.19(c), change A0 in the numerator to A.Chapter 11� In Problem 11.13, ... such that the circuit operates withVDD = 3 V.� In Problems 11.17 and 11.18, the top terminal of R2 shouldbe connected to the top terminal of R1.� In Problem 11.22, assume K = 4.Chapter 12� In Problem 12.8, assume CH = 1 pF.� In Problem 12.12, assume all switches are NMOS devices.� In Problem 12.14, assume Cin = 0:2 pF and calculate C1
and C2.� In Problem 12.16, the output is sensed at the drains of M1
and M2.Chapter 13� In Problem 13.5, change the figure number to 13.6(a).