Random Access Memory using Perovskite Materials · 2020-01-23 · Random Access Memory using...
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Random Access Memory using Perovskite Materials Mr. Oluchi Onwuvuche University of the District of Columbia Electrical Engineering PLATFORM FOR THE ACCELERATED REALIZATION, ANALYSIS & DISCOVERY OF INTERFACE MATERIALS 1 Academic Collaborators (Cornell) Industrial Collaborators (Xallent) PI: Dr. Darrell Schlom Mentor: Matthew Baron Dr. Kwame Amponsah Mehmet Ozdogan August 12, 2019 August 12, 2019 Academic Collaborators (Cornell) Industrial Collaborators (Xallent) PI: Dr. Darrell Schlom Mentor: Matthew Baron Dr. Kwame Amponsah Mehmet Ozdogan Mr. Oluchi Onwuvuche University of the District of Columbia Electrical Engineering
Transcript of Random Access Memory using Perovskite Materials · 2020-01-23 · Random Access Memory using...
Random Access Memory using PerovskiteMaterials
Mr. Oluchi OnwuvucheUniversity of the District of Columbia
Electrical Engineering
PLATFORM FOR THE ACCELERATED REALIZATION, ANALYSIS & DISCOVERY OF INTERFACE MATERIALS 1
Academic Collaborators (Cornell) Industrial Collaborators (Xallent)
PI: Dr. Darrell SchlomMentor: Matthew Baron
Dr. Kwame AmponsahMehmet Ozdogan
August 12, 2019
August 12, 2019
Academic Collaborators (Cornell) Industrial Collaborators (Xallent)
PI: Dr. Darrell SchlomMentor: Matthew Baron
Dr. Kwame AmponsahMehmet Ozdogan
Mr. Oluchi OnwuvucheUniversity of the District of Columbia
Electrical Engineering
Blue Print
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Si
SrO
SrO
TiO2
TiO2
AlO2
AlO2
AlO2
LaO
LaO
LaO
LaO
AlO2
LaO -1/2
-1/2
TiO2
SrOTiO2
SrO
TiO2
SrO
Lanthanum Aluminate(LaAlO3 or LAO)
Strontium Titanate(SrTiO3 or STO)
Nanoscale Testing Solutions
Ideal Capacitor
3
LAO STO
Conducting Interface
Metal Contacts
Actual Capacitor
4
STOLAO
SiO2
SrTiO3
LaAlO3
Si
SiO2STOLAO
SiO2
LaAlO3SrTiO3
SiSiO2
5
SiO2
Memristor Switching
STO
LAO
SiO2
LAO
STO
High Resistance State (HRS) Low Resistance State (LRS)
+
- +
-
Process Flow
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Step #1
Step #2
Step #3
Step #4
Step #5
Step #6
Silicon
LAO/STO
LOR Resist
Photoresist
Metal
Step #7
5 µm Diameter
Finished Chip
7
5 µm Diameter
Testing
8
Memristor
9
e-
LAO STO SiO2 SiPt
-
Pt LAO STO SiO2 Si
Scanning Probe Lithography
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Polycrystalline
width <10 nm
Oxides+-
H2O O2
e-
O2
e-
O2
+-
H2O O2
Polycrystalline
width <10 nm
Oxides
+-
H2O O2
Conclusion & Acknowledgements
R-RAM Creation of Chip Characteristics High Density Memory
Reference: Creativecommons.org
The Chukwunyere Family Dr. Darrell Schlom Mr. Matthew Barone Mr. Jake Sun Dr. Kwame Amponsah Mr. Mehmet Ozdogan Mr. Sirui Tan Dr. Julie Nucci Ms. Melanie-Claire Mallison CNF staff Dr. Schlom’s Group
Your contributions are most appreciated.
11Nanoscale Testing Solutions
National Science Foundation (Platform for Accelerated Realization, Analysis, and Discovery of Interface Materials (PARADIM)) under Cooperative Agreement No. DMR-1539918.
