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XAPP996 (v1.3) October 6, 2008 www.xilinx.com 1

© 2007-2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners.

Summary This is the Xilinx Dual Processor Reference Designs suite. The designs illustrate a few different dual-core architectures based on the MicroBlaze™ and PowerPC® processors. The designs illustrate various concepts described in the Xilinx White Paper WP262 titled, Designing Multiprocessor Systems in Platform Studio. There are simple software applications included with the reference designs that show various forms of interaction between the two processors.

Hardware and Software Requirements

The hardware and software requirements are:

• Xilinx ML505 development board (MicroBlaze processor reference design) and power supplies

• ML410 development board (PowerPC 405 reference designs) and power supplies

• ML507 development board (PowerPC 440 reference design) and power supplies

• Xilinx Platform USB Cable or Parallel IV Cable

• RS232 Cable

• Hyperterminal or some other terminal client

• Xilinx Platform Studio 10.1.03

• Xilinx Integrated Software Environment (ISE®) 10.1.03

Included Systems

The Dual Processor Reference Design Suite can be downloaded from:

https://secure.xilinx.com/webreg/clickthrough.do?cid=92894

The Dual Processor Reference design suite has four reference systems with various combinations of dual processor systems. The below Table 1 shows the contents and description of the files in the xapp996.zip file.

Table 1: Directory Structure and Functional Description

Application Note: Embedded Processing

XAPP996 (v1.3) October 6, 2008

Dual Processor Reference Design SuiteAuthor: Vasanth Asokan

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Directory Name Description

ml505 dual mb.zip Dual MicroBlaze processor design for Xilinx ML505 board.

ml410 dual ppc.zip Dual PowerPC processor design for ML410 board.

ml410_dual_proc_mb_ppc.zip Dual processor, MicroBlaze and PowerPC design processors for the ML410 board.

ml507_dual_proc_ppc440_mb.zip Dual processor, PowerPC 440 and MicroBlaze processors design for the ML507 board.

http://www.xilinx.com

http://www.xilinx.com/support/documentation/white_papers/wp262.pdf

https://secure.xilinx.com/webreg/clickthrough.do?cid=92894

Reference Design Specifics


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The Dual Processor Reference design suite has four reference systems with various combinations of dual processor systems. All four designs illustrate two fully functional processor systems interacting with each other via interprocessing communication cores. These cores provide simple synchronization, and message passing features for use between the two processors. These cores are:

1. XPS_Mutex

The XPS Mutex core helps achieve synchronization between multiple processors when accessing shared resources. The core has a configurable number of mutexes and has a write to lock scheme. More information about the core is present in the Mutex data sheet is available by right clicking on the Mutex core in the Platform Studio IDE. The software interface is provided by the mutex_v1_00_a driver.

2. XPS_Mailbox

The XPS Mailbox core helps a processor pass simple messages to another processor in a FIFO fashion. The Mailbox is suited for small to medium sized messages (< a few 100 bytes). The mailbox also offers an interrupt line which indicates the presence of data in the mailbox. More information about the core is present in the Mailbox data sheet which is available by right clicking on the Mailbox core in the Platform Studio IDE. The software interface is provided by the mbox_v1_00_a driver.

All the designs have software applications illustrating communication using these cores. All the processors also have shared memory (external and internal) between them providing for a more heavy-weight and application-specific data-sharing scheme.

The architecture of the four different systems is explained in the subsequent sections.




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Dual MicroBlaze Processor Design

This design illustrates a topology with two MicroBlaze processors on independent PLB buses. The processors use an XPS_Mutex core and an XPS_Mailbox core to synchronize and pass messages. Both processors have access to external DDR memory via the MPMC memory controller. Apart from sharing external memory, the two processors share local memory (BRAM) via XPS BRAM memory controllers. Each processor has an interrupt controller assigned to it to handle various in the interrupts in the system. Both processors have a debugger interface via the MDM core. Figure 1 shows a block diagram of the dual MicroBlaze processor design.

X-Ref Target - Figure 1

Figure 1: Dual MicroBlaze Processor Design

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Dual PowerPC Processor Design

This design illustrates a topology with two PowerPC 405 processors on independent PLB buses. The processors use an XPS_Mutex core and an XPS_Mailbox core to synchronize and pass messages. Both processors have access to external DDR memory via the PLB interface. External memory is cached by both processors. In addition to sharing external memory, the two processors share local memory (BRAM) via OCM and PLB interfaces. There is an interrupt controller assigned to each processor to handle various in the interrupts in the system. Both processors have a debugger interface via the jtag_ppc controller. Figure 2 shows a block diagram of this design.


Figure 2: Dual PowerPC Processor Design

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Dual Processor PowerPC 405 and MicroBlaze Processor Design

This design illustrates a topology with a PowerPC405 and a MicroBlaze processor, each on their own PLB buses. The processors use an XPS_Mutex core and an XPS_Mailbox core to synchronize and pass messages. Both processors have access to external DDR memory via the MPMC memory controller. In this design, apart from sharing external memory, the two processors share local memory (BRAM) via XPS BRAM memory controllers. Each processor has an interrupt controller assigned to it to handle various interrupts in the system. Both processors have a debugger interface via the jtag_ppc controller and the MDM cores. The MDM core also provides a UART interface for the second processor. Figure 3 shows a block diagram of this design.


Figure 3: Dual Processor PowerPC 405 and MicroBlaze Processor Design

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Dual Processor PowerPC 440 and MicroBlaze Processor Design

This design illustrates a topology with a PowerPC 440 and a MicroBlaze processor, each on their own PLB buses. The processors use an XPS_Mutex core and an XPS_Mailbox core to synchronize and pass messages. Both processors have access to external DDR memory via the MPMC memory controller. In this design, apart from sharing external memory, the two processors share local memory (BRAM) via XPS BRAM memory controllers. Each processor has an interrupt controller assigned to it to handle various interrupts in the system. Both processors have a debugger interface via the jtag_ppc controller and the MDM cores. The MDM core also provides a UART interface for the second processor. Figure 4 shows a block diagram of this design.


Figure 4: Dual Processor PowerPC 440 and MicroBlaze Processor Design

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Creating the Designs


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Creating the Designs

This section discusses how these designs were created in the first place. While this application note will not cover the exact set of steps in tutorial form, the broad series of steps are similar across all the three designs. These broad steps are,

1. Create a single processor design targeting a particular development board, with all the necessary peripherals, local and external memory using Base System Builder Wizard.

2. Add the second processor via drag-drop in the IP Catalog and connect it to a new PLBv46 system bus.

3. Connect the debug interface of the processor to the debug peripheral (JTAGPPC or MDM). Configure the debug peripheral, if necessary, to handle the second processor as well.

4. Provide local memory (to hold boot code) for the newly added processor. This is ILMB and DLMB memory for the MicroBlaze processor and IOCM and DOCM for the PowerPC processor. The local memory buses must be first added, followed by a connection to the processor and a connection to the memory controller. Alternatively, this boot memory can be on the PLBv46 bus.

5. Add new ports and connect the MPMC external memory to the second processor. Connect cache links if required.

6. Add the interprocessor communication cores (Mutex & Mailbox) and configure them

7. Add shared local memory by connecting it via DLMB for the MicroBlaze processor and DOCM for the PowerPC processor. The PLBv46 core can also be used to interface the shared local BRAM memory.

8. Add bridge peripherals, if necessary.

9. Add other miscellaneous peripherals, such as timer or interrupt controller, that are necessary to run reasonable software applications.

10. Go to the address view in the system assembly panel and configure a valid address range for all the peripherals and memories added above.

11. Verify clock and reset connections to all the peripherals added from the clock_generator and proc_sys_reset cores.

Implementing the Designs

Unzip the entire reference design zip file into a directory of your choice. To implement a particular design, open the design up in XPS and click on Device Configuration → Update Bitstream.

Running the Software

All the software applications for the reference designs is under the XPS Software Applications tab.

Downloading the Bitstream

To download the bitstream, click on Device Configuration → Program Hardware.

Processor STDIN/STDOUT

The sample applications communicate to the outside world via UARTs. Processor 1 typically uses the dedicated RS232 UART on the board. To be able to receive useful output from the second processor in the system, a JTAG UART (via the MDM core) is available on each design.

To connect to the first processor's STDOUT, connect a hyperterminal session (configured for 9600 baud, 8 data bits, no parity, 1 stop bit, and no flow control) to the COM port on your computer to which the RS232 cable from the board is connected. On the ML410 board, COM0 is the serial port from which output is received.

To connect to the second processor's STDOUT,




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1. Once the bitstream is downloaded, open up an XMD console by clicking on Xilinx Tools → View XMD Console.

2. Connect to the MDM UART in the XMD console, by typing in connect mdm -uart.

3. Open a TCP terminal tunnel in XMD, by typing in terminal -jtag_uart_server 4321

4. Connect a hyperterminal session via TCP/IP to localhost:4321 (4321 is the TCP terminal port opened by in the previous step). This establishes a connection to the JTAG UART, tunneled via TCP/IP by XMD. Thus there can be two hyperterminal window open, each displaying output from the corresponding processor.

Running an Application Set

Running an Application Set

There are four different categories of applications included in each design. They are,

Each example application consists of a software project each for processor 0 and one for processor 1. Hence to be able to see the demonstration of a particular concept, download and run the each application on the corresponding processor using the XMD console.

For example, to run any demonstration application, use the following steps.

1. Open a XMD console in XPS by selecting Debug → Launch XMD...

2. While selecting the processor, choose the first processor (microblaze_0, ppc405_0, or ppc440_0) from the drop down menu. Once XMD connects, type debugconfig -reset_on_run disable. This will prevent XMD from issuing a system reset whenever an application is downloaded.

3. Open another XMD console in XPS by selecting Debug → Launch XMD...

4. While selecting the processor to connect, choose the second processor (microblaze_1 or ppc405_1) in the drop down menu bar. Once XMD connects, type debugconfig -reset_on_run disable. This will prevent XMD from issuing a system reset whenever an application is downloaded.

5. To run an application set, download the respective applications to both the processors and execute them at the same time. Below is the example for running the shared memory application using the dual processor suite. In XMD console for the first processor, download the shared memory application (shm0) executable, then run it using the following commands.

dow shm0.elf

run

6. In XMD console for the Second processor, download the shared memory application (shm1) executable, then run it using the following commands.

dow shm1.elf

run

7. This will start off the shared memory application on both the processors. Output from this processor should be visible on the respective hyperterminal window. To check the state of the processor, you can type the state command on the respective XMD console.

8. Similarly for other application sets, download the respective applications, then execute them simultaneously.




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Demonstration Applications1. Shared memory example

(Software Projects shm0 and shm1)

This example illustrates the use of simple shared memories between the two processors. Processor 1 writes a value to a shared memory location, sets a shared flag indicating that data is available and waits for Processor 2 to read it. Processor 2 reads the value and sets a flag indicating that it has consumed the data. This process is repeated on the shell.


Figure 5: Output From Shared Memory Example (shm0)


Figure 6: Output From Shared Memory Example (shm1

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2. Synchronization example

(Software Projects sharedconsole0 and sharedconsole1)

This example illustrates the use of the XPS_Mutex core to perform synchronization when accessing a shared resource. The shared resource in this example is the primary on board RS232 interface. Both processors redirect their STDOUT to this shared console. Without synchronization, the console output would become very garbled and useless. Hence, each processor locks the XPS_Mutex core before doing any output and unlocks the mutex when output is done. The two processors also modify a shared variable called state in their critical sections using the XPS Mutex lock.


Figure 7: Output from Synchronization Example (sharedconsole0 and sharedconsole1)

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3. Mailbox message passing example

(Software Projects prodcon0 and prodcon1)

This example illustrates the use of the XPS_Mailbox core to pass data from a producer processor down to a consumer processor. The two processors exchange a greeting message first and then the producer passes multiple larger kilobyte sized data structure to the consumer. The consumer verifies the transferred data against a known golden value.


Figure 8: Output From Mailbox Message Passing Example (producer)


Figure 9: Output From Mailbox Message Passing Example (consumer)

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4. Mailbox interrupt generation example

(Software Projects ipi0 and ipi1)

This example illustrates the use of the XPS_Mailbox core to interrupt one processor from the other. The interrupt signals of the XPS_Mailbox are used for this purpose. Once the mailbox interrupts are enabled, processor 1 starts sending messages to processor 2. Processor 2 receives every message through an interrupt. It sends an acknowledge message (interrupt) back to Processor 1 to indicate receipt of the event.


Figure 10: Output From Mailbox Interrupt Generation Example (ip10)


Figure 11: Output From Mailbox Interrupt Generation Example (ipi1)

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Conclusion


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Conclusion This reference design set can be used as a starting point for creating custom multiprocessor systems based on the MicroBlaze, PowerPC 405, and PowerPC 440 processors. These designs can be ported to other compatible boards in a relatively straightforward fashion. More processors and peripherals can be added to customize the design for the final application.

Revision History

The following table shows the revision history for this document:

Notice of Disclaimer

Xilinx is disclosing this Application Note to you “AS-IS” with no warranty of any kind. This Application Noteis one possible implementation of this feature, application, or standard, and is subject to change withoutfurther notice from Xilinx. You are responsible for obtaining any rights you may require in connection withyour use or implementation of this Application Note. XILINX MAKES NO REPRESENTATIONS ORWARRANTIES, WHETHER EXPRESS OR IMPLIED, STATUTORY OR OTHERWISE, INCLUDING,WITHOUT LIMITATION, IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, ORFITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL XILINX BE LIABLE FOR ANY LOSS OFDATA, LOST PROFITS, OR FOR ANY SPECIAL, INCIDENTAL, CONSEQUENTIAL, OR INDIRECTDAMAGES ARISING FROM YOUR USE OF THIS APPLICATION NOTE.

Date Version Description of Revisions

5/17/07 1.0 Initial Xilinx release.

11/20/07 1.1 Updated for EDK 9.2i; updated to new application note template.

7/25/08 1.2 Updated for EDK 10.1.2i; removed the SDK flow and updated the application note to use the normal XPS flow to run the applications.

10/6/08 1.3 Added dual core design for ML507; updated for EDK 10.1.03.


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