Quartus II Handbook Volume 1: Design and...

Quartus II Handbook Volume 1: Design and Synthesis

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The Quartus II software organizes and manages the elements of your design within a project. The projectencapsulates information about your design hierarchy, libraries, constraints, and project settings. ClickFile > New Project Wizard to quickly create a new project and specify basic project settings

When you open a project, a unified GUI displays integrated project information. The Project Navigatorallows you to view and edit the elements of your project. The Messages window lists important informa‐tion about project processing.

You can save multiple revisions of your project to experiment with settings that achieve your design goals.Quartus II projects support team-based, distributed work flows and a scripting interface.

Quick StartTo quickly create a project and specify basic settings, click File > New Project Wizard.

New Project Wizard

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Note: The New Project Wizard offers project templates based on fully functioning design examples.Select the Project template option to choose a project template that is ready to compile. Alteraprovides additional project templates as available.

Understanding Quartus II ProjectsA single Quartus II Project File (.qpf) represents each project. The text-based . qpf references the QuartusII Settings File (.qsf), that lists all project files and stores project and entity settings. When you makeproject changes in the GUI, these text files automatically store the changes. The GUI helps to manage:

• Design, EDA, IP core, and Qsys system files• Project settings and constraint files• Project archive and migration files

Table 1-1: Quartus II Project Files

File Type Contains To Edit Format

Project file Project and revision name File > New ProjectWizard

Quartus II Project File (.qpf)

Projectsettings

Lists design files, entitysettings, target device,synthesis directives,placement constraints

Assignments > Settings Quartus II Settings File (.qsf)

Projectdatabase

Compilation results Project > ExportDatabase

Exported Partition File (.qxp)

Timingconstraints

Clock properties,exceptions, setup/hold

Tools > TimeQuestTiming Analyzer

Synopsys Design Constraints File(.sdc)

Logic designfiles

RTL and other designsource files

File > New All supported HDL files

Program‐ming files

Device programmingimage and information

Tools > Programmer SRAM Object File (.sof)Programmer Object File (.pof)

Projectlibrary

Project and global libraryinformation

Tools > Options >Libraries

.qsf(project)

quartus2.ini (global)

IP core files IP core logic, synthesis,and simulationinformation

Tools > IP Catalog All supported HDL files

Quartus II IP File (.qip)

Qsys systemfiles

Qsys system and IP corefiles

Tools > Qsys Qsys System File (.qsys)

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File Type Contains To Edit Format

EDA toolfiles

Generated for third-partyEDA tools

Tools > Options > EDATool Options

Verilog Output File (.vo)

VHDL Output File (.vho)

Verilog Quartus Mapping File(.vqm)

Archive files Complete project as singlecompressed file

Project > Archive Project Quartus II Archive File (.qar)

Viewing Basic Project InformationView basic information about your project in the Project Navigator, Report panel, and Messages window.View project elements in the Project Navigator ( View > Utility Windows > Project Navigator). TheProject Navigator displays key project information, including design files, IP components, and revisionsof your project. Use the Project Navigator to:

• View and modify the design hierarchy (right-click > Set as Top-Level Entity)• Set the project revision (right-click > Set Current Revision)• View and update logic design files and constraint files (right-click > Open)• Update IP component version information (right-click > Upgrade IP Component)

Figure 1-1: Project Navigator Hierarchy, Files, Revisions, and IP

Viewing Project ReportsThe Report panel (Processing > Compilation Report) displays detailed reports after project processing,including the following:

• Analysis & Synthesis reports• Fitter reports• Timing analysis reports• Power analysis reports• Signal integrity reports

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Analyze the detailed project information in these reports to determine correct implementation. Right-click report data to locate and edit the source in project files.

Figure 1-2: Report Panel

Related InformationList of Compilation Reports

Viewing Project MessagesThe Messages window (View > Utility Windows > Messages) displays information, warning, and errormessages about Quartus II processes. Right-click messages to locate the source or get message help.

• Processing tab—displays messages from the most recent process• System tab—displays messages unrelated to design processing• Search—locates specific messages

Messages are written to stdout when you use command-line executables.

Figure 1-3: Messages Window

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You can suppress display of unimportant messages so they do not obscure valid messages.

Figure 1-4: Message Suppression by Message ID Number

Suppressing MessagesTo supress messages, right-click a message and choose any of the following:

• Suppress Message—suppresses all messages matching exact text• Suppress Messages with Matching ID—suppresses all messages matching the message ID number,

ignoring variables• Suppress Messages with Matching Keyword—suppresses all messages matching keyword or

hierarchy

Message Suppression Guidelines

• You cannot suppress error or Altera legal agreement messages.• Suppressing a message also suppresses any submessages.• Message suppression is revision-specific. Derivative revisions inherit any suppression.• You cannot edit messages or suppression rules during compilation.

Managing Project SettingsThe New Project Wizard helps you initially assign basic project settings. Optimizing project settingsenables the Compiler to generate programming files that meet or exceed your specifications.

The .qsf stores each revision’s project settings.

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Click Assignments > Settings to access global project settings, including:

• Project files list• Synthesis directives and constraints• Logic options and compiler effort levels• Placement constraints• Timing constraint files• Operating temperature limits and conditions• File generation for other EDA tools• Target device (click Assignments > Device)

The Quartus II Default Settings File (_assignment_defaults.qdf) stores initial settingsand constraints for each new project revision.

Figure 1-5: Settings Dialog Box for Global Project Settings

The Assignment Editor (Tools > Assignment Editor) provides a spreadsheet-like interface for assigningall instance-specific settings and constraints.

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Figure 1-6: Assignment Editor Spreadsheet

Optimizing Project SettingsOptimize project settings to meet your design goals. The Quartus II Design Space Explorer II iterativelycompiles your project with various setting combinations to find the optimal setting for your goals.Alternatively, you can create a project revision or project copy to manually compare various projectsettings and design combinations.

Optimizing with Design Space Explorer IIUse Design Space Explorer II (Tools > Launch Design Space Explorer II) to find optimal project settingsfor resource, performance, or power optimization goals. Design Space Explorer II (DSE II) processes yourdesign using various setting and constraint combinations, and reports the best settings for your design.

DSE II attempts multiple seeds to identify one meeting your requirements. DSE II can run differentcompilations on multiple computers in parallel to streamline timing closure.

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Figure 1-7: Design Space Explorer II

Optimizing with Project RevisionsYou can save multiple, named project revisions within your Quartus II project (Project > Revisions).

Each revision captures a unique set of project settings and constraints, but does not capture any logicdesign file changes. Use revisions to experiment with different settings while preserving the original.Youcan compare revisions to determine the best combination, or optimize different revisions for variousapplications. Use revisions for the following:

• Create a unique revision to optimize a design for different criteria, such as by area in one revision andby fMAX in another revision.

• When you create a new revision the default Quartus II settings initially apply.• Create a revision of a revision to experiment with settings and constraints. The child revision includes

all the assignments and settings of the parent revision.

You create, delete, specify current, and compare revisions in the Revisions dialog box. Each time youcreate a new project revision, the Quartus II software creates a new .qsf using the revision name.

To compare each revision’s synthesis, fitting, and timing analysis results side-by-side, click Project >Revisions and then click Compare.

In addition to viewing the compilation results of each revision, you can also compare the assignments foreach revision. This comparison reveals how different optimization options affect your design.

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Figure 1-8: Comparing Project Revisions

Copying Your ProjectClick Project > Copy Project to create a separate copy of your project, rather than just a revision withinthe same project.

The project copy includes all design files, .qsf(s), and project revisions. Use this technique to optimizeproject copies for different applications. For example, optimize one project to interface with a 32-bit databus, and optimize a project copy to interface with a 64-bit data bus.

Managing Logic Design FilesThe Quartus II software helps you create and manage the logic design files in your project. Logic designfiles contain the logic that implements your design. When you add a logic design file to the project, theCompiler automatically compiles that file as part of the project. The Compiler synthesizes your logicdesign files to generate programming files for your target device.

The Quartus II software includes full-featured schematic and text editors, as well as HDL templates toaccelerate your design work. The Quartus II software supports VHDL Design Files (.vhd), Verilog HDLDesign Files (.v), SystemVerilog (. sv) and schematic Block Design Files (. bdf). The Quartus II softwarealso supports Verilog Quartus Mapping (.vqm) design files generated by other design entry and synthesistools. In addition, you can combine your logic design files with Altera and third-party IP core design files,including combining components into a Qsys system (. qsys).

The New Project Wizard prompts you to identify logic design files. Add or remove project files by clickingProject > Add/Remove Files in Project. View the project’s logic design files in the Project Navigator.

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Figure 1-9: Design and IP Files in Project Navigator

Right-click files in the Project Navigator to:

• Open and edit the file• Remove File from Project• Set as Top-Level Entity for the project revision• Create a Symbol File for Current File for display in schematic editors• Edit file Properties

Including Design LibrariesYou can include design files libraries in your project. Specify libraries for a single project, or for allQuartus II projects. The.qsf stores project library information.

The quartus2.ini file stores global library information.

Related InformationDesign Library Migration Guidelines on page 1-41

Specifying Design LibrariesTo specify project libraries from the GUI:

1. Click Assignment > Settings.2. Click Libraries andspecify the Project Library name or Global Library name.Alternatively, you can

specify project libraries with SEARCH_PATH in the .qsf, and global libraries in the quartus2.ini file.

Related Information

• Recommended Design Practices on page 11-1• Recommended HDL Coding Styles on page 12-1

Managing Timing ConstraintsView basic information about your project in the Project Navigator, Report panel, and Messages window.

Apply appropriate timing constraints to correctly optimize fitting and analyze timing for your design. TheFitter optimizes the placement of logic in the device to meet your specified timing and routingconstraints.

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Specify timing constraints in the TimeQuest Timing Analyzer (Tools > TimeQuest Timing Analyzer), orin an .sdc file. Specify constraints for clock characteristics, timing exceptions, and external signal setupand hold times before running analysis. TimeQuest reports the detailed information about the perform‐ance of your design compared with constraints in the Compilation Report panel.

Save the constraints you specify in the GUI in an industry-standard Synopsys Design Constraints File(.sdc). You can subsequently edit the text-based .sdc file directly.

Figure 1-10: TimeQuest Timing Analyzer and SDC Syntax Example

Related InformationQuartus II TimeQuest Timing Analyzer

Introduction to Altera IP CoresAltera® and strategic IP partners offer a broad portfolio of off-the-shelf, configurable IP cores optimizedfor Altera devices. The Quartus® II software installation includes the Altera IP library. You can integrateoptimized and verified Altera IP cores into your design to shorten design cycles and maximizeperformance. You can evaluate any Altera IP core in simulation and compilation in the Quartus IIsoftware. The Quartus II software also supports integration of IP cores from other sources. Use the IPCatalog to efficiently parameterize and generate synthesis and simulation files for a custom IP variation.

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The Altera IP library includes the following categories of IP cores:

• Basic functions• DSP functions• Interface protocols• Low power functions• Memory interfaces and controllers• Processors and peripherals

Note: The IP Catalog (Tools > IP Catalog) and parameter editor replace the MegaWizard™ Plug-InManager for IP selection and parameterization, beginning in Quartus II software version 14.0. Usethe IP Catalog and parameter editor to locate and paramaterize Altera and other supported IPcores.

Related Information

• IP User Guide Documentation• Altera IP Release Notes

Installing and Licensing IP CoresThe Altera IP Library provides many useful IP core functions for your production use without purchasingan additional license. Some Altera MegaCore® IP functions require that you purchase a separate licensefor production use. However, the OpenCore® feature allows evaluation of any Altera IP core in simulationand compilation in the Quartus II software. After you are satisfied with functionality and perfformance,visit the Self Service Licensing Center to obtain a license number for any Altera product.

Figure 1-11: IP Core Installation Path

acds

quartus - Contains the Quartus II softwareip - Contains the Altera IP Library and third-party IP cores

altera - Contains the Altera IP Library source code - Contains the IP core source files

Note: The default IP installation directory on Windows is :\altera\; on Linux it is/altera/ .

Related Information

• Altera Licensing Site• Altera Software Installation and Licensing Manual

OpenCore Plus IP EvaluationAltera's free OpenCore Plus feature allows you to evaluate licensed MegaCore IP cores in simulation andhardware before purchase. You need only purchase a license for MegaCore IP cores if you decide to takeyour design to production. OpenCore Plus supports the following evaluations:

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• Simulate the behavior of a licensed IP core in your system.• Verify the functionality, size, and speed of the IP core quickly and easily.• Generate time-limited device programming files for designs that include IP cores.• Program a device with your IP core and verify your design in hardware.

OpenCore Plus evaluation supports the following two operation modes:

• Untethered—run the design containing the licensed IP for a limited time.• Tethered—run the design containing the licensed IP for a longer time or indefinitely. This requires a

connection between your board and the host computer.

Note: All IP cores that use OpenCore Plus time out simultaneously when any IP core in the design timesout.

IP Catalog and Parameter EditorThe Quartus II IP Catalog (Tools > IP Catalog) and parameter editor help you easily customize andintegrate IP cores into your project. You can use the IP Catalog and parameter editor to select, customize,and generate files representing your custom IP variation.

Note: The IP Catalog (Tools > IP Catalog) and parameter editor replace the MegaWizard™ Plug-InManager for IP selection and parameterization, beginning in Quartus II software version 14.0. Usethe IP Catalog and parameter editor to locate and paramaterize Altera IP cores.

The IP Catalog lists installed IP cores available for your design. Double-click any IP core to launch theparameter editor and generate files representing your IP variation. The parameter editor prompts you tospecify an IP variation name, optional ports, and output file generation options. The parameter editorgenerates a top-level Qsys system file (.qsys) or Quartus II IP file (.qip) representing the IP core in yourproject. You can also parameterize an IP variation without an open project.

Use the following features to help you quickly locate and select an IP core:

• Filter IP Catalog to Show IP for active device family or Show IP for all device families. If you have noproject open, select the Device Family in IP Catalog.

• Type in the Search field to locate any full or partial IP core name in IP Catalog.• Right-click an IP core name in IP Catalog to display details about supported devices, open the IP core's

installation folder, and view links to documentation.• Click Search for Partner IP, to access partner IP information on the Altera website.

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Figure 1-12: Quartus II IP Catalog

Search for installed IP cores

Double-click to customize, right-click for detailed information

Show IP only for target device

Note: The IP Catalog is also available in Qsys (View > IP Catalog). The Qsys IP Catalog includesexclusive system interconnect, video and image processing, and other system-level IP that are notavailable in the Quartus II IP Catalog. For more information about using the Qsys IP Catalog, referto Creating a System with Qsys in the Quartus II Handbook.

Related InformationCreating a System With Qsys on page 5-1

Using the Parameter EditorThe parameter editor helps you to configure IP core ports, parameters, and output file generation options.

• Use preset settings in the parameter editor (where provided) to instantly apply preset parameter valuesfor specific applications.

• View port and parameter descriptions, and links to documentation.• Generate testbench systems or example designs (where provided).

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Figure 1-13: IP Parameter Editors

View IP portand parameter details

Apply preset parameters forspecific applications

Specify your IP variationname and target device

Legacy parameter editors

Adding IP Cores to IP CatalogThe IP Catalog automatically displays Altera IP cores found in the project directory, in the Alterainstallation directory, and in the defined IP search path. The IP Catalog can include Altera-provided IPcomponents, third-party IP components, custom IP components that you provide, and previouslygenerated Qsys systems.

You can use the IP Search Path option (Tools > Options) to include custom and third-party IPcomponents in the IP Catalog. The IP Catalog displays all IP cores in the IP search path. The Quartus IIsoftware searches the directories listed in the IP search path for the following IP core files:

• Component Description File (_hw.tcl)—Defines a single IP core.• IP Index File (.ipx)—Each .ipx file indexes a collection of available IP cores, or a reference to other

directories to search. In general, .ipx files facilitate faster searches.

The Quartus II software searches some directories recursively and other directories only to a specificdepth. When the search is recursive, the search stops at any directory that contains an _hw.tcl or .ipx file.

In the following list of search locations, a recursive descent is annotated by **. A single * signifies any file.

Table 1-2: IP Search Locations

Location Description

PROJECT_DIR/* Finds IP components and index files in the Quartus II projectdirectory.

PROJECT_DIR/ip/**/* Finds IP components and index files in any subdirectory of the /ipsubdirectory of the Quartus II project directory.

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Figure 1-14: Specifying IP Search Locations

Adds new global IP search paths

Changes search path order

Adds new project-specific IP search paths

Lists current project and global search paths

If the Quartus II software recognizes two IP cores with the same name, the following search pathprecedence rules determine the resolution of files:

1. Project directory.2. Project database directory.3. Project IP search path specified in IP Search Locations, or with the SEARCH_PATH assignment in the

Quartus II Settings File (.qsf) for the current project revision.4. Global IP search path specified in IP Search Locations, or with the SEARCH_PATH assignment in the

quartus2.ini file.5. Quartus software libraries directory, such as \libraries.Note: If you add a component to the search path, you must refresh your system by clicking File > Refresh

to update the IP Catalog.

General Settings for IPYou can use the following settings to control how the Quartus II software manages IP cores in yourproject.

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Table 1-3: IP Core General Setting Locations

Setting Location Description

Tools > Options > IPSettings

Or

Assignments > Settings >IP Settings (only enabledwith open project)

• Specify your IP generation HDL preference. The parameter editorgenerates IP files in your preferred HDL by default.

• Increase Maximum Qsys memory usage size if you experience slowprocessing for large systems, or if Qsys reports an Out of Memory error.

• Specify whether to Automatically add Quartus II IP files to all projects.Disable this option to control addition of IP files manually. You maywant to experiment with IP before adding to a project.

• Use the IP Regeneration Policy setting to control when synthesis filesare regenerated for each IP variation. Typically you Always regeneratesynthesis files for IP cores after making changes to an IP variation.

Tools > Options > IPCatalog Search Locations

Or

Assignments > Settings >IP Catalog SearchLocations

• Specify project and global IP search locations. The Quartus II softwaresearches for IP cores in the project directory, in the Altera installationdirectory, and in the IP search path.

Assignments > Settings >Simulation

• NativeLink Settings allow you to automatically compile testbenches forsupported simulators. You can also specify a script to compile thetestbench, and a script to set up the simulation.

Specifying IP Core Parameters and OptionsYou can quickly configure a custom IP variation in the parameter editor. Use the following steps tospecify IP core options and parameters in the parameter editor. Refer to Specifying IP Core Parametersand Options (Legacy Parameter Editors) for configuration of IP cores using the legacy parameter editor.

1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize.The parameter editor appears.

2. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variationsettings in a file named .qsys. Click OK.

3. Specify the parameters and options for your IP variation in the parameter editor, including one ormore of the following. Refer to your IP core user guide for information about specific IP coreparameters.

• Optionally select preset parameter values if provided for your IP core. Presets specify initialparameter values for specific applications.

• Specify parameters defining the IP core functionality, port configurations, and device-specificfeatures.

• Specify options for processing the IP core files in other EDA tools.4. Click Generate HDL, the Generation dialog box appears.5. Specify output file generation options, and then click Generate. The IP variation files generate

according to your specifications.

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6. To generate a simulation testbench, click Generate > Generate Testbench System.7. To generate an HDL instantiation template that you can copy and paste into your text editor, click

Generate > HDL Example.8. Click Finish. The parameter editor adds the top-level .qsys file to the current project automatically. If

you are prompted to manually add the .qsys file to the project, click Project > Add/Remove Files inProject to add the file.

9. After generating and instantiating your IP variation, make appropriate pin assignments to connectports.

Figure 1-15: IP Parameter Editor

View IP portand parameter details

Apply preset parameters forspecific applications

Specify your IP variation nameand target device

Files Generated for Altera IP CoresThe Quartus II software generates the following IP core output file structure:

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Figure 1-16: IP Core Generated Files

_tb.csv

_tb.spd

.cmp - VHDL component declaration file

.ppf - XML I/O pin information file

.qip - Lists IP synthesis files

.sip - Contains assingments for IP simulation files

.v or .vhdTop-level IP synthesis file

.v or .vhdTop-level simulation file

.qsys - System or IP integration file

_bb.v - Verilog HDL black box EDA synthesis file

_inst.v or .vhd - Sample instantiation template

_generation.rpt - IP generation report

.debuginfo - Contains post-generation information.html - Connection and memory map data

.bsf - Block symbol schematic

.spd - Combines simulation scripts for multiple cores

_tb.qsysTestbench system file

.sopcinfo - Software tool-chain integration file

IP variation files_tb

testbench system

sim

Simulation files

synth

IP synthesis files

sim

simulation files

Simulator scripts

_tb

nSubcore libraries

simSubcore

Simulation files

synthSubcore

synthesis files

n

IP variation files

testbench files

Table 1-4: IP Core Generated Files

File Name Description

.qsys The Qsys system or top-level IP variation file. is the namethat you give your IP variation.

.sopcinfo Describes the connections and IP component parameterizations inyour Qsys system. You can parse its contents to get requirementswhen you develop software drivers for IP components.

Downstream tools such as the Nios II tool chain use this file.The .sopcinfo file and the system.h file generated for the Nios II toolchain include address map information for each slave relative to eachmaster that accesses the slave. Different masters may have a differentaddress map to access a particular slave component.

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.cmp The VHDL Component Declaration (.cmp) file is a text file thatcontains local generic and port definitions that you can use in VHDLdesign files.

.html A report that contains connection information, a memory mapshowing the address of each slave with respect to each master towhich it is connected, and parameter assignments.

_generation.rpt IP or Qsys generation log file. A summary of the messages during IPgeneration.

.debuginfo Contains post-generation information. Used to pass System Consoleand Bus Analyzer Toolkit information about the Qsys interconnect.The Bus Analysis Toolkit uses this file to identify debug componentsin the Qsys interconnect.

.qip Contains all the required information about the IP component tointegrate and compile the IP component in the Quartus II software.

.csv Contains information about the upgrade status of the IP component.

.bsf A Block Symbol File (.bsf) representation of the IP variation for usein Quartus II Block Diagram Files (.bdf).

.spd Required input file for ip-make-simscript to generate simulationscripts for supported simulators. The .spd file contains a list of filesgenerated for simulation, along with information about memoriesthat you can initialize.

.ppf The Pin Planner File (.ppf) stores the port and node assignments forIP components created for use with the Pin Planner.

_bb.v You can use the Verilog black-box (_bb.v) file as an empty moduledeclaration for use as a black box.

.sip Contains information required for NativeLink simulation of IPcomponents. You must add the .sip file to your Quartus project.

_inst.v or _inst.vhd HDL example instantiation template. You can copy and paste thecontents of this file into your HDL file to instantiate the IP variation.

.regmap If the IP contains register information, the .regmap file generates.The .regmap file describes the register map information of masterand slave interfaces. This file complements the .sopcinfo file byproviding more detailed register information about the system. Thisenables register display views and user customizable statistics inSystem Console.

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.svd Allows HPS System Debug tools to view the register maps ofperipherals connected to HPS within a Qsys system.

During synthesis, the .svd files for slave interfaces visible to SystemConsole masters are stored in the .sof file in the debug section.System Console reads this section, which Qsys can query for registermap information. For system slaves, Qsys can access the registers byname.

.v

or

.vhd

HDL files that instantiate each submodule or child IP core forsynthesis or simulation.

mentor/ Contains a ModelSim® script msim_setup.tcl to set up and run asimulation.

aldec/ Contains a Riviera-PRO script rivierapro_setup.tcl to setup and run asimulation.

/synopsys/vcs

/synopsys/vcsmx

Contains a shell script vcs_setup.sh to set up and run a VCS®simulation.

Contains a shell script vcsmx_setup.sh and synopsys_ sim.setup file toset up and run a VCS MX® simulation.

/cadence Contains a shell script ncsim_setup.sh and other setup files to set upand run an NCSIM simulation.

/submodules Contains HDL files for the IP core submodule./ For each generated child IP core directory, Qsys generates /synth and /

sim sub-directories.

Specifying IP Core Parameters and Options (Legacy Parameter Editors)Some IP cores use a legacy version of the parameter editor for configuration and generation. Use thefollowing steps to configure and generate an IP variation using a legacy parameter editor.

Note: The legacy parameter editor generates a different output file structure than the latest parametereditor. Refer to Specifying IP Core Parameters and Options for configuration of IP cores that use thelatest parameter editor.

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Figure 1-17: Legacy Parameter Editors

Legacy parameter editors

1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize.The parameter editor appears.

2. Specify a top-level name and output HDL file type for your IP variation. This name identifies the IPcore variation files in your project. Click OK.

3. Specify the parameters and options for your IP variation in the parameter editor. Refer to your IP coreuser guide for information about specific IP core parameters.

4. Click Finish or Generate (depending on the parameter editor version). The parameter editor generatesthe files for your IP variation according to your specifications. Click Exit if prompted when generationis complete. The parameter editor adds the top-level .qip file to the current project automatically.

Note: To manually add an IP variation generated with legacy parameter editor to a project, clickProject > Add/Remove Files in Project and add the IP variation .qip file.

Files Generated for Altera IP Cores (Legacy Parameter Editors)The Quartus II software generates one of the following output file structures for Altera IP cores that use alegacy parameter editor.

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Figure 1-18: IP Core Generated Files (Legacy Parameter Editor)

Generated IP File Output C Generated IP File Output D

Generated IP File Output B

.html - IP core generation report

_testbench.v or .vhd - Testbench file1

.bsf - Block symbol schematic file

_syn.v or .vhd - Timing & resource estimation netlist 1

_bb - Verilog HDL black box EDA synthesis file

.vo or .vho - IP functional simulation model 2

.qip - Quartus II IP integration file

.v or .vhd - Top-level HDL IP variation definition

_block_period_stim.txt - Testbench simulation data 1

-library - Contains IP subcomponent synthesis libraries

Generated IP File Output A

.v or .vhd - Top-level IP synthesis file

_inst.v or .vhd - Sample instantiation template


.vo or .vho - IP functional simulation model 2_syn.v or .vhd - Timing & resource estimation netlist 1

_bb.v - Verilog HDL black box EDA synthesis file


greybox_tmp 3

.cmp - VHDL component declaration file

_sim 1

_instance.vo - IPFS model 2


.sip - Lists files for simulation

_testbench or _example - Testbench or example1

.v, .sv. or .vhd - Top-level IP synthesis file

_instance

_syn.v or .vhd - Timing & resource estimation netlist 1.cmp - VHDL component declaration file .bsf - Block symbol schematic file

- IP core synthesis files

.sv, .v, or .vhd - HDL synthesis files.sdc - Timing constraints file

.ppf - XML I/O pin information file.spd - Combines individual simulation scripts 1

_sim.f - Refers to simulation models and scripts 1

_bb.v - Verilog HDL black box EDA synthesis file_inst.v or .vhd - Sample instantiation template

synthesis - IP synthesis files

.qip - Lists files for synthesis

testbench - Simulation testbench files 1

- Testbench for supported simulators

.v or .vhd - Top-level IP variation synthesis file

simulation - IP simulation files.sip - NativeLink simulation integration file

- Simulator setup scripts

- IP core variation files

.qip or .qsys - System or IP integration file

_generation.rpt - IP generation report


.ppf - XML I/O pin information file

.spd - Combines individual simulation startup scripts 1

.html - Contains memory map

.sopcinfo - Software tool-chain integration file

_syn.v or .vhd - Timing & resource estimation netlist 1

.debuginfo - Lists files for synthesis

.v, .vhd, .vo, .vho - HDL or IPFS models2

_tb - Testbench for supported simulators_tb.v or .vhd - Top-level HDL testbench file

Notes:1. If supported and enabled for your IP variation2. If functional simulation models are generated3. Ignore this directory

Note: To manually add an IP variation to a Quartus II project, click Project > Add/Remove Files inProject and add only the IP variation .qip or .qsys file, but not both, to the project. Do notmanually add the top-level HDL file to the project.

Scripting IP Core GenerationYou can alternatively use command-line utilities to define and generate an IP core variation outside of theQuartus II GUI.Use qsys-script to run a Tcl file that parameterizes an IP variation you define in ascript. Then, use qsys-generate to generate a .qsys file representing your parameterized IP variation.

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The qsys-generate command is the same as when generating using the Qsys GUI. For command-linehelp listing all options for these executables, type --help

To create a instance of a parameterizable Altera IP core at the command line, rather than using the GUI,follow these steps:

1. Run qsys-script to execute a Tcl script, similar to the example, that instantiates the IP and sets the IPparameters defined by the script:

qsys-script --script=.tcl

2. Run qsys-generate to generate the RTL for the IP variation:

qsys-generate .qsys

Note: Creating an IP generation script is an advanced feature that requires access to special IP coreparameters. For more information about creating an IP generation script, contact your Altera salesrepresentative.

Table 1-5: qsys-generate Command-Line Options

Option Usage Description

Required The name of the .qsys system file togenerate.

--synthesis= Optional Creates synthesis HDL files that Qsys usesto compile the system in a Quartus IIproject. You must specify the preferredgeneration language for the top-level RTLfile for the generated Qsys system.

--block-symbol-file Optional Creates a Block Symbol File (.bsf) for theQsys system.

--simulation= Optional Creates a simulation model for the Qsyssystem. The simulation model containsgenerated HDL files for the simulator, andmay include simulation-only features. Youmust specify the preferred simulationlanguage.

--testbench= Optional Creates a testbench system that instantiatesthe original system, adding bus functionalmodels (BFMs) to drive the top-levelinterfaces. When you generate the system,the BFMs interact with the system in thesimulator.

--testbench-simulation= Optional After you create the testbench system, youcan create a simulation model for thetestbench system.

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Option Usage Description

--search-path= Optional If you omit this command, Qsys uses astandard default path. If you provide thiscommand, Qsys searches a comma-separated list of paths. To include thestandard path in your replacement, use "$",for example, "/extra/dir,$".

--jvm-max-heap-size= Optional The maximum memory size that Qsys usesfor allocations when running qsys-generate. You specify the value as , where unit is m (or M) formultiples of megabytes or g (or G) formultiples of gigabytes. The default value is512m.

--family= Optional Specifies the device family.

--part= Optional Specifies the device part number. If set, thisoption overrides the --family option.

--allow-mixed-language-simulation Optional Enables a mixed language simulationmodel generation. If true, if a preferredsimulation language is set, Qsys uses afileset of the component for thesimulation model generation. When false,which is the default, Qsys uses thelanguage specified with --file-set= for all components forsimulation model generation. The currentversion of the ModelSim-Altera simulatorsupports mixed language simulation.

Modifying an IP VariationYou can easily modify the parameters of any Altera IP core variation in the parameter editor to matchyour design requirements. Use any of the following methods to modify an IP variation in the parametereditor.

Table 1-6: Modifying an IP Variation

Menu Command Action

File > Open Select the top-level HDL (.v, or .vhd) IP variation file tolaunch the parameter editor and modify the IP variation.Regenerate the IP variation to implement your changes.

View > Utility Windows > ProjectNavigator > IP Components

Double-click the IP variation to launch the parametereditor and modify the IP variation. Regenerate the IPvariation to implement your changes.

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Menu Command Action

Project > Upgrade IP Components Select the IP variation and click Upgrade in Editor tolaunch the parameter editor and modify the IP variation.Regenerate the IP variation to implement your changes.

Upgrading IP CoresIP core variants generated with a previous version of the Quartus II software may require upgradingbefore use in the current version of the Quartus II software. Click Project > Upgrade IP Components toidentify and upgrade outdated IP core variants.

Icons in the Upgrade IP Components dialog box indicate when IP upgrade is required, optional, orunsupported for IP cores in your design. This dialog box may open automatically when you open aproject containing upgradeable IP variations. You must upgrade IP cores that require upgrade before youcan compile the IP variation in the current version of the Quartus II software.

The upgrade process preserves the original IP variation file in the project directory as _BAK.qsys for IP targeting Arria 10 and later devices, and as _BAK.v, .sv, or .vhd for legacy IPtargeting 28nm devices and greater.

Note: Upgrading IP cores for Arria 10 and later devices may append a unique identifier to the original IPcore entity name(s), without similarly modifying the IP instance name. There is no requirement toupdate these entity references in any supporting Quartus II file; such as the Quartus II Settings File(.qsf), Synopsys Design Constraints File (.sdc), or SignalTap File (.stp), if these files contain instancenames. The Quartus II software reads only the instance name and ignores the entity name in pathsthat specify both names. Use only instance names in assignments.

Table 1-7: IP Core Upgrade Status

IP Core Status Description

IP Upgraded

Your IP variation uses the lastest version of the IP core.

IP Upgrade Optional

Upgrade is optional for this IP variation in the current version of the QuartusII software. You can upgrade this IP variation to take advantage of the latestdevelopment of this IP core. Alternatively you can retain previous IP corecharacteristics by declining to upgrade. Refer to the Description for detailsabout IP core version differences. If you do not upgrade the IP, the IP variationsynthesis and simulation files are unchanged and you cannot modifyparameters until upgrading.

IP Upgrade MismatchWarning

Warning of non-critical IP core differences in migrating IP to another devicefamily.

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IP Core Status Description

IP Upgrade Required

You must upgrade the IP variation before compiling in the current version ofthe Quartus II software. Refer to the Description for details about IP coreversion differences.

IP Upgrade Unspported

Upgrade of the IP variation is not supported in the current version of theQuartus II software due to incompatibility with the current version of theQuartus II software. You are prompted to replace the unsupported IP corewith a supported equivalent IP core from the IP Catalog. Refer to the Descrip‐tion for details about IP core version differences and links to Release Notes.

IP End of Life

Altera designates the IP core as end-of-life status. You may or may not be ableto edit the IP core in the parameter editor. Support for this IP corediscontinues in future releases of the Quartus II software.

Encrypted IP Core

The IP variation is encrypted.

Follow these steps to upgrade IP cores:

1. In the latest version of the Quartus II software, open the Quartus II project containing an outdated IPcore variation. The Upgrade IP Components dialog automatically displays the status of IP cores inyour project, along with instructions for upgrading each core. Click Project > Upgrade IPComponents to access this dialog box manually.

2. To upgrade one or more IP cores that support automatic upgrade, ensure that the Auto Upgradeoption is turned on for the IP core(s), and then click Perform Automatic Upgrade. The Status andVersion columns update when upgrade is complete. Example designs provided with any Altera IP coreregenerate automatically whenever you upgrade an IP core.

3. To manually upgrade an individual IP core, select the IP core and then click Upgrade in Editor (orsimply double-click the IP core name. The parameter editor opens, allowing you to adjust parametersand regenerate the latest version of the IP core.

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Figure 1-19: Upgrading IP Cores

Runs “Auto Upgrade” on all supported outdated coresOpens editor for manual IP upgrade

“Auto Upgrade”supported

Upgrade required

Upgradeoptional

Upgrade details

“Auto Upgrade”successful

Note: IP cores older than Quartus II software version 12.0 do not support upgrade. Altera verifies thatthe current version of the Quartus II software compiles the previous version of each IP core.The Altera IP Release Notes reports any verification exceptions for Altera IP cores. Altera doesnot verify compilation for IP cores older than the previous two releases.

Related InformationAltera IP Release Notes

Migrating IP Cores to a Different DeviceIP migration allows you to target the latest device families with IP originally generated for a differentdevice. Some Altera IP cores migrate automatically, some IP cores require manual IP regeneration, andsome do not support device migration and must be replaced in your design.The text and icons in the Upgrade IP Components dialog box identifies the migration support for eachIP core in the design.

Note: Migration of some IP cores requires installed support for the original and migration devicefamilies. For example, migration from a Stratix V device to an Arria 10 device requires installationof Stratix V and Arria 10 device families with the Quartus II software.

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Figure 1-20: Upgrading IP Cores

Double-click to upgrade in editor(no auto upgrade)

Upgrade required

Migration details

Supports Auto upgrade

Upgrade success

1. Click File > Open Project and open the Quartus II project containing IP for migration to anotherdevice in the original version of the Quartus II software.

2. To specify a different target device for migration, click Assignments > Device and select the targetdevice family.

3. To display IP cores requiring migration, click Project > Upgrade IP Components. The Descriptionfield prompts you to run auto update or double-click IP cores for migration.

4. To migrate one or more IP cores that support automatic upgrade, ensure that the Auto Upgradeoption is turned on for the IP core(s), and then click Perform Automatic Upgrade. The Status andVersion columns update when upgrade is complete.

5. To migrate an IP core that does not support automatic upgrade, double-click the IP core name, andthen click OK. The parameter editor appears.a. If the parameter editor specifies a Currently selected device family, turn off Match project/

default, and then select the new target device family.b. Click Finish to migrate the IP variation using best-effort mapping to new parameters and settings.

A new parameter editor opens displaying best-effort mapped parameters.c. Click Generate HDL, and then confirm the Synthesis and Simulation file options. Verilog HDL is

the defauilt output file format specified. If your original IP core was generated for VHDL, selectVHDL to retain the original output format.

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6. To regenerate the new IP variation for the new target device, click Generate. When generation iscomplete, click Close.

7. Click Finish to complete migration of the IP core. Click OK if you are prompted to overwrite IP corefiles. The Device Family column displays the new target device name when migration is complete. Themigration process replaces .qip with the .qsys top-level IP file in your project.

Note: If migration does not replace .qip with .qsys, click Project > Add/RemoveFiles in Project to replace the file in your project.

8. Review the latest parameters in the parameter editor or generated HDL for correctness. IP migrationmay change ports, parameters, or functionality of the IP core. During migration, the IP core's HDLgenerates into a library that is different from the original output location of the IP core. Update anyassignments that reference outdated locations. If your upgraded IP core is represented by a symbol in asupporting Block Design File schematic, replace the symbol with the newly generated .bsfafter migration.

Note: The migration process may change the IP variation interface, parameters, and functionality.This may require you to change your design or to re-parameterize your variant after theUpgrade IP Components dialog box indicates that migration is complete. The Descriptionfield identifies IP cores that require design or parameter changes.

Related InformationAltera IP Release Notes

Simulating Altera IP Cores in other EDA ToolsThe Quartus II software supports RTL and gate-level design simulation of Altera IP cores in supportedEDA simulators. Simulation involves setting up your simulator working environment, compilingsimulation model libraries, and running your simulation.

You can use the functional simulation model and the testbench or example design generated with your IPcore for simulation. The functional simulation model and testbench files are generated in a projectsubdirectory. This directory may also include scripts to compile and run the testbench. For a complete listof models or libraries required to simulate your IP core, refer to the scripts generated with the testbench.You can use the Quartus II NativeLink feature to automatically generate simulation files and scripts.NativeLink launches your preferred simulator from within the Quartus II software.

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Figure 1-21: Simulation in Quartus II Design Flow

Post-fit timing simulation netlist

Post-fit timing simulation (3)

Post-fit functional simulation netlist

Post-fit functional simulation

Analysis & Synthesis

Fitter(place-and-route)

TimeQuest Timing Analyzer

Device Programmer

Quartus II Design Flow Gate-Level Simulation

Post-synthesis functional

simulation

Post-synthesis functional simulation netlist

(Optional) Post-fit timing simulation

RTL Simulation

Design Entry(HDL, Qsys, DSP Builder)

Altera Simulation Models

EDA Netlist Writer

Note: Post-fit timing simulation is supported only for Stratix IV and Cyclone IV devices in the currentversion of the Quartus II software. Altera IP supports a variety of simulation models, includingsimulation-specific IP functional simulation models and encrypted RTL models, and plain textRTL models. These are all cycle-accurate models. The models support fast functional simulation ofyour IP core instance using industry-standard VHDL or Verilog HDL simulators. For some cores,only the plain text RTL model is generated, and you can simulate that model. Use the simulationmodels only for simulation and not for synthesis or any other purposes. Using these models forsynthesis creates a nonfunctional design.

Related InformationSimulating Altera Designs

Generating Simulation ScriptsYou can automatically generate simulation scripts to set up supported simulators. These scripts compilethe required device libraries and system design files in the correct order, and then elaborate or load thetop-level design for simulation. You can also use scripts to modify the top-level simulation environment,independent of IP simulation files that are replaced during regeneration. You can modify the scripts to setup supported simulators.

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Use the NativeLink feature to generate simulation scripts to automate simulation steps. You can reusethese generated files and simulation scripts in a custom simulation flow. NativeLink optionally generatesscripts for your simulator in the project subdirectory.

1. Click Assignments > Settings.2. Under EDA Tool Settings, click Simulation.3. Select the Tool name of your simulator.4. Click More NativeLink Settings.5. Turn on Generate third-party EDA tool command scripts without running the EDA tool.

Table 1-8: NativeLink Generated Scripts for RTL Simulation

Simulator(s) Simulation File Use

Mentor GraphicsModelSimQuestaSim

/simulation/modelsim/.do Source directly with your simulator.

Aldec Riviera Pro /simulation/modelsim/.do Source directly with your simulator.

Synopsys VCS /simulation/modelsim/_.vcs

Add your testbench file name to this options fileto pass the file to VCS using the -file option.If you specify a testbench file to NativeLink,NativeLink generates an .sh script that runsVCS.

SynopsysVCS MX

/simulation/scsim/_vcsmx__.tcl

Run this script at the command line using thecommand:quartus_sh -t

Any testbench you specify with NativeLink isincluded in this script.

Cadence Incisive(NC SIM)

/simulation/ncsim/_ncsim__.tcl

Run this script at the command line using thecommand:quartus_sh -t .

Any testbench you specify with NativeLink isincluded in this script.

You can use the following script variables:

• TOP_LEVEL_NAME—The top-level entity of your simulation is often a testbench that instantiates yourdesign, and then your design instantiates IP cores and/or Qsys systems. Set the value ofTOP_LEVEL_NAME to the top-level entity.

• QSYS_SIMDIR—Specifies the top-level directory containing the simulation files.• Other variables control the compilation, elaboration, and simulation process.

Generating Custom Simulation Scripts with ip-make-simscriptUse the ip-make-simscript utility to generate simulation command scripts for multiple IP cores or Qsyssystems. Specify all Simulation Package Descriptor files (.spd), each of which lists the required simulationfiles for the corresponding IP core or Qsys system. The IP parameter editor generates the .spd files.

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ip-make-simscript compiles IP simulation models into various simulation libraries. Use the compile-to-work option to compile all simulation files into a single work library. Use this option only if yourequire a simplified library structure.

When you specify multiple .spd files, the ip-make-simscript utility generates a single simulation scriptcontaining all required simulation information. The default value of TOP_LEVEL_NAME is theTOP_LEVEL_NAME defined in the IP core or Qsys .spd file.

Set appropriate variables in the script, or edit the variable assignment directly in the script. If thesimulation script is a Tcl file that is sourced in the simulator, set the variables before sourcing the script. Ifthe simulation script is a shell script, pass in the variables as command-line arguments to the shell script.

• Type ip-make-simscript at the command prompt to run.• Type ip-make-simscript --help for help on command options and syntax.

Table 1-9: ip-make-simscript Examples

Option Description Status

--spd= Describes the list of compiled filesand memory model hierarchy. Ifyour design includes multiple IPcores or Qsys systems thatinclude .spd files, use this option foreach file. You can specifymultiple .spd files as a comma-separated list. For example:

ip-make-simscript --

spd=,ip1.spd, ip2.spd,

Required

--output-directory= Specifies the location of output files.If unspecified, the default setting isthe directory from which ip-make-simscript is run.

Optional

--compile-to-work Compiles all design files to thedefault work library. Use this optiononly if you encounter problemsmanaging your simulation withmultiple libraries.

Optional

--use-relative-paths Uses relative paths wheneverpossible.

Optional

Synthesizing Altera IP Cores in Other EDA ToolsYou can use supported EDA tools to synthesize a design that includes Altera IP cores. When you generatethe IP core synthesis files for use with third-party EDA synthesis tools, you can optionally create an areaand timing estimation netlist. To enable generation, turn on Create timing and resource estimates forthird-party EDA synthesis tools when customizing your IP variation.

The area and timing estimation netlist describes the IP core connectivity and architecture, but does notinclude details about the true functionality. This information enables certain third-party synthesis tools tobetter report area and timing estimates. In addition, synthesis tools can use the timing information toachieve timing-driven optimizations and improve the quality of results.

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The Quartus II software generates the _syn.v netlist file in Verilog HDL format regardless ofthe output file format you specify. If you use this netlist for synthesis, you must include the IP corewrapper file .v or .vhd in your Quartus II project.

Related InformationQuartus II Integrated Synthesis

Instantiating IP Cores in HDLYou can instantiate an IP core directly in your HDL code by calling the IP core name and declaring itsparameters, in the same manner as any other module, component, or subdesign. When instantiating an IPcore in VHDL, you must include the associated libraries.

Example Top-Level Verilog HDL ModuleVerilog HDL ALTFP_MULT in Top-Level Module with One Input Connected to Multiplexer.

module MF_top (a, b, sel, datab, clock, result); input [31:0] a, b, datab; input clock, sel; output [31:0] result; wire [31:0] wire_dataa; assign wire_dataa = (sel)? a : b; altfp_mult inst1 (.dataa(wire_dataa), .datab(datab), .clock(clock), .result(result)); defparam inst1.pipeline = 11, inst1.width_exp = 8, inst1.width_man = 23, inst1.exception_handling = "no"; endmodule

Example Top-Level VHDL ModuleVHDL ALTFP_MULT in Top-Level Module with One Input Connected to Multiplexer.

library ieee;use ieee.std_logic_1164.all; library altera_mf;use altera_mf.altera_mf_components.all;

entity MF_top is port (clock, sel : in std_logic; a, b, datab : in std_logic_vector(31 downto 0); result : out std_logic_vector(31 downto 0));end entity;

architecture arch_MF_top of MF_top issignal wire_dataa : std_logic_vector(31 downto 0);begin

wire_dataa 11, width_exp => 8, width_man => 23, exception_handling => "no") port map (

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dataa => wire_dataa, datab => datab, clock => clock, result => result); end arch_MF_top;

Integrating Other EDA ToolsYou can integrate supported EDA design entry, synthesis, simulation, physical synthesis, and formalverification tools into the Quartus II design flow. The Quartus II software supports netlist files from otherEDA design entry and synthesis tools. The Quartus II software optionally generates various files for use inother EDA tools.

The Quartus II software manages EDA tool files and provides the following integration capabilities:

• Automatically generate files for synthesis and simulation and automatically launch other EDA tools(Assignments > Settings > EDA Tool Settings > NativeLink Settings ).

• Compile all RTL and gate-level simulation model libraries for your device, simulator, and designlanguage automatically (Tools > Launch Simulation Library Compiler).

• Include files (.edf, .vqm) generated by other EDA design entry or synthesis tools in your project assynthesized design files (Project > Add/Remove File from Project) .

• Automatically generate optional filesfor board-level verification (Assignments > Settings > EDA ToolSettings).

Figure 1-22: EDA Tool Settings

Related InformationMentor Graphics Precision Synthesis SupportGraphics on page 18-1

Simulating Altera Designs

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Managing Team-based ProjectsThe Quartus II software supports multiple designers, design iterations, and platforms. You can use thefollowing techniques to preserve and track project changes in a team-based environment. Thesetechniques may also be helpful for individual designers.

Related Information

• Preserving Compilation Results on page 1-36• Archiving Projects on page 1-38• Using External Revision Control on page 1-39• Migrating Projects Across Operating Systems on page 1-40

Preserving Compilation ResultsThe Quartus II software maintains a database of compilation results for each project revision. Thedatabases files store results of incremental or full compilation. Do not edit these files directly. However,you can use the database files in the following ways:

• Preserve compilation results for migration to a new version of the Quartus II software. Export a post-synthesis or post-fit, version-compatible database (Project > Export Database), and then import itinto a newer version of the Quartus II software (Project > Import Database), or into another project.

• Optimize and lock down the compilation results for individual blocks. Export the post-synthesis orpost-fit netlist as a Quartus II Exported Partition File (.qxp) (Project > Export Design Partition). Youcan then import the partition as a new project design file.

• Purge the content of the project database (Project > Clean Project) to remove unwanted previouscompilation results at any time.

Factors Affecting Compilation ResultsChanges to any of the following factors can impact compilation results:

• Project Files—project settings (. qsf), design files, and timing constraints (.sdc).• Hardware—CPU architecture, not including hard disk or memory size differences. Windows XP x32

results are not identical to Windows XP x64 results. Linux x86 results is not identical to Linux x86_64.• Quartus II Software Version—including build number and installed patches. Click Help > About to

obtain this information.• Operating System—Windows or Linux operating system, excluding version updates. For example,

Windows XP, Windows Vista, and Windows 7 results are identical. Similarly, Linux RHEL, CentOS 4,and CentOS 5 results are identical.

Related Information

• Quartus II Incremental Compilation for Hierarchical and Team-Based Design on page 3-1• Design Planning for Partial Reconfiguration on page 4-1The Partial Reconfiguration (PR) feature in the Quartus II software allows you to reconfigure a portion ofthe FPGA dynamically, while the remainder of the device continues to operate. The Quartus II softwaresupports the PR feature for the Altera® Stratix® V device family.

Migrating Results Across Quartus II Software VersionsView basic information about your project in the Project Navigator, Report panel, and Messages window.

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To preserve compilation results for migration to a later version of the Quartus II software, export aversion-compatible database file, and then import it into the later version of the Quartus II software. Afew device families do not support version-compatible database generation, as indicated by projectmessages.

Exporting and Importing the Results DatabaseTo save the compilation results in a version-compatible format for migration to a later version of theQuartus II software, follow these steps:

1. Open the project for migration in the original version of the Quartus II software.2. Generate the project database and netlist with one of the following:

• Click Processing > Start > Start Analysis & Synthesis to generate a post-synthesis netlist.• Click Processing > Start Compilation to generate a post-fit netlist.

3. Click Project > Export Database and specify the Export directory.4. In a later version of the Quartus II software, click New Project Wizard and create a new project with

the same top-level design entity name as the migrated project.5. Click Project > Import Database and select the /export_db/exported database

directory. The Quartus II software opens the compiled project and displays compilation results.Note: You can turn on Assignments > Settings > Compilation Process Settings > Export version-

compatible database if you want to always export the database following compilation.Figure 1-23: Quartus II Version-Compatible Database Structure

Cleaning the Project DatabaseTo clean the project database and remove all prior compilation results, follow these steps:

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1. Click Project > Clean Project.2. Select All revisions to remove the databases for all revisions of the current project, or specify a

Revision name to remove only that revision’s database.3. Click OK. A message indicates when the database is clean.

Archiving ProjectsYou can save the elements of a project in a single, compressed Quartus II Archive File (. qar) by clickingProject > Archive Project.

The .qar captures logic design, project, and settings files required to restore the project.

Use this technique to share projects between designers, or to transfer your project to a new version of theQuartus II software, or to Altera support. You can optionally add compilation results, Qsys system files,and third-party EDA tool files to the archive. If you restore the archive in a different version of theQuartus II software, you must include the original .qdf in the archive to preserve original compilationresults.

Manually Adding Files To ArchivesTo manually add files to an archive:

1. Click Project > Archive Project and specify the archive file name.2. Click Advanced.3. Select the File set for archive or select Custom. Turn on File subsets for archive.4. Click Add and select Qsys system or EDA tool files. Click OK.5. Click Archive.

Archiving Compilation ResultsYou can include compilation results in a project archive to avoid recompilation and preserve originalresults in the restored project. To archive compilation results, export the post-synthesis or post-fit versioncompatible database and include this file in the archive.

1. Export the project database.2. Click Project > Archive Project and specify the archive file name.3. Click Advanced.4. Under File subsets, turn on Version-compatible database files and click OK.5. Click Archive.To restore an archive containing a version-compatible database, follow these steps:

1. Click Project > Restore Archived Project.2. Select the archive name and destination folder and click OK.3. After restoring the archived project, click Project > Import Database and import the version-

compatible database.

Related InformationExporting and Importing the Results Database on page 1-37

Archiving Projects for Altera Service RequestsWhen archiving projects for an Altera service request, include all of the following file types for properdebugging by Altera Support:

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To quickly identify and include appropriate archive files for an Altera service request:

1. Click Project > Archive Project and specify the archive file name.2. Click Advanced.3. In File set, select Service Request to include files for Altera Support.

• Project source and setting files (.v, .vhd, .vqm, .qsf, .sdc, .qip, .qpf, .cmp, .sip)• Automatically detected source files (various)• Programming output files (. jdi, .sof, .pof)• Report files (.rpt, .pin, .summary, .smsg)• Qsys system and IP files (.qsys, . qip)

4. Click OK, and then click Archive.Figure 1-24: Archiving Project for Service Request

Using External Revision ControlYour project may involve different team members with distributed responsibilities, such as sub-moduledesign, device and system integration, simulation, and timing closure. In such cases, it may be useful totrack and protect file revisions in an external revision control system.

While Quartus II project revisions preserve various project setting and constraint combinations, externalrevision control systems can also track and merge RTL source code, simulation testbenches, and buildscripts. External revision control supports design file version experimentation through branching andmerging different versions of source code from multiple designers. Refer to your external revision controldocumentation for setup information.

Files to Include In External Revision ControlInclude the following Quartus project file types in external revision control systems:

• Logic design files (.v, .vdh, .bdf, edf, .vqm)• Timing constraint files (.sdc)• Quartus project settings and constraints (.qdf, .qpf, .qsf)• IP files (.v, .sv, .vhd, .qip, .sip, .qsys)• Qsys-generated files (.qsys, .qip, .sip)• EDA tool files (.vo, .vho )

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You can generate or modify these files manually if you use a scripted design flow. If you use an externalsource code control system, you can check-in project files anytime you modify assignments and settingsin the Quartus software.

Migrating Projects Across Operating SystemsConsider the following cross-platform issues when moving your project from one operating system toanother (for example, from Windows to Linux).

Migrating Design Files and LibrariesConsider the following file naming differences when migrating projects across operating systems:

• Use appropriate case for your platform in file path references.• Use a character set common to both platforms.• Do not change the forward-slash (/) and back-slash (\) path separators in the .qsf. The Quartus II

software automatically changes all back-slash (\) path separators to forward-slashes (/ )in the .qsf.• Observe the target platform’s file name length limit.• Use underscore instead of spaces in file and directory names.• Change library absolute path references to relative paths in the .qsf.• Ensure that any external project library exists in the new platform’s file system.• Specify file and directory paths as relative to the project directory. For example, for a project titled

foo_design , specify the source files as: top.v, foo_folder /foo1.v, foo_folder /foo2.v, and foo_folder/bar_folder/bar1.vhdl.

• Ensure that all the subdirectories are in the same hierarchical str

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