Quantum encryption system - receiver.1 D0525 Project Receiver for Quantum Encryption System By:...
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Quantum encryption system - receiver. 1
D0525 ProjectD0525 ProjectReceiver for Quantum Encryption Receiver for Quantum Encryption
SystemSystem
By: Dattner Yony & Sulkin Alex
Supervisor: Yossi Hipsh& Eli Shohan
High Speed Digital Systems Laboratory
Winter 2007
Summary Presentation Part A
Quantum encryption system - receiver. 2
Reminder : The overall system.Reminder : The overall system.
► The system is a communication system, like many others – but what makes this particular system “unique” that would require that much attention in the form of three whole separate projects (transmitter, synchronization and receiver team )?
► The answer is security.
► Quantum encryption using the BB84 protocol has been mathematically proven to be 100% secure in an ideal world without noise. This is mainly due to the uncertainty principle regarding photons.
► Generally speaking the purpose of this electro-optical communication array is to successfully encrypt a single photon, to transmit it via a secure channel to the receiver which is responsible for successful decryption of the photon and to keep track of the photons received.
Quantum encryption system - receiver. 3
Reminder : The overall Reminder : The overall system.system.
► The communication system is dived into three main sub-systems:
► The transmitter - is responsible for the encryption of the photon and its transmission into the fiber optic data line.
► The synchronization unit – serves as a link between the transmitter and the receiver, simply speaking its role is to let the receiver know when he should be expecting a photon that was transmitted.
► The receiver – is responsible for receiving the signal from the sync unit and
use it in order to receive the photon from the data channel (also known as quant channel).
Transmitter unit (encrypt)
Synchronization unit
Receiver unit (decrypt and count)
Sync optical lineData optical
line
Quantum encryption system - receiver. 4
► A more detailed view of the overall system can obtained through the following schematic:A more detailed view of the overall system can obtained through the following schematic:
Reminder : The overall Reminder : The overall system.system.
AMP1_ZPUL30P
INJ1.1
OUT
24+
24-
Hand
le
FAN1
24+
24-
FAN2
24+ 24-
Power Switch
In+In-
Out+Out-
USB
Out
Fuse
In-Out-In+Out+
U77Cable
Out-Out+
Gnd
On
Off
U68 Reciever Cards 1&2
J1.2
J2.2
V+12
Gnd
cntrl_1.1cntrl_1.2
To_counter_1To_sync_1To_counter_2To_sync_2
cntrl_1.5cntrl_1.4cntrl_1.3
cntrl_1.6
TP_1.3
TP_2.2
TP_2.3TP_1.2
J1.1
J2.1
V-12
F rom_Sync1+From_Sync1-
From_Sync2+From_Sync2-
cntrl_2.1cntrl_2.2cntrl_2.3cntrl_2.4cntrl_2.5
TP_1.1TP_2.1TP_1.4TP_2.4
Power Supply 1
IN 220+
In 220-
Out 12+
Out 12-
From_Sync1+
Power Supply 2
IN 220+
In 220-
Out 24+
Out 24-
To_Geiger2
From_Sync1-From_Geiger1
From_Geiger2
TP_1.1To_sync_1 To_Counter_1
To_sync_2 To_counter_2 From_Sync2-From_Sync2+
TP_1.3 TP_1.2
TP_2.3
TP_1.4
TP_2.2 TP_2.1
Channel 1
AMP1_ZPUL30P
OUTJ1.2
24+
24-
IN
Channel 2
AMP1_ZPUL30P
INJ2.1
OUT
24+
24-
FPGA
Delay data1DDL1_shift_enDDL1_fast1_enDDL1_fast2_enSync_cntrl1
InCard_en
Delay data2DDL2_shift_enDDL2_fast1_enDDL2_fast2_enSync_cntrl2
AMP1_ZPUL30P
IN OUTJ2.2
24+
24-
Side Panel Back PanelSide Panel
Front Panel
Inside
TP_2.4
To_Geiger1
Reminder : The overall system - interface.Reminder : The overall system - interface.
Quantum encryption system - receiver. 6
► Let us briefly recall the various modes of operation of the system:
► STAB – in this mode we calibrate the interferometers that precede the Geigers , this process is not directly related to the receiver. During this stabilization high energy photons are sent to the receiver. In order not to damage the Geiger, we block it.
► SYNC – before we are ready to receive the data photons we must synchronize the system, details to follow.
► QUANT – this is the normal operation of the system where the transmitter transmits data photons and we receive them (available only after STAB and SYNC have been completed).
Reminder : Modes of operationReminder : Modes of operation
Quantum encryption system - receiver. 7
1) It is able to detect 1) It is able to detect singlesingle photons. photons.2) It converts the optical data to electrical.2) It converts the optical data to electrical.
The Geiger is actually a very unstable photo diode that The Geiger is actually a very unstable photo diode that avalanches with the impact of a single photon. Principal of avalanches with the impact of a single photon. Principal of operation:operation:
Reminder : The Geiger.Reminder : The Geiger.
►The Geiger is an electro-optical device that enables us to detect the incoming The Geiger is an electro-optical device that enables us to detect the incoming photons, it has two purposesphotons, it has two purposes::
Quantum encryption system - receiver. 8
► The output of the Geiger when The output of the Geiger when
there is there is nono photon impacting: photon impacting:
Reminder : Geiger – continued.Reminder : Geiger – continued.
► The output of the Geiger when The output of the Geiger when
there is a photon impacting:there is a photon impacting:
► The Geiger is opened when we provide it with an additional reverse voltage of The Geiger is opened when we provide it with an additional reverse voltage of 10V that comes from the sync unit (this pulse is 3ns wide).10V that comes from the sync unit (this pulse is 3ns wide).
Quantum encryption system - receiver. 9
The receiver.The receiver.
Quantum encryption system - receiver. 10
The receiver - continued.The receiver - continued.
inputs sync_1 sync_2 Start_en quant_en Sync_cntrl1_req
Sync_cntrl2_req
outputs
to_count1 to_count2
to_sync1 to_sync2 Tp1_4 Tp2_4
► The inputs and the outputs of the receiver are:
Quantum encryption system - receiver. 11
PCB – block diagram.PCB – block diagram.
Quantum encryption system - receiver. 12
► The synchronization process is divided into two parts:
1. The sync unit performs rough synchronization with their DDLs – shifting their sync pulse until a detection of the data photon occurs .
2. The receiver unit performs delicate synchronization with their DDLs – shifting their pulse until it coincides with the desired area inside the sync pulse (close to the left shoulder)
After the both parts of this process are completed than we are ready to receive the photon – and to switch to the QUANT mode.
We present two flow charts that explain the both parts of the SYNC mode in more detail:
SYNC mode.SYNC mode.
Quantum encryption system - receiver. 13
► The QUANT and STAB modes are periodically intertwined , after every QUANT photon that is The QUANT and STAB modes are periodically intertwined , after every QUANT photon that is transmitted we block the receiver ( and the Geiger) than transmit ten STAB photons that stabilize transmitted we block the receiver ( and the Geiger) than transmit ten STAB photons that stabilize the interferometers.the interferometers.
QUANT + STAB QUANT + STAB modes.modes.
The STAB photons are more energetic then the QUANT photons – may damage the Geiger if not blocked.
Quantum encryption system - receiver. 14
The components.The components.Part # Part name Part type Serial # Vendor Quantity
1 MUX 2:1 ECL NBSG86A ON-SEMI 2
2 Buff 1:2 ECL MC100EP11 ON-SEMI 5
3 DDL ECL MC100EP195 ON-SEMI 4
4 AND gate ECL MC100LVEL05 ON-SEMI 1
5 Comparator ECL ADCMP572 ANALOG 2
6 DFF ECL MC100EP31 ON-SEMI 1
7 ECL-TTL N/A MC100EPT21 ON-SEMI 1
8 Buff 1:4 TTL NB3L553 ON-SEMI 1
9 DDL TTL 3D7408-0.25 3D 1
10 TTL-ECL N/A MC100EPT20 ON-SEMI 1
11 FPGA PCB connector
Flat cable 2x25 ##100285 NI (eBay) 2
12 HS PCB connector SMA PLUG PCB mount
SMA3401-0000 Jayebo 24
Quantum encryption system - receiver. 15
► The original plan was to use ECL only parts, but as you can see we needed a few TTL devices for two main reasons:
1) The counters at the computer receive TTL levels.
2) For the stretcher we need a relatively large range of delay (~30ns) – this can be achieved by DDL TTL.
The very first thing we need to verify is the voltage compatibility between our components:
The components - The components - continued.continued.
Quantum encryption system - receiver. 16
► Notes:
1) This device (MUX 2:1) comes with OLS (Output level selection) that allows us to control its V_ol in 5 steps – when connecting the OLS pin to V_cc we get the numbers in the table.
2) The comparator input is NOT ECL but it is an analog input that is restricted by the minimum and maximum voltages allowed in its input. So the minimum is -0.2V and the maximum 3.1V, given that V_cco=5.2V (output stage source).
3) Here we have a problem: the driver’s DC level is too high and its swing is too low. Fortunately, the receiver’s minimum differential input sensitivity is 150mV. All we need to do is to put an attenuator between the comparator and the Buff 1:2 to reduce the DC level. (From 2135mV to about 1880mV).
The components - The components - continued.continued.
Quantum encryption system - receiver. 17
► For TTL parts we will check the voltage level compatibility by assuring are positive.
► We build another table for the TTL parts:
The components - The components - continued.continued.
OH IH
L IL OL
V -V
NM V -VHNM
► Notes:
1) Although in this case – we don’t believe this will pose a big problem because :
a) The for 3d7408-1 is given when - in practice we have so should rise a little giving us larger .
b) Even if is still not positive but is good enough for our application.
0HNM
OHV 4.75CCV V 5CCV V OHV
HNM
HNM 0HNM V
Quantum encryption system - receiver. 18
► is the negative reference voltage.► is the positive reference voltage (in our case – the input).► are on-chip termination pins ( ).► are resistors that control the voltage level ( is a variable resistor).► is some reference voltage ( for example).► All the capacitors ( ) are standard cooling capacitors.
The components - The components - Comparator.Comparator.
nV
pV
tn tpV andV 50 to gnd
32, 33R R nV 33R
refV ttV
0.1 , 0.01 1and
Quantum encryption system - receiver. 19
► Note that in order to get a wider range of the input voltage we select but the output is standard differential PECL so .
► are standard receiver ECL termination resistors.
► is also a variable resistor used to determine the level of hysteresis we require ( this must be based on the study of Geigers output characteristics).
► The amount of hysteresis as a function of :
Comparator - continued.Comparator - continued.
2 5CCI CCV V V 3.3CCO CCV V V
30, 31R R
_ 2R hyst
_ 2R hyst
Quantum encryption system - receiver. 20
► The DDL cascade connection feature:The DDL cascade connection feature:
► The DDL-ECL (MC100EP195) has an option that allows us to connect several DDLs in a cascade configuration. In order to save FPGA control lines we choose this cascade configuration for our two serial DDLs.
The DDL (ECL).The DDL (ECL).
► Step: .► Delay range: .
10ps
20about ns
Quantum encryption system - receiver. 21
► The balun we use is a passive self-made circuit; we use it in order to feed AMP1. On each PCB we have two such baluns, one for the AMP1 and the other used as TP1:
The BALUN.The BALUN.
C 70 . 1 u
R 7
1 4 0 O h m
R 61 5 0 O h m
C 80 . 0 0 1 u
R 56 8 O h m
R 8
6 8 O h m
TOAMP1
C 90 . 1 u
J 1
S M A
1
2
C 1 00 . 0 0 1 u
From Buff 1:2 ECL
Quantum encryption system - receiver. 22
► According to the power dissipation of the parts we suggest the use of ON-Semi’s NCP1086 as a regulator both for the 5V and the 3.3V supplies.
Power.Power.
► The NCP1086 linear regulator provides 1.5 A at 3.3 V or adjustable
output voltage.We will also use it as a regulator for our voltage.
ttV
Quantum encryption system - receiver. 23
► First we extract the following timing data from the DFF’s datasheet:
► Since are measured with 50 ohm termination to Vtt – if we take into account the C_in of the next component – we will get larger .
► We have to make sure that D pin will be stable before clk rise and after clk rise.► Since we have a minimum value for we take care and take for our calculations.
The DFF timing constraints.The DFF timing constraints.
min
min
100
150
SETUP
HOLD
t ps
t ps
130
130
r typical
f typical
t ps
t ps
r ft and t
r ft and t
SETUPt HOLDt
SETUPt 150SETUPt ps
Quantum encryption system - receiver. 24
► The figure shows the relevant part of the logical schematic; you can see the DFF and three separate paths (red, blue and pink).
► Remember that the red one has to be stable before and after the blue and pink ones.► The width of the red pulse (coming from the Geiger – indicates the detection of the photon) is well
over , otherwise – the sampling is not possible.
► We just have to make sure that the pink and the blue rise arrive inside the “logical zone” of the red pulse:
The DFF timing constraints - The DFF timing constraints - continued.continued.
SETUPt minHOLDt
minSETUP HOLDt t
Quantum encryption system - receiver. 25
► We notice that for the pink path, there is no problem making it into the “logical zone” because there are two serial DDLs in the way .Both the fine delay resolution and the delay range allow us to make it to the “logic zone” (that is exactly the delicate stage of the synchronization process done by the receiver team).
► Now we have to check the blue path, when Mix_sel_1=HIGH. That happens when we are in the coarse synchronization stage (done by the sync team). That is when we are required to sample the output of the Geiger as it is, not with our second window (which is much narrower).
► It is clear that: Or:
► We can see that which guarantees the setup condition is fulfilled.
► This means that in order for the hold condition to be fulfilled, the Geiger’s output must have:
.► That is, if the width of the Geiger’s output is large enough then both setup and hold
condition will be fulfilled.
The DFF timing constraints - The DFF timing constraints - continued.continued.
( 1: 2) ( 1: 2) ( 2 :1)pd pdppd dd pt Buf tf t Bu tt ff MUX 220 385ppd dt ps t ps
16220 5 ( )385pd Sd TUPp Eps tt Ft D F
( ) ( ) ( ) ( )WIDTH SETUP HOLD rt geiger t DFF t DFF t geiger
The electrical diagram.The electrical diagram.
MC1 0 0 EP11
Q01
Q0 n o t2
Q13
Q1 n o t4
Ve e5
Dn o t6
D7
Vc c8
C3 .1 C3 .7C3 .3
R1 85 0
C3 .1 0
R1 95 0
C3 .2 C3 .8C3 .6 C3 .9C3 .4 C3 .11
Control 3
C3 .5
Vc c
V_ re f1 .1
Vtt
C10 .1 u C2
0 .0 0 1 u
D3
D7
D7
TP 1 .3 -
C9 6
1 0 u
C9 72 2 u
VCC(5 V)
REGUL ATOR2NCP1 0 8 6
Vin
Adj
Vo u t
BODY
R6 3
3 7 0
R6 2
1 2 4
D0
Vtt
R6 95 0
R6 85 0 From AMP2
D1
D7
R7 05 0
R7 15 0
Vtt
D5D1
MC100EP195MC10EP195
D81
D92
D1 03
IN4
INn o t5
Vb b6
Ve f7
Vc f8
NC1 7
Vc c1 8
Vc c1 9
Qn o t2 0
Q2 1
Vc c2 2
D02 3
Ve e2 4
ENno
t16
CASC
ADE
15CA
SCAD
Enot
14Vc
c13
SETM
AX12
SETM
IN11
LEN
10Ve
e9
D125
D226
D327
Vee
28D4
29D5
30D6
31D7
32
D6 D2
D1
D2
D9
D5
C2 6
0 .1 u
LEN
C2 5
0 .0 0 1 u
D4
ECL DDL module
D4
D5
TOTP1
D2
D10 (cascadeoption)
D4D0
R7 4
5 0
D6
Fro m_ s y n c +
Fro m_ s y n c -
D8
D3
R6 6
1 0 0 KR6 7
Rre f0
D6
D0
Control 1From FPGA
Control 3From FPGA
C9 81 0 u
VCC(1 .3 V)
REGUL ATOR3NCP1 0 8 6
Vin
Adj
Vo u tBO
DY
C9 92 2 u
Control 2From FPGA
R6 4
1 2 4
R6 5
5
V_ tra n s (1 2 V)
MC100EP195MC10EP195
D81
D92
D1 03
IN4
INn o t5
Vb b6
Ve f7
Vc f8
NC1 7
Vc c1 8
Vc c1 9
Qn o t2 0
Q2 1
Vc c2 2
D02 3
Ve e2 4
ENno
t16
CASC
ADE
15CA
SCAD
Enot
14Vc
c13
SETM
AX12
SETM
IN11
LEN
10Ve
e9
D125
D226
D327
Vee
28D4
29D5
30D6
31D7
32
J 4
CONNECTOR_ 5 0 PIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
C3 30 .1 u
C3 40 .0 0 1 u
VCC(7 V)
Vc c
MC1 0 0 EP11
Q01
Q0 n o t2
Q13
Q1 n o t4
Ve e5
Dn o t6
D7
Vc c8
Vc c
C5 80 .1 u
Vc c
R2 45 0
R2 55 0
C5 70 .0 0 1 u
R2 25 0
R2 35 0
Vc c
VEE(GND)
VCC(3 .3 V) Vc c
Vc c
D3
Vc c
LEN
C3 10 .1 u
C3 20 .0 0 1 u
Vc c 2
R7 8
5 0 0
Vtt
TOAMP1
REGUL ATOR1NCP1 0 8 6
Vin
Adj
Vo u t
BODY
Vtt
VTT=VCC-2V
LEN
MC100EP195MC10EP195
D81
D92
D1 03
IN4
INn o t5
Vb b6
Ve f7
Vc f8
NC1 7
Vc c1 8
Vc c1 9
Qn o t2 0
Q2 1
Vc c2 2
D02 3
Ve e2 4
ENno
t16
CASC
ADE
15CA
SCAD
Enot
14Vc
c13
SETM
AX12
SETM
IN11
LEN
10Ve
e9
D125
D226
D327
Vee
28D4
29D5
30D6
31D7
32
C3 60 .1 u
Vc c
C1 5
0 .1 u
C1 6
0 .0 0 1 u
C3 50 .0 0 1 u
C1 4
0 .0 0 1 u
Vc c
C1 3
0 .1 u
C1 .1C1 .2C1 .4 C1 .3C1 .5C1 .7 C1 .6C1 .8C1 .9
C3 .3
C5 90 .1 u
C1 7
0 .0 0 1 u
C1 8
0 .1 u
C6 00 .0 0 1 u
MC100EP195MC10EP195
D81
D92
D1 03
IN4
INn o t5
Vb b6
Ve f7
Vc f8
NC1 7
Vc c1 8
Vc c1 9
Qn o t2 0
Q2 1
Vc c2 2
D02 3
Ve e2 4
ENno
t16
CASC
ADE
15CA
SCAD
Enot
14Vc
c13
SETM
AX12
SETM
IN11
LEN
10Ve
e9
D125
D226
D327
Vee
28D4
29D5
30D6
31D7
32
VCC(7 V)
Vc c
C11
0 .1 uC1 2
0 .0 0 1 u
C2 70 .1 u C2 80 .0 0 1 u
R6 0
1 2 4
C5 2
0 .1 uC5 1
0 .0 0 1 u
VCC(5 V) Vc c 2
Vc cVc c
C5 60 .1 u
C5 5
0 .0 0 1 u
Vc c
Vc c
Vc c
R2 65 0
R2 75 0
C1 .1 0
R2 85 0
C1 .11
R2 95 0
C1 .1 2
Vtt
AND1
D01
D0 n o t2
D13
D1 n o t4
Vc c8
Q7
Qn o t6
Ve e5
C5 30 .1 u C5 40 .0 0 1 u
C2 90 .1 u
C3 0
0 .0 0 1 u
C3 .1C3 .5 C3 .2C3 .1 0 C3 .4C3 .6C3 .8 C3 .7C3 .9
R6 1
2 0 0
Vc c
C4 70 .1 u
MC1 0 0 EP11
Q01
Q0 n o t2
Q13
Q1 n o t4
Ve e5
Dn o t6
D7
Vc c8
C4 80 .0 0 1 u
Ca rd _ e nCa rd _ e n _ n o tC3 .11
C2 .2 C2 .1C2 .1 0 C2 .5C2 .6C2 .8 C2 .4C2 .7C2 .9
J 3SMA
1
2
R5 61 K
D9
D8
C2 .11C2 .1 0
R5 98 .1 3 3 K
R5 7 1 K
J 2
SMA
1
2
R61 5 0 Oh m
R5 8
6 .6 7 K
C1 0 0 .0 0 1 u
C90 .1 u
J 1
SMA
1
2
R56 8 Oh m R8
6 8 Oh m
C70 .1 u
R7
1 4 0 Oh m
C80 .0 0 1 u
R1 2
5 0
C9 4
1 0 u
Vtt
C1 0 0
1 u
Vc c
Vtt
C1 0 10 .0 1 u
NBSG8 6 A
OL S1
SEL _ n o t2
SEL3
VT SEL4
VTD1
5D1
6D1
_not
7VT
D1_n
ot8
Ve e1 2
Q_ n o t11
Q1 0
Vc c0 9
VTD0
16D0
15D0
_not
14VT
D0_n
ot13
C2 .3
Vtt
C1 .1 2C1 .3C1 .4 C1 .6 C1 .11C1 .2 C1 .9
Vc c
C1 .1 C1 .5 C1 .7
C1 9
0 .1 u
R1 35 0
C4 50 .0 1 u
C1 .1 0
Vtt
C1 .8
R1 65 0
R1 0
Rre f1Vc c
C2 0
0 .0 0 1 u
R16 8 Oh m
R21 5 0 Oh m
R3
1 4 0 Oh m
R4
6 8 Oh m
C4 20 .0 1 u
C4 90 .1 u
C40 .0 0 1 u
C30 .1 u
C50 .1 u
C6 0 .0 0 1 u
C2 3
0 .1 u
MC1 0 0 EP11
Q01
Q0 n o t2
Q13
Q1 n o t4
Ve e5
Dn o t6
D7
Vc c8
C3 81 u
Vc c 2
R1 75 0
C2 4
0 .0 0 1 u
C5 00 .0 0 1 u
C4 61 u
Vtt
C3 70 .0 1 u
R9
R1 4
5 0
Vc c
Vtt
C4 31 uVtp
1
Vp2
Vn3
Vtn4
Vcci
5LE
_not
6LE
7Vc
co/Vtt
8
Vc c o1 2
Q11
Q_ n o t1 0
Vc c o9
Vcci
16GN
D15
HYS
14GN
D13
R1 55 0
C4 4
0 .0 1 u
Vc c 2
C4 11 u
Vtt
R2 15 0
R2 05 0
Vc c
C2 .11
C9 52 2 u
Vc c
Vtt
Vc c
Vc c
Control 1
TP 1 .3 +
VCC(3 .3 V)
C2 .4 C2 .8C2 .5C2 .1
D8
C2 .6 C2 .9C2 .3C2 .2 C2 .7
Control 2
VCC(1 .3 V)
R11
R_hyst 1
C2 1
0 .1 u
C2 2
0 .0 0 1 u
NBSG 86A
O LS1
SEL_not2
SEL3
VTSEL4
VTD1
5D1
6D1_
not7
VTD1_n
ot8
Vee12
Q _not11
Q10
Vcc09
VTD0
16D0
15D0_
not14
VTD0_n
ot13
V_r ef 1. 2
Vcc2
C86
0. 001uC87
0. 1u
C84
0. 001u
Vcc2
C85
0. 1u
To_count er _1
R3850
TP 1. 2+TP 1. 2-
Vt t
R3750
C83 15p
R51 33
M C100EP11
Q 01
Q 0not2
Q 13
Q 1not4
Vee5
Dnot6
D7
Vcc8Vcc
R73
50
R72
50
Vt t
C730. 1u C740. 001u
3D7408- 1
I N1
AE2
S0/ P03
P14
P25
P36
P47
G ND8
Vdd16
O UT15
M D14
P713
P612
SC11
P510
SI09
Vcc2
M CEPT20
NC1
Q2
Q _not3
NC4
Vcc8
D7
NC6
G ND5
C88 15pC82 15p
R50 33
R75
50
R76
50
Vt t
Vcc
C93
0. 001uC920. 1u
Vcc2
C77
0. 001uC78
0. 001u
C79
1n
R77
50
R40
50R3050
R3150
R5450
R55
50Vt t
R42
50
R52 33
Vcc
R79
500
1. 5V
Vt t
C690. 01u
C701u
Vcc2
Vcc2
Vcc
C671u
C680. 01u
R4825k
R32
R39
50 R4650
Vt t
R4750
C89 5p
R53 33
Vcc
TP_Sig_1. 4 To_sync_1
Vt t
R34
R_ h y s t2
Vcc
M ix_sel_1M ix_sel_1_not
C71
1u
C720. 01u
R491k
Vcc2
C90
0. 001uC91
0. 1u
Vt p1
Vp2
Vn3
Vt n4
Vcci
5LE_
not6
LE7
Vcco/V
tt8
Vcco12
Q11
Q _not10
Vcco9
Vcci
16GN
D15
HYS14
GND
13
M C10EP31
SET1
D2
CLK3
RESET4
VCC8
Q7
Q not6
VEE5
Vt t
C621u
C610. 01u
M C100EPT21
NC1
D2
Dnot3
Vbb4
Vcc8
Q7
NC6
G ND5
R41
50
Vt t
R4350
Vcc2
C76
0. 1u
C75
0. 001u
Vt t
Vcc
C81
0. 1u
C80
0. 001u
Vcc
C651u
Vcc
C660. 01u
R3550
R3650
Vt t
NB3L553
Vdd1
Q 02
Q 13
G ND4
O E8
Q 37
Q 26
I _clk5
R33
Rr ef 2
Quantum encryption system - receiver. 28
► In Part A we were introduced to:In Part A we were introduced to:
► The overall system + modes of operation.The overall system + modes of operation.► Receiver structure.Receiver structure.► The block diagram of the receiver’s PCB.The block diagram of the receiver’s PCB.► The electrical parts.The electrical parts.► Power considerations.Power considerations.► Timing.Timing.► The electrical diagram.The electrical diagram.
Conclusion.Conclusion.
► In Part B we will see :In Part B we will see :
► Control interface.Control interface.► FPGA programming.FPGA programming.► Logical simulation.Logical simulation.► Stack-up design.Stack-up design.► Signal integrity issues + HYPERLYNKS simulations.Signal integrity issues + HYPERLYNKS simulations.