Analog Integrated Circuits and Signal Processing, 42, 253–264, 2005c© 2005 Springer Science + Business Media, Inc. Manufactured in The Netherlands.

Quantifying Error in Dynamic Power Estimation of CMOS Circuits∗

PUNEET GUPTA,1 ANDREW B. KAHNG1,2 AND SWAMY MUDDU1

1Department of Electrical and Computer Engineering, UC San Diego, La Jolla, CA, USA2Department of Computer Science and Engineering, UC San Diego, La Jolla, CA, USA

E-mail: puneet@ucsd.edu; abk@ucsd.edu; smuddu@ucsd.edu

Received April 19, 2004; Revised May 15, 2004; Accepted July 7, 2004

Abstract. Conventional power estimation techniques are prone to many sources of error. With increasing domi-nance of coupling capacitances, capacitive coupling potentially contributes significantly to power consumption inthe deep sub-micron regimes. We analyze potential sources of inaccuracy in power estimation, focusing on thosedue to coupling. Our results suggest that traditional power estimates can be off by as much as 50%.

Key Words: power, crosstalk, coupling

1. Introduction

The advent of low-power portable devices along withcontinued increases in device density and operating fre-quency make power consumption a major concern inmodern VLSI design. In this work, we seek to iden-tify sources of error in power estimation, focusing onthose which arise if effects of capacitive coupling areignored. Our aim is not to propose new coupling-awarepower estimation techniques but rather to quantify theerror in non-coupling aware methods. Here, “ignoring”coupling includes ignoring crosstalk noise, as well asignoring neighbor switching and its effect on effec-tive value of coupling capacitance. This paper is or-ganized as follows. In this section we present a re-view of coupling-aware power estimation literature.We describe two main classes of techniques viz., sim-ulative and probabilistic, and give review of literatureon these topics. In Section 2 we enumerate and ex-plain several sources of inaccuracies in power estima-tion. In Section 3 we give details of experimental setupto quantify inaccuracy in traditional power estimationtechniques. We validate our assumptions in Section 4.In Section 5 we give experimental results and presentconclusions.

Capacitive switching, leakage, short-circuit currentand standby current are the sources of power consump-

∗This research was supported in part by the MARCO Gi- gascaleSilicon Research Center and Cadence Design Systems, Inc.

tion. Static power refers to the sum of leakage andstandby power while dynamic power is the sum ofshort-circuit and switching power.1 In this work, weconcern ourselves with dynamic power consumptionand capacitive switching in particular. Power estima-tion approaches can be classified into two categories,as follows.

• Simulative Techniques. These techniques employ di-rect simulation or statistical sampling techniques. Is-sues such as hazard generation and propagation, orreconvergent fanoutinduced correlations, are auto-matically taken into consideration. If performed afterlayout and parasitic extraction, accurate estimationof capacitances (including coupling) and their ef-fects is possible. A circuit simulator such as HSpice[1] or Powermill [2] is used for estimation of averagepower. A gate-level HDL simulation using tools suchas NC-Verilog can also be adapted to report powerdissipation using power models of gates from thelibrary.

• Probabilistic Techniques. To avoid the strong patterndependence and huge running times of simulation-based approaches, probabilistic approaches are used.These calculate probabilities of switching activityfor each circuit node and multiply by CV2

dd to ob-tain the node’s energy consumption. This dynamiccapacitive power is summed up over all nodes toobtain total energy consumption of the circuit. Thetransition probability of each gate is sometimes

254 Gupta, Kahng and Muddu

referred to as the activity factor [4, 5]. The GSRCTechnology Extrapolation System [6] predicts con-stant activity factor of 0.15 through all technologynodes.

Except for transistor-level simulation, typical powerestimation techniques are oblivious to coupling. Ac-cording to [6], at the 90 nm technology node capaci-tance density from interconnect is 0:8 nF/mm2 whilethe logic capacitance density is 0:13 nF/mm2. Couplingcapacitances can contribute 0–80% (a conservative es-timate) of the total interconnect capacitance. Hence,coupling can account for up to 60% of the dynamicpower consumption.

Uchino and Cong [7] and Sotiriadis et al. [8] presentalgorithms to compute the total energy consumptionconsidering coupling but [8] assumes complete volt-age transitions and ignores crosstalk noise. The modeloutlined in [7] takes into account incomplete voltagetransitions but ignores crosstalk noise. Both of theseapproaches assume zero driver output resistance (infi-nite driver) and ignore short-circuit power. Taylor et al.[9] follows a simple Spice simulation based approachto generate three wire look-up tables for various in-terconnect lengths; these are used to compute energyconsumption using interpolation. It is not clear whethersimple linear interpolation is a correct assumption. Allthe above three approaches assume a known input vec-tor (and thus suffer from pattern dependence) and es-sentially replace the circuit simulation step in the sim-ulative techniques. Henkel and Lekatsas [10] and Shinand Sakurai [11] take a switch factor based approach tomodel capacitive coupling. Henkel and Lekatsas [10]incorrectly assumes the worst-case switch factor to beone, and also assumes all lines to be transitioning simul-taneously. Shin and Sakurai [11] essentially modifiesactivity factors of lines to take into account neighborswitching. Effect of slew times and switching windowsis ignored. Moreover, it is not clear how the switch-ing correlation between lines is being estimated. Theabove-mentioned techniques compute average powerconsumption in a design. However, the worst-case im-pact of capacitive coupling can be large, and is morevisible in the case of peak power computation whichis relevant for worst-case voltage drop calculations.Even recent literature [12, 13] ignores this. For in-stance, [12] assumes just gate fanout to be a measure ofcapacitance.

2. Sources of Inaccuracies

We have identified the following as potential sourcesof error in conventional power estimation. In later sec-tions, we experimentally quantify all except numbers5, 7 and 8.

1. Crosstalk noise. This error source is distinct fromglitches arising from mismatched arrival times. Ca-pacitive coupling can cause powerdrawing voltageglitches on a silent line. Also, a transition on a vic-tim line may become nonmonotone due to couplingwith neighbors. In this case, the supply has to pro-vide more current than in the case of a monotonewaveform.

2. Short-circuit power due to crosstalk. Due to ca-pacitive coupling, the victim receiver may spenda large (small) time in the middle transitionregion—essentially due to increased (decreased)slew time—and the transition waveform may not bemonotone. This can cause a larger (smaller) short-circuit power dissipation in the victim receiver. Sim-ilarly, for the victim driver the output transition timechanges due to capacitive coupling and can lead toincreased or decreased short-circuit power depend-ing on the transitions of the aggressors.

3. Incorrect switch factors. Coupling capacitancesneed to be treated differently as their power contri-bution is dependent on two transitions (victim andaggressor) rather than one. The typical approach toaccount for coupling capacitances is to convert themto equivalent grounded capacitances via a switchfactor or Miller factor that depends on the overlapbetween victim and aggressor switching windows aswell as their relative slew times. For delay, switchfactor is typically computed as 1 − �Va

Vthwhere �Va

is the change in the aggressor voltage for a vic-tim voltage swing of Vth (typically 50% Vdd) [14].For power computations the switch factor shouldbe computed for a rail-to-rail victim swing. Thismeans that delay-based switch factors can overes-timate the power consumption: −1 ≤ SFdelay ≤ 3[14, 15] while 0 ≤ SFpower ≤ 2.

4. Incomplete voltage swings. If slew times are large,then a transition may not be rail-to-rail. In this casethe total charge drawn from supply, and hence thepower consumption, is reduced. This considerationis even more relevant for glitches which may not

Quantifying Error in Dynamic Power Estimation 255

have enough time for a complete swing. Glitchesdue to mismatched arrival times of input signalsare modeled as logic glitches by both logic simu-lators and probabilistic techniques. This means thepower drawn by these glitches is computed assum-ing complete voltage swings while in most casesthey will be smaller than complete voltage swings.Only simulative techniques can correctly take in-complete voltage swings into account. Power cal-culation as outlined in the IEEE Delay and PowerCalculation System [16] has function prototypes tohandle partial swing events.

5. Incorrect estimation of activity factors. Besidesthe above-mentioned errors due to approximations,probabilistic determination of activity factors suf-fers from errors due to ignoring of neighboring tran-sitions. Transition probabilities are found for eachgate in isolation while the power consumption alsodepends on the neighboring transitions. To com-pute power consumption, activity factors of gatetriplets should be considered as opposed to single-gate activity factor. The gates in the triplet sharecommon interconnect path comprising of aggressorand victim lines. For e.g., transition probabilitiesshould be specified as P(000 → 011) instead ofP(0 → 1). The calculation of these activity factorsrequires consideration of transitions on interconnectsegments rather than just gates. Moreover, switch-ing windows and slew rates of the transitions mustbe taken into account. Quantifying this error is be-yond the scope of our work as it requires extensiveknowledge of switching correlations in the designunder analysis.

6. Incorrect estimation of load capacitances. If we as-sume that all voltage swings in circuit are rail-to-rail(i.e., 0 ↔ Vdd), then there is no resistive shield-ing of capacitances for switchingpower calculationpurposes. Thus, all ground capacitances should belumped together, rather than using effective capac-itance models such as those given in [17, 18]. Foruncoupled lines [17] gives Cramp ≤ Ceff ≤ Ctotal

for delay computation, but for power computationCtotal must be used.

In chip design flows, parasitic information is ex-pressed in detailed standard parasitic format (DSPF)or reduced standard parasitic format (RSPF). Modelorder reduction steps used for DSPF to RSPF con-version potentially lead to incorrect power calcula-tions. However, any model order reduction methodwhich preserves the first moment of the driving point

admittance function will also preserve the total ca-pacitance. The commonly used II model of [19] pre-serves the total capacitance, and to our knowledge,commercial tools use Ctotal and DSPF [20]. Hence,we do not expect this error to be present in mostpower estimation methodologies and do not addressit in our experiments. It is worth noting that for cal-culation of short-circuit power, Ceff which preservesthe output slew time needs to be used. If Ctotal isused instead, driver short-circuit power will be un-derestimated and receiver short-circuit power willbe overestimated, as it decreases with increasingoutput slew time.

(This error presently is likely to be small, as short-circuit power is a small component of total powerconsumption.)

7. Incorrect propagation of glitches. Verilog basedsimulation reports only complete logic glitches(lower bound) while probabilistic estimates basedon static timing analysis and gate delay modelsoverestimate the number of glitches. This is a well-known error [3, 12] and we do not address it in thiswork.

8. Other Errors. Probabilistic power estimation suf-fers from various other errors such as inaccurategate delay models and spatial and temporal inde-pendence assumptions. These sources of errors arewell known [3, 21] and are again beyond the scopeof this work.

The above sources of errors motivate the questionof where accurate coupling-aware power estimation ispossible in the design flow. From the above discussion,we see that switching of neighboring wires can poten-tially have sizable impact on average as well as peakpower consumption. Exact adjacency information canbe known only after detailed routing, hence a switchingactivity aware power estimation which correctly takescapacitive coupling into account is best done only afterdetailed routing. An approximation can be to computeguardbanded values of power consumption ignoringneighbor-switching (and therefore assuming worst andbest case values of coupling capacitance) and usingindependent activity factors. This can be done at anypoint in the flow where coupling and ground capaci-tances can be estimated with reasonable accuracy (e.g.,based on post-placement global routing). In our exper-iments we assume that accurately extracted parasiticsare available.

256 Gupta, Kahng and Muddu

Fig. 1. Two parallel coupled interconnects, with inverter as driver and capacitance as load. The coupled RC equivalent of victim and aggressorlines is also shown.

3. Experimental Testbed

Our experimental testbed consists of systems of eitherone or two global RC interconnect lines in 180 nmtechnology. Specifically, a 5 mm coupled interconnectas shown in Fig. 1 is simulated with a real inverter atthe source end and a load capacitance at the sink end.All values of interconnect and device parameters arederived from [22]. Device models from [23] are usedand simulations are performed using Synopsys Star-HSpice [1]. Unless otherwise stated, interconnect ismodeled with lumped L segments.

We model distributed interconnect by 250 µm-longsegments.

Interconnect resistance per unit length isr = 0.04 �/µm, ground capacitance per unitlength is cg = 0.06 fF/µm, and coupling capacitanceis cc = 0.12 fFµm per nearest-neighbor aggressor.

The load capacitance CL is kept equal to the total in-terconnect ground capacitance in all our experiments;this is typical of global buffered interconnect. W/Lratio is taken to be 83 for NMOS transistors for alldrivers, and W/L for PMOS is twice that of NMOS. Ifparameter values differ from the ones given here, wecall this out in the experiment description. We adoptthe following notation.

• Line 1 in a two-line system is the designated victimline, while Line 2 is the only aggressor.2

• U represents a 0 → Vdd transition on the line.• D represents a Vdd → 0 transition on the line.• represents a static 0 on the line.• 1 denotes a static 1 on the line.

For example, 0U means that Line 1 is quiet at 0 V andLine 2 is making an upward transition on the inverter

Quantifying Error in Dynamic Power Estimation 257

output. We measure the average current drawn over aperiod of 1800 ps on the power supply of the designatedvictim line; this measurement interval is kept largeto ensure that a rail-to-rail transition occurs. We takecharge drawn from supply as the measure of power (en-ergy drawn can be obtained by multiplying the chargedrawn by Vdd).

4. Assumptions and Confirmations

The following basic assumptions are implicit in ourexperiments. (1) We approximate total current by ca-pacitive switching current. (2) We perform experimentswith only one slew time. Then, to show that our resultsare applicable for a wide range of slew times, we showthat the dependence of power consumption on slewtime is weak. (3) Finally, we model interconnect by alumped model which is also verified to only insignif-icantly affect the current drawn. In this section, weprovide justifications for these basic assumptions. (Forsimplicity of presentation, we do not present exhaus-tive simulation results, but rather show the essential(and representative) data.)

Negligible Leakage Power. The leakage componentof power is small for 180 nm technology but can riserapidly in future technology nodes, particularly forhigh-performance devices as opposed to low operating-power or low standby-power devices [22]. Typical val-ues of leakage power for the inverters used in our exper-iments are summarized in Table 1. The leakage currentis 3–4 orders of magnitude smaller than the switchingcurrent. More important, it is independent of load ca-pacitances. We therefore ignore the leakage componentof power in all our experiments.

Small and/or Constant Short-circuit Power. To mea-sure the short-circuit power, we measure the currentpassing through the ground terminal of the driver.

Table 1. Leakage power for typical global buffersused in our simulations.

Output logic-level W/L (NMOS) ILeakage (nA)

0 83 22

1 83 12

0 55 15

1 55 8

Table 2. Variation of short-circuit power with tslew and de-vice W/L . This is the worst-case short-circuit power (zeroload capacitance). Note that the average current includes self-loading current of the driver. Further, it has weak dependenceon load capacitance.

Transition tslew (ps) W/L (NMOS) Avg. curr. (mA)

D 100 55 0.085

U 100 55 0.026

D 200 55 0.11

U 200 55 0.055

D 100 83 0.126

U 100 83 0.039

D 200 83 0.165

U 200 83 0.082

Table 2 tabulates worst-case (zero load capacitance)values for short-circuit power; Table 3 shows that short-circuit power decreases as load capacitance increases.To compute the switching current (Isw) we considerthe U transition and subtract ISC from the total currentdrawn. With respect to Table 3, we observe that typi-cal values of load capacitance for drivers and repeatersin global buffered interconnects are greater than 500fF [22]. We further observe that (i) the dependenceof short-circuit current on load capacitance is weak,while the switching current is strongly dependent onload capacitance; and (ii) short-circuit power, can bekept to less than 10% of total dynamic power withproper design (balanced input and output slew times)[24, 25]. Our experiments involve the input to the driverswitching much faster than its output, resulting in verysmall short-circuit power. In light of these observations,we consider any variation in total power drawn fromthe supply to stem from switching current alone. Tostrengthen this conclusion, we analyze the variation ofself-loading (SL) current of the driver with varying load

Table 3. Variation of short-circuit powerwith load capacitance for NMOS W/L = 83 andinput slew time = 200 ps. Note that typical val-ues of load capacitance for drivers of bufferedglobal interconnect will exceed 500 fF.

CL (fF) Avg. ISC (mA) Avg. ITotal (mA)

0 0.082 0.175

50 0.076 0.219

500 0.052 0.64

258 Gupta, Kahng and Muddu

Table 4. Variation of self-loading current for different transi-tions when the lines are terminated with (1) inverters and (2) loadcapacitances respectively. The load capacitance value used forsimulation is 1200 fF and the input capacitance of the receiverinverter is equivalent to NMOS with W/L = 83.

Transition SL I (inverter) (mA) SL I (capacitance) (mA)

U0 0.093 0.0928

UD 0.09 0.0924

UU 0.094 0.0931

capacitance. We perform simulation of two line inter-connect with (1) load capacitance as termination and(2) inverter (of the same size as the driver) as termina-tion. Table 4 gives the values of self-loading current ofthe driver for different transitions. We can observe thatthere is negligible change in the values with differentload capacitances.

Independence of Slew Times and Power Estimation.For uncoupled lines, the power drawn should dependonly on the total switched capacitance. Short-circuitpower is affected by the slew time but, as discussedabove, is a very small component of the total dynamicpower. Table 5 shows the variation of total power withvarying slew times for a single uncoupled line. Forcoupled lines, the effective coupling capacitance varieswith relative slew times and switching windows of thevictim and the aggressor. If the aggressor signal arrivesafter the victim signal, then the effective capacitance isalmost independent of the slew time, so that poweris only weakly dependent on slew times. This phe-nomenon is examined in greater depth in Section 5.2.Table 6 shows results with total coupling capacitanceCc = Cg + CL = 600 fF, where Cg and CL are totalground and load capacitance respectively. We see thatthe power depends on transition time but not on slewtime; thus, below we use only one slew time (100 ps)to quantify errors in power estimation.

Table 5. Power consumption for anuncoupled line. Cg = CL = 300 fF.

Input tslew (ps) Avg. curr. (mA)

50 0.73

100 0.74

200 0.76

300 0.80

Table 6. Power consumption for a coupledline. We assume that victim and aggressor ar-rival times are the same if they are switchingsimultaneously.

tVictimslew tAggressor

slew Victim curr.(ps) (ps) Transition (mA)

100 100 U0 1.33

50 100 U0 1.31

100 100 U D 1.91

50 100 U D 1.90

100 100 UU 0.73

50 100 UU 0.72

Little Effect of Distributed Nature of Interconnect.Since the power consumption depends only on the totalcapacitance, it is independent of the interconnect resis-tance. For an uncoupled line there is no effect of itsdistributed nature on power. For a coupled line, thereis a small impact of its distributed nature: slew timesand arrival times will differ along the aggressor andvictim lines, leading to different switch factors alongthe victim line. Table 7 compares the power consump-tion in a distributed versus lumped coupled intercon-nect. The UU case, which essentially corresponds toan uncoupled interconnect, shows almost no effect ofdistribution while other cases show close to 1% ef-fect. We are concerned with the relative rather than theabsolute difference between the UU, U0, U D cases,and our experiments show that this relative differenceremains almost constant, with or without distribution.Therefore, for simplicity of analysis, we use a lumpedinterconnect model for power computation.3

Table 7. Power consumption in the victim lineof a 2-line coupled interconnect system, shownversus the number of segments used in thelumped-distributed model.

Avg. curr. (mA)

No. of segments

Transition 1 2 10 20

UU 0.731 0.730 0.728 0.728

U0 1.307 1.322 1.324 1.324

UD 1.884 1.914 1.921 1.921

Quantifying Error in Dynamic Power Estimation 259

5. Experimental Results

We now seek to quantify the sources of errors listed inSection 2. Since logic simulation and probabilistic es-timation of switching probabilities is beyond the scopeof this work, we do not present any results for errors5, 7 and 8 from Section 2. Errors 7 and 8 are indepen-dent of other errors, hence the inaccuracy due to themwould be beyond any error calculated in this and thenext section. To model error 5, we consider expectedand worst-case values of activity factors in Section 6.

5.1. Incomplete Voltage Swings

Partial voltage swings can occur if the slew time is largerelative to the clock period. We use a distributed inter-connect for this experiment. Table 8 shows the impactof clock period on power consumption. The UD transi-tion has the largest slew time and therefore requiresmore time for the victim transition to settle. Givengood design practices for high-performance designs,the clock period is about 6 times the input rise time [6].Therefore, we can consider the values given in Table 8to represent the energy drawn for the driver switchingonce (600 ps measurement interval), twice (1200 ps)or thrice (1800 ps) in the given measurement interval.These correspond to average activity factors of 0.5,0.33 and 0.25 respectively.4 If we assume an activityfactor of 0.15, as in the high-performance MPU modelof the 2001 ITRS [22], this error becomes essentiallynegligible. Note that in case of glitches, the problem of

Table 8. Total energy drawn from Vdd for various transi-tions with varying measurement intervals. The clock periodcorresponds to the measurement interval of the current. Theinput slew in all the cases is 100 ps. tfall is the victim falltime in ps.

Transition tclock (ps) Energytotal (pJ) tfall (ps)

U0 600 3.79 633

U0 1200 4.24

U0 1800 4.29

UU 600 2.33 237

UU 1200 2.36

UU 1800 2.36

UD 600 5.20 842

UD 1200 6.12

UD 1800 6.22

partial swings would be more pronounced as they areusually short-lasting, transient switching events. Sub-ject to our ignoring glitching in our analysis, we canconclude: The effect of incomplete voltage swings isnegligible for designs with typical activity factors.

5.2. Incorrect Switch Factors

For delay analyses, the appropriate switch factor is typ-ically computed as [14]

SFdelay = 1 − �Va

�Vv

(1)

where �Va is the change in the aggressor voltage fora victim voltage swing of �Vv (typically 50% of Vdd)[14]. For power computations the switch factor shouldbe computed for a threshold of 100% of Vdd. Moreover,if the aggressor transition starts after the victim tran-sition and the clock period is large enough, the victimwill always “see” almost the complete aggressor tran-sition since the theoretical 100% threshold delay foran RC network is ∞ and the voltage waveforms have a“knee” beyond which slope of the curve is very small.Therefore, if the aggressor and victim knee points liewithin the clock period and the aggressor signal arrivesafter the victim, we will have SFpower ∈ {0, 1, 2}. Theswitch factor for power (UD transition) can hence beapproximated by

SFpower = 1 +(

1 − t Av − t A

a

t Ra

)∀t A

v ≥ t Aa

1 t Av ≥ t A

a + t Ra (2)

2 otherwise (3)

where t Av and t A

a are the arrival times for victim and ag-gressor, and t R

a denotes the slew time of the aggressor.For the UU transition, the expression for switch factoris

SFpower = 1 −(

1 − t Av − t A

a

t Ra

)∀t A

v ≥ t Aa

1 t Av ≥ t A

a + t Ra (4)

0 otherwise (5)

and when the aggressor is quiet,

SFpower = SFdelay = 1 (6)

260 Gupta, Kahng and Muddu

Table 9. Switch factor based estimation of power.

Coupled lines Measured SFdelay Theoretical SFpower

Delay Avg. curr. Delay Avg. curr. Delay Avg. curr.Transition (ps) (mA) Value (ps) (mA) Value (ps) (mA)

UD 343 1.87 1.7 342 1.72 2 377 1.88

UU 214 0.74 0.6 215 1.09 0 145 0.73

UD 391 1.88 2.15 393 1.95 2 377 1.88

UU 159 0.73 0.15 162 0.82 0 145 0.73

For our experiments, we define the following terms.

• Measured SFdelay: This is the SF computed exper-imentally such that the delays in the coupled anddecoupled cases are the same.

• Theoretical SFpower : This is the SF computed ac-cording to Eq. (3), (5) and (6). As we will see, thisaccurately models the power consumption.

Table 9 shows the results for a set of simulations fora two-line system. Variation of SFpower with the dif-ference between victim and aggressor arrival times areshown in Figs. 2 and 3. From Table 9, we can conclude:Using delay-based switch factors for grounding cou-pling capacitances in power calculations leads to esti-mation errors; furthermore, the proposed power-basedswitch factors accurately model coupling capacitancesfor power analysis.

−200 −150 −100 −50 0 50 100 150 2001

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2

Victim Arrival-Aggressor Arrival (ps)

Sw

itch

Fac

tor

for

pow

er

Fig. 2. Variation of SFpower with the difference between victimand aggressor arrival times for the UD transition. Both victim andaggressor have slew times of 100 ps at the coupling point; the linestransition in opposite directions.

−200 −150 −100 −50 0 50 100 150 2000

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Victim Arrival-Aggressor Arrival (ps)

Sw

itch

Fac

tor

for

pow

er

Fig. 3. Variation of SFpower with the difference between victimand aggressor arrival times for the UU transition. Both victim andaggressor have slew times of 100 ps at the coupling point; the linestransition in the same directions.

5.3. Crosstalk Noise Power

A transitioning aggressor can cause a powerconsum-ing glitch on a quiet victim line as shown in Fig. 4.

Victim Input

Agg. Input

time

Voltage

Victim Output

maxminT T

0.5V

V

Fig. 4. Waveform of coupled victim and aggressor wires. The vic-tim waveform is non-monotone due to aggressor switching. The de-lay of the victim line increases from Tmin to Tmax because the ag-gressor switching slows down the falling victim signal.

Quantifying Error in Dynamic Power Estimation 261

Table 10. Crosstalk noise power for the 1Dtransition.

Victim W/L Cc Peak Avg. curr.(NMOS) (fF) noise (V) (mA)

83 600 0.35 0.578

110 600 0.34 0.580

83 300 0.23 0.298

110 300 0.22 0.298

Moreover, as mentioned above, if the victim transitionis non-monotone, the total charge drawn is greater thanCV since the victim driver has to pull up the switchedcapacitance by more than Vdd. Capacitive coupling cancause such nonmonotone transitions. It is difficult to es-timate the power consumed by such non-monotonicity.Here, we estimate crosstalk noise pulse power on aquiet victim only. We consider only the 1D transitionto be power-consuming (drawing current from Vdd, andignore all other glitches.5 Comparing values of currentin Table 10 with the current drawn for normal logictransitions in Table 7, we easily conclude: Power con-sumption due to crosstalk noise glitches is significantand cannot be ignored in power calculation.

6. Extrapolating to Full Chip Error Estimate

In this section we give an estimate of cumulative errorin power estimation, extrapolated to the whole chip.We stress that this is a rough estimate in that it doesnot take into account any switching correlations, andassumes an average activity factor. On the other hand,our estimate points out the significance of the errorsources that we have analyzed above.

From the previous sections we may derive an esti-mate of expected error for each of the power consumingtransitions (i.e., U0, UU, UD and 1D6). The baselinepower is calculated assuming a U0 transition with zerocrosstalk noise power. As in [6, 22], we assume a givenaverage activity factor A. A corresponds to the averagedtransition probability for the 0 → 1 transition. Then,the probabilities of transition pairs are as given in Ta-ble 11. Note that these probability values are derivedassuming spatial and temporal independence. For theU0 transition, the probability of transition is the prod-uct of probabilities of individual transitions U and 0.The probability of the line remaining quiescent at 0 isequal to the probability of absence of either the U or

Table 11. Probabilities of transition andexpected SFpower for a given average ac-tivity factor A.

Transition Probability SFExpectedpower

U0 A(1 − 2A) 1

UU A2 0.25

UD A2 1.75

1D A(1−2A)2 + A2

4 0

D transitions and can be given by (1 − 2A). The tran-sition probabilities for the UU transition is the productof individual transition probabilities and is equal to A2.This is the same for UD transition also. For the caseof 1D transition, we derive the probability as follows.The transition probability of 1 is given by (1 − 2A)/2.Combined with the D transition, the probability be-comes A(1 − 2A)/2. Note that the additional A2/4comes from the partial glitch assumption. Part of UDtransition can cause glitch if the signal arrives at ag-gressor before signal at victim. Assuming difference,t Av and t A

a are bounded by the relation t Aa > t A

v − tslew.The average glitch time is 0:5 times the 1D glitch timeand its probability is given by A2/2 (the transitionswhen t A

v > t Aa do not count).

Table 11 also gives the corresponding expected valueof SFpower, assuming a uniform distribution of rela-tive arrival times of the aggressor and the victim. Notethat the entry 1D in the table corresponds to crosstalkglitches, and we also take into account partial glitcheswhen the aggressor arrives before the victim in the UDcase (the aggressor must be transitioning down for thevictim to draw power). The amplitude of the partialglitch is assumed to be proportional to the differencebetween aggressor and victim arrival times. The ex-pected switch factors of 0.25 and 1.75 and partial glitchprobability of A2/4 are calculated assuming that theclock period is comparable to the sum of slew times ofvictim and aggressor. If the clock period is large, thenthe corresponding values would be 0.5, 1.5 and A2/2.

For each of the transitions, error in short-circuitpower may also be taken into account. An average-case analysis based on Table 11 yields a very smallerror in power estimation (essentially due to crosstalknoise power). Similarly, a worst-case analysis can beperformed. The highest power consumption involvesall U transitions corresponding to UD transitions,while the lowest power consumption occurs with alltransitions being UU. Thus, a guardbanding range can

262 Gupta, Kahng and Muddu

be constructed. In the following, we try to derive somecrude values for power consumption with various levelsof accuracy.7

• Conventional non-coupling aware estimation. In thiscase, coupling capacitance is treated as ground ca-pacitance with switch factor of 1. In this case, thetotal capacitance becomes Cg + 1 ∗ Cc + CL and thepower is given by

Pconventional = A(Cg + Cc + CL )V 2dd (7)

• Expected coupling “aware” estimation. This useseither simulation or correct switch factors but ig-nores crosstalk noise. If we assume neighbor switch-ing to be completely independent, we end up withtransition probabilities as in Table 11. In this casecoupling-aware power is the same as the conven-tional power estimate.

Pcoupled = A(Cg + Cc + CL )V 2dd (8)

• Correct noise-aware estimate. This takes crosstalkglitches into account. Total power is the sum of con-ventional power and power Pnoise, due to crosstalkglitches. Pnoise can be computed from noise ampli-tude (proportional to difference between aggressorand victim arrival times) and (Cg + CL ).

Pcorrect = Pconventional +(

(A(1 − 2A)

2+ A2

4

)Pnoise

(9)

• Worst-case estimate. This assumes all U transitionsto be UD and all D transitions to be DU. Total worst-case power can be calculated as

PWC = A(Cg + 0.25 ∗ Cc + CL ) ∗ V 2dd

+ A(Cg + 1.75 ∗ Cc + CL ) ∗ V 2dd

= A(Cg + 2Cc + CL )V 2dd (10)

• Best-case estimate. This assumes all U transitions tobe UU and all D transitions to be DD. In the best-case, we assume that there is no coupling betweenvictim and aggressor lines (SF = 0). Following this,the best-case power can be given by

PBC = A(Cg + CL )V 2dd (11)

Assuming A = 0.15 [6, 22] and other values fromSections 5 and 4, we get the following:8

• We calculate expected error as Pcorrect−PconventionalPconventional

. FromSection 5 and Eq. (7) and (9) we estimate this er-ror to be +18%. I.e., conventional power estimationtechniques are likely to underestimate power con-sumption.

• We calculate worst-case error as PWC−PconventionalPconventional

. FromSection 5 and Eqs. (7) and (10) we estimate this errorto be +50%.

• Best-case error is calculated as PBC−PconventionalPconventional

. FromSection 5 and Eqs. (7) and (11), we infer that theconventional power estimation techniques can over-estimate by 50%.

The above analysis not only suggests that certain guard-banding may be necessary in power estimation, butalso guides such guardbanding. For example, the aboveanalysis specifically implies that guardbanding the con-ventional power estimate by +18% will lead to zeroexpected error, 27% worst-case error and −58% bestcase error.

7. Conclusions and Future Work

We have shown that current power estimation meth-ods suffer from various inaccuracies which can re-sult in over 50% error in estimation. In the absenceof switching correlations (which are hard to compute),the expected power estimate given in Section 6 canbe used to give more accurate results without beingas pessimistic as the worst-case estimate. Of course,power estimation errors can result from various sourcesother than the ones highlighted in this work (e.g., para-sitic extraction, input pattern dependence, etc.). Thevalues of the errors given above assume zero errorfrom these “other” sources. We have also given expres-sions for power-based switch factors as distinct fromdelay-based switch factors. These switch factors shouldbe used when coupling capacitances are grounded forpower computation purposes.

There are several interesting implications of the workthat we have reported, notably the large impact of cou-pling on power consumption.

1. All coupling delay reduction techniques (segmentpermutation, repeater staggering, etc.) are also ap-plicable for power optimization. Moreover, sincethere is no parallel for hold-time violations in power,any approach which reduces delay due to cou-pling strictly improves power consumption. Due to

Quantifying Error in Dynamic Power Estimation 263

coupling, there is a direct correspondence betweendelay uncertainty and power uncertainty.

2. Reducing switching activity factor may not alwaysreduce power consumption. To see this, considerthe example of 2n parallel lines coupled along theirentire length to their immediate neighbors. As inour experiments assume Cc = Cg + CL = C . Nowwe compare two transitions U0U0.. and UUUU· · ·.The first transition draws power PU0 = (3n−1)CV2

while the second transition draws power PUU =2nCV2. Further assume that all odd-indexed lines(starting from 1) have an activity factor A1 while alleven-indexed lines (starting from 2) have an activityfactor A2. Also assume that switching activities arecorrelated such that a U transition occurs on anyeven-index line only when a U transition occurs onthe neighboring oddindex lines.9 Thus, A1 > A2.The power consumption of the n-line system is thengiven by P = A2 PUU + (A1 − A2)PU0 + A1(A1 −A2)Pnoise. Clearly, increasing A2 decreases powerconsumption until we reach A2 = A1.

3. The fact that a major component of power comesfrom interconnect capacitance suggests renewed at-tention to wirelength- and activity-driven layoutmethodologies to optimize power. The goal of rout-ing the most frequently switching nets with small-est wirelengths has been wellunderstood for the pastdecade, but the relative significance of such an ob-jective increases with technology scaling.

Our ongoing and future work includes the following.

• Estimation of power for non-monotone transitions,which was ignored in the crosstalk glitch power.

• Estimation of error in short-circuit power estimation.We expect this error to be small as short-circuit cur-rent itself can be limited to small values by properdesign.

• Assessment of crosstalk glitches, which can alsocause an increase in receiver short-circuit power ifthe amplitude of the glitch exceeds transistor thresh-old voltages. This effect is likely to be small as theglitches are usually not of high amplitude.

• Accounting for all crosstalk glitch transitions. Cur-rently, we just consider the 1D transition as the powerconsuming transition. This needs to be verified withrespect to, e.g., 1U transitions driving power to thesupply or power being drawn from ground in the 0Dcase.10

Acknowledgments

We thank Professor Dennis Sylvester of the Universityof Michigan at Ann Arbor for his continuous help andguidance during the course of this work. We also thankDr. Tak Young of Monterey Design Systems for pro-viding valuable input and reviewing several previousdrafts.

Notes

1. There may be some clash of terminology here as the term dy-namic power is sometimes used to refer to total instantaneouspeak power rather than the time averaged power we use it for.We use the terminology presented in [3].

2. Implicitly, this means that if there are multiple aggressors, theireffects on current drawn can be summed.

3. The lumped interconnect model will overestimate the receivershort-circuit power and underestimate driver short-circuit power.We ignore this effect because short-circuit power is a small com-ponent of the total power.

4. Note that a more accurate probabilistic analysis may be per-formed, as in Section 6 below, but the impact of partial swingevents is likely to be small. Hence, we do not give a detailedanalysis here.

5. Four transitions 1D, 0D, 0U , 1U can cause glitches. The 0U ,1U glitches do not draw any power from the victim supply: an0U transition causes current to flow to victim ground throughthe NMOS while a 1U transition causes current to flow to victimsupply through the PMOS. In the 0D case, current is drawn fromthe victim ground through the NMOS while in case of 1D glitch,power is drawn from the victim supply through the PMOS. Wetherefore consider only the 1D transition as power consuming.

6. We may assume that U1 is subsumed by U0.7. We assume just one aggressor. The worst (and best) case effect

of two or more aggressors can be modeled by simply scaling thecoupling capacitance and assuming validity of linear superposi-tion.

8. A positive error means underestimation by the conventionalmethods, while a negative error means overestimation.

9. Note that this implicitly assumes that all odd-indexed lines switchtogether, as do all even-indexed lines.

10. For instance, consider the 1U transition. If the victim is beingheld high and a neighboring wire goes high as well, positivecharge is injected across the coupling cap (displacement cur-rent) which temporarily causes the victim voltage to exceed Vdd.The PMOS driver of the victim then removes this charge byconducting current since it sees a non-zero Vds.

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