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1708 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 12, DECEMBER 1999

A 14-bit Intrinsic AccuracyRandom Walk CMOS DAC

Geert A. M. Van der Plas, Jan Vandenbussche, Willy Sansen, Fellow, IEEE,Michel S. J. Steyaert, Senior Member, IEEE, and Georges G. E. Gielen, Senior Member, IEEE

Abstract In this paper, a 14-bit, 150-MSamples/s currentsteering digital-to-analog converter (DAC) is presented. It usesthe novel

Q

2 Random Walk switching scheme to obtain full 14-bit accuracy without trimming or tuning. The measured integraland differential nonlinearity performances are 0.3 and 0.2 LSB,respectively; the spurious-free dynamic range is 84 dB at 500 kHzand 61 dB at 5 MHz. Running from a single 2.7-V power supply,it has a power consumption of 70 mW for an input signal of500 kHz and 300 mW for an input signal of 15 MHz. The DAChas been integrated in a standard digital single-poly, triple-metal0.5-

m CMOS process. The die area is 13.1 mm 2 .

Index Terms CMOS analog integrated circuits, digital-to-analog conversion, matching, mixed analogdigital integratedcircuits.

I. INTRODUCTION

BROAD-BAND communication ICs [1] demand embed-ded high-speed, high-accuracy digital-to-analog convert-ers (DACs) and analog-to-digital converters (ADCs), typi-

cally with 10-bit or higher linearity and sampling rates up to

200 MSamples/s. These specifications push the designs to the

technological limits of current digital CMOS processes. For

this situation current-steering DACs are often used, since they

can drive an output resistive load directly without requiring

the use of an extra buffer.Current steering DACs are based on an array of matched

current cells organized in unary encoded or binary weighted

elements that are steered to the DAC output depending on

the digital input code. The segmented architecture is most

frequently used to combine high conversion rate and high

resolution. In this architecture the least significant bits steer

binary weighted current sources, while the most significant

bits are thermometer encoded and steer a unary current source

array [2][7]. The limitations of these architectures in terms of

accuracy, linearity (INL), and speed are technology dependent

[2]. In [3], a special biasing technique is used to avoid

accumulation of graded errors and thus achieve the targeted 10-

bit linearity: the biasing of the current source array is split into

four separate quadrants. In [4], the current source array is split

into four smaller current source arrays in parallel, referred to

as the two-dimensional centroidswitching scheme. This results

in spatial averaging of the systematic and graded errors, which

would otherwise deteriorate the targeted 12-bit linearity. In this

Manuscript received April 13, 1999; revised July 8, 1999.The authors are with the Department of Elektrotechniek, ESAT-MICAS,

Katholieke Universiteit Leuven, Heverlee B-3001 Belgium.Publisher Item Identifier S 0018-9200(99)08977-5.

paper, the first intrinsic 14-bit current steering CMOS DAC

known to the authors is presented. This has been achieved

through a novel current steering architecture using the

Random Walkswitching scheme, which reduces the systematic

and graded errors by a factor of more than 50 over classical

approaches [5], [6], thus overcoming the technological barriers

of current and near future digital CMOS processes. As opposed

to [7], no tuning is used to obtain static linearity.

The DAC is implemented in a standard twin-well, single-

poly, triple-metal layer, digital 0.5- m CMOS technology

and can thus be used as an embedded converter. With aspurious-free dynamic range (SFDR) of 84 dB at 500 kHz

(spurs measured up until 40 MHz, dictated by measurement

equipment), this chip is the first current steering DAC to

achieve 14-bit linearity without trimming, calibration, tuning,

or dynamic averaging. This static linearity is in general a

prerequisite to obtain good dynamic linearity. The total chip

area is only 3.2 4.1 mm which is outstanding compared to

reported 10-bit [3] and 12-bit [4] implementations in similar

technologies, knowing that the area requirement increases

quadratically with the number of bits. The total power con-

sumption from a single 2.7-V power supply is only 300 mW

for an output signal of 15 MHz at an update rate of 150

MSamples/s.This paper is organized as follows. Section II describes the

DAC architecture. Section III explains the implementation and

the Random Walk switching scheme. The measurement

results are given in Section IV. Conclusions are drawn in

Section V.

II. DAC ARCHITECTURE

To overcome the technology constraints to obtain 14-bit

linearity, a modified segmented DAC architecture and a new

switching scheme, called Random Walk, were developed,

which are described next. The block diagram of the pre-

sented 14-bit segmented architecture is depicted in Fig. 1.The eight most significant bits (MSBs) (referred to as

in Fig. 1) are encoded from binary to thermometer code in

the thermometer encoder, which steers the unary weighted

current source array. The six least significant bits (LSBs)

(referred to as in Fig. 1), which steer the binary weighted

current source array, are delayed by the binary delay block to

have equal delay with the MSBs. This architecture reflects

directly in the floorplan of the chip (see also Fig. 9). Unlike

other implementations [3], [4], all digital coding (thermometer

encoder and binary delay block) has been grouped at the top of

00189200/99$10.00 1999 IEEE

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VAN DER PLAS et al.: 14-BIT RANDOM WALK CMOS DAC 1709

Fig. 1. Block diagram and floorplan of the modified segmented 14-bit DAC.

Fig. 2. Implementation of unary and binary current sources.

the chip. The latches and the current switches M2a and M2b

(see Fig. 1) are grouped in the switch/latch array in the middle

of the chip. Finally, all current sources (binary weighted as

well as unary weighted) can be found on the bottom of the

chip in an array of 74 by 72 units. Every unary current

source (referred to as in Fig. 1) is split in 16 units,

which are spread across the current source array to compensate

systematic and graded errors required for the 14-bit linearity,as will be explained in the next section. The binary current

sources (referred to as in Fig. 1) are implemented by

connecting units of the array in parallel/series, as depicted in

Fig. 2. The least significant bit is implemented as four times

16 units in series, which are again spread across the array. Bit

is implemented as four times eight units in series, bit as

four times four units in series, bit as four times two units

in series, bit as four units in parallel, and bit as eight

units in parallel.

The presented architecture leaves full flexibility concerning

the switching sequence of the unary current sources. This

is impossible with the traditional row-column encoder [5],

[6], where a complete row of cells has to be turned onbefore switching on a following row. This flexibility has been

exploited to implement a new switching scheme capable of

obtaining 14-bit intrinsic static linearity, as will be explained

in the following section.

III. DAC IMPLEMENTATION

A. Static Performance

Intrinsic 14-bit linearity can only be achieved by tackling

all possible random, systematic, and graded errors. Important

effects that must be taken into account are:1) random errors:

a) device mismatches;

2) systematic and graded errors:

output impedance of the current source and switch;

edge effects;

voltage drops in the supply lines;

thermal gradients;

CMOS technology related error components:

a) doping gradients;

b) oxide thickness gradients resulting in a shift

across the die.1) Random Errors: The random error of the current

sources is determined by matching properties, which determine

the dimensions of the unit current source M1 (see Fig. 1). An

estimation of the minimum channel area of transistor M1 was

made through Monte Carlo simulations of the circuit yield

as a function of the unit current source matching accuracy

[2]. For a yield of 99.7%, this results in a required relative

current matching of 0.06%. Based on the statistical

mismatch model of [8] and [9], for which mismatch data

of our process were available, and for the overdrive voltage

chosen, the active area of an LSB current source

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is derived

V

and thus

m (1)

The full-scale current is used to calculate the width-

over-length ratio of the LSB current source device

mA (2)

From (1) and (2). the current source dimensions and

are then derived

m m (3)

These are the dimensions of the LSB current source. In the

current source array, a current source transistor is used thatis four times wider. The unary and binary current sources are

then built up out of this basic current source transistor, as

indicated in Fig. 2.

2) Systematic and Graded Errors: A bigger problem for

14-bit linearity is the systematic and graded errors. One source

of nonlinearity is the finite output impedance of the current

source. When the output voltage varies between zero and full

scale, a different number of current sources are connected to

the output, and therefore different impedances are seen at the

output node

(4)

The parameter indicates the number of current sources that

are switched on by the thermometer encoder. is the load,

and is the output resistance of the current source transistor

M1 and the switch transistor M2 in cascode (see Fig. 1)

(5)

This variation in output impedance causes nonlinearity at the

output, given by [10]

INL (6)

where is the full-scale current and is the number of

current sources. Due to the large of the unit current source

M1, the output resistance of the cascode configuration

of the unit current source and the current switch transistor is

sufficiently high to avoid any impact on the linearity error.

The edge effect (current matching errors at the edge of the

current source array) can be avoided by placing sufficient rows

and columns of dummy current source cells at the edges. For

the presented 14-bit DAC, four rows and three columns of

dummy cells were added. The number of dummy cells was

derived from test-chip measurements.

The current error caused by the voltage drop in the ground

lines [5] is given by

(7)

where is the coordinate of the current source along the

ground line. Eliminating the voltage drop in the ground lineto achieve 14-bit linearity by properly sizing the ground

line would incur an unacceptable increase in the area of the

current source array. Therefore, this error is preferred to be

compensated by the switching scheme.

The thermal gradients and technology-related errors (e.g.,

doping, oxide thickness gradients, etc.) are approximated by

a Taylor series expansion around the center of the current

source array

(8)

where is the coordinate of the unit in the current sourcearray.

The current source array thus contains units with errors that

are (to first order) linear and quadratic in spatial distribution;

see (7) and (8). Let us call these spatial error profiles

and for first and second order, respectively. In Fig. 3,

these linear and quadratic error profiles are shown in the left

column. In [3] and [6], every current source is implemented

as one single unit [see Figs. 3(a) and 4(a)], concentrated at

one position, having a total residual error equal to

the spatial error

(9)

In the case of 8- and 10-bit converters, this error is sufficientlylow. The 10-bit DAC presented in [3] already uses systematic

error compensation by separate biasing for each quadrant of

the current source array. In the 12-bit converter presented in

[4], every current source is split into four units of 1/4 the

value in four different locations [see Figs. 3(b) and 4(b)].

By splitting the current source, a spatial averaging of the

error is achieved. When the distribution of the current source

transistors is symmetric around the and axes, the linear

terms are compensated (as is the case with all odd higher order

terms of the Taylor series expansion). However, the quadratic

errors are left unaltered (as is the case with all even higher

order terms of the Taylor series expansion)

(10)

The residual error distribution for a basic segment is shown

in Fig. 3(b) on the right-side plot. In order to suppress the

quadratic error, the current source must be split in a higher

number of current source units. By splitting the current source

into 16 units, as depicted in Fig. 4(c), the systematic and

graded errors are suppressed by a factor of four in the

direction and a factor of eight in the direction [Fig. 3(c)]

(11)

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Fig. 3. Compensation of first-order ( 1 )

s p

( x ; y ) and second-order ( 2 )

s p

( x ; y ) spatial errors. (a) Classical switching scheme, no compensation. (b) Centroidswitching scheme: compensation of linear and odd higher order systematic errors. (c) Q 2 switching scheme: compensation of linear and odd higher ordersystematic errors, and suppression of quadratic and even higher order errors.

This switching scheme will be referred to as quad quad-

rant , as four (quad) units in every quadrant altogether

compose one current source.

The linearity of the DAC is now determined by the accu-

mulation of these residual errors when the current sources are

switched on one by one. It is essential to keep the accumulated

error as low as possible, or in other words, to turn on current

sources in a sequence such that the systematic error residues

are not accumulating. Note that some current sources have a

residual error higher than average (positive DNL) while others

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(a) (b) (c)

Fig. 4. Three different current source implementations: (a) unary current source implemented as one unit, (b) unary current source implemented as fourunits in parallel, and (c) unary current source implemented as 16 units in parallel.

Fig. 5. Switching sequence of the Q 2 Random Walk switching scheme.

have a residual error below the average (negative DNL). This

leads us to the choice of the switching sequence for the 86

segmented 14-bit DAC. From a test chip, an error profile ofthe 256 unary current sources has been estimated. If quadratic

errors are taken into account and using the quad quadrant

scheme of Fig. 3(c), an error residue as shown in Fig. 3(c) on

the right is found in every quadrant. Only 255 current sources

are required for the DAC function. So one of the 256 current

sources is used as a biasing circuit.

The switching sequence of the 255 unary current sources is

an important design parameter to limit the INL. Therefore, to

select the sequence of the current sources and determine the

best switching scheme (256 possible solutions), an optimiza-

tion in two steps (hierarchically) has been undertaken. The goal

is to randomize the different error contributions (positive andnegative) so that no error accumulation occurs. The 16 16

current source matrix of cells with the above quadratic-like

error residue (which is calculated from the assumed error

profile) is divided into 16 4 4 regions (referred to with A-P),

as shown in Fig. 5. The switching sequence of these regions

(A-P) has been optimized to compensate for the quadratic-

like residual errors. Since the 16 current sources in every

4 4 region do not have exactly the same residue, there still

is a remaining small second-order residue within every 4 4

region. This can be approximated as linear, and the switching

sequence within each 4 4 region therefore has been optimized

to compensate for these linear-like second-order residues. This

leads to the overall switching sequence of the unary current

sources

1. current source 0 in region A,

2. current source 0 in region B,

3.

17. current source 1 in region A

18. current source 1 in region B

19.

254. current source 15 in region N

255. current source 15 in region O.

By random walking through the 255 current sources, the

residual error is not accumulated but rather randomized,

hence the name Random Walk switching scheme. Fig. 6

compares simulations of the resulting INL, for the sameerror profiles extracted from test structures, in case of the

classical switching scheme used in [6] and the presented

Random Walk switching scheme. The resulting INL is

about ten times smaller using the Random Walk switching

scheme, although in both cases a quad quadrant current

source array was used. The overall nonlinearity suppression

thus equals 4 10 in the direction and 8 10 in the

direction, overcoming the technology limits and resulting in

the first CMOS DAC with intrinsic 14-bit static linearity.

Current source 15 in region P is not used as a current source.

It is configured as a MOS diode and used as a biasing reference

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(a)

(b)

Fig. 6. Simulation of INL for the same error profiles using (a) Q 2 classicalswitching scheme [6] and (b) Q 2 Random Walk switching scheme.

for the current source array. Since it is spread across the array

in the same way as any other unary current source, it tracks

these sources accurately.

B. Dynamic Performance

The dynamic performance of this DAC can be characterized

by the dynamic nonlinearities associated with current sourceswitching. These nonlinearities are mainly caused by the

following effects:

an imperfect synchronization of the input signals of the

current switches;

current variation due to a drain voltage variation of

the current sources caused by the fact that both current

switches are simultaneously in the off-state;

the worst case glitch appears at the boundary between

binary and unary current sources (going from code 63 to

code 64).

transients in the output response of the current source.

(a)

(b)

Fig. 7. Dynamic latch of the (a) switch/latch array and (b) output signals.

The following measures have been taken to reduce the dy-

namic nonlinearities. To improve the synchronization, a latch

is placed directly in front of the current switches M2 (see

block diagram of Fig. 1). This latch is depicted in Fig. 7. It

provides the two complementary signals needed at the input

of the current switches. The input signals and of the

latch are given directly by the encoder, so there is no need for

an extra inverter. This latch also reduces the current variation

due to the drain voltage variation of the current sources. In the

conventional driving scheme, the driving voltages at the input

of the switching transistors M2a and M2b (see Fig. 1) change

simultaneously and cross each other in the middle. In this case,both switching transistors will be off for a short period. As a

result, the capacitance at the drain of current transistor M1

will be discharged. By properly sizing the latch, the crossing

point has been shifted to avoid this [4].

Since the current switches of the binary current sources are

smaller, dummy switches have been added. So all latches,

binary and unary, have the same load and delay.

Finally, the major-carry glitch is also determined by the

partitioning between unary and binary current sources. In [3],

it is stated that a complete unary implementation would lead

to the best dynamic performance in terms of total harmonic

distortion. The number of unary implemented bits is limited by

the increased coding complexity ( 2 ) and area constraints.In the available triple-metal technology, area constraints (rout-

ing of switch/latch and current source array) resulted in an 86

segmented architecture as a good tradeoff.

C. Encoder

Using the Random Walk switching, required to average

out the systematic and graded errors, implies that the classical

row-column encoder [2], [3], [5], [6] can no longer be used. In

this classical row-column encoder, a complete row of cells has

to be turned on before switching on a following row, which

results in an accumulation of systematic and graded errors.

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TABLE ITRUTH TABLE FOR THE THERMOMETER ENCODER ( N = 4 bits)

TABLE IITRUTH TABLE FOR THE DIFFERENT CODERS: (a) COARSE

ENCODER, (b) FINE ENCODER, AND (c) ADDRESS DECODER

(a)

(b)

(c)

In our case, the number of output lines of the thermometer

encoder increases with 2 where is the number of bits,

resulting in complex logic and large input capacitance, which

have to be carefully buffered. This complexity exceeds the

behavioral synthesis capabilities of commonly used commer-

cial tools, and a special VHDL implementation using lookup

tables was developed. Table I gives the example in case of

four bits If we look at the truth table from a highlevel (coarse encoding), three different submatrices

can be distinguished: the lower diagonal matrices, which

consist completely of zeros; the upper diagonal matrices,

which consist completely of ones; and the diagonal itself,

whose truth table will be referred to as the fine encoding.

The truth table for the overall coarse encoding is depicted in

Table II(a), where a 0 stands for lower diagonal, 1 stands

for upper diagonal, and stands for fine encoding. The

truth table for the fine encoding is given in Table II(b). The

implementation of the thermometer encoder using fine and

coarse encoders is schematically shown in Fig. 8: the address

Fig. 8. Schematic of the thermometer encoder.

Fig. 9. Microphotograph of the 14-bit DAC.

decoder decides whether at the coarse level the diagonal

submatrices, the upper diagonal submatrices (1s), or the lowerdiagonal submatrices (0s) are used. The address decoder steers

the different multiplexers, resulting in the correct thermometer

code. The truth table for the address decoder is given in

Table II(c).

This lookup-table implementation of the 8-bit thermometer

encoder was synthesized with a standard cell library

using standard commercial tools. An additional pipeline was

inserted to meet the timing constraints. To complete the full

encoder, the 6 LSB bits for the binary current sources are

delayed (see Fig. 1) to arrive at the same time as the outputs

of the pipelined thermometer encoder for the unary current

sources.

D. Layout

The 14-bit linearity requirement has strong influence on the

layout of the chip. The chip photograph is shown in Fig. 9.

The chip has been implemented in a single-poly, triple-metal

0.5- m CMOS process.

The digital encoder was placed on the top of the chip (see

Fig. 9), far away and well shielded from the sensitive analog

parts (current source array). The standard cell placement

and routing was done with commercially available tools.

Digital and analog power supplies have been separated: 2.5

nF of decoupling capacitance has been integrated around the

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Fig. 10. Floorplan of the current source array.

perimeter of the chip. All substrate straps and well straps

have been brought off-chip separately, as has been advised

in [11] and [12]. The output signals have been shielded from

the substrate and any other buses.

Two clock drivers have been added to the chip: one for

driving the digital encoder on top of the chip and the other

driving the analog latches in the switch/latch array at the

right side. Both clock drivers are implemented as inverter

chains with exponential scaling. The analog clock is distributed

through a binary tree, to ensure low skew between the different

analog latches. The clock tree is situated in between the digital

encoder and analog switch/latch array, routed on the top-level

metal layer (lowest capacitance).

The switch/latch array (middle of Fig. 9) has been organized

in a 9 30 matrix. The array has been generated automatically

by the Mondriaan tool [13]. Within this array, the decoupling

of the power supplies has been located close to the latchesand inverters. It has been inserted under the power lines and

inside the cells. As such, an additional 750-pF decoupling

capacitance has been integrated for the switch/latch array. The

latches have been flipped sideways to share power, ground,

clock, and output lines with their respective left and right

neighbors. The unit switch and latch have been designed

to switch a unary current source. The binary switches and

latches have been derived from this by reducing the size of

the current switches M2a and M2b (see Fig. 1) and adding

dummy switches leading to the same amount of total load for

the latches. In this way, an equal delay time and thus glitch

specification has been achieved.

The current source array (bottom of Fig. 9) is organized ina 74 72 matrix and has also been generated automatically by

the Mondriaan tool [13]. The 132 units used for the binary

current sources (see Fig. 2) have been integrated into the

current source array in columns 20 and 21 and 53 and 54, as

shown in Fig. 10. Three rows ( direction) and four columns

( direction) of dummy cells have been added at each side

of the array (Fig. 10). A single current source transistor is

shown in Fig. 11; its current is equivalent to 4 LSB. Since its

width-over-length ratio is extremely small, it has been folded

three times to obtain an acceptable aspect ratio for the current

source cell and current source array.

Fig. 11. Layout of one current source transistor.

To implement the Random Walk switching scheme, the

three metal layers available in the technology were used. The

first metal layer is used to distribute ground and biasing,

horizontally. The second metal layer has been used to connect

the four parallel MOS current sources in one column (seeFig. 10). The third metal layer was then used to connect four

of these metal-2 lines to achieve one unary current source of

16 units. In this way, the current source array was completely

covered by identical metal wires by the Mondriaan tool [13].

As such, degrading of the matching by asymmetrical metal

coverage [14] is avoided.

IV. MEASUREMENTS

The package setup for the measurements is shown in

Fig. 12: the fabricated die is mounted on a ceramic substrate,

where all power supplies have been locally decoupled. The

ceramic substrate is encapsulated in a copper-beryllium case

to shield the circuit from external noise coupling. The staticmeasurements are performed with a 50- doubly terminated

cable. The measurement setup for the dynamic characterization

is shown in Fig. 13. Dynamic measurements were performed

with an HP 3585 spectrum analyzer having a frequency range

of 40 MHz and a guaranteed dynamic range of 80 dB, with

a typical value of 84 dB.

The modified segmented architecture using the Random

Walk switching scheme resulted in the measured INL and DNL

plots shown in Figs. 14 and 15. An INL smaller than 0.3

LSB and a DNL smaller than 0.2 LSB are obtained. Fig. 16

shows the SFDR as a function of the output signal frequency

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Fig. 12. Photograph of the measurement setup.

Fig. 13. Block diagram of the dynamic measurement setup.

Fig. 14. Measured INL performance of the 14-bit DAC.

at an update rate of 150 MSamples/s. An SFDR of 84 dB

was obtained for signal frequencies below 1 MHz. The outputspectrum of the chip is shown in Fig. 17: no measurable spurs

occurred for an output frequency of 500 kHz. Fig. 18 shows

the measured SFDR as a function of the update rate for a full-

scale input signal with a frequency of 500 kHz. Fig. 19 shows

the output spectrum at a signal frequency of 5 MHz.

The total chip area (bonding pads included) is only 13.1

mm The power consumption is 70 mW at a 500-kHz output

signal and 300 mW at a 15-MHz output signal, running from a

single power supply of 2.7 V. These results compare favorably

to other reported designs [2][6], as the chip area is entirely

determined by the requirement to reduce the mismatch effect

Fig. 15. Measured DNL performance of the 14-bit DAC.

Fig. 16. SFDR as a function of the output signal frequency (update rate of150 MSamples/s).

Fig. 17. Output spectrum at 150 MSamples/s update rate (approximately500-kHz signal, 0 dBFS).

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Fig. 18. SFDR as a function of the update rate (input signal of 500 kHzat 0 dBFS).

Fig. 19. Output spectrum at 150 MSamples/s update rate (approximately5-MHz signal, 0 dBFS).

TABLE IIIMEASURED PERFORMANCE OF THE 14-BIT DAC

down to 14-bit linearity. Unlike [7], no tuning was used to

achieve 14-bit linearity.

The measured performance is summarized in Table III.

V. CONCLUSIONS

A novel DAC architecture and switching scheme called

Random Walk able to overcome technological constraints

has been presented. A 14-bit, 150-MSamples/s update rate,

current steering DAC has been fabricated in a standard digital

0.5- m CMOS technology. The intrinsic 14-bit linearity (no

trimming or tuning was used) was achieved by compensation

of the systematic and graded errors using the RandomWalk switching scheme. With an SFDR of 84 dB at 500-kHz

output signal, and spurs measured up until 40 MHz (dictated

by measurement equipment), it is the first reported intrinsic

14-bit linear CMOS DAC known to the authors. The DAC is

implemented in only 13.1 mm has low power consumption,

and operates from a single 2.7-V power supply.

REFERENCES

[1] H. Samueli, Broadband communications ICs: Enabling high-bandwidthconnectivity in the home and office, in Proc. IEEE 1999 ISSCC, Feb.1999, pp. 2630.

[2] J. Bastos, M. Steyaert, and W. Sansen, A high yield 12-bit 250-MS/s

CMOS D/A converter, in Proc. IEEE 1996 CICC, May 1996, pp.431434.

[3] C-H. Lin and K. Bult, A 10b 500 MSamples/s CMOS DAC in 0.6mm2 , IEEE J. Solid-State Circuits, vol. 33, pp. 19481958, Dec. 1998.

[4] J. Bastos, A. M. Marques, M. S. J. Steyaert, and W. Sansen, A 12-bit intrinisic accuracy high-speed CMOS DAC, IEEE J. Solid-StateCircuits, vol. 33, pp. 19591969, Dec. 1998.

[5] Y. Nakamura, T. Miki, A. Maeda, H. Kondoh, and N. Yazawa, A 10-b70-MS/s CMOS D/A converter, IEEE J. Solid-State Circuits, vol. 26,pp. 637642, Apr. 1991.

[6] T. Miki, Y. Nakamura, M. Nakaya, S. Asai, Y. Akasaka, and Y. Horiba,An 80-MHz 8-bit CMOS D/A converter, IEEE J. Solid-State Circuits,vol. SC-21, pp. 983988, Dec. 1986.

[7] A. R. Bugeja, B.-S. Song, P. L. Rakers, and S. F. Gillig, A 14b 100MSample/s CMOS DAC designed for spectral performance, in Proc.

IEEE 1999 ISSCC, Feb. 1999, pp. 148149.[8] K. Lakshmikumar, R. Hadaway, and M. Copeland, Characterization

and modeling of mismatch in MOS transistors for precision analog

design, IEEE J. Solid-State Circuits, vol. SC-21, pp. 10571066, Dec.1986.

[9] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, Matchingproperties of MOS transistors, IEEE J. Solid-State Circuits, vol. 24, pp.14331439, Oct. 1989.

[10] B. Razavi, Principles of Data Conversion System Design. Piscataway,NJ: IEEE Press, 1995, pp. 6263.

[11] D. K. Su, M. J. Loinaz, S. Masui, and B. A. Wooley, Experimentalresults and modeling techniques for substrate noise in mixed-signalintegrated circuits, IEEE J. Solid-State Circuits, vol. 28, pp. 420429,Apr. 1993.

[12] M. Ingels and M. Steyaert, Design strategies and decoupling techniquesfor reducing the effects of electrical interference in mixed-mode ICs,

IEEE J. Solid-State Circuits, vol. 32, pp. 11361141, July 1997.[13] G. Van der Plas, J. Vandenbussche, G. Gielen, and W. Sansen, Mondri-

aan: A tool for automated layout synthesis of array-type analog blocks,in Proc. IEEE 1998 CICC, May 1998, pp. 485488.

[14] H. P. Tuinhout and M. Vertregt, Test structures for investigation ofmetal coverage effects on MOSFET matching, in Proc. IEEE 1997 Int.Conf. Microelectronic Test Structures, Mar. 1997, vol. 10, pp. 179183.

Geert A. M. Van der Plas was born in Merchtem,Belgium, in 1969. He received the M.Sc. degreefrom the Katholieke Universiteit Leuven, Belgium,in 1992, where he is pursuing the Ph.D. degree.

Since 1992, he has been a Research Assistantat the ESAT-MICAS Laboratory at the KatholiekeUniversiteit Leuven. His main research interest isin the field of computer-aided design of analogintegrated circuits.

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Jan Vandenbussche was born in Leuven, Belgium,in 1971. He received the M.Sc. degree in electricaland mechanical engineering from the KatholiekeUniversiteit Leuven, Belgium, in 1994, where heis pursuing the Ph.D. degree.

His research is on the design automation ofanalog-to-digital and digital-to-analog converters.Currently, he is a Research Assistant at the ESAT-MICAS laboratory of the university. His researchinterests are in design and design automation of

analog integrated circuits.

Willy Sansen (S66M72SM86F95) was bornin Poperinge, Belgium, on May 16, 1943. He re-ceived the masters degree in electrical engineeringfrom the Katholieke Universiteit (K.U.) Leuven in1967 and the Ph.D. degree in electronics from theUniversity of California, Berkeley, in 1972.

Since 1981, he has been a full Professor atthe ESAT Laboratory of K.U. Leuven. During theperiod 19841990, he was Head of the ElectricalEngineering Department. He was a Visiting Profes-sor at Stanford University, Stanford, CA, in 1978,

at the Federal Technical University Lausanne in 1983, at the University of

Pennsylvania, Philadelphia, in 1985, and at the Technical University Ulmin 1994. He has been involved in design automation and in numerousanalog integrated circuit designs for telecom, consumer electronics, medicalapplications, and sensors. He has been supervisor of 39 Ph.D. theses in thatfield and has authored and coauthored more than 400 papers in international journals and conference proceedings and six books, among them (with K.Laker) Design of Analog Integrated Circuits and Systems. He is a member ofthe editorial committee of Sensors and Actuators and High Speed Electronics.

Dr. Sansen is a member of the editorial committee of the IEEE J OURNALOF SOLID-STATE CIRCUITS. He servers regularly on the program commit-tees of conferences such as ISSCC, ESSCIRC, ASCTT, Eurosensors, andTransducers.

Michel S. J. Steyaert (S85A89SM92), for a photograph and biography,see p. 911 of the July 1999 issue of this JOURNAL.

Georges G. E. Gielen (S87M92SM99) re-ceived the M.Sc. and Ph.D. degrees in electricalengineering from the Katholieke Universiteit (K.U.)

Leuven, Belgium, in 1986 and 1990, respectively.From 1986 to 1990, he was a Research Assis-tant with the Belgian National Fund of ScientificResearch. In 1990, he was a Postdoctoral ResearchAssistant and Visiting Lecturer at the Departmentof Electrical Engineering and Computer Science ofthe University of California, Berkeley. From 1991to 1993, he was a Postdoctoral Research Assistant

of the Belgian National Fund of Scientific Research at the ESAT Laboratoryof K.U. Leuven. In 1993, he was appointed as a tenured Research Associate ofthe Belgian National Fund of Scientific Research and an Assistant Professorat the Katholieke Universiteit Leuven. In 1995, he became an AssociateProfessor there. His research interests are in the design of analog and mixed-signal integrated circuits, especially in analog and mixed-signal CAD toolsand design automation (modeling, simulation and symbolic analysis, analogsynthesis, analog layout generation, and analog and mixed-signal testing). Heis coordinator or partner of several (industrial) research projects in this area.

He is the author or coauthor of one book and more than 100 papers in editedbooks, international journals, and conference proceedings. He is a member ofthe Editorial Board of the Kluwer International Journal on Analog IntegratedCircuits and Signal Processing.

He received the 1995 Best Paper Award from the Wiley InternationalJournal on Circuit Theory and Applications. He regularly is a member of theProgram Committees of international conferences, including ICCAD, DATE,and ISCAS. He has been an Associate Editor of the IEEE T RANSACTIONS ONCIRCUITS AND SYSTEMS PART I: FUNDAMENTAL THEORY AND APPLICATION, andrecently also of PART II: ANALOG AND DIGITAL SIGNAL PROCESSING. He wasthe 1997 Laureate of the Belgian National Academy of Sciences, Literatureand Arts.

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