PyMTL:'A'Uniﬁed'Framework'for'Ver8cally'Integrated'...

Cornell'University'Computer'Systems'Laboratory'

PyMTL:'A'Unified'Framework'for'Ver8cally'Integrated'

Computer'Architecture'Research'

Derek'Lockhart,'Gary'Zibrat,'and'Christopher'Ba>en'

Outline(

1'/'39'PyMTL:'A'Unified'Framework'for'Ver8cally'Integrated'Computer'Architecture'Research'

The'Computer'Architecture'Research'Methodology'Gap'

The'PerformanceFProducGvity'Gap'

PyMTL'

SimJIT'

Trends(in(Computing(Systems(


Energy'&'Power'Constrained'

Credible''Energy'and'Power'

Analysis'



Extensive'SpecializaGon'



Analysis'

ProducGve'Design'Space'ExploraGon'

of'Specialized'Units'



CrossFLayer'OpGmizaGon'

Extensive'SpecializaGon'


EffecGve'Strategies'for'

VerGcally'Integrated'Design'


Analysis'

ProducGve'Design'Space'ExploraGon'

of'Specialized'Units'

Managing(Increasing(Design(Complexity(

3'/'39'

• AbstracGons'

''' • Methodologies'

''' • Pa>erns,'Languages,'Tools'

PyMTL:'A'Unified'Framework'for'Ver8cally'Integrated'Computer'Architecture'Research'

Computer(Architecture(Research(Abstractions(

3'/'39'



• AbstracGons'


Sea'of'Transistors'

ApplicaGons'


4'/'39'

Algorithms'

InstrucGon'Set'Architecture'

Microarchitecture'

VLSI'

Compilers'


Sea'of'Transistors'

ApplicaGons'


4'/'39'

Algorithms'


Microarchitecture'

VLSI'

Compilers'Academic'Research'

'A'Few''

Researchers'

Industry'Development'

'Hundreds'of'Engineers'



4'/'39''

Algorithms'


Microarchitecture'

VLSI'

Compilers'Academic'Research'

'A'Few''

Researchers'

Industry'Development'

'Hundreds'of'Engineers'

Sea'of'Transistors'

ApplicaGons'


Computer(Architecture(Research(Methodologies(

5'/'39'

• AbstracGons'




Sea'of'Transistors'

ApplicaGons'


6'/'39'

Cycle'Level'

•  Behavior'•  Timing'

Algorithms'


Microarchitecture'

VLSI'

Compilers'



6'/'39'

Cycle'Level'



Sea'of'Transistors'

ApplicaGons'

Algorithms'

VLSI'

Compilers'


Microarchitecture'


6'/'39'

Cycle'Level'


FuncGonal'Level'

•  Behavior'


Sea'of'Transistors'

ApplicaGons'

Microarchitecture'

VLSI'


Algorithms'

Compilers'

Algorithms'


Compilers'


6'/'39'

Cycle'Level'


Microarchitecture'

FuncGonal'Level'

•  Behavior'

VLSI'

Register'Transfer'Level'

•  Behavior'•  Timing'•  Physical'Resources'Sea'of'Transistors'

ApplicaGons'



Algorithms'

Compilers'


6'/'39'

Cycle'Level'


Microarchitecture'

FuncGonal'Level'

•  Behavior'

VLSI'


•  Behavior'•  Timing'•  Physical'Resources'Sea'of'Transistors'

ApplicaGons'




Cycle'Level'


FuncGonal'Level'

•  Behavior'


•  Behavior'•  Timing'•  Physical'Resources'

Modeling'Towards'Layout



FuncGonal'Level'

Cycle'Level'


Algorithm'and'ISA'Development'

Design'Space'Explora8on'

Area/Energy/Timing'Valida8on'and'

Prototype'Development'

Modeling'Towards'Layout

Greater''Simula8on'Speed'

Greater''Model'Detail'

Computer(Architecture(Research(Frameworks(

8'/'100''

• AbstracGons'





9'/'100''

FuncGonal'Level'

Cycle'Level'






MATLAB/Python'Algorithm'or'C++'InstrucGon'Set'Simulator'

C++'Computer'Architecture''SimulaGon'Framework'(ObjectFOriented)'

Verilog'or'VHDL'Design'with'EDA'Toolflow'(ConcurrentFStructural)'



9'/'100''

FuncGonal'Level'

Cycle'Level'






Different'languages,''pa>erns,'and'tools!

The'Computer'Architecture'Research'Methodology'Gap


Great(Ideas(From(Prior(Work(

10'/'100''PyMTL:'A'Unified'Framework'for'Ver8cally'Integrated'Computer'Architecture'Research'

•  ConcurrentVStructural'Modeling'(Liberty,'Cascade,'SystemC)!!

Consistent'interfaces'across'abstracGons''




•  Unified'Modeling'Languages'(SystemC)''

Consistent'interfaces'across'abstracGons'''Unified'design'environment'for'FL,'CL,'RTL'''





•  Hardware'Genera8on'Languages'(Chisel,'Genesis2,'BlueSpec,'MyHDL)''

Consistent'interfaces'across'abstracGons'''Unified'design'environment'for'FL,'CL,'RTL'''ProducGve'RTL'design'space'exploraGon'''






•  HDLVIntegrated'Simula8on'Frameworks'(Cascade)!'

Consistent'interfaces'across'abstracGons'''Unified'design'environment'for'FL,'CL,'RTL'''ProducGve'RTL'design'space'exploraGon'''ProducGve'RTL'validaGon'and'cosimulaGon'''






•  HDLVIntegrated'Simula8on'Frameworks'(Cascade)!!

•  LatencyVInsensi8ve'Interfaces'(Liberty,'BlueSpec)'

Consistent'interfaces'across'abstracGons'''Unified'design'environment'for'FL,'CL,'RTL'''ProducGve'RTL'design'space'exploraGon'''ProducGve'RTL'validaGon'and'cosimulaGon'''Component'and'test'bench'reuse'

Outline(




PyMTL'

SimJIT'

What(is(PyMTL?(

12'/'39'

• A'Python'DSEL'for'concurrentFstructural'hardware'modeling'

Model'DSEL'


What(is(PyMTL?(

12'/'39'

'• A'Python'DSEL'for'concurrentFstructural'hardware'modeling'• A'Python'API'for'analyzing'models'described'in'the'PyMTL'DSEL''

API'


Model'DSEL'

What(is(PyMTL?(

12'/'39'

'• A'Python'DSEL'for'concurrentFstructural'hardware'modeling'• A'Python'API'for'analyzing'models'described'in'the'PyMTL'DSEL'• A'Python'tool'for'simulaGng'PyMTL'FL,'CL,'and'RTL'models'

API'

SimulaGon'Tool'


Model'DSEL'

What(is(PyMTL?(

12'/'39'

'• A'Python'DSEL'for'concurrentFstructural'hardware'modeling'• A'Python'API'for'analyzing'models'described'in'the'PyMTL'DSEL'• A'Python'tool'for'simulaGng'PyMTL'FL,'CL,'and'RTL'models'• A'Python'tool'for'translaGng'PyMTL'RTL'models'into'Verilog'

API'

SimulaGon'Tool'

TranslaGon'Tool'


Model'DSEL'

What(is(PyMTL?(

12'/'39'

'• A'Python'DSEL'for'concurrentFstructural'hardware'modeling'• A'Python'API'for'analyzing'models'described'in'the'PyMTL'DSEL'• A'Python'tool'for'simulaGng'PyMTL'FL,'CL,'and'RTL'models'• A'Python'tool'for'translaGng'PyMTL'RTL'models'into'Verilog'• A'Python'tesGng'framework'for'model'validaGon'


API'

SimulaGon'Tool'

TranslaGon'Tool'

Model'DSEL'

TesGng'Framework'

What(Does(PyMTL(Enable?(

13'/'39'

'•  Incremental'refinement'from'algorithm'to'accelerator'implementaGon'

FL'Model'

Test'Harness'



13'/'39'

•  Incremental'refinement'from'algorithm'to'accelerator'implementaGon'

FL'Model'

Test'Harness'

CL'Model'

Test'Harness'



13'/'39'

•  Incremental'refinement'from'algorithm'to'accelerator'implementaGon'

FL'Model'

Test'Harness'

CL'Model'

Test'Harness'

RTL'Model'

Test'Harness'



14'/'39'

•  Incremental'refinement'from'algorithm'to'accelerator'implementaGon'•  Automated'tesGng'and'integraGon'of'PyMTLFgenerated'Verilog'


FL'Model'

Test'Harness'

CL'Model'

Test'Harness'

RTL'Model'

Test'Harness'


14'/'39'

•  Incremental'refinement'from'algorithm'to'accelerator'implementaGon'•  Automated'tesGng'and'integraGon'of'PyMTLFgenerated'Verilog'

FL'Model'

Test'Harness'

CL'Model'

Test'Harness'

RTL'Model'

Test'Harness'

Verilog'RTL'

Model'

Verilog'RTL'

Model'

Test'Harness'



15'/'39'

'•  Incremental'refinement'from'algorithm'to'accelerator'implementaGon'•  Automated'tesGng'and'integraGon'of'PyMTLFgenerated'Verilog'• MulGFlevel'coFsimulaGon'of'FL,'CL,'and'RTL'models'

FL'Model'

CL'Model'

RTL'Model'



16'/'39'

'•  Incremental'refinement'from'algorithm'to'accelerator'implementaGon'•  Automated'tesGng'and'integraGon'of'PyMTLFgenerated'Verilog'• MulGFlevel'coFsimulaGon'of'FL,'CL,'and'RTL'models'•  ConstrucGon'of'highlyFparameterized'RTL'chip'generators'

Verilog'RTL'

Model'



17'/'39'

'•  Incremental'refinement'from'algorithm'to'accelerator'implementaGon'•  Automated'tesGng'and'integraGon'of'PyMTLFgenerated'Verilog'• MulGFlevel'coFsimulaGon'of'FL,'CL,'and'RTL'models'•  ConstrucGon'of'highlyFparameterized'RTL'chip'generators'•  Embedding'within'C++'frameworks'&'integraGon'of'C++/Verilog'models'


'gem5'

PyMTL'

C++'Model' PyMTL' Verilog'

Model'


18'/'39'

'•  Incremental'refinement'from'algorithm'to'accelerator'implementaGon'•  Automated'tesGng'and'integraGon'of'PyMTLFgenerated'Verilog'• MulGFlevel'coFsimulaGon'of'FL,'CL,'and'RTL'models'•  ConstrucGon'of'highlyFparameterized'RTL'chip'generators'•  Embedding'within'C++'frameworks'&'integraGon'of'C++/Verilog'models'(see!Srinath!et.!al.!in!MICRO247,!Session!6B!)!


'gem5'

PyMTL'

C++'Model' PyMTL' Verilog'

Model'

The(PyMTL(Framework(


Model'

Specifica8on' Tools' Output'



Model'

Config'

Elaborator' Model'Instance'




Model'

Config'

Test'&'Sim'Harness'

Traces'&'VCD'

Elaborator'

SimulaGon'Tool'

Model'Instance'




Model'

Config'

Test'&'Sim'Harness'

Verilog'

Traces'&'VCD'

Elaborator'

SimulaGon'Tool'

TranslaGon'Tool'

Model'Instance'

EDA'Toolflow'




Model'

Config'

Test'&'Sim'Harness'

Verilog'

Traces'&'VCD'

User'Tool'Output'

Elaborator'

SimulaGon'Tool'

TranslaGon'Tool'

User'Tool'

Model'Instance'

EDA'Toolflow'




Model'

Config'

Test'&'Sim'Harness'

Verilog'

Traces'&'VCD'

User'Tool'Output'

Elaborator'

SimulaGon'Tool'

TranslaGon'Tool'

User'Tool'

Model'Instance'

EDA'Toolflow'


VisualizaGon' StaGc'Analysis'

Dynamic'Checking'

FPGA'SimulaGon'

High'Level'Synthesis'

The(PyMTL(DSEL(

20'/'39'

def sorter_network( input ): ! return sorted( input ) !!


['3,'1,'2,'0']' ['0,'1,'2,'3']'f(x)'

The(PyMTL(DSEL(

21'/'39'

def sorter_network( input ): ! return sorted( input ) !!class SorterNetworkFL( Model ) !'


f(x)'

['3,'1,'2,'0']' ['0,'1,'2,'3']'f(x)'

The(PyMTL(DSEL(

21'/'39'

def sorter_network( input ): ! return sorted( input ) !!class SorterNetworkFL( Model ) ! def __init__( s, nbits, nports ): ! type = Bits( nbits ) ! s.in_ = InPort [nports]( type ) ! s.out = OutPort[nports]( type ) !'


f(x)'

['3,'1,'2,'0']' ['0,'1,'2,'3']'f(x)'

The(PyMTL(DSEL(

21'/'39'

def sorter_network( input ): ! return sorted( input ) !!class SorterNetworkFL( Model ) ! def __init__( s, nbits, nports ): !! s.in_ = InPort [nports](nbits) ! s.out = OutPort[nports](nbits) !'


f(x)'

['3,'1,'2,'0']' ['0,'1,'2,'3']'f(x)'

The(PyMTL(DSEL(

21'/'39'

def sorter_network( input ): ! return sorted( input ) !!class SorterNetworkFL( Model ) ! def __init__( s, nbits, nports ): !! s.in_ = InPort [nports](nbits) ! s.out = OutPort[nports](nbits) !!! @s.tick_fl! def logic(): ! '


f(x)'

['3,'1,'2,'0']' ['0,'1,'2,'3']'f(x)'

The(PyMTL(DSEL(

21'/'39'

def sorter_network( input ): ! return sorted( input ) !!class SorterNetworkFL( Model ) ! def __init__( s, nbits, nports ): !! s.in_ = InPort [nports](nbits) ! s.out = OutPort[nports](nbits) !!! @s.tick_fl! def logic(): ! for i, v in enumerate( sorted( s.in_ ) ): ! s.out[i].next = v'


f(x)'

['3,'1,'2,'0']' ['0,'1,'2,'3']'f(x)'

The(PyMTL(DSEL(

22'/'39'

def sorter_network( input ): ! return sorted( input ) !!class SorterNetworkCL( Model ) ! def __init__( s, nbits, nports, delay=3 ): !! s.in_ = InPort [nports](nbits) ! s.out = OutPort[nports](nbits) !!! @s.tick_cl! def logic(): ! '


f(x)'

['3,'1,'2,'0']' ['0,'1,'2,'3']'f(x)'

The(PyMTL(DSEL(

22'/'39'

def sorter_network( input ): ! return sorted( input ) !!class SorterNetworkCL( Model ) ! def __init__( s, nbits, nports, delay=3 ): !! s.in_ = InPort [nports](nbits) ! s.out = OutPort[nports](nbits) ! s.pipe = Pipeline( delay ) !! @s.tick_cl! def logic(): ! s.pipe.xtick() ! s.pipe.push( sorted( s.in_ ) ) !! if s.pipe.ready(): ! for i, v in enumerate( s.pipe.pop() ): ! s.out[i].next = v !! '


f(x)'

['3,'1,'2,'0']' ['0,'1,'2,'3']'f(x)'

The(PyMTL(DSEL(

23'/'39'

def sorter_network( input ): ! return sorted( input ) !!class SorterNetworkRTL( Model ) ! def __init__( s, nbits ): !! s.in_ = InPort [4](nbits) ! s.out = OutPort[4](nbits) !! '


['3,'1,'2,'0']' ['0,'1,'2,'3']'f(x)'

The(PyMTL(DSEL(

23'/'39'

def sorter_network( input ): ! return sorted( input ) !!class SorterNetworkRTL( Model ) ! def __init__( s, nbits ): !! s.in_ = InPort [4](nbits) ! s.out = OutPort[4](nbits) !! s.m = m = MinMaxRTL[5](nbits) !!! '


['3,'1,'2,'0']' ['0,'1,'2,'3']'f(x)'

The(PyMTL(DSEL(

23'/'39'

def sorter_network( input ): ! return sorted( input ) !!class SorterNetworkRTL( Model ) ! def __init__( s, nbits ): !! s.in_ = InPort [4](nbits) ! s.out = OutPort[4](nbits) !! s.m = m = MinMaxRTL[5](nbits) !! s.connect( s.in_[0], m[0].in_[0] ) ! s.connect( s.in_[1], m[0].in_[1] ) ! s.connect( s.in_[2], m[1].in_[0] ) ! s.connect( s.in_[3], m[2].in_[1] ) !! . . . ! '


['3,'1,'2,'0']' ['0,'1,'2,'3']'f(x)'

The(PyMTL(DSEL(

24'/'39'

class MinMaxRTL( Model ) ! def __init__( s, nbits ): ! s.in_ = InPort [2](nbits) ! s.out = OutPort[2](nbits) ! @s.combinational! def logic(): ! swap = s.in_[0] > s.in_[1] ! s.out[0].value = s.in[1] if swap else s.in[0] ! s.out[1].value = s.in[0] if swap else s.in[1] !!


The(PyMTL(DSEL(

24'/'39'

class MinMaxRTL( Model ) ! def __init__( s, nbits ): ! s.in_ = InPort [2](nbits) ! s.out = OutPort[2](nbits) ! @s.combinational! def logic(): ! swap = s.in_[0] > s.in_[1] ! s.out[0].value = s.in[1] if swap else s.in[0] ! s.out[1].value = s.in[0] if swap else s.in[1] !!class RegRTL( Model ) ! def __init__( s, nbits ): ! s.in_ = InPort (nbits) ! s.out = OutPort(nbits) ! @s.tick_rtl! def logic(): ! s.out.next = s.in_ ! '


The(PyMTL(DSEL(

25'/'39'

TesGng'of'SorterFL,'SorterCL,'and'SorterRTL'can'be'greatly'simplified'by'using'latencyFinsensiGve'interfaces.''''


The(PyMTL(DSEL(

25'/'39'

TesGng'of'SorterFL,'SorterCL,'and'SorterRTL'can'be'greatly'simplified'by'using'latencyFinsensiGve'interfaces.'Produc8vity'helpers:''''


• MemoryProxies'•  QueueAdapters'

•  PortBundles'•  BitStructs'

•  TestSource'•  TestSink''''

The(PyMTL(DSEL(

25'/'39'

TesGng'of'SorterFL,'SorterCL,'and'SorterRTL'can'be'greatly'simplified'by'using'latencyFinsensiGve'interfaces.'Produc8vity'helpers:''''


''

See'the'paper'for''more'examples!'

• MemoryProxies'•  QueueAdapters'

•  PortBundles'•  BitStructs'

•  TestSource'•  TestSink''''

Why(Python?(

26'/'39'

Benefits:''• Modern'language'features'enable'rapid'prototyping'(dynamicFtyping,'reflecGon,'metaprogramming)'•  Lightweight,'pseudocodeFlike'syntax'• BuiltFin'support'for'integraGng'C/C++'code'•  Large,'acGve'developer'and'support'community'


Why(Python?(

26'/'39'

Benefits:''• Modern'language'features'enable'rapid'prototyping'(dynamicFtyping,'reflecGon,'metaprogramming)'•  Lightweight,'pseudocodeFlike'syntax'• BuiltFin'support'for'integraGng'C/C++'code'•  Large,'acGve'developer'and'support'community''Drawbacks:''•  Performance'


Outline(




PyMTL'

SimJIT'

PerformanceHProductivity(Gap(

28'/'39'

Experiment:''•  Simple'8x8'Mesh'Network'Model''• CycleFPrecise'CL'Model:'•  PyMTL'Model'Simulated'with'the'CPython'Interpreter'•  HandFWri>en'C++'Model'and'Simulator'

'



28'/'39'

Experiment:''•  Simple'8x8'Mesh'Network'Model''• CycleFPrecise'CL'Model:'•  PyMTL'Model'Simulated'with'the'CPython'Interpreter'•  HandFWri>en'C++'Model'and'Simulator'

• BitFAccurate'RTL'Model:'•  PyMTL'Model'Simulated'with'CPython'Interpreter'•  HandFWri>en'Verilog'RTL'Simulated'with'Verilator'




RTLNetworkCLNetwork

SimulatedCyclesSimulatedCycles1K 10K 100K 1M10M

1x

5x10x

30x

75x150x300x

60x

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CPython

1K10K 100K 1M

10x5x

1x

CPython



RTLNetworkCLNetwork


1x

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1000x

CPython VerilatorC++

1K10K 100K 1M

10x5x

1x

CPython

RTLNetworkCLNetwork


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1K10K 100K 1M

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Performance'degrada8on'due'to'Compila8on'

RTLNetworkCLNetwork


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1K10K 100K 1M

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Short'Simula8ons:'LargeVCompila8on'Overhead'

RTLNetworkCLNetwork


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1K10K 100K 1M

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Long'Simula8ons:'Compila8on'Overhead'Amor8zed'

RTLNetworkCLNetwork


1x

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1K10K 100K 1M

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300x' 1200x'


30'/'39'

Python'is'growing'in'popularity'in'many'domains'of'scienGfic'and'highFperformance'compuGng.''How'do'they'close'this'gap?'



30'/'39'

Python'is'growing'in'popularity'in'many'domains'of'scienGfic'and'highFperformance'compuGng.''How'do'they'close'this'gap?'


•  PythonVWrapped'C/C++'Libraries'(NumPy,!CVXOPT,!NLPy,!pythonOCC,!GEM5)''

•  Numerical'JustVInVTime'Compilers'(Numba,!Parakeet)!!

•  JustVInVTime'Compiled'Interpreters'(PyPy,!Pyston)!

•  Selec8ve'Embedded'JustVInVTime'Specializa8on'(SEJITS)!

RTLNetworkCLNetwork


1x

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CPython



300x' 1200x'

RTLNetworkCLNetwork


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CPython PyPy VerilatorC++

1K10K 100K 1M

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30x'240x'

Outline(




PyMTL'

SimJIT'

PyMTL(SimJIT(Architecture(


PyMTL'RTL'Model'Instance'

TranslaGon'

Verilog'Source'

SimJITFRTL'Tool'




TranslaGon'

Verilator'Verilog'Source'

RTL'C++'Source'

SimJITFRTL'Tool'




TranslaGon'

Verilator'Verilog'Source'

RTL'C++'Source'

C'Interface'Source'

SimJITFRTL'Tool'




TranslaGon'

Verilator'

LLVM/GCC'

Verilog'Source'

RTL'C++'Source'

C'Interface'Source'

C'Shared'Library'

SimJITFRTL'Tool'




TranslaGon'

Verilator'

LLVM/GCC' Wrapper'Gen'

Verilog'Source'

PyMTL'CFFI'Model'Instance'

RTL'C++'Source'

C'Interface'Source'

C'Shared'Library'

SimJITFRTL'Tool'




TranslaGon'

Verilator'


Verilog'Source'


RTL'C++'Source'

C'Interface'Source'

C'Shared'Library'

TranslaGon'Cache'

SimJITFRTL'Tool'

33'/'39'




TranslaGon'

Verilator'


Verilog'Source'


RTL'C++'Source'

C'Interface'Source'

C'Shared'Library'

TranslaGon'Cache'

SimJITFRTL'Tool'

33'/'39'

Fairly'robust,'ready'for'use'in'research!'


PyMTL:'A'Unified'Framework'for'Ver8cally'Integrated'Computer'Architecture'Research' 34'/'39'

PyMTL'CL'Model'Instance'

TranslaGon' LLVM/GCC' Wrapper'Gen'


CL'C++'Source'

C'Interface'Source'

C'Shared'Library'

SimJITFCL'Tool'

Just'a'prototype!'

RTLNetworkCLNetwork


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CPython PyPy VerilatorC++

1K10K 100K 1M

10x5x

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CPython PyPy



30x'240x'

35'/'39'

RTLNetworkCLNetwork


1x

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CPython PyPySimJIT-CL SimJIT-RTL

VerilatorC++

1K10K 100K 1M

10x5x

1x

CPython PyPy

PyMTL(SimJIT(Performance(


10x' 20x'

35'/'39'

RTLNetworkCLNetwork


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200x

1000x

CPython PyPySimJIT-CL SimJIT-RTLSimJIT-CL+PyPy SimJIT-RTL+PyPy

VerilatorC++

1K10K 100K 1M

10x5x

1x

CPython PyPy



4.5x' 6x'


37'/'39'

OpportuniGes'to'further'reduce'the'performance'gap:''

•  Reduce'overhead'of'PythonVtoVC++'interfaces'

•  OpGmized'(nonFPython)'event'queue'

•  Be>er'code'generaGon'

•  Be>er'event'queue'scheduling'

•  Removal'of'unnecessary'doubleFbuffering'

•  Parallel'simulaGon'


Contributions(

38'/'39'

PyMTL'is'a'producGve'Python'framework'for'FL,'CL,'and'RTL'modeling,'enabling:'

•  VerGcally'Integrated'Computer'Architecture'Research'

•  Accelerator'Design'Space'ExploraGon'

•  ConstrucGon'of'Flexible'RTL'Chip'Generators''SimJIT'considerably'closes'the'performanceFproducGvity'gap'between'Python'and'C++'simulaGons.'•  72x'Speedup'over'CPython'for'SimJITFCL'(within'4.5x'of'C++)'•  200x'Speedup'over'CPython'for'SimJITFRTL'(within'6x'of'Verilator)'


Conclusion(

39'/'39'

PyMTL'is'a'producGve,'openVsource'Python'framework'for'FL/CL/RTL'modeling'and'hardware'design.'

''

heps://github.com/cornellVbrg/pymtl''

Thank'you'to'our'sponsors'for'their'support:''NSF,'DARPA,'and'donaGons'from'Intel'CorporaGon'and'Synopsys,'Inc.'


PyMTL '

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