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2008 IEEE Region 10 Colloquium and the Third International Conference on Industrial and Information Systems,Kharagpur, INDIA December 8 -10, 2008.

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978-1-4244-2806-9/08/$25.00 2008 IEEE

Abstract This paper describes on how to formulate a self-balancing space vector modulator for the three-level neutralpoint clamp topology typically used for high power induction

motor drives. Dependence of the DC link capacitor voltage

deviation on DC-link current and inverter switching states is

established for proposed three-level inverter. Pulse pattern

rearrangements for space vector PWM (SVPWM) using degree

of freedom available in choice of redundant space vectors,

sequencing of vectors, and splitting of duty cycles of vector are

best exploited. Self neutral-point voltage deviation control in feed

forward is proposed in this paper. The effectiveness of proposed

scheme is verified by experimental results. The modulator was

successfully implemented using DSP-TMS320F2811 with a 45-

kW (60 HP) motor drive. Lab test results are given for

effectiveness of the modulator.

Index TermsNeutral point clamped (NPC) inverter, selfbalancing space vector modulation (SVM), three-level

inverter, VSI.

I. INTRODUCTIONHE Three-Level neutral point clamped topology hasattracted attention in high power medium voltage drive

applications. Fig. 1 shows main circuit of NPC voltage sourceinverter. Other interesting applications of this technologyinclude static VAR compensation systems, HVDCtransmission systems, active filtering applications, as well as

applications in power conditioning systems forsuperconductive magnetic energy storage (SMES).

Three-level topology is advantageous in constructingmedium voltage high power drives by using highest voltagedevices because the voltage across the switch is half that of

the conventional inverter. They can reduce harmonics in theoutput voltage and current due to the multilevel output voltage

This work was supported by Amtech Electronics (I) Ltd., Gandhinagar,

India.

IEEE Kharagpur Section & IEEE Sri Lanka Section

[1], [2]. The effect of capacitor voltage unbalance duringsteady state condition is analyzed in this paper. In the worst

case of unbalance one capacitor is fully charged to full DC-link voltage that results in double stress on the capacitor andthe switching devices, reducing output waveforms to two levelfrom normal three-level. The effect of the zero sequence

voltage on the neutral point variation and the dependence ofDC-link voltage unbalance on the system parameters like loadcurrents, load power factor, value of capacitance of capacitor,and modulation index have been extensively analyzed forthree-level NPC inverter [3]- [5]. The neutral point balancing

schemes, for the three-level neutral point clamped inverter, arebased on the effective use of the redundant switching states ofthe inverter voltage vectors. The redundant switching statesare used alternately such that the neutral point voltage

unbalance caused by the first switching state combination iscompensated by another state; thus, bringing the totalunbalance in one switching cycle to zero [6]. Detailed study ofNPC inverter, space vectors, dwell timings, and pulse pattern

arrangement with division of middle regions for neutral pointbalance and even harmonic elimination scheme are addressed[7]. Neutral point voltage control is achieved by utilizing thephase current polarity and distribution of the redundantvoltage vectors. A control strategy is proposed to maintain

average current drawn from neutral-point to the minimum [8],[9]. Hysteresis control for DC-link variation control andcommon mode voltage elimination in an open end windinginduction motor fed from two three-level inverters from either

side is investigated [10]. ANN based neutral-point self-voltagebalancing SVPWM is discussed for NPC inverter [11].Mathematical modeling and open loop and closed loopneutral-point control is proposed for three-level voltage sourceinverter [12]. The space vector PWM signal generation for

multi-level inverters using only the sampled amplitudes ofreference phase voltages is discussed in detail [13]. Theexperimental studies are carried out on a 45-kW inductionmotor drive and the experimental results are presented.

Pinkal J. Patel, Rakesh A. Patel,Electrical Department, R & D Department,

Sankalchand Patel College of Engineering, Hirel Electronics (I) Ltd.,Visnagar, India. Gandhinagar, [email protected] [email protected]

Vinod Patel P. N. TekwaniR & D Department, Electrical Department,Amtech Electronics (I) Ltd., Nirma Institute of Technology,Gandhinagar, India. Ahmedabad, [email protected] [email protected]

Implementation of Self Balancing Space VectorSwitching Modulator for Three-Level Inverter

T


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II. THREE-LEVELINVERTERSCHEMEWITHSELF-BALANCINGSVMFORANINDUCTIONMOTORDRIVE

Fig. 1 shows the simplified circuit diagram of a popular

three-level neutral point clamped (NPC) inverter. The inverterleg 'a' is composed of four IGBT switches S1 to S4 with four

antiparallel diodes D1 to D4. On the DC side of the inverter,

the DC bus capacitor is split into two sources, providing a

neutral point 'n'. When switches S2 and S3 are turned on, the

inverter output terminal a is connected to the neutral point

through one of the clamping diodes Dn1 and Dn2. Ideally, the

voltage across each of the DC capacitors is Vdc/2 which is half

of the total DC-link voltage Vdc,. With a finite value for C1and C2, the capacitors can be charged or discharged by neutral

current in, causing neutral-point voltage deviation. The

important problem of voltage unbalance between upper and

lower capacitors in three-level NPC inverter is discussedfurther.

As indicated earlier, the neutral-point voltage Vn = Vc1

varies with the operating condition of the NPC inverter. If the

neutral point voltage deviates too far, an uneven voltage

distribution takes place, which may lead to failure of the

switching devices and cause an increase in the harmonic of the

inverter output voltage [1].

The switches S1 and S3 operate in a complementary manner

similar to switches S2 and S4.The operating status of the

switches in the NPC inverter can be represented by the

switching states shown in Table 1. Switching state + denotes

that the upper two switches in leg 'a' are on and the inverter

pole voltage Va, which is ideally +Vdc/2, whereas '-' indicates

that the lower two switches conduct, leading to Va = -Vdc/2.

Switching state '0' signifies that the inner two switches S 2 and

S3 are on and Va is clamped to zero through the clamping

diodes. Depending on the direction of the load current ia, one

of the two claming diodes is turned on. For instance, a

positive load current (ia > 0) forces Dn1 to turn on, and the

terminal 'a' is connected to the neutral point 'n' through the

conduction of Dn1 and S2.

The space-vector PWM method is an advanced,

computation-intensive PWM method and is possibly the best

among all the PWM techniques for variable-frequency drive

applications still known.

In case of a two-level inverter there are total of 8-vectors

(6-non zero vectors and 2-zero vectors). The number of

vectors for n-level inverter is given by,

No. of space (stationary) vector = n 3 (1)

Hence in case of a three-level inverter there are 27 vectorsand among them, there are 3-zero vectors and 24-non zerovectors. Similarly, five-level inverter shall have 125 vectors.Each switching state, or combination of phase-leg switches,produces a defined set of three-phase voltages, which can be

represented in a hexagon form as shown in fig.2.

III. ANALYSIS OF DC LINKCAPACITORVOLTAGE

UNBALANCE FORTHREE-LEVEL INVERTERSCHEMEIn the NPC three-level inverter, the current drawn throughthe mid-point of dc link will result in the unbalance of thecapacitor voltage [3]. This section presents the analysis todetermine the unbalance in the dc link capacitor voltages forthe three level inverter schemes for induction motor drive.

A. System Model

The system model of the proposed inverter scheme isshown in Fig. 3. The voltage across the bottom and top dc linkcapacitors is referred as Vc1 and Vc2. Under the balanced

condition, Vc1= Vc2 = Vdc/2. Each leg of individual three-level

+

-

Vdc Induction

Motor

ThreePh

ase

ACMains

S1

S2

S3

S4

D1

D2

D3

D4

n

Dn1

Dn2

a

b

c

Uncontrolled

Rectifier

C1

C2

Fig. 1. Three level neutral point clamped inverter fed induction motor drive

TABLEI

SWITCHSTATUSANDDEFINITIONOFSTATE

Switching

States

Device Switching Status(Phase a)

PoleVoltage

Va

S1 S2 S3 S4

+ ON ON OFF OFF + Vdc/2

O OFF ON ON OFF 0

- OFF OFF ON ON -Vdc/2

Sector 1

Sector 2

Sector 3

Sector 4

Sector 5

Sector 6

+oo

o--ooo

+++

--- +--

++ooo-

+o-

++-

o+o-o-

o++

-oo

oo+--o

+o+

o-o

o+--+-

-+o

-++

-o+

--+ o-+ +-+

+-o

V*

1

23

4

0n

Fig. 2. Space vector diagram for three-level inverter


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inverter can be modeled as a switch, with the three outputlevels 1, 2, 3, (this is used instead of - , 0, + for the ease ofmathematical analysis in the following section) when the pole

is connected to negative, mid-point and positive bus of the dclink, respectively, as shown in Fig. 3. The load currents aredeoted as ia, ib and ic while the total current drawn by theinverter from the bottom, middle, and top rails of the dc link

are denoted as i1, i2 and i3 respectively.B. Determination of Capacitor Voltage Unbalance

In general the inverter pole voltage with respect to thenegative DC bus can be written in terms of capacitor voltagesand the switching functions as,

va1(Sa) = (Sa 1 )vc1 + (Sa 2 )(vc1 + vc2)

vb1(Sb) = (Sb 1 )vc1 + (Sb 2 )(vc1 + vc2) (2)

vc1(Sc) = (Sc 1 )vc1 + (Sc 2 )(vc1 + vc2)

In (2) (.) is the Dirac delta function, vc1 and vc2 are thevoltage across lower and upper capacitors. The currents drawn

from the DC-link nodes can be represented in terms of themotor currents as shown in (3)

=

c

b

a

cba

cba

cba

i

i

i

SSS

SSS

SSS

i

i

i

)3()3()3(

)2()2()2(

)1()1()1(

3

2

1

(3)

For the three wire load,

ia + ib + ic = 0i1 + i2 + i3 = 0 (4)Substituting ic = -ia -ib and removing the dependent variable i3,(2) gets reduced to

[ ][ ]

=

b

a

ca

ca

i

i

SS

SS

i

i

)2()2(

)1()1(

2

1

(5)

The current flowing through capacitor is given by

ic2 = is i3 = is ( i2 i1) = is + i2 + i1

ic1 = is + i1 (6)

=

1

2

1

2

101

111

i

i

i

i

is

c

c

(7)

Thus, the currents flowing through capacitors is directlyrelated to the voltage across the capacitors and the relationshipis given by

=

=

dt

i

i

i

Cdt

i

i

Cv

vs

c

c

c

c

1

2

1

2

1

2

101

1111

10

011

(8)

Let vc be the change in the capacitor voltage, Substitutingvalue from (5) into (7), results in

vc = vc1 - vc2 (9)

= dtiCvc 21 (10)

Thus the load current drawn from the middle node of theDC-link is responsible for the variation in the capacitor

voltages. Whenever switching functions Sa, Sb, and Sc, assumevalue equal to 2, there exists a tendency of capacitor voltageunbalancing.

IV. SWITCHINGCOMBINATIONSANDTHEIREFFECTONDCLINKCAPACITORVOLTAGES

Fi . 3. Three-level inverter and load s stem model

L

O

A

D

Vdcn

Vn

C1

C2 a

b

c

+

-

(a) Zero voltage vector

+ + +

L

O

A

D

Vdcn

Vn

C1

C2 a

b

c

+

-

(b) P-type small vector

+ O O

in

L

O

A

D

Vdcn

Vn

C1

C2 a

b

c

+

-

(c) N-type small vector

O - -

inL

O

A

D

n

Vn

C1

C2 a

b

c

+

-

(d) Medium voltage vector

+ O -

Vdc

L

O

A

D

n

Vn

C1

C2 a

b

c

+

-

(e) Large voltage vector

+ - -

Vdc

Fig. 4. Effect of switching states on Neutral point voltage deviation


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The effect of switching states on neutral voltage deviationis illustrated in fig.4 When the inverter is operated withswitching state [+++] of zero vector, the upper two switches ineach of the three inverter legs are turned on, connecting the

inverter terminals a, b, and c to the positive DC bus as shownin fig.4(a). Since the neutral point 'n' is left unconnected, thisswitching state does not affect Vn. Similarly, the other zero

switching states [000] and [---] do not cause Vn to shift either.Fig 4(b) shows the inverter operation with P-type switching

state [+OO] of small vector. Since the three phase load isconnected between the positive DC bus and neutral point 'n',the neutral current in1 flows in 'n', causing Vn to increase. Onthe contrary, the N-type switching state [O--] of small vector

makes Vn to decrease as shown in fig. 4(c). For mediumvector with switching state [+O-] in fig. 4(d), load terminals a,b, and c are connected to the positive bus, the neutral point,and the negative bus, respectively. Depending on the inverteroperating conditions, the neutral-point voltage Vn may rise or

drop. Considering a large vector with switching state [+--] asshown in fig. 4(e), the load terminals are connected between

the positive and negative DC buses. The neutral point 'n' is leftunconnected and thus the neutral voltage is not affected.

It is summarized that zero and large vectors do not affectthe neutral point voltage. Medium vectors affect Vn, but thedirection of voltage deviation is undefined so, redundant smallvectors having dominant influence on Vn are used for neutralpoint voltage control. Above discussion is made under the

assumption that the inverter is in motoring mode.In addition to the influence of switching states, the neutral-

point voltage may also be affected by a number of otherfactors like unbalanced DC capacitors due to manufacturing

tolerances, inconsistency in switching device characteristics,unbalanced three-phase operation, motoring/regenerative

mode of operation etc. As compared to motoring mode, anopposite capacitor voltage charging-discharging action takesplace in the regenerative mode due to the reversal of current.

V. DC-LINKCAPACITORVOLTAGE BALANCINGSCHEME

Various space vector modulation (SVM) schemes have

been proposed for the three-level NPC inverter using eitheropen loop scheme or closed loop scheme [7]. This paper Fig. 6. Photograph of hardware prototype

(a)

(b)

(c)

(d)

Ts Ts

o

-

o o + + + + + +

+ + + +

- - - -

+ +

- - -- - -

o o o

o o o o o o

o o o

o o o

-a

b

c

o oo o+ ++ ++ +

o o o + + oo o

- -

- -- -- -

a

b

co oo o

o o+ ++ ++ +

- -- -o oo o

- -- -- -o o

o o+ ++ ++ +

a

b

c

a

b

c

o oo o+ ++ +

- -- -- -o o

Fig. 5. Switching Signals of Sector 1 for (a) Region-1, (b) Region-2,

(c) Region-3, (d) Region-4

TABLE II

EFFECT OF DIFFERENT VECTORGROUPS ON CAPACITOR

VOLTAGES

Group Capacitor C1 Capacitor C2

ZV No effect No effectPSV Charging Discharging

NSV Discharging Charging

MVLess Charging or

Discharging effect

Less Charging or

Discharging effect

LV No effect No effect


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presents ability of open loop (self-balancing) SVPWMscheme.

Open loop capacitor voltage (self balancing) SVPWM

scheme is described below. This section proposes modifiedSVM scheme for better neutral point stabilization. To reduce

neutral-point voltage deviation, the dwell time of a givensmall vector can be equally distributed between the P-type and

N-type switching states over a sampling period. For nearestthree vectors (NTV) selection SVM either one small vector ortwo small vectors among the three selected vectors areavailable according to the triangular regions in which thereference vector V* lies. When the reference vector V* is in

region 2 or 4, only one small vector is in NTV where as inregion 1 or 3 two small vectors are in NTV. In conventionalSVM seven segments pulse pattern is chosen for all regions.

Seven segments SVM divide dwell time of only one small

vector in P-type and N-type out of two small sectors availablein region 1 and 3. So, neutral point deviation is not minimized

in these regions. To reduce neutral-point voltage deviationaccording to location of region, optimized pulse patternarrangement is proposed here. Switching sequences of

modified SVM pulse pattern arrangement for regions l, 2, 3,and 4 of sector 1 are shown in fig.5. Here, two redundantpositive and negative small vectors are used for neutral pointvoltage control. Switching sequence in opposite sectors (1-4,

2-5 and 3-6) is selected to be of a complimentary nature forneutral point balancing.

VI. EXPERIMENTAL RESULTS AND DISCUSSION

The photograph of hardware prototype of three-level

inverter is shown in fig.6. The proposed scheme is tested on a45 kW three-phase induction motor drive with open loop V/fcontrol for different modulation indices covering the entirespeed range. The dc link voltage of around 600 V is used, thus

the individual dc link capacitor voltages are kept around 300V. The carrier frequency used for PWM generation is limitedto 2 kHz. The open loop dc link capacitor voltage-balancingscheme is implemented using DSP-TMS320F2811 control

card. The 3-level SVPWM scheme is used for the PWMsignal generation, based on the sampled amplitudes ofreference phase voltages. The line voltage and line current

Fig. 8. Line Voltage & Line Current Waveforms at 20 Hz, mi = 0.69,

(X- axis: 1 div = 10 ms, Y- axis: 1 div= 20 A, 1 div= 200 V)



Fig. 10. Line Voltage & Line Current Waveforms at 40 Hz, mi =1.38,

(X- axis: 1 div = 5 ms, Y- axis: 1 div= 20 A, 1 div= 200 V)Fig. 7. Line Voltage & Line Current Waveforms at 10 Hz, mi = 0.34,



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waveforms for inverter operation in inner layer (two-level) arepresented in Figs. 7 and 8. The line voltage and line currentwaveforms for inverter operation in outer layer (three-level)

operation are presented in Figs. 9,10 and 11. The switchingcombinations from Positive Small Vector or Negative Small

Vector groups to bring back the capacitor voltages to their

balanced condition as shown in Fig.12. This proves theoperation of the dc link capacitor voltage-balancing scheme.The Results includes Output Line Voltage, Output Line

Current, DC Link voltages for no load condition of Inductionmotor.

The difference between capacitors voltage is observed lessthan 5 Volt as shown in fig.12. This proves the ability of openloop (self balancing) SVPWM scheme.

VII. CONCLUSIONIn this paper a self-balancing space vector pulse width

modulator is proposed to generate switching patterns for athree-level neutral point clamp inverter from an input

command voltage vector. The geometry of the voltagecomplex plane is utilized to define sectors, triangles andregions such that minimum on time violation belts can be

avoided naturally. The switching patterns available from thethree level inverter is arranged such that no direct switching

between positive and negative half buses is violated all timesand minimum switching is assured. The feasibility of the

proposed method has been proven via laboratory experiments.Furthermore, a low-cost implementation of the controltechnique has been shown to provide satisfactoryperformance. Therefore, the economical feasibility of thegeneral-purpose NPC three-level inverter in low voltage drive

applications has been strengthened and its application rangewidened.

REFERENCES

[1] Jos Rodriguez, Jih-Sheng Lai and Fang Zheng Peng MultilevelInverters: A Survey of Topologies, Controls, and Applications, IEEE

transactions on industrial electronics, vol. 49, no. 4, pp. 724738august 2002

[2] H. L. Liu, N. S. Choi, and G. H. Cho, DSP based space vector PWMfor three-level inverter with DC-link voltage balancing, in Proc. IEEE

IECON Conf., 1991, pp. 197203.[3] K. R. M. N. Ratnayake, Y. Murai, T. Watanabe, "Novel PWM scheme to

control neutral point voltage variation in three-level voltage source

inverter", in proc. 1999 ofIEEE Ind. App. 34h IAS Annual Meeting

Conf:, vol. 3, pp.1950 - 1955.

[4] S. Ogasawara and H. Akagi, "Analysis of variation of neutral pointpotential in neutral-point-clamped voltage source PWM Inverters", in

Proc. 1993IEEE Industrial Applications Society Conf:, pp. 965-970.

[5] A. Nabae, I. Takahashi, and H. Akagi, A new neutral point clampedPWM inverter,IEEE Trans. Ind. Appl., vol. IA-17, no. 5, pp. 518523,

Sep./Oct. 1981.

[6] Nikola Celanovicand Dushan Boroyevich, A Comprehensive Study ofNeutral-Point Voltage Balancing Problem in Three-Level Neutral-Point-Clamped Voltage Source PWM Inverters,IEEE transactions on power

electronics, vol. 15, no. 2, pp.242-249, March 2000

[7] B. Wu, High-Power Converters and AC Drives, IEEE Press and Wiley, 2006, pp 143-176.

[8] C. Newton and M. Summer, "Neutral point control for multi-levelinverters: Theory, design and operation limitations," in Proc. 1997,IEEE

IAS Conf: Rec., pp. 1336-1343.

[9] K. Yamanaka, A. M. Hava, H. Kirino, Y. Tanaka, N. Koga and T. J.Kume, "A novel neutral potential stabilization technique using the

information of output current polarities and voltage vector," IEEE Trans.

on Ind. App., vol. 38(6), pp. 1572-1580, Nov/Dec. 2002.

[10] R. S. Kanchan, P. N. Tekwani and K. Gopakumar, Three-Level InverterScheme With Common Mode Voltage Elimination and DC Link

Capacitor Voltage Balancing for an Open-End Winding Induction Motor

Drive,IEEE transactions on power electronics, vol. 21, no. 6, pp.1976-

1683 November 2006[11] J. 0. P. Pinto, B. K. Bose, L. E. B. Da Silva and M. P. Kazmierkowski,"Neural-network-based space-vector PWM controller for voltage-fed

inverter induction motor drive", IEEE Trans. Ind. App., vol. 36(6), pp.

1628-1636, Nov/Dec 2000.

[12] Kalpesh H. Bhalodi, and Pramod Agrawal, Space Vector Modulationwith DC-Link Voltage Balancing Control for Three-Level Inverters,

IEEE Conf. PEDES., Dec.2006, pp.1-6.

[13] R. S. Kanchan, M. R. Baiju, K. K. Mohapatra, P. P. Ouseph, and K.Gopakumar, Space vector PWM signal generation for multi-level

inverters using only the sampled amplitudes of reference phase

voltages, inProc. Inst. Elect. Eng., Mar. 2005, vol. 152, no. 2, pp. 297

309.



Fig. 12. DC Link Capacitors Voltages Vc1 and Vc2

(X- axis: 1 div = 1 ms, Y- axis: 1 div= 50 V)

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