PT55 User Manual Rev.0.4 - SingMai Electronics User Manual Rev.0.4.pdf · aCVi_Cin.v ... PT55 User...

SingMai Electronics

PT55 User Manual Revision 0.4 of 32

PT55

Advanced CompositeVideo Interface:Encoder IP Core

User Manual

Revision 0.417th July 2016

SingMai Electronics


Revisions

Date Revisions Version

01-05-2016 First Draft. 0.1

28-05-2106 Timing diagrams updated.Block diagram updated.

0.2

13-07-2016 1080i standards added.IP core resource usage added.aCVi description modified.Data transfer description added.Cable compensation description added.Simulation information added.Altera encryption description added.

0.3

17-07-2016 FPGA resource use updated.Reg_clk port removed.Insertion test signal modified.Data transmit register locations corrected.Register address range changed to A[4:0].Text corrections and additions.

0.4

SingMai Electronics


Contents

Revisions .................................................................................................................................................. 2Contents................................................................................................................................................... 3Tables ....................................................................................................................................................... 3Figures...................................................................................................................................................... 31. Introduction ................................................................................................................................... 52. PT55 Module description...............................................................................................................63. Signal Interconnections................................................................................................................. 74. aCVi Overview .............................................................................................................................. 105. Technical Overview.......................................................................................................................12

aCVi_encoder.v ..................................................................................................................................12aCVi_Register_control.v ....................................................................................................................12aCVi_Yin.v...........................................................................................................................................12aCVi_Cin.v...........................................................................................................................................13aCVi_SPG.v ........................................................................................................................................ 14aCVi_Modulator.v ............................................................................................................................. 16aCVi_Preemphasis.v...........................................................................................................................17

6. aCVi Cable Compensation............................................................................................................207. Data Transfers ...............................................................................................................................218. Register interface ........................................................................................................................ 259. Register descriptions ...................................................................................................................2610. Output Interface.......................................................................................................................2811. PT55 Simulation.............................................................................................................................3112. Altera Encrypted files .................................................................................................................. 32

Tables

Table 1 PT55 Altera FPGA resource requirements.................................................................................. 5Table 2 PT55 Verilog file structure. .........................................................................................................6Table 3 PT55 Input/Output signals..........................................................................................................8Table 4 aCVi supported video formats. ................................................................................................ 10Table 5 aCVi Line and carrier frequencies..............................................................................................17Table 6 Data transfer instructions: Receiver > Transmitter ................................................................ 22Table 7 aCVi Control words Transmitter > Receiver............................................................................. 22Table 8 Register Descriptions. .............................................................................................................. 27Table 9 Encrypted file naming. ............................................................................................................. 32

Figures

Figure 1 PT55 Block schematic. ............................................................................................................... 7Figure 2 aCVi Spectrum. ......................................................................................................................... 11Figure 3 PT55 Block diagram. .................................................................................................................12Figure 4 Luma low pass filter frequency response. ..............................................................................13Figure 5 Cb/Cr Interpolation filter response......................................................................................... 14Figure 6 720p/60 Horizontal Timing. .....................................................................................................15Figure 7 720p/50-60Hz Vertical Timing. .................................................................................................15Figure 8 1080p/30 Horizontal Timing.................................................................................................... 16Figure 9 1080p/25-30Hz Vertical Timing. .............................................................................................. 16Figure 10 Sinx/x Filter response. ........................................................................................................... 18Figure 11 Pre-emphasis filter response - RG59 cable. ........................................................................... 18Figure 12 aCVi output, 30MHz sweep (Pre-emphasis = minimum)...................................................... 19Figure 13 aCVi output, 30MHz sweep (Pre-emphasis = maximum)..................................................... 19Figure 14 Insertion test signal. ..............................................................................................................20

SingMai Electronics


Figure 15 aCVi Data format. ....................................................................................................................21Figure 16 SM06 UTP cable data receiver. ............................................................................................. 23Figure 17 SM06 Coaxial data receiver. .................................................................................................. 24Figure 18 aCVi Tx Register control. ....................................................................................................... 25Figure 19 PT21 coaxial output stage......................................................................................................29Figure 20 PT21 twisted pair output stage. ............................................................................................30

SingMai Electronics


1. Introduction

PT55 is an aCVi encoder IP (intellectual property) core compatible with the aCVi AdvancedComposite Video Interface.

aCVi is a method to transmit high quality HD video over existing coaxial/twisted-pair cablenetworks or allow the use of less expensive RG-59/UTP cable in long distance installations.

The encoder IP accepts separate YCbCr 4:2:2 digital component data together with its video clock(74.25MHz/74.17582418MHz) and horizontal and vertical timing signals, which it encodes to asingle 10 bit straight binary composite output for driving a suitable DAC (digital to analogueconverter) and amplifier. PT55 supports 720p-50Hz/59Hz/60Hz, 1080p-24Hz/25Hz/29Hz/30Hz and1080i-50Hz/59Hz/60Hz video formats.

Control and status registers are written to and read from using a conventional 8 bit widemicroprocessor interface.

The intellectual property block is provided as RTL compliant Verilog-2001 source code for FPGAsfrom all vendors or for ASICs.

Typical resource usage for an Altera FPGA is shown in Table 1.

Logic Cells Memory Bits M9K blocks 9x9 Multipliers 18x18 multipliers

11066 33158 7 2 8

Table 1 PT55 Altera FPGA resource requirements

An approximate equivalent for ASIC resource usage is 12406 LCs (logic cell only compile for AlteraFPGA) x 14 ~ 173k 2 input NAND gate equivalent. The memory is one 13k of single port ROM (512 x24) and one 20k single port ROM (1280 x 10).

SingMai Electronics


2. PT55 Module description

The PT55 aCVi encoder IP core comprises 10 Verilog modules in a hierarchical structure, (see Table2).

aCVi_encoder.v

aCVI_Register_control.v

aCVi_Cin.v

aCVi_Yin.v

aCVI_Tx_SPG.v

aCVi_Modulator.v Tx_SinCos_ROM.v

aCVi_Preemphasis.v Multiburst30_720_Y.v

aCVi_data.v

Table 2 PT55 Verilog file structure.

The top level file is aCVi_encoder.v which, in turn, calls seven of the other modules.aCVi_Modulator.v calls a third level file, Tx_SinCos_ROM.v and aCVi_Preemphasis.v callsMultiburst30_720.Y.v.

SingMai Electronics


3. Signal Interconnections

The PT55 signal interconnect diagram is shown in Figure 1.

Figure 1 PT55 Block schematic.

The signal descriptions are shown in Table 3, below.

Inputs

Signal Description

Clk74 Luma pixel clock input (74.25MHz/ 74.17582418MHz). Alldata inputs should be valid at the rising edge of this clock.

Clk148 Twice the Clk74 input frequency(148.5MHz/148.3516484MHz). Output data is valid on therising edge of this clock. Rising edges of Clk74 and Clk148should be coincident.

RESETn Asynchronous active low reset signal. Asserting this inputsets all the control registers to their default value andresets all registers.

A[4:0] Control address bus input used to select the controlregister to be written to/read from.

Din[7:0] Control data input bus.

aCVi_Tx_CSn Control chip select input, active low. Used in combinationwith the WRn input to control writing to the controlregisters.

SingMai Electronics


aCVi_Tx_WRn Active low write enable input. Used in combination withthe CSn input to control writing to the control registers.

HSync_in Horizontal synchronization input. For 720p/60Hz operationthis input is at 45kHz. Active low input, the falling edge isthe 0H timing reference point. This input must be at least 4Clk74 clock periods wide.

VSync_in Vertical synchronization input. For 720p/60Hz operationthis input is at 60Hz. Active low input, the falling edge isthe 0V timing reference point. This input must be at least 4Clk74 clock periods wide.

FSync_in Frame synchronization input. For interlaced inputs thisinput indicates the first (=’0’) or second (=’1’) field of theframe. For non-interlaced inputs this input should be tiedto ‘0’.

Y_in[9:0] Y (luma) input to the encoder. The input is straight binary,blanking level is 6410 and peak level 96010. The data inputshould be valid at the rising edge of Clk74. Y_in[9] is theMSB. If the input is 8-bits wide, the bottom 2 bits should betied to ‘0’.

Cb_in[9:0] Cb (B-Y chroma) input to the encoder. The input is offsetbinary, blanking level is 51210. The data input should bevalid at the rising edge of Clk74. Cb_in[9] is the MSB. If theinput is 8-bits wide, the bottom 2 bits should be tied to ‘0’.

Cr_in[9:0] Cr (R-Y chroma) input to the encoder. The input is offsetbinary, blanking level is 51210. The data input should bevalid at the rising edge of Clk74. Cr_in[9] is the MSB. If theinput is 8-bits wide, the bottom 2 bits should be tied to ‘0’.

Outputs

Signal Description

aCVi_Tx_Register_out[7:0] Control output data bus. Outputs the control/statusregister data selected by the A[4:0] bus.

CSync Digital composite sync output.

aCVi_out[9:0] Encoded aCVi output data. aCVi_out[9] is the MSB. Theoutput is straight binary coded and is valid at the risingedge of Clk148.

aCVi_test[1:0] Test outputs. Do not connect.

Table 3 PT55 Input/Output signals

SingMai Electronics


The Verilog instantiation of PT55 is shown below:

aCVi_encoder aCVi_encoder_inst(

.Clk74(Clk74_sig) , // input Clk74_sig

.Clk148(Clk148_sig) , // input Clk148_sig

.RESETn(RESETn_sig) , // input RESETn_sig

.A(A_sig) , // input [4:0] A_sig

.Din(Din_sig) , // input [7:0] Din_sig

.aCVi_Tx_CSn(aCVi_Tx_CSn_sig) , // input aCVi_Tx_CSn_sig

.aCVi_Tx_WRn(aCVi_Tx_WRn_sig) , // input aCVi_Tx_WRn_sig

.HSync_in(HSync_in_sig) , // input HSync_in_sig

.VSync_in(VSync_in_sig) , // input VSync_in_sig

.FSync_in(FSync_in_sig) , // input FSync_in_sig

.Video_Vin(Video_Vin_sig) , // input Video_Vin_sig

.Y_in(Y_in_sig) , // input [9:0] Y_in_sig

.Cb_in(Cb_in_sig) , // input [9:0] Cb_in_sig

.Cr_in(Cr_in_sig) , // input [9:0] Cr_in_sig

.Data_in(Data_in_sig) , // input Data_in_sig

.aCVi_Tx_Register_out(aCVi_Tx_Register_out_sig) , // output [7:0] aCVi_Tx_Register_out_sig

.CSync(CSync_sig) , // output CSync_sig

.aCVi_out(aCVi_out_sig) , // output [9:0] aCVi_out_sig

.aCVi_test(aCVi_test_sig) // output [1:0] aCVi_test_sig);

SingMai Electronics


4. aCVi Overview

The following is a brief overview of the aCVi interface.

The basic concept of the aCVi interface is to build on the proven and reliable transport method ofNTSC, (the advantages of PAL – v.v. multi-path reception – is not relevant to a cable system soNTSC is used as the model). NTSC transmissions are capable of transmitting more than 1km acrossRG-59 cable but the bandwidth is limited to 5MHz.

Because the cable system is a closed system, it is only necessary for the transmitter and receiver to‘understand’ each other and we can modify the basic NTSC method to suit HD transmissions.

According to the SMPTE-296M specification, HD (74.25MHz sampling) video transmission requiresa luma bandwidth of 30MHz and chroma bandwidth of 15MHz. To save on system costs aCVisupports the 30MHz luma bandwidth but constrains the chroma bandwidth to 7.5MHz (4:1:1sampling).

The colour difference signals are modulated onto a carrier in quadrature so they effectively usethe same bandwidth: the chroma subcarrier is ~27.8MHz.. The high frequency luma and themodulated chroma overlap above 18.6MHz but because of the line to line phase relationship of thechroma, may be separated using a luine comb filter (and also because of the use of single chipimage sensors, there is usually little high frequency content to cause image artifacts).

The effective bandwidth of the complete signal is therefore approximately 9.3MHz (chroma uppersideband + filter roll off) + 27.8MHz or about 37MHz, setting a minimum sampling frequency of 2 x37MHz or 74MHz. For convenience we choose 74.25MHz as a sampling frequency as this is relatedto the SMPTE272M standard; (see Figure 2).

For transmission over 300m of RG-59 cable we can expect 18dB loss at higher frequencies(6.2dB/100m @ 50MHz). However the synchronizing signals are at a much lower frequency wherethe loss is only about 1-2dB so reliable rastering of the received signal should always be assured.

The peak to peak video level of aCVi is 1.26V (100% colour bars) which maintains compatibility withany legacy SD equipment on the network and also allows common low-power 3.3V drivers to beused.

Table 4 lists the currently supported video formats for aCVi.

Format Pixels/line Line frequency FSC/FH ratio Subcarrier

720p/50Hz 1980 37.500kHz 741.5 27.80625MHz

720p/59.94Hz1 1650 44.955kHz 618.5 27.804695MHz

720p/60Hz 1650 45.000kHz 617.5 27.7875MHz

1080p/24Hz 2750 27.0kHz 1029.5 27.7965MHz

1080p/25Hz 2640 28.125kHz 988.5 27.8015625MHz

1080p/29.97Hz1 2200 33.716kHz 824.5 27.7990759MHz

1080p/30Hz 2200 33.750kHz 823.5 27.793125MHz

1080i/50Hz 2640 28.125kHz 988.5 27.8015625MHz

1080i/59.94Hz1 2200 33.716kHz 824.5 27.7990759MHz

1080i/60Hz 2200 33.750kHz 823.5 27.793125MHz

Table 4 aCVi supported video formats.

1 Input clock is 148.3516484MHz (else 148.5MHz).

SingMai Electronics


Figure 2 aCVi Spectrum.

SingMai Electronics


5. Technical Overview

A simplified block diagram of the PT55 aCVi encoder is shown in Figure 3.

Figure 3 PT55 Block diagram.

aCVi_encoder.v

This is the top level design file and it interconnects all the following modules.The PT55 accepts separate Y, Cb and Cr inputs together with their associated horizontal, verticaland frame-ID syncs and rising edge aligned 74.25MHz/74.17582418MHz and148.5MHz/148.3516484MHz clocks.

aCVi_Register_control.v

A conventional 8 bit microprocessor style control interface is used to write and read to the PT55control registers. Details of the interface may be found in Chapter 8 and the register descriptionsmay be found in Chapter 9.

aCVi_Yin.v

An offset of 6410 is subtracted from the Y input to force the nominal black level of the input downto a digital value of 0. The resulting output is low pass filtered using a 23 tap FIR filter, with a passband of 29.7MHz and a stop band of 37.125MHz. The filter response is shown below.

SingMai Electronics


Figure 4 Luma low pass filter frequency response.

aCVi_Cin.v

The Cb and Cr inputs are at half of the Clk_in frequency (37.125MHz) and should be applied to theCb[9:0] and Cr[9:0] input ports; (again the bottom two LSBs should be tied to ground if the inputis 8-bit).

The Cb and Cr (chroma) inputs are offset binary with an expected blanking level of 51210. Theinputs are latched on the rising edge of the Clk74 input.

The Cb and Cr inputs are converted to 2’s complement format and then interpolated from37.125MHz (4:2:2) mode to 74.25MHz in a 95-tap FIR filter. The filter has a pass-band of 7.5MHz anda stop band attenuation of > -50dB at 9.3MHz. The filter response is shown below.

Inphase Filter Frequency Response

Frequency in MHz

Mag

nit

ud

ein

dB

0 4 8 12 16 20 24 28 32 36 40-60

-55

-50

-45

-40

-35

-30

-25

-20

-15

-10

-5

0

5

SingMai Electronics


Figure 5 Cb/Cr Interpolation filter response.

Horizontal and vertical blanking is applied to the output.

aCVi_SPG.v

Hin (horizontal), Vin (vertical field) and Fin (frame – if the input is interlaced) signals are used forpicture synchronization.

The falling edge of the horizontal pulse input is used to reset a 12-bit counter clocked at 74.25MHz.This is the 0H reference for the horizontal timing according to the SMPTE specifications and is themid-point of the analogue tri-level synchronizing pulse.

The outputs of this horizontal counter are decoded to produce blanking, synchronization, burstgate and broad pulses. The positions of these pulses are preset according to the selected videostandard.

Similarly the falling edge of the vertical pulse input is used to reset an 11-bit counter clocked at thebeginning of each horizontal line (e.g. a line counter). The outputs from this counter are decodedto produce the vertical sync and blanking pulses. The positions of these pulses are presetaccording to the selected video standard.

A composite sync pulse is formed from gated combinations of the horizontal, vertical and broadpulses. An analogue version of the digital pulse is also created using a look-up table, giving theedges an approximate raised cosine shape to avoid ringing during the transmission. The 10-90%transition time of the sync edges is approximately 215ns. The amplitude of the sync pulse can beset by Register $08.


Frequency in MHz

Mag

nit

ud

ein

dB

0 2 4 6 8 10 12-70

-60

-50

-40

-30

-20

-10

0

10

SingMai Electronics


Figure 6 720p/60 Horizontal Timing.

Figure 7 720p/50-60Hz Vertical Timing.

SingMai Electronics


Figure 8 1080p/30 Horizontal Timing.

Figure 9 1080p/25-30Hz Vertical Timing.

aCVi_Modulator.v

The luma and chroma are frequency modulated onto a carrier, generated using a 32 bit ratiocounter clocked from the 148.5MHz clock. The carrier seed is preset according to the videostandard as shown in Table 5.

32sc

1sc

2

seedsubcarrier

360

θ

148.5MHz

F

lineperpixels

lineperchangephase

ratio

SingMai Electronics


Format Pixels/line Line frequency FSC/FH ratio Subcarrier Seed value

720p/50Hz 1980 37.500kHz 741.5 27.80625MHz 2FEF7354H

720p/59.94Hz1 1650 44.955kHz 618.5 27.804695MHz 2FFB08F6H

720p/60Hz 1650 45.000kHz 617.5 27.7875MHz 2FE72CFEH

1080p/24Hz 2750 27.0kHz 1029.5 27.7965MHz 2FEB25CBH

1080p/25Hz 2640 28.125kHz 988.5 27.8015625MHz 2FED61BEH

1080p/29.97Hz1 2200 33.716kHz 824.5 27.7990759MHz 2FF88D7EH

1080p/30Hz 2200 33.750kHz 823.5 27.793125MHz 2FE9A87EH

1080i/50Hz 2640 28.125kHz 988.5 27.8015625MHz 2FED61BEH

1080i/59.94Hz1 2200 33.716kHz 824.5 27.7990759MHz 2FF88D7EH

1080i/60Hz 2200 33.750kHz 823.5 27.793125MHz 2FE9A87EH

Table 5 aCVi Line and carrier frequencies.

1 Input clock is 148.3516484MHz (else 148.5MHz).

The top 11 bits of this ratio counter (the phase word) are used by the demodulator to generate thesine and cosine waveforms.

The subcarrier phase word is used to address a ROM containing sine and cosine values. A sampleof the sine waveform is added, after shaping, to the back porch of the video signal to synchronisethe chroma demodulator of the receiver. This colour burst is blanked during the field pulse. Theamplitude of the colour burst is programmable by Register $07.

The interpolated Cb and Cr chroma inputs are multiplied by two scaling coefficients, U = 0.493Cb,V=0.877Cr. These are multiplied in turn by the sine and cosine waveforms. The resultingU.sin(2πFsc.t) and V.cos(2πFsc.t) data is added together to form the final chroma signal which isscaled by the UV_scaling register value, Register $06.

aCVi_Preemphasis.v

The luma, sync, chroma and burst are added to create the complete aCVi output waveform.

A sinx/x filter is applied to the composite signal to compensate for the high frequency samplinglosses in the output DAC. The response of the sinx/x filter is shown in Figure 10.

SingMai Electronics


Figure 10 Sinx/x Filter response.

This resulting signal is then subjected to a variable degree of pre-emphasis with a maximum boostof >24dB at >50MHz. The pre-emphasis filter is a 5 tap FIR.

The degree of pre-emphasis is dependent on the cable length and is designed to approximatelycompensate for the loss of >300m of RG-59 or UTP cable. The response of the pre-emphasis filteris shown below.

Figure 11 Pre-emphasis filter response - RG59 cable.


Frequency in MHz

Mag

nit

ud

ein

dB

0 10 20 30 40 50 600.0

0.4

0.8

1.2

1.6

2.0

2.4

2.8

3.2

3.6


Frequency in MHz

Ma

gn

itu

de

ind

B

0 10 20 30 40 50 60 70 80-25.0

-22.5

-20.0

-17.5

-15.0

-12.5

-10.0

-7.5

-5.0

-2.5

0.0

SingMai Electronics


The resulting digital aCVI encoded output should be input to a digital to analogue converter (DAC)and then buffered to drive the cable.

Figure 12 aCVi output, 30MHz sweep (Pre-emphasis = minimum).

Figure 13 aCVi output, 30MHz sweep (Pre-emphasis = maximum).

SingMai Electronics


6. aCVi Cable Compensation

The following description only applies to aCVi video.

Figure 14 Insertion test signal.

To be completed.

SingMai Electronics


7. Data Transfers

The following description only applies to aCVi video.

The aCVi interface allows for the bi-directional transmission of control data between thetransmitter and receiver. The data is transferred during two dedicated lines of the vertical blankinginterval, one for transmitter to receiver transmission, the other for receiver to transmitter. Thepre-defined video lines used for the transfer of data are the same for all standards. Data istransmitted between transmitter to receiver on Line 7 and between receiver and transmitter online 8.

One byte of data is sent for each line, allowing a maximum of 60 bytes (480 bits) to be transferredeach second (for a 60Hz frame rate).

The format of the data transfer is shown in Figure 15.

Figure 15 aCVi Data format.

The format is the same regardless of the direction of transfer. The symbol rate is 2.32MHz(74.25/MHz/32) which allows reliable transfer even without the correct cable equalization.

The first 8 bits are the framing byte which is a unique code signifying the beginning of data. Thereceiving device must monitor the pre-defined vertical blanking line for this framing byte.

The next four bits are a control word which defines the function of the following data byte. Thecontrol words between transmitter and receiver and receiver and transmitter are different. (SeeTables 6 and 7). Three control words are reserved and must not be used.

SingMai Electronics


C3 C2 C1 C0 Decimal Function

0 0 0 0 0 Pre-emphasis value for transmitter (auto cable equalization)

0 0 0 1 1 Select video Pattern:$00 – Video$01 – 75% colour bars$02 – 30MHz luma frequency sweep$03 – 2T/30T pulse bar

0 0 1 0 2

0 0 1 1 3

0 1 0 0 4

0 1 0 1 5

0 1 1 0 6

0 1 1 1 7

1 0 0 0 8

1 0 0 1 9

1 0 1 0 10

1 0 1 1 11

1 1 0 0 12

1 1 0 1 13

1 1 1 0 14

1 1 1 1 15

Table 6 Data transfer instructions: Receiver > Transmitter

C3 C2 C1 C0 Decimal Function

0 0 0 0 0 Interface test.

0 0 0 1 1

0 0 1 0 2

0 0 1 1 3

0 1 0 0 4

0 1 0 1 5

0 1 1 0 6

0 1 1 1 7

1 0 0 0 8

1 0 0 1 9

1 0 1 0 10

1 0 1 1 11

1 1 0 0 12

1 1 0 1 13

1 1 1 0 14

1 1 1 1 15

Table 7 aCVi Control words Transmitter > Receiver

The next three bits must be a 010 sequence (to ensure the uniqueness of the framing byte). Thenext 9 bits are the data for the control function. This is an 8-bit byte with any value between 0 and255. The data byte is separated into ‘nibbles’ each of 4 bits, separated by a ‘0’, again to ensure theuniqueness of the framing byte.

The last two bits are parity bits, one for the control word and one for the data word. The paritybits are both even parity.

The total length of the data sequence is 27 bits. Each symbol (bit) is 32 x 1/74.25MHz long = 430ns.The low bit rate ensures that the data is received over long cable lengths even if the pre-emphasisis incorrectly set, (the symbol length equates to a 2.23MHz data rate, which is attenuated<2dB/100m of cable).

The total data sequence length is just under 12µs and it should be positioned centrally in the activevideo period, although the exact position is not important.

SingMai Electronics


To transmit a data word: first the control word must be written to the register $11. Next the dataword is written to register $12. Once this is written the two words are signalled for transfer on thenext video frame. A status bit, write busy, is set during this time (register $13, bit 0): further datatransfers should not be initiated until this bit is reset.

Figures 16 and 17 show the schematics used on the PT55 evaluation module (SM06) to buffer andslice the vertical interval data sent from the aCVi receiver to the transmitter.

U10-A buffers the output aCVi video. J9 selects the input from either the coaxial connector(connect J9 pins 1-2) or the UTP connector (connect J9 pins 2-3). U10-B filters the input signal andC50 and D3 form a sync tip clamp to ensure stable DC levels into the data slicer. The data slicer isformed by comparator U10-D and buffered by U11 before being decoded by the PT55 aCVi encoderIP core.

Figure 16 SM06 UTP cable data receiver.

SingMai Electronics


Figure 17 SM06 Coaxial data receiver.

SingMai Electronics


8. Register interface

Figure 18 shows the timing diagram for the register interface; it is a conventional microprocessorinterface. Each register is selected via a 6 bit address bus. Writes to unused register locations areignored.

To write to the selected register the aCVi_Tx_CSn (chip select) input must be asserted low and theA[4:0] register address and the data for this register set up. The aCVi_Tx_WRn input must then bedriven low and high again: On the rising edge of this pulse the data is latched into the addressselected. The aCVi_Tx_CSn input should then be returned high.

For the write to occur reliably the address (A[4:0]) and data (Din[7:0]) must be stable and validduring the low to high transition of the aCVi_Tx_WRn pulse.

The address input also selects the register data that is presented on theaCVi_Tx_Register_out[7:0] bus. This output is independent of the aCVi_Tx_CSn or aCVi_Tx_WRninputs.

Figure 18 aCVi Tx Register control.

SingMai Electronics


9. Register descriptions

Table 8 lists all of the control and status registers. All of the registers are 8 bit; unused register bitsread back as zeros.

Please note that some registers can be set to values that are illegal and will produce invalidoutputs.

Asserting the RESETn input sets the PT55 registers to their default values.

RegisterOffset

Register Name R/W Bit Value Description

Control Registers

$01 Control 1 R/W aCVi Tx control (video standard)

7-4 Not used.

3-0 Value Standard

0000 720p25

0001 720p30

0010 720p50

0011 720p59

0100 720p60

0101 1080p24

0110 1080p25

0111 1080p29

1000 1080p30

1001 1080i50

1010 1080i59

1011 1080i60

Video Input

$04 aCVi_gain_value R/W 7:0 8 bit unsigned value setting the amplitude of the output aCViwaveform. Default value = 12810. Value range = 0-16610

$05 Luma_scaling R/W 7:0 8 bit unsigned value setting the amplitude of the output Y(luma) component. Default value = 12810. Value range = 0-16610

$06 UV_scaling R/W 7:0 8 bit unsigned value setting the amplitude of the output UV(chroma) component. Default value = 12810. Value range = 0-16610

$07 Burst amplitude R/W 7:0 8 bit unsigned value setting the amplitude of the outputchroma burst component. Default value = 12810. Value range = 0-16610

$08 Sync_scaling R/W 7:0 8 bit unsigned value setting the amplitude of the outputcomposite sync waveform. Default value = 12810. Value range =0-16610

$09 Black_level R/W 7:0 8 bit signed value setting the DC offset value for active video(pedestal). Default value = 010. Value range = -128 - +12710

Output stage

$10 Pre-emphasis gain R/W 7:0 Controls the degree of pre-emphasis applied to the aCVi output.Default = 0 = no pre-emphasis. Maximum pre-emphasis = 25510.

Data Insertion control

$11 Data_Instruction R/W 3:0 Instruction word to be transmitted between receiver andtransmitter.

$12 Data_Word R/W 7:0 Data word to be transmitted between receiver and transmitter.Transmission is initiated when writing to this register.

$13 Tx_status R 7:1 Not used

0 When the data word is written for transmission (register $4D)this bit will be set to ‘1’. When the data has been transmitted(the next occurring line 8) the flag will be reset to ‘0’. New datashould not be written for transmission while this flag is high.

$14 Rx_Data_instruction

R 3:0 Received data instruction.

$15 Rx_Data_word R 7:0 Received data word.

$16 Rx_status R 7:6 Not used.

5 Calculated instruction word parity.

SingMai Electronics


RegisterOffset

Register Name R/W Bit Value Description

4 Received instruction word parity.

3:2 Not used.

1 Calculated data word parity.

0 Received data word parity.

Table 8 Register Descriptions.

SingMai Electronics


10. Output Interface

The output of the aCVi encoder is 10-bit, straight binary, video data at 148.5MHz.

This has to be converted to analogue using a digital to analogue converter. On the evaluationboard (SM06) an Analog Devices 10-bit DAC, the AD9705, is used for this purpose.

The FPGA also provides a 148.5MHz clock for the DAC.

The analogue output from the DAC is then filtered to remove clock noise and amplified to 2.5V pk-pk, (100% colour bars), and driven through a 75Ω series resistor to the coaxial cable.

The schematics for this are shown in Figure 19, and for driving differentially into UTP cable, inFigure 20.

SingMai Electronics


Figure 19 PT21 coaxial output stage.

SingMai Electronics


Figure 20 PT21 twisted pair output stage.

SingMai Electronics


11. PT55 Simulation

To be completed.

SingMai Electronics


12. Altera Encrypted files

For evaluation of the PT55 using an Altera FPGA, SingMai can provide encrypted Verilog files,specific to the computer you will compile the design on. For us to provide these files SingMaineeds to have the NIC number of the computer you will be running Quartus on.

The encrypted files name have a similar naming to the original files – see Table 9. The files may becompiled and simulated exactly as the original files, the only difference is they cannot be viewed.

Original module name Encrypted module name

aCVI_Register_control.v aCVI_Register_control_enc.v

aCVi_Cin.v aCVi_Cin_enc.v

aCVi_Yin.v aCVi_Yin_enc.v

aCVI_Tx_SPG.v aCVI_Tx_SPG_enc.v

aCVi_Modulator.v aCVi_Modulator_enc.v

aCVi_Preemphasis.v aCVi_Preemphasis_enc.v

aCVi_data.v aCVi_data_enc.v

Tx_SinCos_ROM.v Tx_SinCos_ROM_enc.v

Multiburst30_720_Y.v Multiburst30_720_Y_enc.v

Table 9 Encrypted file naming.

First copy the files across into your main project directory.

It is necessary to add the design file to your project which is done by clicking on ‘Project’ and then‘Add/Remove Files in Project…’ (within Quartus II). See Figure

Next we need to tell Quartus where to find the associated license file.

Within Quartus click on ‘Tools’ and then ‘License Setup’. Click on the browse button to the right ofthe ‘License file’ dialog box and point to the PT55_license.dat file.

The files should then be able to be compiled and simulated.

The license file is unique to you but allows unlimited use of the PT55 across the whole family ofAltera programmable devices. It will usually expire 2 months after the date of issue. Please contactSingMai if you need an extension of this.

PT55 User Manual Rev.0.4 - SingMai Electronics User Manual Rev.0.4.pdf · aCVi_Cin.v ... PT55 User...

Documents

Transcript of PT55 User Manual Rev.0.4 - SingMai Electronics User Manual Rev.0.4.pdf · aCVi_Cin.v ... PT55 User...