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Protocol Translator MODBus User Manual
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Revision Table
Rev Detail of Change
01 Initial issue
02 Format and style update.
This document is in support of the Multitrode Translator.
Version 1.0.9
Revision 02
This document is valid for MultiTrode Translator firmware version 1.09 or newer.
Multitrode reserves the right to update this document without notification.
MULTITRODE® and MULTISMART® are registered trademarks of MultiTrode Pty Ltd in Australia, USA and many countries worldwide.
PUMPVIEW® is a registered trademark of MultiTrode Pty Ltd in Australia. Design registration is pending for the MultiSmart Pump Controller Remote and Base Modules in Australia, USA and many countries worldwide. Patents pending in Australia, USA and many
countries worldwide.
©2007 MultiTrode Pty Ltd. This publication is protected by copyright. No part of this publication may be reproduced by any process, electronic or otherwise, without the express written permission of MultiTrode Pty Ltd.
Although every attempt has been made to ensure the correctness of the information contained herein, no liability is accepted by Multitrode or its staff for any errata contained.
Protocol Translator MODBus User Manual
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Contents
1 Introduction .......................................................................................................................................7 1.1 The MultiTrode Translator ....................................................................................................................7
2 Quick Installation Guide...................................................................................................................8
3 MODBus Guide................................................................................................................................10 3.1 Introducing MODBus Protocol ...........................................................................................................10 3.2 The Query-Response Cycle................................................................................................................10 3.3 The Query.............................................................................................................................................10 3.4 The Response......................................................................................................................................11
3.4.1 RTU Mode...............................................................................................................................11 3.4.2 RTU Framing...........................................................................................................................11 3.4.3 How the Address Field is Handled ..........................................................................................12 3.4.4 How the Function Field is Handled..........................................................................................12 3.4.5 Contents of the Data Field.......................................................................................................13 3.4.6 Cyclic Redundancy Check [CRC]............................................................................................13
3.5 MultiTrode Translator Interfaces........................................................................................................14 3.5.1 MultiTrode MonitorPro.............................................................................................................14 3.5.2 MODBus Interface...................................................................................................................14 3.5.3 Locally Generated Points ........................................................................................................15
3.6 MODBus Commands...........................................................................................................................16 3.6.1 01 Read Coil Status ................................................................................................................16 3.6.2 02 Read Input Status...............................................................................................................17 3.6.3 03 Read Holding Registers......................................................................................................18 3.6.4 04 Read Input Registers..........................................................................................................19 3.6.5 05 Force Single Coil ................................................................................................................19 3.6.6 06 Preset Single Register........................................................................................................20 3.6.7 08 Diagnostics Function ..........................................................................................................21 3.6.8 15 (0F Hex) Force Multiple Coils .............................................................................................22 3.6.9 16 (10 Hex) Preset Multiple Registers.....................................................................................23
3.7 Mirror Input Status Mode ....................................................................................................................25 3.7.1 Configuring the MultiTrode Translator for Mirror Mode............................................................25
4 Specifications..................................................................................................................................26
5 Full List of MODBUS Points...........................................................................................................27
Figures Figure 1 Overview Connection Diagram.................................................................................................................8 Figure 2 MODBus query cycle..............................................................................................................................10
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1 Introduction Congratulations on the purchase of the advanced MultiTrode Translator. In order to gain maximum benefit from the use of the MultiTrode Translator it is recommended that a good understanding is developed of MODBus protocol. It is not the intention of this manual to cover this protocol in detail but only to explain its basic operation to assist with the functional installation of the unit.
1.1 The MultiTrode Translator The MultiTrode Translator gathers information from a MultiTrode MonitorPRO or Remote Reservoir Monitor by issuing continuous “assembled status” requests. This information is mapped to and stored in a pair of native databases (one for MODBus, one for DNP3) which can then be accessed by a Master using the appropriate protocol. Local inputs on the MultiTrode Translator are also placed into these databases. The Master may request control operations and/or point writes to control the MultiTrode device via the MultiTrode Translator. Control operations that relate to MultiTrode devices will be acknowledged immediately by the MultiTrode Translator and the appropriate MultiTrode command issued at the earliest possible time. The success or failure of a control operation is determined by subsequently reading status information for the relevant point.
The MonitorPRO is a state-of-the-art pump station supervisor, which has been specifically designed to provide a high level of motor protection, capable of monitoring and protecting pumps by measuring pump currents and voltages. The MonitorPRO, in conjunction with the MT2/3PC Pump Controllers have many desirable features. Together they provide a complete pump station management system, which is not only more efficient than conventional systems, but also provides a smaller, more-cost-effective and more reliable solution.
The MultiTrode Pump Controller (MTxPC) is an advanced microprocessor-based pump controller designed to control two or three pumps, depending on the model chosen. It is specifically designed for use in water and sewage pumping stations and provides automatic level control, pump alternation, pump protection logic and level alarms.
These two products form the Remote Terminal Unit MultiTrode Translator, which is connected to a Master SCADA system via land line or radio. The existing SCADA system works by using MultiTrode’s proprietary protocol working into special SCADA software. However, via the MultiTrode Translator all these MultiTrode points can be accessed via the MODBus protocol.
Protocol Translator MODBus User Manual
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2 Quick Installation Guide As the default setting of the MultiTrode Translator will meet most applications needs, the only necessity is to set the site address and desired protocol option of the unit to allow polling of the remote site by the SCADA or PLC controlling system.
• Connect the MultiTrode Translator as per diagram below.
Protocol Translator
Radio
MonitorPro
PC
10-30VDCPower Supply
Figure 1 Overview Connection Diagram
• Using HyperTerminal® or some similar terminal emulation program, send the word “login” to the MultiTrode Translator using [MB]Com. 2. The word “login should be preceded with a 1 second silent period. The login command is lower case and strictly “login” without an “enter”.
Default communication settings should be 9600bps, 1 Start bit, no Parity and 2 Stop bits.
The MultiTrode Translator will display the Main Menu to HyperTerminal®.
• From the Main Menu select option 1.
MultiTrode Translator (MultiTrode - DNP / MODBus converter) v1.00.
Main Menu.
1) MultiTrode Translator Address [1]
Change the MultiTrode Translator’s address to the address used by the Master to communicate with it.
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• Again from the Main Menu select option 2
MultiTrode Translator (MultiTrode - DNP / MODBus converter) v1.00.
Main Menu.
1) MultiTrode Translator Address [1]
2) Configure COM ports.
• By selecting option 1) Next port, the com. Port desired for DNP3 operation can be configured.
COM2 (RS-232) Port Configuration.
1) Next port
2) Protocol [MODBus Slave]
3) Baud rate [9600]
Select option 2) Protocol to set desired protocol.
• Press “Esc” twice and close down HyperTerminal®.
• Notice that the MTRX, MTTX, LEDs are polling.
• The MultiTrode units should now be available via the MultiTrode Translator by the Central Monitoring Facility [CMF].
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3 MODBus Guide
3.1 Introducing MODBus Protocol The common language used by most controllers is the MODBus protocol. This protocol defines a message structure that controllers will recognize and use, regardless of the type of networks over which they communicate. It describes the process a controller uses to request access to another device, how it will respond to requests from the other devices, and how errors will be detected and reported. It establishes a common format for the layout and contents of message fields.
The MODBus protocol provides an international standard that all controllers can use for passing messages. During communications on a MODBus network, the protocol determines how each controller will know its device address, recognize a message addressed to it, determine the kind of action to be taken, and extract any data or other information contained in the message. If a reply is required, the controller will construct the reply message and send it using MODBus protocol.
The following sections describe the MODBus commands as used in the MultiTrode Translator. Commands not listed are not supported by the MultiTrode Translator and if requested, an error message will be returned to the Master.
3.2 The Query-Response Cycle
RTU Device AddressFunction Code
CRC Error Check
Eight BitData Bytes
RTU Device AddressFunction Code
CRC Error Check
Eight BitData Bytes
MASTERRTU
SLAVERTU
MASTERRTU
QUERY
RESPONSE
Figure 2 MODBus query cycle
3.3 The Query The function code in the query tells the addressed Slave device what kind of action to perform. The data bytes contain any additional information that the Slave will need to perform the function. For example, function code 03 will query the Slave to read holding registers and respond with their contents. The data field must contain the information which tells the Slave at what register to start, and how many registers to read. The error check field provides a method for the Slave to validate the integrity of the message contents.
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3.4 The Response If the Slave makes a normal response, the function code in that response is an echo of the function code in the query the data bytes contain the data collected by the Slave, such as register values or status. If an error occurs, the function code is modified to indicate that the response is an error response, and the data bytes contain a code that describes the error. The error check field allows the Master to validate the integrity of the message.
3.4.1 RTU Mode
When controllers are set up to communicate on a MODBus network using RTU (Remote Terminal Unit) mode, each eight-bit byte in a message contains two four-bit hexadecimal characters. The main advantage of this mode is that its greater character density allows better data throughput than ASCII for the same baud rate. Each message must be transmitted in a continuous stream.
3.4.1.1 Coding System • Eight-bit binary, hexadecimal 0--9, A--F
• Two hexadecimal characters contained in each eight-bit field of the message
3.4.1.2 Bits per Byte • 1 start bit
• 8 data bits, least significant bit sent first
• 1 bit for even/odd parity—no bit for no parity
• 1 stop bit if parity is used—2 bits if no parity
3.4.1.3 Error Check Field • Cyclical Redundancy Check (CRC)
3.4.2 RTU Framing
In RTU mode, messages start with a silent interval period of at least 3.5 characters. This is most easily implemented as a multiple of character times at the baud rate that is being used on the network (shown as T1-T2-T3-T4 in the figure below). The first field then transmitted is the device address.
The allowable characters transmitted for all fields are hexadecimal 0--9, A--F Networked devices monitor the network bus continuously, including during the silent intervals. When the first field (the address field) is received, each device decodes it to find out if it is the addressed device.
Following the last transmitted character, a similar interval of at least a period of 3.5 characters marks the end of the message. A new message can begin after this interval.
The entire message frame must be transmitted as a continuous stream. If a silent interval period of more than 1.6 characters occurs before completion of the frame, the receiving device flushes the incomplete message and assumes that the next byte will be the address field of a new message.
Similarly, if a new message begins earlier than a period of 8.6 characters following a previous message, the receiving device will consider it a continuation of the previous message. This will set an error, as the value in the final CRC field will not be valid for the combined messages. A typical message frame is shown below.
START Address Function Data CRC Check END
T1-T2-T3-T4 8-bits 8-bits n x 8-bits 16-bits T1-T2-T3-T4
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3.4.3 How the Address Field is Handled
The address field of a message frame contains 1 byte or 8-bits for MODBus RTU protocol. Valid Slave device addresses are in the range of 0--247 decimal. The individual Slave devices are assigned addresses in the range of 1--247. A Master addresses a Slave by placing the Slave address in the address field of the message. When the Slave sends it’s response, it places it’s own address in this address field of the response to let the Master know which Slave is responding.
Address 0 is used for the broadcast address, which all Slave devices recognize.
When MODBus protocol is used on higher level networks, broadcasts may not be allowed or may be replaced by other methods.
3.4.4 How the Function Field is Handled
The function code field of a message frame contains 1 byte or eight bits for MODBus RTU protocol. Valid codes are in the range of 1-- 255 decimal. Of these 255 possible function codes only 9 codes are used by the MultiTrode Translator.
When a message is sent from a Master to a Slave device the function code field tells the Slave what kind of action to perform. Examples are:
• read the ON/OFF states of a group of discrete coils or inputs,
• read the data contents of a group of registers or
• write to designated coils or registers.
When the Slave responds to the Master, it uses the function code field to indicate either a normal (error-free) response or that some kind of error occurred (called an exception response). For a normal response, the Slave simply echoes the original function code. For an exception response, the Slave returns a code that is equivalent to the original function code with it’s most significant bit set to a logic 1. For example, a message from Master to Slave to read a group of holding registers would have the following function code:
• 0000 0011 (Hexadecimal 03)
If the Slave device takes the requested action without error, it returns the same code in it’s response. If an exception occurs, it returns:
• 1000 0011 (Hexadecimal 83)
In addition to it’s modification of the function code for an exception response, the Slave places a unique code into the data field of the response message. This tells the Master what kind of error occurred, or the reason for the exception. There are several error codes defined in MODBus but the MultiTrode Translator only returns two. These are:
• 01 - Illegal function (function code not recognised or supported)
• 02 - Illegal data address (referencing a point number that does not exist)
The Master device’s application program has the responsibility of handling exception responses. Typical processes are to post subsequent retries of the message, to try diagnostic messages to the Slave, and to notify operators.
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3.4.5 Contents of the Data Field
The data field is constructed using sets of two hexadecimal digits, in the range of 00 to FF hexadecimal. These can be made from a pair of ASCII characters, or from one RTU character, according to the network’s serial transmission mode.
The data field of messages sent from a Master to Slave devices contains additional information, which the Slave must use to take the action defined by the function code. This can include items like discrete and register addresses, the quantity of items to be handled, and the count of actual data bytes in the field.
For example, if the Master requests a Slave to read a group of holding registers (function code 03), the data field specifies the starting register and how many registers are to be read. If the Master writes to a group of registers in the Slave (function code 11 hexadecimal), the data field specifies the starting register, how many registers to write, the count of data bytes to follow in the data field, and the data to be written into the registers.
If no error occurs, the data field of a response from a Slave to a Master contains the data requested. If an error occurs, the field contains an exception code that the Master application can use to determine the next action to be taken. The data field can be non-existent (of zero length) in certain kinds of messages.
3.4.6 Cyclic Redundancy Check [CRC]
In RTU mode, messages include an error-checking field that is based on a CRC method. The CRC field checks the contents of the entire message. It is applied regardless of any parity check method used for the individual characters of the message.
The CRC field is two bytes, containing a 16-bit binary value. The CRC value is calculated by the transmitting device, which appends the CRC to the message. The receiving device recalculates a CRC during receipt of the message, and compares the calculated value to the actual value it received in the CRC field. If the two values are not equal, an error result is assumed and corrective action may be taken.
When the CRC is appended to the message, the low-order byte is appended first, followed by the high-order byte. The CRC generation algorithm is given in the table below.
Step 1 Load a 16-bit register with FFFF hex (all l’s). Call this the CRC register.
Step 2 Exclusive OR the first eight-bit byte of the message with the low order byte of the 16-bit CRC register, putting the result in the CRC register.
Step 3 Shift the CRC register one bit to the right (toward the LSB), zero-filling the MSB. Extract and examine the LSB.
Step 4 If the LSB is 0, repeat Step 3 (another shift). If the LSB is 1, Exclusive OR the CRC register with the polynomial value A001 hex (1010 0000 0000 0001).
Step 5 Repeat Steps 3 and 4 until eight shifts have been performed. When this is done, a complete eight-bit byte will have been processed.
Step 6 Repeat Steps 2 ... 5 for the next eight-bit byte of the message. Continue doing this until all bytes have been processed. The final content of the CRC register is the CRC value.
Step 7 When the CRC is placed into the message, it’s upper and lower bytes must be swapped.
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3.5 MultiTrode Translator Interfaces This section outlines the design of the MultiTrode Translator firmware. The MultiTrode Translator acts as a protocol converter for MultiTrode MonitorPro devices to MODBus by maintaining a database image in MODBus format. This database is accessible to the MODBus Masters through RS232 and/or FSK ports, using MODBus RTU function set.
3.5.1 MultiTrode MonitorPro
Connection to the MultiTrode MonitorPRO is via a dedicated RS-232 port. All information is retrieved using the “Assembled Status Request” Command. Once collected, this information is separated into four data types commonly used by MODBus for storage:
• Coils: Read/write single bit values (digital outputs) (0xxxx references)
• Input Status: Read only single bit values (digital inputs) (1xxxx references)
• Holding Registers: Read/write 16-bit values (analog outputs, configuration, modifiable registers) (4xxxx references)
• Input Registers: Read only 16-bit values (analog inputs, non-modifiable registers) (3xxxx references)
When a MODBus coil or holding register is modified, the associated MultiTrode command is sent to the MonitorPRO using MultiTrode protocol. The status of some of these coils and holding registers is available in an “Assembled Status Response”. For MODBus points where status is not available, the last written value is returned instead.
3.5.2 MODBus Interface
MODBus access is available via the second RS-232 port or the FSK port. The device will behave as a Slave and service the following Master function requests using the MODBus RTU protocol:
Function Description
01 Read Coil Status
02 Read Input Status
03 Read Holding Registers
04 Read Input Registers
05 Force Single Coil
06 Preset Single Register
15 Force Multiple Coils
16 Force Multiple Registers
08 Diagnostic Loop Back
Any other function codes in a request will result in a code 01 (Illegal Function) response.
There is a separate MODBus driver installed on each com port (except the one assigned to the Monitor PRO) functioning independently allowing simultaneous access via multiple ports.
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3.5.3 Locally Generated Points
The MultiTrode Translator generates some of its own data via its analogue and digital inputs. These points are depicted in the MODBus Point Map:
3.5.3.1 Digital Inputs Six digital inputs are available and appear as Input Status points (948 to 953). These inputs are individually configurable as normal or latched.
3.5.3.2 Normal Mode: In normal mode the Input Status Point reflects the instantaneous value of the digital input.
3.5.3.3 Latched Mode: In latched mode, a transition from 0 to 1 sets the Input Status Point to 1. A transition from 1 to 0 has no effect and the Input Status Point remains in the 1 state. As this Input Status Point is latched it needs to be reset before it can resume it function. Each input has an associated “clear latch” Output Coil. Writing a 1 to this coil sets the Input Status Point to the instantaneous value of the digital input.
Additionally, each digital input has an associated 32-bit accumulator that occupies a pair of holding registers (16 to 27). Writing zero to both of the holding registers of the pair will reset the accumulator.
3.5.3.4 Analogue Inputs Two analogue inputs appear as input registers. Each analogue input has an associated 16-bit byte that occupies an input registers (302 & 303). The values returned are pre-scaled. The pre-scaling of the analog inputs is done in the MultiTrode Translator Configuration Menu. See the MultiTrode Translator Installation Manual for further details on how to set up the pre-scaling.
3.5.3.5 MultiTrode Translator status Loss of communication between the MultiTrode Translator and MultiTrode MonitorPRO is reflected as a 1 in an Input Status Point 956.
A stale data indicator is available as an Input Status Point 957. This is cleared whenever new information arrives from the MonitorPRO. A timer is also started at this point and runs for a configurable period. When it expires, the stale data indicator is set. See the MultiTrode Translator Installation Manual for further details on setting the stale data timer period.
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3.6 MODBus Commands
3.6.1 01 Read Coil Status
Reads the ON/OFF status of discrete outputs coils (0xxxx references) in the Slave. Broadcast is not supported. When a read request is received the data is retrieved immediately from the MultiTrode Translator’s database and returned to the Master.
3.6.1.1 Query The query message specifies the starting coil and quantity of coils to be read. Coils are addressed starting at zero, i.e. coils 1--16 are addressed as 0--15. Following is an example of a query to read coils 20--56 from Slave device 17:
Field Name Example (Hex) Slave Address 11 Function 01 Starting Address Hi 00 Starting Address Lo 13 Number of Points Hi 00 Number of Points Lo 25 Error Check (LRC or CRC) --
3.6.1.2 Response The coil status in the response message is packed as one coil per bit of the data field. Status is indicated as: 1 = ON; 0 = OFF. The LSB of the first data byte contains the first coil addressed in the query. The other coils follow toward the high order end of this byte, and from low order to high order in subsequent bytes. If the returned coil quantity is not a multiple of eight, the remaining bits in the final data byte will be padded with zeros (toward the high order end of the byte). The Byte Count field specifies the quantity of complete bytes of data. Following is an example of a response to the above query:
Field Name Example (Hex) Slave Address 11 Function 01 Byte Count 05 Data (Coils 27--20) CD Data (Coils 35--28) 6B Data (Coils 43--36) B2 Data (Coils 51--44) 0E Data (Coils 56--52) 1B Error Check (LRC or CRC) --
The status of coils 27--20 is shown as the byte value CD hex, or binary 1100 1101. Coil 27 is the MSB of this byte, and coil 20 is the LSB. Left to right, the status of coils 27--20 is ON-ON-OFF-OFF-ON-ON-OFF-ON. By convention, bits within a byte are shown with the MSB to the left, and the LSB to the right. Thus the coils in the first byte are 27--20, from left to right. The next byte has coils 35--28, left to right. As the bits are transmitted serially, they flow from LSB to MSB: 20--27, 28--35, and so on.
In the last data byte, the status of coils 56--52 is shown as the byte value lB hex, or binary 0001 1011. Coil 56 is in the fourth bit position from the left, and coil 52 is the LSB of this byte. The status of coils 56--52 is: ON-ON-OFF-ON-ON.
Note: The three remaining bits (toward the high-order end) are zero-filled.
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3.6.2 02 Read Input Status
Reads the ON/OFF status of discrete inputs (1xxxx references) in the Slave. Broadcast is not supported. When a read request is received the data is retrieved immediately from the MultiTrode Translator’s database and returned to the Master.
3.6.2.1 Query The query message specifies the starting input and quantity of inputs to be read. Inputs are addressed starting at zero, i.e. inputs 1--16 are addressed as 0--15. Following is an example of a request to read inputs 10197--10218 from Slave device 17:
Field Name Example (Hex)
Slave Address 11
Function 02
Starting Address Hi 00
Starting Address Lo C4
Number of Points Hi 00
Number of Points Lo 16
Error Check (LRC or CRC) --
3.6.2.2 Response The input status in the response message is packed as one input per bit of the data field. Status is indicated as: 1 = ON; 0 = OFF. The LSB of the first data byte contains the first input addressed in the query. The other inputs follow toward the high order end of this byte, and from low order to high order in subsequent bytes.
If the returned input quantity is not a multiple of eight, the remaining bits in the final data byte will be padded with zeros (toward the high-order end of the byte). The Byte Count field specifies the quantity of complete bytes of data. Following is an example of a response to the query:
Field Name Example (Hex)
Slave Address 11
Function 02
Byte Count 03
Data (Inputs 10204 -- 10197) AC
Data (Inputs 10212 – 10205) DB
Data (Inputs 10218 -- 10213) 35
Error Check (LRC or CRC) --
The status of inputs 10204--10197 is shown as the byte value AC hex, or binary 1010 1100. Input 10204 is the MSB of this byte, and input 10197 is the LSB. Left to right, the status of inputs 10204--10197 is ON-OFF-ON-OFF-ON-ON-OFF-OFF
The status of inputs 10218--10213 is shown as the byte value 35 hex, or binary 0011 0101. Input 10218 is in the third bit position from the left, and input 10213 is the LSB. The status of inputs 10218--10213 is: ON-ON-OFF-ON-OFF-ON.
Note: The two remaining bits (toward the high order end) are zero-filled.
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3.6.3 03 Read Holding Registers
Read the binary contents of holding registers (4xxxx references) in the Slave. Broadcast is not supported. When a read request is received the data is retrieved immediately from the MultiTrode Translator’s database and returned to the Master.
3.6.3.1 Query The query message specifies the starting register and quantity of registers to be read. Registers are addressed starting at zero, i.e. registers 1--16 are addressed as 0--15. Following is an example of a request to read registers 40108--40110 from Slave device 17:
Field Name Example (Hex)
Slave Address 11
Function 03
Starting Address Hi 00
Starting Address Lo 6B
Number of Points Hi 00
Number of Points Lo 03
Error Check (LRC or CRC) --
3.6.3.2 Response The register data in the response message are packed as two bytes per register; with the binary contents right justified within each byte. For each register, the first byte contains the high order bits and the second contains the low order bits. Following is an example of a response to the query:
Field Name Example (Hex)
Slave Address 11
Function 03
Byte Count 06
Data Hi (Register 40108) 02
Data Lo (Register 40108) 2B
Data Hi (Register 40109) 00
Data Lo (Register 40109) 00
Data Hi (Register 40110) 00
Data Lo (Register 40110) 64
Error Check (LRC or CRC) --
The contents of register 40108 are shown as the two byte values of 02 2B hex, or 555 decimal. The contents of registers 40109--40110 are 00 00 and 00 64 hex, or 0 and 100 decimal respectively.
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3.6.4 04 Read Input Registers
Reads the binary content of input registers (3xxxx references) in the Slave. Broadcast is not supported. When a read request is received the data is retrieved immediately from the MultiTrode Translator’s database and returned to the Master.
3.6.4.1 Query The query message specifies the starting register and quantity of registers to be read. Registers are addressed starting at zero, i.e. registers 1--16 are addressed as 0--15. Following is an example of a request to read register 30009 from Slave device 17:
Field Name Example (Hex)
Slave Address 11
Function 04
Starting Address Hi 00
Starting Address Lo 08
Number of Points Hi 00
Number of Points Lo 01
Error Check (LRC or CRC) --
3.6.4.2 Response The register data in the response message are packed as two bytes per register, with the binary contents right-justified within each byte. For each register, the first byte contains the high-order bits and the second contains the low-order bits. Following is an example of a response to the query:
Field Name Example (Hex)
Slave Address 11
Function 04
Byte Count 02
Data Hi (Register 30009) 00
Data Lo (Register 30009) 0A
Error Check (LRC or CRC) --
The contents of register 30009 are shown as the two byte values of 00 OA hex, or 10 decimal.
3.6.5 05 Force Single Coil
Forces a single coil in the Slave unit (0xxxx reference) to either ON or OFF. When broadcast, the function forces the same coil reference in all attached Slaves.
When a force command is received, the MultiTrode Translator will update its database and pass a command through to the MonitorPRO via the “command queue”. The command queue is a MultiTrode Translator buffer area to queue commands to the MonitorPRO. The MultiTrode Translator then issues this command to the MonitorPRO at the next opportunity.
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Page 20 of 28 MultiTrode_MTT_MODBus_Manual_v1-0-9_R02.doc
3.6.5.1 Query The query message specifies the coil reference to be forced. Coils are addressed starting at zero, i.e. coil 1 is addressed as 0.
The requested ON/OFF state is specified by a constant in the query data field. A value of FF 00 hex requests the coil to be ON. A value of 00 00 requests it to be OFF. All other values are illegal and will not affect the coil. Following is an example of a request to force coil 173 ON in Slave device 17:
Field Name Example (Hex)
Slave Address 11
Function 05
Coil Address Hi 00
Coil Address Lo AC
Force Data Hi FF
Force Data Lo 00
Error Check (LRC or CRC) --
3.6.5.2 Response The normal response is an echo of the query, returned after the coil state has been forced. Following is an example of a response to the query:
Field Name Example (Hex)
Slave Address 11
Function 05
Coil Address Hi 00
Coil Address Lo AC
Force Data Hi FF
Force Data Lo 00
Error Check (LRC or CRC) --
3.6.6 06 Preset Single Register
Presets a value into a single holding register (4xxxx reference) in the addressed Slave unit. When broadcast, the function presets have the same register reference in all attached Slaves.
When a Preset command is received, the MultiTrode Translator will update its database and passes a command through to the MonitorPRO via the “command queue”. The command queue is a MultiTrode Translator buffer area to queue commands to the MonitorPRO. The MultiTrode Translator then issues this command to the MonitorPRO at the next opportunity.
Protocol Translator MODBus User Manual
MultiTrode_MTT_MODBus_Manual_v1-0-9_R02.doc Page 21 of 28
3.6.6.1 Query The query message specifies the register reference to be preset. Registers are addressed starting at zero, i.e. register 1 is addressed as 0. Following is an example of a request to preset register 40002 to 00 03 hex in Slave device 17:
Field Name Example (Hex)
Slave Address 11
Function 06
Register Address Hi 00
Register Address Lo 01
Preset Data Hi 00
Preset Data Lo 03
Error Check (LRC or CRC) --
3.6.6.2 Response The normal response is an echo of the query, returned after the register contents have been preset. Following is an example of a response to the query:
Field Name Example (Hex)
Slave Address 11
Function 06
Register Address Hi 00
Register Address Lo 01
Preset Data Hi 00
Preset Data Lo 03
Error Check (LRC or CRC) --
3.6.7 08 Diagnostics Function
MODBus function 08 provides a test for checking the communication system between the Master and Slave.
Only the “Return Query Data” diagnostic function is supported. This means that any data sent to the Slave will be echoed to the Master without any actions.
3.6.7.1 Query Here is an example of a request to Slave device 17 to Return Query Data. This uses a sub-function code of zero (00 00 hex in the two-byte field). The data to be returned is sent in the two-byte data field (A5 37 hex).
Field Name Example (Hex)
Slave Address 11
Function 08
Sub-function Hi 00
Sub-function Lo 00
Data Hi A5
Data Lo 37
Error Check (LRC or CRC) --
Protocol Translator MODBus User Manual
Page 22 of 28 MultiTrode_MTT_MODBus_Manual_v1-0-9_R02.doc
3.6.7.2 Response The normal response to the Return Query Data request is to loop-back the same data. The function code and sub-function code are also echoed.
Field Name Example (Hex)
Slave Address 11
Function 08
Sub-function Hi 00
Sub-function Lo 00
Data Hi A5
Data Lo 37
Error Check (LRC or CRC) --
The data fields in responses to other kinds of queries could contain error counts or other information requested by the sub-function code.
3.6.8 15 (0F Hex) Force Multiple Coils
This command forces each coil (0xxxx reference) in a sequence of coils to either ON or OFF ‘When broadcast, the function forces the same coil references in all attached Slaves. When a force command is received, the MultiTrode Translator will update its database and sends a command through to the MonitorPRO via the “command queue”. The command queue is a MultiTrode Translator buffer area to queue a command to the MonitorPRO. The MultiTrode Translator then issues this command to the MonitorPRO at the next opportunity.
3.6.8.1 Query The query message specifies the coil references to be forced. Coils are addressed starting at zero, i.e. coil 1 is addressed as 0.
The requested ON/OFF states are specified by contents of the query data field. A logical 1 in a bit position of the field requests the corresponding coil to be ON. A logical 0 requests it to be OFF.
The following shows an example of a request to force a series of ten coils starting at coil 20 in Slave device 17.
The query data contents are two bytes: CD 01 hex (1100 1101 0000 0001 binary). The binary bits correspond to the coils in the following way:
Query data: 1 1 0 0 1 1 0 1 0 0 0 0 0 0 0 1
Coil: 27 26 25 24 23 22 21 20 - - - - - - 29 28
The first byte transmitted (CD hex) addresses coils 27--20, with the least significant bit addressing the lowest coil (20) in this set.
Protocol Translator MODBus User Manual
MultiTrode_MTT_MODBus_Manual_v1-0-9_R02.doc Page 23 of 28
The next byte transmitted (01 hex) addresses coils 29 and 28, with the least significant bit addressing the lowest coil (28) in this set. Unused bits in the last data byte should be zero-filled.
Field Name Example (Hex)
Slave Address 11
Function 0F
Coil Address Hi 00
Coil Address Lo 13
Quantity of Coils Hi 00
Quantity of Coils Lo 0A
Byte Count 02
Force Data Hi (Coils 27—20) CD
Force Data Hi (Coils 29—28) 01
Error Check (LRC or CRC) --
3.6.8.2 Response The normal response returns the Slave address, function code, starting address, and quantity of coils forced. Here is an example of a response to the query shown above:
Field Name Example (Hex)
Slave Address 11
Function 0F
Coil Address Hi 00
Coil Address Lo 13
Quantity of Coils Hi 00
Quantity of Coils Lo 0A
Error Check (LRC or CRC) --
3.6.9 16 (10 Hex) Preset Multiple Registers
Presets are a sequence of values into holding registers (4xxxx references) in a Slave unit. When broadcast, the function presets are the same register references in all attached Slaves. When a Preset command is received, the MultiTrode Translator will update its database and pushes a command through to the MonitorPRO via the “command queue”. The command queue is a MultiTrode Translator buffer area to queue a command to the MonitorPRO. The MultiTrode Translator then issues this command to the MonitorPRO at the next opportunity.
3.6.9.1 Query The query message specifies the register references to be preset. Registers are addressed starting at zero-register, i.e. register 1 is addressed as 0. The requested preset values are specified in the query data field. Data is packed as two bytes per register.
Protocol Translator MODBus User Manual
Page 24 of 28 MultiTrode_MTT_MODBus_Manual_v1-0-9_R02.doc
Here is an example of a request to preset two registers starting at 40002 to 00 OA and 01 02 hex, in Slave device 17:
Field Name Example (Hex)
Slave Address 11
Function 10
Starting Address Hi 00
Starting Address Lo 01
Number of Registers Hi 00
Number of Registers Lo 02
Byte Count 04
Data Hi 00
Data Lo 0A
Data Hi 01
Data Lo 02
Error Check (LRC or CRC) --
3.6.9.2 Response The normal response returns the Slave address, function code, starting address, and quantity of registers preset. Here is an example of a response to the query shown above.
Field Name Example (Hex)
Slave Address 11
Function 10
Starting Address Hi 00
Starting Address Lo 01
Number of Registers Hi 00
Number of Registers Lo 02
Error Check (LRC or CRC) --
Protocol Translator MODBus User Manual
MultiTrode_MTT_MODBus_Manual_v1-0-9_R02.doc Page 25 of 28
3.7 Mirror Input Status Mode An option exists to allow all of the Input Status points to be mirrored to a block of Input Registers (16 status points to each register). Normally, digital inputs will appear as MODBus Input Status Points and 16-bit values as MODBus Input Registers. However, when using a SCADA or PLC Master Control system, it is sometimes desirable to minimise the tag count so as to lower licence costs. To this end the MultiTrode Translator has the ability to mirror Input Status Points into the Input Registers.
By default this feature is off, but if enabled, the Input Status Points will also appear in a configurable block of Input Registers. For example if the feature is enabled and the base register set to 1000, then a single byte read of Input Register 1000 will return Digital Status Points 1 to 16. This allows 957 Digital Input Points to be read using only 59 registers.
Some extra effort is needed within the Master control system to split each register into its component digital points once they have been retrieved, but this involves the use of internal tags.
3.7.1 Configuring the MultiTrode Translator for Mirror Mode
For more details on configuring the MultiTrode Translator, see the MultiTrode Translator Installation Manual. The following steps give a quick configuration guide when using a terminal emulation program such as HyperTerminal®.
• Login to the MultiTrode Translator by entering “login”.
• In the Main Menu select option 5) MODBus Parameters.
• In the Database Menu select option 1
MODBus Database Configuration. 1) Mirror 'Input Status' into 'Input Registers' [Yes]. 2) Base Register For Mirrored Block [312]. ESC) Back.
In the Database Menu select option 2 and set the base address to a number higher than the existing number of Input Registers (311), remembering that this register number is zero based.
Protocol Translator MODBus User Manual
Page 26 of 28 MultiTrode_MTT_MODBus_Manual_v1-0-9_R02.doc
4 Specifications
Dimensions: 118H x 45W x 135D - DIN Rail mounted
Supply:
Typically: 100mA at 12VDC. Minimum supply voltage 8V DC. Maximum supply voltage 38V DC. Supply is fused at 250mA (self-resetting fuse).
Inputs:
6 x digital: Voltage free input contacts. Cable length should not exceed 50m. ESD and EMC protected. -ve line is common ground. Maximum input frequency of 100Hz (10 milliseconds) 2 x analog: 0 to 22mA input. Input resistance 220 Ohms. 10bit ADC accuracy, linearity ±1lsb (0.025%). ADC value scaleable via configuration menu. External supply range 12 to 48VDC. ESD and EMC protected. -ve line is common ground.
Communications Ports: 2 x RS232 Asynchronous:- 9 pin male D type connector with TD, RD, RTS, CTS, DTR and DSR.
Modem:
1 x Radio port to Bell 202, FSK - 1200 baud(fixed) Audio output: adjustable via trimpot to 400mVp-p Audio input sensitivity: 10-500mVp-p Squelch input: 5-30VDC common ground Press To Talk (PTT): Open drain 200mA at 40VDC
Indicators: 9 status LEDS
EMC: C-Tick and CE compliant
AS/NZS3548 (C-Tick) CISPR 24:1997; EN55024:1998 EN61000-4-2:1995, Including Amendment A1 EN61000-4-3:1995, Including Amendment 1:1998 EN61000-4-4:1995. IEC61000-4-5:1995. IEC61000-4-6:1995, Including Amendment A1 IEC61000-4-8:1993 IEC61000-4-11:1994.
Environmental: Temperature -10°C to 60°C Humidity 0 to 95% non- condensing
Protocol Translator MODBus User Manual
MultiTrode_MTT_MODBus_Manual_v1-0-9_R02.doc Page 27 of 28
5 Full List of MODBUS Points Following is the full list of MODBus points that can be retrieved from a station, using the MultiTrode Translator.
Note: A number of points are reserved for future MultiTrode use.
MultiTrode Pty Ltd—Head Office Ph: +61 7 3340 7000 Fx: +61 7 3340 7077
E-mail: [email protected]
MultiTrode Inc—USA Ph: +1 561 994 8090 Fx: +1 561 994 6282
E-mail: [email protected]
Visit www.multitrode.com for the latest information
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Sta
tus:
Sin
gle
bit d
igita
l (re
ad o
nly)
* Th
e m
irror
ed in
put r
egis
ter o
ffest
nee
ds to
be
adde
d to
the
conf
igur
ed "M
irror
Bas
e" o
f the
Pro
con
V to
get
act
ual r
egis
ter n
umbe
r. In
dex
Mirr
ored
Inpu
t Reg
iste
rD
escr
iptio
nM
ultit
rode
Cro
ss-R
efer
ence
Offs
et *
Bit
Varia
ble
Bit
0100
00Th
is b
it w
ill b
e hi
gh if
ther
e is
any
faul
t on
pum
p 1
and
low
oth
erw
ise
Sta
tus_
quic
k[2]
702
0001
This
bit
will
be
high
if th
ere
is a
ny fa
ult o
n pu
mp
1 th
at is
una
ckno
wle
dged
(i.e
. fa
ult n
ot p
rese
nt A
ND
un
ackn
owle
dged
) and
low
oth
erw
ise
Sta
tus_
quic
k[2]
6
0300
02Th
is b
it w
ill b
e hi
gh if
ther
e is
any
faul
t on
pum
p 2
and
low
oth
erw
ise
Sta
tus_
quic
k[2]
504
0003
This
bit
will
be
high
if th
ere
is a
ny fa
ult o
n pu
mp
2 th
at is
una
ckno
wle
dged
(i.e
. fa
ult n
ot p
rese
nt A
ND
un
ackn
owle
dged
) and
low
oth
erw
ise
Sta
tus_
quic
k[2]
4
0500
04Th
is b
it w
ill b
e hi
gh if
ther
e is
any
faul
t on
pum
p 3
and
low
oth
erw
ise
Sta
tus_
quic
k[2]
306
0005
This
bit
will
be
high
if th
ere
is a
ny fa
ult o
n pu
mp
3 th
at is
una
ckno
wle
dged
(i.e
. fa
ult n
ot p
rese
nt A
ND
un
ackn
owle
dged
) and
low
oth
erw
ise
Sta
tus_
quic
k[2]
2
0700
06Th
is b
it w
ill b
e hi
gh if
ther
e is
any
faul
t on
pum
p 4
and
low
oth
erw
ise
Sta
tus_
quic
k[2]
108
0007
This
bit
will
be
high
if th
ere
is a
ny fa
ult o
n pu
mp
4 th
at is
una
ckno
wle
dged
(i.e
. fa
ult n
ot p
rese
nt A
ND
un
ackn
owle
dged
) and
low
oth
erw
ise
Sta
tus_
quic
k[2]
0
0900
08Th
is b
it w
ill b
e hi
gh if
ther
e is
any
faul
t on
pum
p 5
and
low
oth
erw
ise
Sta
tus_
quic
k[3]
710
0009
This
bit
will
be
high
if th
ere
is a
ny fa
ult o
n pu
mp
5 th
at is
una
ckno
wle
dged
(i.e
. fa
ult n
ot p
rese
nt A
ND
un
ackn
owle
dged
) and
low
oth
erw
ise
Sta
tus_
quic
k[3]
6
1100
10Th
is b
it w
ill b
e hi
gh if
ther
e is
any
faul
t on
pum
p 6
and
low
oth
erw
ise
Sta
tus_
quic
k[3]
512
0011
This
bit
will
be
high
if th
ere
is a
ny fa
ult o
n pu
mp
6 th
at is
una
ckno
wle
dged
(i.e
. fa
ult n
ot p
rese
nt A
ND
un
ackn
owle
dged
) and
low
oth
erw
ise
Sta
tus_
quic
k[3]
4
1300
12Th
is b
it w
ill b
e hi
gh if
ther
e is
any
faul
t on
pum
p 7
and
low
oth
erw
ise
Sta
tus_
quic
k[3]
314
0013
This
bit
will
be
high
if th
ere
is a
ny fa
ult o
n pu
mp
7 th
at is
una
ckno
wle
dged
(i.e
. fa
ult n
ot p
rese
nt A
ND
un
ackn
owle
dged
) and
low
oth
erw
ise
Sta
tus_
quic
k[3]
2
1500
14Th
is b
it w
ill b
e hi
gh if
ther
e is
any
faul
t on
pum
p 8
and
low
oth
erw
ise
Sta
tus_
quic
k[3]
116
0015
This
bit
will
be
high
if th
ere
is a
ny fa
ult o
n pu
mp
8 th
at is
una
ckno
wle
dged
(i.e
. fa
ult n
ot p
rese
nt A
ND
un
ackn
owle
dged
) and
low
oth
erw
ise
Sta
tus_
quic
k[3]
0
1701
00Th
is b
it w
ill b
e hi
gh if
ther
e is
any
faul
t on
pum
p 9
and
low
oth
erw
ise
Sta
tus_
quic
k[4]
718
0101
This
bit
will
be
high
if th
ere
is a
ny fa
ult o
n pu
mp
9 th
at is
una
ckno
wle
dged
(i.e
. fa
ult n
ot p
rese
nt A
ND
un
ackn
owle
dged
) and
low
oth
erw
ise
Sta
tus_
quic
k[4]
6
1901
02Th
is b
it w
ill b
e hi
gh if
pum
p 1
is a
vaila
ble
and
low
oth
erw
ise
Sta
tus_
quic
k[4]
520
0103
This
bit
will
be
high
if p
ump
2 is
ava
ilabl
e an
d lo
w o
ther
wis
eS
tatu
s_qu
ick[
4]4
2101
04Th
is b
it w
ill b
e hi
gh if
pum
p 3
is a
vaila
ble
and
low
oth
erw
ise
Sta
tus_
quic
k[4]
322
0105
This
bit
will
be
high
if p
ump
4 is
ava
ilabl
e an
d lo
w o
ther
wis
eS
tatu
s_qu
ick[
4]2
2301
06Th
is b
it w
ill b
e hi
gh if
pum
p 5
is a
vaila
ble
and
low
oth
erw
ise
Sta
tus_
quic
k[4]
124
0107
This
bit
will
be
high
if p
ump
6 is
ava
ilabl
e an
d lo
w o
ther
wis
eS
tatu
s_qu
ick[
4]0
2501
08Th
is b
it w
ill b
e hi
gh if
pum
p 7
is a
vaila
ble
and
low
oth
erw
ise
Sta
tus_
quic
k[5]
726
0109
This
bit
will
be
high
if p
ump
8 is
ava
ilabl
e an
d lo
w o
ther
wis
eS
tatu
s_qu
ick[
5]6
2701
10Th
is b
it w
ill b
e hi
gh if
pum
p 9
is a
vaila
ble
and
low
oth
erw
ise
Sta
tus_
quic
k[5]
528
0111
This
bit
will
be
high
if th
ere
is a
ny fa
ult o
n th
e M
aste
r Mon
itorP
RO
and
low
oth
erw
ise
Sta
tus_
quic
k[5]
429
0112
This
bit
will
be
high
if th
ere
is a
ny fa
ult o
n S
lave
1 M
onito
rPR
O a
nd lo
w o
ther
wis
eS
tatu
s_qu
ick[
5]3
3001
13Th
is b
it w
ill b
e hi
gh if
ther
e is
any
faul
t on
Sla
ve 2
Mon
itorP
RO
and
low
oth
erw
ise
Sta
tus_
quic
k[5]
231
0114
This
bit
will
be
high
if th
ere
is a
ny c
hang
e to
the
faul
t sta
tus
and
low
oth
erw
ise
Sta
tus_
quic
k[5]
132
0115
This
bit
will
be
high
if th
ere
is a
ny c
hang
e to
any
of t
he d
igita
l inp
uts
or o
utpu
ts o
r ana
logu
e in
puts
and
low
oth
erw
ise
Sta
tus_
quic
k[5]
0
3302
00Th
is b
it is
hig
h if
pum
p 1
is ru
nnin
g an
d lo
w o
ther
wis
eS
tatu
s_qu
ick[
6]7
3402
01Th
is b
it is
hig
h if
pum
p 1
is a
vaila
ble
and
low
oth
erw
ise
Sta
tus_
quic
k[6]
6
Pag
e 1
Inpu
t Sta
tus
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Sta
tus:
Sin
gle
bit d
igita
l (re
ad o
nly)
* Th
e m
irror
ed in
put r
egis
ter o
ffest
nee
ds to
be
adde
d to
the
conf
igur
ed "M
irror
Bas
e" o
f the
Pro
con
V to
get
act
ual r
egis
ter n
umbe
r. In
dex
Mirr
ored
Inpu
t Reg
iste
rD
escr
iptio
nM
ultit
rode
Cro
ss-R
efer
ence
Offs
et *
Bit
Varia
ble
Bit
3502
02If
inde
x 34
=0 a
nd in
dex
35=0
then
pum
p 1
is in
aut
o m
ode.
If
inde
x 34
=0 a
nd in
dex
35=1
then
pum
p 1
is o
ff.
If in
dex
34=1
and
inde
x 35
=0 th
en p
ump
1 is
off.
If
inde
x 34
=1 a
nd in
dex
35=1
then
pum
p 1
is in
man
ual m
ode
Sta
tus_
quic
k[6]
5
3602
03S
ee a
bove
.S
tatu
s_qu
ick[
6]4
3702
04Th
is b
it is
hig
h if
pum
p 2
is ru
nnin
g an
d lo
w o
ther
wis
eS
tatu
s_qu
ick[
6]3
3802
05Th
is b
it is
hig
h if
pum
p 2
is a
vaila
ble
and
low
oth
erw
ise
Sta
tus_
quic
k[6]
239
0206
If in
dex
38=0
and
inde
x 39
=0 th
en p
ump
2 is
in a
uto
mod
e.
If in
dex
38=0
and
inde
x 39
=1 th
en p
ump
2 is
off.
If
inde
x 38
=1 a
nd in
dex
39=0
then
pum
p 2
is o
ff.
If in
dex
38=1
and
inde
x 39
=1 th
en p
ump
2 is
in m
anua
l mod
e
Sta
tus_
quic
k[6]
1
4002
07S
ee a
bove
.S
tatu
s_qu
ick[
6]0
4102
08Th
is b
it is
hig
h if
pum
p 3
is ru
nnin
g an
d lo
w o
ther
wis
eS
tatu
s_qu
ick[
7]7
4202
09Th
is b
it is
hig
h if
pum
p 3
is a
vaila
ble
and
low
oth
erw
ise
Sta
tus_
quic
k[7]
643
0210
If in
dex
42=0
and
inde
x 43
=0 th
en p
ump
3 is
in a
uto
mod
e.
If in
dex
42=0
and
inde
x 43
=1 th
en p
ump
3 is
off.
If
inde
x 42
=1 a
nd in
dex
43=0
then
pum
p 3
is o
ff.
If in
dex
42=1
and
inde
x 43
=1 th
en p
ump
3 is
in m
anua
l mod
e
Sta
tus_
quic
k[7]
5
4402
11S
ee a
bove
.S
tatu
s_qu
ick[
7]4
4502
12Th
is b
it is
hig
h if
pum
p 4
is ru
nnin
g an
d lo
w o
ther
wis
eS
tatu
s_qu
ick[
7]3
4602
13Th
is b
it is
hig
h if
pum
p 4
is a
vaila
ble
and
low
oth
erw
ise
Sta
tus_
quic
k[7]
247
0214
If in
dex
46=0
and
inde
x 47
=0 th
en p
ump
4 is
in a
uto
mod
e.
If in
dex
46=0
and
inde
x 47
=1 th
en p
ump
4 is
off.
If
inde
x 46
=1 a
nd in
dex
47=0
then
pum
p 4
is o
ff.
If in
dex
46=1
and
inde
x 47
=1 th
en p
ump
4 is
in m
anua
l mod
e
Sta
tus_
quic
k[7]
1
4802
15S
ee a
bove
.S
tatu
s_qu
ick[
7]0
4903
00Th
is b
it is
hig
h if
pum
p 5
is ru
nnin
g an
d lo
w o
ther
wis
eS
tatu
s_qu
ick[
8]7
5003
01Th
is b
it is
hig
h if
pum
p 5
is a
vaila
ble
and
low
oth
erw
ise
Sta
tus_
quic
k[8]
651
0302
If in
dex
50=0
and
inde
x 51
=0 th
en p
ump
5 is
in a
uto
mod
e.
If in
dex
50=0
and
inde
x 51
=1 th
en p
ump
5 is
off.
If
inde
x 50
=1 a
nd in
dex
51=0
then
pum
p 5
is o
ff.
If in
dex
50=1
and
inde
x 51
=1 th
en p
ump
5 is
in m
anua
l mod
e
Sta
tus_
quic
k[8]
5
5203
03S
ee a
bove
.S
tatu
s_qu
ick[
8]4
5303
04Th
is b
it is
hig
h if
pum
p 6
is ru
nnin
g an
d lo
w o
ther
wis
eS
tatu
s_qu
ick[
8]3
5403
05Th
is b
it is
hig
h if
pum
p 6
is a
vaila
ble
and
low
oth
erw
ise
Sta
tus_
quic
k[8]
255
0306
If in
dex
54=0
and
inde
x 55
=0 th
en p
ump
6 is
in a
uto
mod
e.
If in
dex
54=0
and
inde
x 55
=1 th
en p
ump
6 is
off.
If
inde
x 54
=1 a
nd in
dex
55=0
then
pum
p 6
is o
ff.
If in
dex
54=1
and
inde
x 55
=1 th
en p
ump
6 is
in m
anua
l mod
e
Sta
tus_
quic
k[8]
1
5603
07S
ee a
bove
.S
tatu
s_qu
ick[
8]0
5703
08Th
is b
it is
hig
h if
pum
p 7
is ru
nnin
g an
d lo
w o
ther
wis
eS
tatu
s_qu
ick[
9]7
5803
09Th
is b
it is
hig
h if
pum
p 7
is a
vaila
ble
and
low
oth
erw
ise
Sta
tus_
quic
k[9]
6
Pag
e 2
Inpu
t Sta
tus
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Sta
tus:
Sin
gle
bit d
igita
l (re
ad o
nly)
* Th
e m
irror
ed in
put r
egis
ter o
ffest
nee
ds to
be
adde
d to
the
conf
igur
ed "M
irror
Bas
e" o
f the
Pro
con
V to
get
act
ual r
egis
ter n
umbe
r. In
dex
Mirr
ored
Inpu
t Reg
iste
rD
escr
iptio
nM
ultit
rode
Cro
ss-R
efer
ence
Offs
et *
Bit
Varia
ble
Bit
5903
10If
inde
x 58
=0 a
nd in
dex
59=0
then
pum
p 7
is in
aut
o m
ode.
If
inde
x 58
=0 a
nd in
dex
59=1
then
pum
p 7
is o
ff.
If in
dex
58=1
and
inde
x 59
=0 th
en p
ump
7 is
off.
If
inde
x 58
=1 a
nd in
dex
59=1
then
pum
p 7
is in
man
ual m
ode
Sta
tus_
quic
k[9]
5
6003
11S
ee a
bove
.S
tatu
s_qu
ick[
9]4
6103
12Th
is b
it is
hig
h if
pum
p 8
is ru
nnin
g an
d lo
w o
ther
wis
eS
tatu
s_qu
ick[
9]3
6203
13Th
is b
it is
hig
h if
pum
p 8
is a
vaila
ble
and
low
oth
erw
ise
Sta
tus_
quic
k[9]
263
0314
If in
dex
62=0
and
inde
x 63
=0 th
en p
ump
8 is
in a
uto
mod
e.
If in
dex
62=0
and
inde
x 63
=1 th
en p
ump
8 is
off.
If
inde
x 62
=1 a
nd in
dex
63=0
then
pum
p 8
is o
ff.
If in
dex
62=1
and
inde
x 63
=1 th
en p
ump
8 is
in m
anua
l mod
e
Sta
tus_
quic
k[9]
1
6403
15S
ee a
bove
.S
tatu
s_qu
ick[
9]0
6504
00Th
is b
it is
hig
h if
pum
p 9
is ru
nnin
g an
d lo
w o
ther
wis
eS
tatu
s_qu
ick[
10]
766
0401
This
bit
is h
igh
if pu
mp
9 is
ava
ilabl
e an
d lo
w o
ther
wis
eS
tatu
s_qu
ick[
10]
667
0402
If in
dex
66=0
and
inde
x 67
=0 th
en p
ump
9 is
in a
uto
mod
e.
If in
dex
66=0
and
inde
x 67
=1 th
en p
ump
9 is
off.
If
inde
x 66
=1 a
nd in
dex
67=0
then
pum
p 9
is o
ff.
If in
dex
66=1
and
inde
x 67
=1 th
en p
ump
9 is
in m
anua
l mod
e
Sta
tus_
quic
k[10
]5
6804
03S
ee a
bove
.S
tatu
s_qu
ick[
10]
469
0404
Res
erve
dS
tatu
s_qu
ick[
10]
370
0405
Res
erve
dS
tatu
s_qu
ick[
10]
271
0406
Res
erve
dS
tatu
s_qu
ick[
10]
172
0407
Res
erve
dS
tatu
s_qu
ick[
10]
073
0408
Ala
rm 1
stat
us_d
ig7
7404
09A
larm
2st
atus
_dig
675
0410
Com
mon
Ala
rmst
atus
_dig
576
0411
Dat
alog
Ful
l Fla
gst
atus
_dig
477
0412
Spa
rest
atus
_dig
378
0413
Spa
rest
atus
_dig
279
0414
Spa
rest
atus
_dig
180
0415
Spa
rest
atus
_dig
081
0500
This
bit
will
be
high
if a
crit
ical
faul
t is
PR
ES
EN
T on
pum
p 1
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
pres
ent[0
]7
8205
01Th
is b
it w
ill b
e hi
gh if
a n
on-c
ritic
al fa
ult i
s P
RE
SE
NT
on p
ump
1 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_pr
esen
t[0]
683
0502
This
bit
will
be
high
if a
del
ay fa
il fa
ult i
s P
RE
SE
NT
on p
ump
1 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_pr
esen
t[0]
584
0503
This
bit
will
be
high
if a
sea
l fau
lt is
PR
ES
EN
T on
pum
p 1
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
pres
ent[0
]4
8505
04Th
is b
it w
ill b
e hi
gh if
a fl
ygt s
eal f
ault
is P
RE
SE
NT
on p
ump
1 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_pr
esen
t[0]
386
0505
This
bit
will
be
high
if a
flyg
t the
rmis
tor f
ault
is P
RE
SE
NT
on p
ump
1 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_pr
esen
t[0]
287
0506
If th
e m
axim
um s
tarts
per
hou
r on
pum
p 1
has
been
exc
eede
d th
en th
is b
it is
hig
h an
d lo
w o
ther
wst
atus
_xpc
_pum
p_pr
esen
t[0]
188
0507
This
bit
will
be
high
if a
ther
mis
tor f
ault
is P
RE
SE
NT
on p
ump
1 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_pr
esen
t[0]
089
0508
This
bit
will
be
high
if a
crit
ical
faul
t is
PR
ES
EN
T on
pum
p 2
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
pres
ent[1
]7
9005
09Th
is b
it w
ill b
e hi
gh if
a n
on-c
ritic
al fa
ult i
s P
RE
SE
NT
on p
ump
2 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_pr
esen
t[1]
691
0510
This
bit
will
be
high
if a
del
ay fa
il fa
ult i
s P
RE
SE
NT
on p
ump
2 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_pr
esen
t[1]
592
0511
This
bit
will
be
high
if a
sea
l fau
lt is
PR
ES
EN
T on
pum
p 2
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
pres
ent[1
]4
9305
12Th
is b
it w
ill b
e hi
gh if
a fl
ygt s
eal f
ault
is P
RE
SE
NT
on p
ump
2 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_pr
esen
t[1]
3
Pag
e 3
Inpu
t Sta
tus
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Sta
tus:
Sin
gle
bit d
igita
l (re
ad o
nly)
* Th
e m
irror
ed in
put r
egis
ter o
ffest
nee
ds to
be
adde
d to
the
conf
igur
ed "M
irror
Bas
e" o
f the
Pro
con
V to
get
act
ual r
egis
ter n
umbe
r. In
dex
Mirr
ored
Inpu
t Reg
iste
rD
escr
iptio
nM
ultit
rode
Cro
ss-R
efer
ence
Offs
et *
Bit
Varia
ble
Bit
9405
13Th
is b
it w
ill b
e hi
gh if
a fl
ygt t
herm
isto
r fau
lt is
PR
ES
EN
T on
pum
p 2
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
pres
ent[1
]2
9505
14If
the
max
imum
sta
rts p
er h
our o
n pu
mp
2 ha
s be
en e
xcee
ded
then
this
bit
is h
igh
and
low
oth
erw
stat
us_x
pc_p
ump_
pres
ent[1
]1
9605
15Th
is b
it w
ill b
e hi
gh if
a th
erm
isto
r fau
lt is
PR
ES
EN
T on
pum
p 2
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
pres
ent[1
]0
9706
00Th
is b
it w
ill b
e hi
gh if
a c
ritic
al fa
ult i
s P
RE
SE
NT
on p
ump
3 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_pr
esen
t[2]
798
0601
This
bit
will
be
high
if a
non
-crit
ical
faul
t is
PR
ES
EN
T on
pum
p 3
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
pres
ent[2
]6
9906
02Th
is b
it w
ill b
e hi
gh if
a d
elay
fail
faul
t is
PR
ES
EN
T on
pum
p 3
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
pres
ent[2
]5
100
0603
This
bit
will
be
high
if a
sea
l fau
lt is
PR
ES
EN
T on
pum
p 3
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
pres
ent[2
]4
101
0604
This
bit
will
be
high
if a
flyg
t sea
l fau
lt is
PR
ES
EN
T on
pum
p 3
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
pres
ent[2
]3
102
0605
This
bit
will
be
high
if a
flyg
t the
rmis
tor f
ault
is P
RE
SE
NT
on p
ump
3 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_pr
esen
t[2]
210
306
06If
the
max
imum
sta
rts p
er h
our o
n pu
mp
3 ha
s be
en e
xcee
ded
then
this
bit
is h
igh
and
low
oth
erw
stat
us_x
pc_p
ump_
pres
ent[2
]1
104
0607
This
bit
will
be
high
if a
ther
mis
tor f
ault
is P
RE
SE
NT
on p
ump
3 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_pr
esen
t[2]
010
506
08Th
is b
it w
ill b
e hi
gh if
a c
ritic
al fa
ult i
s P
RE
SE
NT
on p
ump
4 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_pr
esen
t[3]
710
606
09Th
is b
it w
ill b
e hi
gh if
a n
on-c
ritic
al fa
ult i
s P
RE
SE
NT
on p
ump
4 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_pr
esen
t[3]
610
706
10Th
is b
it w
ill b
e hi
gh if
a d
elay
fail
faul
t is
PR
ES
EN
T on
pum
p 4
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
pres
ent[3
]5
108
0611
This
bit
will
be
high
if a
sea
l fau
lt is
PR
ES
EN
T on
pum
p 4
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
pres
ent[3
]4
109
0612
This
bit
will
be
high
if a
flyg
t sea
l fau
lt is
PR
ES
EN
T on
pum
p 4
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
pres
ent[3
]3
110
0613
This
bit
will
be
high
if a
flyg
t the
rmis
tor f
ault
is P
RE
SE
NT
on p
ump
4 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_pr
esen
t[3]
211
106
14If
the
max
imum
sta
rts p
er h
our o
n pu
mp
4 ha
s be
en e
xcee
ded
then
this
bit
is h
igh
and
low
oth
erw
stat
us_x
pc_p
ump_
pres
ent[3
]1
112
0615
This
bit
will
be
high
if a
ther
mis
tor f
ault
is P
RE
SE
NT
on p
ump
4 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_pr
esen
t[3]
011
307
00Th
is b
it w
ill b
e hi
gh if
a c
ritic
al fa
ult i
s P
RE
SE
NT
on p
ump
5 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_pr
esen
t[4]
711
407
01Th
is b
it w
ill b
e hi
gh if
a n
on-c
ritic
al fa
ult i
s P
RE
SE
NT
on p
ump
5 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_pr
esen
t[4]
611
507
02Th
is b
it w
ill b
e hi
gh if
a d
elay
fail
faul
t is
PR
ES
EN
T on
pum
p 5
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
pres
ent[4
]5
116
0703
This
bit
will
be
high
if a
sea
l fau
lt is
PR
ES
EN
T on
pum
p 5
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
pres
ent[4
]4
117
0704
This
bit
will
be
high
if a
flyg
t sea
l fau
lt is
PR
ES
EN
T on
pum
p 5
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
pres
ent[4
]3
118
0705
This
bit
will
be
high
if a
flyg
t the
rmis
tor f
ault
is P
RE
SE
NT
on p
ump
5 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_pr
esen
t[4]
211
907
06If
the
max
imum
sta
rts p
er h
our o
n pu
mp
5 ha
s be
en e
xcee
ded
then
this
bit
is h
igh
and
low
oth
erw
stat
us_x
pc_p
ump_
pres
ent[4
]1
120
0707
This
bit
will
be
high
if a
ther
mis
tor f
ault
is P
RE
SE
NT
on p
ump
5 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_pr
esen
t[4]
012
107
08Th
is b
it w
ill b
e hi
gh if
a c
ritic
al fa
ult i
s P
RE
SE
NT
on p
ump
6 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_pr
esen
t[5]
712
207
09Th
is b
it w
ill b
e hi
gh if
a n
on-c
ritic
al fa
ult i
s P
RE
SE
NT
on p
ump
6 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_pr
esen
t[5]
612
307
10Th
is b
it w
ill b
e hi
gh if
a d
elay
fail
faul
t is
PR
ES
EN
T on
pum
p 6
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
pres
ent[5
]5
124
0711
This
bit
will
be
high
if a
sea
l fau
lt is
PR
ES
EN
T on
pum
p 6
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
pres
ent[5
]4
125
0712
This
bit
will
be
high
if a
flyg
t sea
l fau
lt is
PR
ES
EN
T on
pum
p 6
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
pres
ent[5
]3
126
0713
This
bit
will
be
high
if a
flyg
t the
rmis
tor f
ault
is P
RE
SE
NT
on p
ump
6 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_pr
esen
t[5]
212
707
14If
the
max
imum
sta
rts p
er h
our o
n pu
mp
6 ha
s be
en e
xcee
ded
then
this
bit
is h
igh
and
low
oth
erw
stat
us_x
pc_p
ump_
pres
ent[5
]1
128
0715
This
bit
will
be
high
if a
ther
mis
tor f
ault
is P
RE
SE
NT
on p
ump
6 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_pr
esen
t[5]
012
908
00Th
is b
it w
ill b
e hi
gh if
a c
ritic
al fa
ult i
s P
RE
SE
NT
on p
ump
7 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_pr
esen
t[6]
713
008
01Th
is b
it w
ill b
e hi
gh if
a n
on-c
ritic
al fa
ult i
s P
RE
SE
NT
on p
ump
7 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_pr
esen
t[6]
613
108
02Th
is b
it w
ill b
e hi
gh if
a d
elay
fail
faul
t is
PR
ES
EN
T on
pum
p 7
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
pres
ent[6
]5
132
0803
This
bit
will
be
high
if a
sea
l fau
lt is
PR
ES
EN
T on
pum
p 7
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
pres
ent[6
]4
133
0804
This
bit
will
be
high
if a
flyg
t sea
l fau
lt is
PR
ES
EN
T on
pum
p 7
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
pres
ent[6
]3
134
0805
This
bit
will
be
high
if a
flyg
t the
rmis
tor f
ault
is P
RE
SE
NT
on p
ump
7 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_pr
esen
t[6]
213
508
06If
the
max
imum
sta
rts p
er h
our o
n pu
mp
7 ha
s be
en e
xcee
ded
then
this
bit
is h
igh
and
low
oth
erw
stat
us_x
pc_p
ump_
pres
ent[6
]1
136
0807
This
bit
will
be
high
if a
ther
mis
tor f
ault
is P
RE
SE
NT
on p
ump
7 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_pr
esen
t[6]
013
708
08Th
is b
it w
ill b
e hi
gh if
a c
ritic
al fa
ult i
s P
RE
SE
NT
on p
ump
8 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_pr
esen
t[7]
7
Pag
e 4
Inpu
t Sta
tus
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Sta
tus:
Sin
gle
bit d
igita
l (re
ad o
nly)
* Th
e m
irror
ed in
put r
egis
ter o
ffest
nee
ds to
be
adde
d to
the
conf
igur
ed "M
irror
Bas
e" o
f the
Pro
con
V to
get
act
ual r
egis
ter n
umbe
r. In
dex
Mirr
ored
Inpu
t Reg
iste
rD
escr
iptio
nM
ultit
rode
Cro
ss-R
efer
ence
Offs
et *
Bit
Varia
ble
Bit
138
0809
This
bit
will
be
high
if a
non
-crit
ical
faul
t is
PR
ES
EN
T on
pum
p 8
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
pres
ent[7
]6
139
0810
This
bit
will
be
high
if a
del
ay fa
il fa
ult i
s P
RE
SE
NT
on p
ump
8 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_pr
esen
t[7]
514
008
11Th
is b
it w
ill b
e hi
gh if
a s
eal f
ault
is P
RE
SE
NT
on p
ump
8 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_pr
esen
t[7]
414
108
12Th
is b
it w
ill b
e hi
gh if
a fl
ygt s
eal f
ault
is P
RE
SE
NT
on p
ump
8 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_pr
esen
t[7]
314
208
13Th
is b
it w
ill b
e hi
gh if
a fl
ygt t
herm
isto
r fau
lt is
PR
ES
EN
T on
pum
p 8
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
pres
ent[7
]2
143
0814
If th
e m
axim
um s
tarts
per
hou
r on
pum
p 8
has
been
exc
eede
d th
en th
is b
it is
hig
h an
d lo
w o
ther
wst
atus
_xpc
_pum
p_pr
esen
t[7]
114
408
15Th
is b
it w
ill b
e hi
gh if
a th
erm
isto
r fau
lt is
PR
ES
EN
T on
pum
p 8
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
pres
ent[7
]0
145
0900
This
bit
will
be
high
if a
crit
ical
faul
t is
PR
ES
EN
T on
pum
p 9
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
pres
ent[8
]7
146
0901
This
bit
will
be
high
if a
non
-crit
ical
faul
t is
PR
ES
EN
T on
pum
p 9
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
pres
ent[8
]6
147
0902
This
bit
will
be
high
if a
del
ay fa
il fa
ult i
s P
RE
SE
NT
on p
ump
9 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_pr
esen
t[8]
514
809
03Th
is b
it w
ill b
e hi
gh if
a s
eal f
ault
is P
RE
SE
NT
on p
ump
9 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_pr
esen
t[8]
414
909
04Th
is b
it w
ill b
e hi
gh if
a fl
ygt s
eal f
ault
is P
RE
SE
NT
on p
ump
9 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_pr
esen
t[8]
315
009
05Th
is b
it w
ill b
e hi
gh if
a fl
ygt t
herm
isto
r fau
lt is
PR
ES
EN
T on
pum
p 9
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
pres
ent[8
]2
151
0906
If th
e m
axim
um s
tarts
per
hou
r on
pum
p 9
has
been
exc
eede
d th
en th
is b
it is
hig
h an
d lo
w o
ther
wst
atus
_xpc
_pum
p_pr
esen
t[8]
115
209
07Th
is b
it w
ill b
e hi
gh if
a th
erm
isto
r fau
lt is
PR
ES
EN
T on
pum
p 9
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
pres
ent[8
]0
153
0908
This
bit
will
be
high
if a
crit
ical
faul
t is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
bee n
ackn
owle
dged
) on
pum
p 1
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[0
]7
154
0909
This
bit
will
be
high
if a
non
-crit
ical
faul
t is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ackn
owle
dged
) on
pum
p 1
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[0
]6
155
0910
This
bit
will
be
high
if a
del
ay fa
il fa
ult i
s U
NA
CK
NO
WLE
DG
ED
(Fau
lt is
NO
T pr
esen
t but
has
NO
T be
enac
know
ledg
ed) o
n pu
mp
1 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_un
ackd
[0]
5
156
0911
This
bit
will
be
high
if a
sea
l fau
lt is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ack
now
ledg
edon
pum
p 1
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[0
]4
157
0912
This
bit
will
be
high
if a
flyg
t sea
l fau
lt is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ackn
owle
dged
) on
pum
p 1
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[0
]3
158
0913
This
bit
will
be
high
if a
flyg
t the
rmis
tor f
ault
is U
NA
CK
NO
WLE
DG
ED
(Fau
lt is
NO
T pr
esen
t but
has
NO
T be
enac
know
ledg
ed) o
n pu
mp
1 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_un
ackd
[0]
2
159
0914
Res
erve
dst
atus
_xpc
_pum
p_un
ackd
[0]
116
009
15Th
is b
it w
ill b
e hi
gh if
a th
erm
isto
r fau
lt is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
bee n
ackn
owle
dged
) on
pum
p 1
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[0
]0
161
1000
This
bit
will
be
high
if a
crit
ical
faul
t is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ackn
owle
dged
) on
pum
p 2
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[1
]7
162
1001
This
bit
will
be
high
if a
non
-crit
ical
faul
t is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ackn
owle
dged
) on
pum
p 2
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[1
]6
163
1002
This
bit
will
be
high
if a
del
ay fa
il fa
ult i
s U
NA
CK
NO
WLE
DG
ED
(Fau
lt is
NO
T pr
esen
t but
has
NO
T be
enac
know
ledg
ed) o
n pu
mp
2 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_un
ackd
[1]
5
164
1003
This
bit
will
be
high
if a
sea
l fau
lt is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ack
now
ledg
edon
pum
p 2
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[1
]4
165
1004
This
bit
will
be
high
if a
flyg
t sea
l fau
lt is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
bee n
ackn
owle
dged
) on
pum
p 2
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[1
]3
166
1005
This
bit
will
be
high
if a
flyg
t the
rmis
tor f
ault
is U
NA
CK
NO
WLE
DG
ED
(Fau
lt is
NO
T pr
esen
t but
has
NO
T be
enac
know
ledg
ed) o
n pu
mp
2 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_un
ackd
[1]
2
167
1006
Res
erve
dst
atus
_xpc
_pum
p_un
ackd
[1]
1
Pag
e 5
Inpu
t Sta
tus
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Sta
tus:
Sin
gle
bit d
igita
l (re
ad o
nly)
* Th
e m
irror
ed in
put r
egis
ter o
ffest
nee
ds to
be
adde
d to
the
conf
igur
ed "M
irror
Bas
e" o
f the
Pro
con
V to
get
act
ual r
egis
ter n
umbe
r. In
dex
Mirr
ored
Inpu
t Reg
iste
rD
escr
iptio
nM
ultit
rode
Cro
ss-R
efer
ence
Offs
et *
Bit
Varia
ble
Bit
168
1007
This
bit
will
be
high
if a
ther
mis
tor f
ault
is U
NA
CK
NO
WLE
DG
ED
(Fau
lt is
NO
T pr
esen
t but
has
NO
T be
enac
know
ledg
ed) o
n pu
mp
2 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_un
ackd
[1]
0
169
1008
This
bit
will
be
high
if a
crit
ical
faul
t is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ackn
owle
dged
) on
pum
p 3
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[2
]7
170
1009
This
bit
will
be
high
if a
non
-crit
ical
faul
t is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ackn
owle
dged
) on
pum
p 3
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[2
]6
171
1010
This
bit
will
be
high
if a
del
ay fa
il fa
ult i
s U
NA
CK
NO
WLE
DG
ED
(Fau
lt is
NO
T pr
esen
t but
has
NO
T be
enac
know
ledg
ed) o
n pu
mp
3 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_un
ackd
[2]
5
172
1011
This
bit
will
be
high
if a
sea
l fau
lt is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ack
now
ledg
edon
pum
p 3
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[2
]4
173
1012
This
bit
will
be
high
if a
flyg
t sea
l fau
lt is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ackn
owle
dged
) on
pum
p 3
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[2
]3
174
1013
This
bit
will
be
high
if a
flyg
t the
rmis
tor f
ault
is U
NA
CK
NO
WLE
DG
ED
(Fau
lt is
NO
T pr
esen
t but
has
NO
T be
enac
know
ledg
ed) o
n pu
mp
3 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_un
ackd
[2]
2
175
1014
Res
erve
dst
atus
_xpc
_pum
p_un
ackd
[2]
117
610
15Th
is b
it w
ill b
e hi
gh if
a th
erm
isto
r fau
lt is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
bee n
ackn
owle
dged
) on
pum
p 3
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[2
]0
177
1100
This
bit
will
be
high
if a
crit
ical
faul
t is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ackn
owle
dged
) on
pum
p 4
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[3
]7
178
1101
This
bit
will
be
high
if a
non
-crit
ical
faul
t is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ackn
owle
dged
) on
pum
p 4
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[3
]6
179
1102
This
bit
will
be
high
if a
del
ay fa
il fa
ult i
s U
NA
CK
NO
WLE
DG
ED
(Fau
lt is
NO
T pr
esen
t but
has
NO
T be
enac
know
ledg
ed) o
n pu
mp
4 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_un
ackd
[3]
5
180
1103
This
bit
will
be
high
if a
sea
l fau
lt is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ack
now
ledg
edon
pum
p 4
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[3
]4
181
1104
This
bit
will
be
high
if a
flyg
t sea
l fau
lt is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ackn
owle
dged
) on
pum
p 4
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[3
]3
182
1105
This
bit
will
be
high
if a
flyg
t the
rmis
tor f
ault
is U
NA
CK
NO
WLE
DG
ED
(Fau
lt is
NO
T pr
esen
t but
has
NO
T be
enac
know
ledg
ed) o
n pu
mp
4 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_un
ackd
[3]
2
183
1106
Res
erve
dst
atus
_xpc
_pum
p_un
ackd
[3]
118
411
07Th
is b
it w
ill b
e hi
gh if
a th
erm
isto
r fau
lt is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
bee n
ackn
owle
dged
) on
pum
p 4
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[3
]0
185
1108
This
bit
will
be
high
if a
crit
ical
faul
t is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ackn
owle
dged
) on
pum
p 5
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[4
]7
186
1109
This
bit
will
be
high
if a
non
-crit
ical
faul
t is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ackn
owle
dged
) on
pum
p 5
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[4
]6
187
1110
This
bit
will
be
high
if a
del
ay fa
il fa
ult i
s U
NA
CK
NO
WLE
DG
ED
(Fau
lt is
NO
T pr
esen
t but
has
NO
T be
enac
know
ledg
ed) o
n pu
mp
5 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_un
ackd
[4]
5
188
1111
This
bit
will
be
high
if a
sea
l fau
lt is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ack
now
ledg
e don
pum
p 5
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[4
]4
189
1112
This
bit
will
be
high
if a
flyg
t sea
l fau
lt is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ackn
owle
dged
) on
pum
p 5
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[4
]3
190
1113
This
bit
will
be
high
if a
flyg
t the
rmis
tor f
ault
is U
NA
CK
NO
WLE
DG
ED
(Fau
lt is
NO
T pr
esen
t but
has
NO
T be
enac
know
ledg
ed) o
n pu
mp
5 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_un
ackd
[4]
2
Pag
e 6
Inpu
t Sta
tus
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Sta
tus:
Sin
gle
bit d
igita
l (re
ad o
nly)
* Th
e m
irror
ed in
put r
egis
ter o
ffest
nee
ds to
be
adde
d to
the
conf
igur
ed "M
irror
Bas
e" o
f the
Pro
con
V to
get
act
ual r
egis
ter n
umbe
r. In
dex
Mirr
ored
Inpu
t Reg
iste
rD
escr
iptio
nM
ultit
rode
Cro
ss-R
efer
ence
Offs
et *
Bit
Varia
ble
Bit
191
1114
Res
erve
dst
atus
_xpc
_pum
p_un
ackd
[4]
119
211
15Th
is b
it w
ill b
e hi
gh if
a th
erm
isto
r fau
lt is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
bee n
ackn
owle
dged
) on
pum
p 5
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[4
]0
193
1200
This
bit
will
be
high
if a
crit
ical
faul
t is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ackn
owle
dged
) on
pum
p 6
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[5
]7
194
1201
This
bit
will
be
high
if a
non
-crit
ical
faul
t is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ackn
owle
dged
) on
pum
p 6
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[5
]6
195
1202
This
bit
will
be
high
if a
del
ay fa
il fa
ult i
s U
NA
CK
NO
WLE
DG
ED
(Fau
lt is
NO
T pr
esen
t but
has
NO
T be
enac
know
ledg
ed) o
n pu
mp
6 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_un
ackd
[5]
5
196
1203
This
bit
will
be
high
if a
sea
l fau
lt is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ack
now
ledg
edon
pum
p 6
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[5
]4
197
1204
This
bit
will
be
high
if a
flyg
t sea
l fau
lt is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ackn
owle
dged
) on
pum
p 6
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[5
]3
198
1205
This
bit
will
be
high
if a
flyg
t the
rmis
tor f
ault
is U
NA
CK
NO
WLE
DG
ED
(Fau
lt is
NO
T pr
esen
t but
has
NO
T be
enac
know
ledg
ed) o
n pu
mp
6 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_un
ackd
[5]
2
199
1206
Res
erve
dst
atus
_xpc
_pum
p_un
ackd
[5]
120
012
07Th
is b
it w
ill b
e hi
gh if
a th
erm
isto
r fau
lt is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
bee n
ackn
owle
dged
) on
pum
p 6
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[5
]0
201
1208
This
bit
will
be
high
if a
crit
ical
faul
t is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ackn
owle
dged
) on
pum
p 7
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[6
]7
202
1209
This
bit
will
be
high
if a
non
-crit
ical
faul
t is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ackn
owle
dged
) on
pum
p 7
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[6
]6
203
1210
This
bit
will
be
high
if a
del
ay fa
il fa
ult i
s U
NA
CK
NO
WLE
DG
ED
(Fau
lt is
NO
T pr
esen
t but
has
NO
T be
enac
know
ledg
ed) o
n pu
mp
7 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_un
ackd
[6]
5
204
1211
This
bit
will
be
high
if a
sea
l fau
lt is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ack
now
ledg
edon
pum
p 7
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[6
]4
205
1212
This
bit
will
be
high
if a
flyg
t sea
l fau
lt is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ackn
owle
dged
) on
pum
p 7
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[6
]3
206
1213
This
bit
will
be
high
if a
flyg
t the
rmis
tor f
ault
is U
NA
CK
NO
WLE
DG
ED
(Fau
lt is
NO
T pr
esen
t but
has
NO
T be
enac
know
ledg
ed) o
n pu
mp
7 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_un
ackd
[6]
2
207
1214
Res
erve
dst
atus
_xpc
_pum
p_un
ackd
[6]
120
812
15Th
is b
it w
ill b
e hi
gh if
a th
erm
isto
r fau
lt is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
bee n
ackn
owle
dged
) on
pum
p 7
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[6
]0
209
1300
This
bit
will
be
high
if a
crit
ical
faul
t is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
bee n
ackn
owle
dged
) on
pum
p 8
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[7
]7
210
1301
This
bit
will
be
high
if a
non
-crit
ical
faul
t is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ackn
owle
dged
) on
pum
p 8
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[7
]6
211
1302
This
bit
will
be
high
if a
del
ay fa
il fa
ult i
s U
NA
CK
NO
WLE
DG
ED
(Fau
lt is
NO
T pr
esen
t but
has
NO
T be
enac
know
ledg
ed) o
n pu
mp
8 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_un
ackd
[7]
5
212
1303
This
bit
will
be
high
if a
sea
l fau
lt is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ack
now
ledg
edon
pum
p 8
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[7
]4
213
1304
This
bit
will
be
high
if a
flyg
t sea
l fau
lt is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ackn
owle
dged
) on
pum
p 8
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[7
]3
Pag
e 7
Inpu
t Sta
tus
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Sta
tus:
Sin
gle
bit d
igita
l (re
ad o
nly)
* Th
e m
irror
ed in
put r
egis
ter o
ffest
nee
ds to
be
adde
d to
the
conf
igur
ed "M
irror
Bas
e" o
f the
Pro
con
V to
get
act
ual r
egis
ter n
umbe
r. In
dex
Mirr
ored
Inpu
t Reg
iste
rD
escr
iptio
nM
ultit
rode
Cro
ss-R
efer
ence
Offs
et *
Bit
Varia
ble
Bit
214
1305
This
bit
will
be
high
if a
flyg
t the
rmis
tor f
ault
is U
NA
CK
NO
WLE
DG
ED
(Fau
lt is
NO
T pr
esen
t but
has
NO
T be
enac
know
ledg
ed) o
n pu
mp
8 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_un
ackd
[7]
2
215
1306
Res
erve
dst
atus
_xpc
_pum
p_un
ackd
[7]
121
613
07Th
is b
it w
ill b
e hi
gh if
a th
erm
isto
r fau
lt is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
bee n
ackn
owle
dged
) on
pum
p 8
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[7
]0
217
1308
This
bit
will
be
high
if a
crit
ical
faul
t is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ackn
owle
dged
) on
pum
p 9
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[8
]7
218
1309
This
bit
will
be
high
if a
non
-crit
ical
faul
t is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ackn
owle
dged
) on
pum
p 9
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[8
]6
219
1310
This
bit
will
be
high
if a
del
ay fa
il fa
ult i
s U
NA
CK
NO
WLE
DG
ED
(Fau
lt is
NO
T pr
esen
t but
has
NO
T be
enac
know
ledg
ed) o
n pu
mp
9 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_un
ackd
[8]
5
220
1311
This
bit
will
be
high
if a
sea
l fau
lt is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ack
now
ledg
edon
pum
p 9
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[8
]4
221
1312
This
bit
will
be
high
if a
flyg
t sea
l fau
lt is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ackn
owle
dged
) on
pum
p 9
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[8
]3
222
1313
This
bit
will
be
high
if a
flyg
t the
rmis
tor f
ault
is U
NA
CK
NO
WLE
DG
ED
(Fau
lt is
NO
T pr
esen
t but
has
NO
T be
enac
know
ledg
ed) o
n pu
mp
9 an
d lo
w o
ther
wis
est
atus
_xpc
_pum
p_un
ackd
[8]
2
223
1314
Res
erve
dst
atus
_xpc
_pum
p_un
ackd
[8]
122
413
15Th
is b
it w
ill b
e hi
gh if
a th
erm
isto
r fau
lt is
UN
AC
KN
OW
LED
GE
D (F
ault
is N
OT
pres
ent b
ut h
as N
OT
bee n
ackn
owle
dged
) on
pum
p 9
and
low
oth
erw
ise
stat
us_x
pc_p
ump_
unac
kd[8
]0
225
1400
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
any
faul
t sho
wn
belo
w b
eing
PR
ES
EN
and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_pr
esen
t[0][0
]7
226
1401
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
an
unde
r cur
rent
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[0
][0]
6
227
1402
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
an
over
cur
rent
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[0
][0]
5
228
1403
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
a th
erm
al a
larm
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[0
][0]
4
229
1404
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
a p
hase
fail
faul
t bei
ng P
RE
SE
NT
and
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[0
][0]
3
230
1405
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
a p
hase
rota
tion
alar
m fa
ult b
ein
PR
ES
EN
T an
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[0
][0]
2
231
1406
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
an
earth
faul
t bei
ng P
RE
SE
NT
and
is lo
othe
rwis
est
atus
_rtu
_pum
p_pr
esen
t[0][0
]1
232
1407
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
an
insu
latio
n te
st fa
ult b
eing
PR
ES
EN
and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_pr
esen
t[0][0
]0
233
1408
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
a lo
w fl
ow fa
ult b
eing
PR
ES
EN
T an
d is
loot
herw
ise
stat
us_r
tu_p
ump_
pres
ent[0
][1]
7
234
1409
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
an
anal
og in
put 2
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[0
][1]
6
235
1410
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
an
anal
og in
put 1
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[0
][1]
5
236
1411
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
a d
igita
l inp
ut 6
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[0
][1]
4
Pag
e 8
Inpu
t Sta
tus
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Sta
tus:
Sin
gle
bit d
igita
l (re
ad o
nly)
* Th
e m
irror
ed in
put r
egis
ter o
ffest
nee
ds to
be
adde
d to
the
conf
igur
ed "M
irror
Bas
e" o
f the
Pro
con
V to
get
act
ual r
egis
ter n
umbe
r. In
dex
Mirr
ored
Inpu
t Reg
iste
rD
escr
iptio
nM
ultit
rode
Cro
ss-R
efer
ence
Offs
et *
Bit
Varia
ble
Bit
237
1412
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
a d
igita
l inp
ut 5
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[0
][1]
3
238
1413
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
a d
igita
l inp
ut 4
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[0
][1]
2
239
1414
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
a d
igita
l inp
ut 3
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[0
][1]
1
240
1415
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
a d
igita
l inp
ut 2
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[0
][1]
0
241
1500
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
a d
igita
l inp
ut 1
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[0
][2]
7
242
1501
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
a d
igita
l out
put 3
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[0
][2]
6
243
1502
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
a d
igita
l out
put 2
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[0
][2]
5
244
1503
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
a d
igita
l out
put 1
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[0
][2]
4
245
1504
Res
erve
dst
atus
_rtu
_pum
p_pr
esen
t[0][2
]3
246
1505
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
a S
CA
DA
lock
out f
ault
bein
g P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[0
][2]
2
247
1506
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
a lo
w fl
ow w
arni
ng fa
ult b
eing
PR
ES
EN
and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_pr
esen
t[0][2
]1
248
1507
Res
erve
dst
atus
_rtu
_pum
p_pr
esen
t[0][2
]0
249
1508
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
any
faul
t sho
wn
belo
w b
eing
PR
ES
EN
and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_pr
esen
t[1][0
]7
250
1509
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
an
unde
r cur
rent
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[1
][0]
6
251
1510
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
an
over
cur
rent
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[1
][0]
5
252
1511
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
a th
erm
al a
larm
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[1
][0]
4
253
1512
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
a p
hase
fail
faul
t bei
ng P
RE
SE
NT
and
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[1
][0]
3
254
1513
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
a p
hase
rota
tion
alar
m fa
ult b
ein
PR
ES
EN
T an
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[1
][0]
2
255
1514
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
an
earth
faul
t bei
ng P
RE
SE
NT
and
is lo
othe
rwis
est
atus
_rtu
_pum
p_pr
esen
t[1][0
]1
256
1515
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
an
insu
latio
n te
st fa
ult b
eing
PR
ES
EN
and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_pr
esen
t[1][0
]0
257
1600
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
a lo
w fl
ow fa
ult b
eing
PR
ES
EN
T an
d is
l oot
herw
ise
stat
us_r
tu_p
ump_
pres
ent[1
][1]
7
258
1601
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
an
anal
og in
put 2
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[1
][1]
6
259
1602
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
an
anal
og in
put 1
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[1
][1]
5
Pag
e 9
Inpu
t Sta
tus
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Sta
tus:
Sin
gle
bit d
igita
l (re
ad o
nly)
* Th
e m
irror
ed in
put r
egis
ter o
ffest
nee
ds to
be
adde
d to
the
conf
igur
ed "M
irror
Bas
e" o
f the
Pro
con
V to
get
act
ual r
egis
ter n
umbe
r. In
dex
Mirr
ored
Inpu
t Reg
iste
rD
escr
iptio
nM
ultit
rode
Cro
ss-R
efer
ence
Offs
et *
Bit
Varia
ble
Bit
260
1603
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
a d
igita
l inp
ut 6
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[1
][1]
4
261
1604
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
a d
igita
l inp
ut 5
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[1
][1]
3
262
1605
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
a d
igita
l inp
ut 4
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[1
][1]
2
263
1606
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
a d
igita
l inp
ut 3
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[1
][1]
1
264
1607
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
a d
igita
l inp
ut 2
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[1
][1]
0
265
1608
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
a d
igita
l inp
ut 1
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[1
][2]
7
266
1609
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
a d
igita
l out
put 3
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[1
][2]
6
267
1610
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
a d
igita
l out
put 2
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[1
][2]
5
268
1611
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
a d
igita
l out
put 1
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[1
][2]
4
269
1612
Res
erve
dst
atus
_rtu
_pum
p_pr
esen
t[1][2
]3
270
1613
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
a S
CA
DA
lock
out f
ault
bein
g P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[1
][2]
2
271
1614
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
a lo
w fl
ow w
arni
ng fa
ult b
eing
PR
ES
EN
and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_pr
esen
t[1][2
]1
272
1615
Res
erve
dst
atus
_rtu
_pum
p_pr
esen
t[1][2
]0
273
1700
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
any
faul
t sho
wn
belo
w b
eing
PR
ES
EN
and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_pr
esen
t[2][0
]7
274
1701
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
an
unde
r cur
rent
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[2
][0]
6
275
1702
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
an
over
cur
rent
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[2
][0]
5
276
1703
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
a th
erm
al a
larm
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[2
][0]
4
277
1704
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
a p
hase
fail
faul
t bei
ng P
RE
SE
NT
and
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[2
][0]
3
278
1705
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
a p
hase
rota
tion
alar
m fa
ult b
ein
PR
ES
EN
T an
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[2
][0]
2
279
1706
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
an
earth
faul
t bei
ng P
RE
SE
NT
and
is lo
othe
rwis
est
atus
_rtu
_pum
p_pr
esen
t[2][0
]1
280
1707
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
an
insu
latio
n te
st fa
ult b
eing
PR
ES
EN
and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_pr
esen
t[2][0
]0
281
1708
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
a lo
w fl
ow fa
ult b
eing
PR
ES
EN
T an
d is
loot
herw
ise
stat
us_r
tu_p
ump_
pres
ent[2
][1]
7
282
1709
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
an
anal
og in
put 2
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[2
][1]
6
Pag
e 10
Inpu
t Sta
tus
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Sta
tus:
Sin
gle
bit d
igita
l (re
ad o
nly)
* Th
e m
irror
ed in
put r
egis
ter o
ffest
nee
ds to
be
adde
d to
the
conf
igur
ed "M
irror
Bas
e" o
f the
Pro
con
V to
get
act
ual r
egis
ter n
umbe
r. In
dex
Mirr
ored
Inpu
t Reg
iste
rD
escr
iptio
nM
ultit
rode
Cro
ss-R
efer
ence
Offs
et *
Bit
Varia
ble
Bit
283
1710
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
an
anal
og in
put 1
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[2
][1]
5
284
1711
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
a d
igita
l inp
ut 6
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[2
][1]
4
285
1712
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
a d
igita
l inp
ut 5
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[2
][1]
3
286
1713
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
a d
igita
l inp
ut 4
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[2
][1]
2
287
1714
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
a d
igita
l inp
ut 3
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[2
][1]
1
288
1715
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
a d
igita
l inp
ut 2
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[2
][1]
0
289
1800
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
a d
igita
l inp
ut 1
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[2
][2]
7
290
1801
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
a d
igita
l out
put 3
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[2
][2]
6
291
1802
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
a d
igita
l out
put 2
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[2
][2]
5
292
1803
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
a d
igita
l out
put 1
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[2
][2]
4
293
1804
Res
erve
dst
atus
_rtu
_pum
p_pr
esen
t[2][2
]3
294
1805
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
a S
CA
DA
lock
out f
ault
bein
g P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[2
][2]
2
295
1806
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
a lo
w fl
ow w
arni
ng fa
ult b
eing
PR
ES
EN
and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_pr
esen
t[2][2
]1
296
1807
Res
erve
dst
atus
_rtu
_pum
p_pr
esen
t[2][2
]0
297
1808
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
any
faul
t sho
wn
belo
w b
eing
PR
ES
EN
and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_pr
esen
t[3][0
]7
298
1809
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
an
unde
r cur
rent
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[3
][0]
6
299
1810
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
an
over
cur
rent
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[3
][0]
5
300
1811
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
a th
erm
al a
larm
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[3
][0]
4
301
1812
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
a p
hase
fail
faul
t bei
ng P
RE
SE
NT
and
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[3
][0]
3
302
1813
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
a p
hase
rota
tion
alar
m fa
ult b
ein
PR
ES
EN
T an
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[3
][0]
2
303
1814
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
an
earth
faul
t bei
ng P
RE
SE
NT
and
is l o
othe
rwis
est
atus
_rtu
_pum
p_pr
esen
t[3][0
]1
304
1815
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
an
insu
latio
n te
st fa
ult b
eing
PR
ES
EN
and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_pr
esen
t[3][0
]0
305
1900
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
a lo
w fl
ow fa
ult b
eing
PR
ES
EN
T an
d is
loot
herw
ise
stat
us_r
tu_p
ump_
pres
ent[3
][1]
7
Pag
e 11
Inpu
t Sta
tus
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Sta
tus:
Sin
gle
bit d
igita
l (re
ad o
nly)
* Th
e m
irror
ed in
put r
egis
ter o
ffest
nee
ds to
be
adde
d to
the
conf
igur
ed "M
irror
Bas
e" o
f the
Pro
con
V to
get
act
ual r
egis
ter n
umbe
r. In
dex
Mirr
ored
Inpu
t Reg
iste
rD
escr
iptio
nM
ultit
rode
Cro
ss-R
efer
ence
Offs
et *
Bit
Varia
ble
Bit
306
1901
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
an
anal
og in
put 2
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[3
][1]
6
307
1902
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
an
anal
og in
put 1
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[3
][1]
5
308
1903
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
a d
igita
l inp
ut 6
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[3
][1]
4
309
1904
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
a d
igita
l inp
ut 5
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[3
][1]
3
310
1905
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
a d
igita
l inp
ut 4
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[3
][1]
2
311
1906
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
a d
igita
l inp
ut 3
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[3
][1]
1
312
1907
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
a d
igita
l inp
ut 2
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[3
][1]
0
313
1908
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
a d
igita
l inp
ut 1
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[3
][2]
7
314
1909
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
a d
igita
l out
put 3
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[3
][2]
6
315
1910
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
a d
igita
l out
put 2
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[3
][2]
5
316
1911
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
a d
igita
l out
put 1
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[3
][2]
4
317
1912
Res
erve
dst
atus
_rtu
_pum
p_pr
esen
t[3][2
]3
318
1913
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
a S
CA
DA
lock
out f
ault
bein
g P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[3
][2]
2
319
1914
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
a lo
w fl
ow w
arni
ng fa
ult b
eing
PR
ES
EN
and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_pr
esen
t[3][2
]1
320
1915
Res
erve
dst
atus
_rtu
_pum
p_pr
esen
t[3][2
]0
321
2000
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
any
faul
t sho
wn
belo
w b
eing
PR
ES
EN
and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_pr
esen
t[4][0
]7
322
2001
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
an
unde
r cur
rent
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[4
][0]
6
323
2002
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
an
over
cur
rent
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[4
][0]
5
324
2003
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
a th
erm
al a
larm
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[4
][0]
4
325
2004
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
a p
hase
fail
faul
t bei
ng P
RE
SE
NT
and
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[4
][0]
3
326
2005
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
a p
hase
rota
tion
alar
m fa
ult b
ein
PR
ES
EN
T an
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[4
][0]
2
327
2006
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
an
earth
faul
t bei
ng P
RE
SE
NT
and
is lo
othe
rwis
est
atus
_rtu
_pum
p_pr
esen
t[4][0
]1
328
2007
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
an
insu
latio
n te
st fa
ult b
eing
PR
ES
EN
and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_pr
esen
t[4][0
]0
Pag
e 12
Inpu
t Sta
tus
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Sta
tus:
Sin
gle
bit d
igita
l (re
ad o
nly)
* Th
e m
irror
ed in
put r
egis
ter o
ffest
nee
ds to
be
adde
d to
the
conf
igur
ed "M
irror
Bas
e" o
f the
Pro
con
V to
get
act
ual r
egis
ter n
umbe
r. In
dex
Mirr
ored
Inpu
t Reg
iste
rD
escr
iptio
nM
ultit
rode
Cro
ss-R
efer
ence
Offs
et *
Bit
Varia
ble
Bit
329
2008
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
a lo
w fl
ow fa
ult b
eing
PR
ES
EN
T an
d is
loot
herw
ise
stat
us_r
tu_p
ump_
pres
ent[4
][1]
7
330
2009
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
an
anal
og in
put 2
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[4
][1]
6
331
2010
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
an
anal
og in
put 1
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[4
][1]
5
332
2011
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
a d
igita
l inp
ut 6
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[4
][1]
4
333
2012
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
a d
igita
l inp
ut 5
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[4
][1]
3
334
2013
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
a d
igita
l inp
ut 4
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[4
][1]
2
335
2014
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
a d
igita
l inp
ut 3
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[4
][1]
1
336
2015
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
a d
igita
l inp
ut 2
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[4
][1]
0
337
2100
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
a d
igita
l inp
ut 1
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[4
][2]
7
338
2101
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
a d
igita
l out
put 3
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[4
][2]
6
339
2102
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
a d
igita
l out
put 2
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[4
][2]
5
340
2103
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
a d
igita
l out
put 1
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[4
][2]
4
341
2104
Res
erve
dst
atus
_rtu
_pum
p_pr
esen
t[4][2
]3
342
2105
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
a S
CA
DA
lock
out f
ault
bein
g P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[4
][2]
2
343
2106
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
a lo
w fl
ow w
arni
ng fa
ult b
eing
PR
ES
EN
and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_pr
esen
t[4][2
]1
344
2107
Res
erve
dst
atus
_rtu
_pum
p_pr
esen
t[4][2
]0
345
2108
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
any
faul
t sho
wn
belo
w b
eing
PR
ES
EN
and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_pr
esen
t[5][0
]7
346
2109
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
an
unde
r cur
rent
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[5
][0]
6
347
2110
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
an
over
cur
rent
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[5
][0]
5
348
2111
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
a th
erm
al a
larm
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[5
][0]
4
349
2112
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
a p
hase
fail
faul
t bei
ng P
RE
SE
NT
and
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[5
][0]
3
350
2113
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
a p
hase
rota
tion
alar
m fa
ult b
ein
PR
ES
EN
T an
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[5
][0]
2
351
2114
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
an
earth
faul
t bei
ng P
RE
SE
NT
and
is lo
othe
rwis
est
atus
_rtu
_pum
p_pr
esen
t[5][0
]1
Pag
e 13
Inpu
t Sta
tus
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Sta
tus:
Sin
gle
bit d
igita
l (re
ad o
nly)
* Th
e m
irror
ed in
put r
egis
ter o
ffest
nee
ds to
be
adde
d to
the
conf
igur
ed "M
irror
Bas
e" o
f the
Pro
con
V to
get
act
ual r
egis
ter n
umbe
r. In
dex
Mirr
ored
Inpu
t Reg
iste
rD
escr
iptio
nM
ultit
rode
Cro
ss-R
efer
ence
Offs
et *
Bit
Varia
ble
Bit
352
2115
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
an
insu
latio
n te
st fa
ult b
eing
PR
ES
EN
and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_pr
esen
t[5][0
]0
353
2200
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
a lo
w fl
ow fa
ult b
eing
PR
ES
EN
T an
d is
loot
herw
ise
stat
us_r
tu_p
ump_
pres
ent[5
][1]
7
354
2201
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
an
anal
og in
put 2
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[5
][1]
6
355
2202
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
an
anal
og in
put 1
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[5
][1]
5
356
2203
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
a d
igita
l inp
ut 6
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[5
][1]
4
357
2204
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
a d
igita
l inp
ut 5
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[5
][1]
3
358
2205
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
a d
igita
l inp
ut 4
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[5
][1]
2
359
2206
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
a d
igita
l inp
ut 3
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[5
][1]
1
360
2207
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
a d
igita
l inp
ut 2
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[5
][1]
0
361
2208
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
a d
igita
l inp
ut 1
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[5
][2]
7
362
2209
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
a d
igita
l out
put 3
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[5
][2]
6
363
2210
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
a d
igita
l out
put 2
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[5
][2]
5
364
2211
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
a d
igita
l out
put 1
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[5
][2]
4
365
2212
Res
erve
dst
atus
_rtu
_pum
p_pr
esen
t[5][2
]3
366
2213
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
a S
CA
DA
lock
out f
ault
bein
g P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[5
][2]
2
367
2214
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
a lo
w fl
ow w
arni
ng fa
ult b
eing
PR
ES
EN
and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_pr
esen
t[5][2
]1
368
2215
Res
erve
dst
atus
_rtu
_pum
p_pr
esen
t[5][2
]0
369
2300
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
any
faul
t sho
wn
belo
w b
eing
PR
ES
EN
and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_pr
esen
t[6][0
]7
370
2301
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
an
unde
r cur
rent
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[6
][0]
6
371
2302
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
an
over
cur
rent
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[6
][0]
5
372
2303
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
a th
erm
al a
larm
faul
t bei
ng P
RE
SE
NT
a nis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[6
][0]
4
373
2304
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
a p
hase
fail
faul
t bei
ng P
RE
SE
NT
and
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[6
][0]
3
374
2305
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
a p
hase
rota
tion
alar
m fa
ult b
ein
PR
ES
EN
T an
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[6
][0]
2
Pag
e 14
Inpu
t Sta
tus
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Sta
tus:
Sin
gle
bit d
igita
l (re
ad o
nly)
* Th
e m
irror
ed in
put r
egis
ter o
ffest
nee
ds to
be
adde
d to
the
conf
igur
ed "M
irror
Bas
e" o
f the
Pro
con
V to
get
act
ual r
egis
ter n
umbe
r. In
dex
Mirr
ored
Inpu
t Reg
iste
rD
escr
iptio
nM
ultit
rode
Cro
ss-R
efer
ence
Offs
et *
Bit
Varia
ble
Bit
375
2306
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
an
earth
faul
t bei
ng P
RE
SE
NT
and
is lo
othe
rwis
est
atus
_rtu
_pum
p_pr
esen
t[6][0
]1
376
2307
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
an
insu
latio
n te
st fa
ult b
eing
PR
ES
EN
and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_pr
esen
t[6][0
]0
377
2308
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
a lo
w fl
ow fa
ult b
eing
PR
ES
EN
T an
d is
loot
herw
ise
stat
us_r
tu_p
ump_
pres
ent[6
][1]
7
378
2309
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
an
anal
og in
put 2
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[6
][1]
6
379
2310
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
an
anal
og in
put 1
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[6
][1]
5
380
2311
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
a d
igita
l inp
ut 6
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[6
][1]
4
381
2312
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
a d
igita
l inp
ut 5
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[6
][1]
3
382
2313
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
a d
igita
l inp
ut 4
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[6
][1]
2
383
2314
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
a d
igita
l inp
ut 3
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[6
][1]
1
384
2315
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
a d
igita
l inp
ut 2
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[6
][1]
0
385
2400
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
a d
igita
l inp
ut 1
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[6
][2]
7
386
2401
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
a d
igita
l out
put 3
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[6
][2]
6
387
2402
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
a d
igita
l out
put 2
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[6
][2]
5
388
2403
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
a d
igita
l out
put 1
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[6
][2]
4
389
2404
Res
erve
dst
atus
_rtu
_pum
p_pr
esen
t[6][2
]3
390
2405
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
a S
CA
DA
lock
out f
ault
bein
g P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[6
][2]
2
391
2406
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
a lo
w fl
ow w
arni
ng fa
ult b
eing
PR
ES
EN
and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_pr
esen
t[6][2
]1
392
2407
Res
erve
dst
atus
_rtu
_pum
p_pr
esen
t[6][2
]0
393
2408
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
any
faul
t sho
wn
belo
w b
eing
PR
ES
EN
and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_pr
esen
t[7][0
]7
394
2409
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
an
unde
r cur
rent
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[7
][0]
6
395
2410
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
an
over
cur
rent
faul
t bei
ng P
RE
SE
NT
a nis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[7
][0]
5
396
2411
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
a th
erm
al a
larm
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[7
][0]
4
397
2412
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
a p
hase
fail
faul
t bei
ng P
RE
SE
NT
and
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[7
][0]
3
Pag
e 15
Inpu
t Sta
tus
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Sta
tus:
Sin
gle
bit d
igita
l (re
ad o
nly)
* Th
e m
irror
ed in
put r
egis
ter o
ffest
nee
ds to
be
adde
d to
the
conf
igur
ed "M
irror
Bas
e" o
f the
Pro
con
V to
get
act
ual r
egis
ter n
umbe
r. In
dex
Mirr
ored
Inpu
t Reg
iste
rD
escr
iptio
nM
ultit
rode
Cro
ss-R
efer
ence
Offs
et *
Bit
Varia
ble
Bit
398
2413
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
a p
hase
rota
tion
alar
m fa
ult b
ein
PR
ES
EN
T an
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[7
][0]
2
399
2414
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
an
earth
faul
t bei
ng P
RE
SE
NT
and
is lo
othe
rwis
est
atus
_rtu
_pum
p_pr
esen
t[7][0
]1
400
2415
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
an
insu
latio
n te
st fa
ult b
eing
PR
ES
EN
and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_pr
esen
t[7][0
]0
401
2500
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
a lo
w fl
ow fa
ult b
eing
PR
ES
EN
T an
d is
loot
herw
ise
stat
us_r
tu_p
ump_
pres
ent[7
][1]
7
402
2501
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
an
anal
og in
put 2
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[7
][1]
6
403
2502
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
an
anal
og in
put 1
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[7
][1]
5
404
2503
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
a d
igita
l inp
ut 6
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[7
][1]
4
405
2504
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
a d
igita
l inp
ut 5
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[7
][1]
3
406
2505
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
a d
igita
l inp
ut 4
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[7
][1]
2
407
2506
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
a d
igita
l inp
ut 3
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[7
][1]
1
408
2507
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
a d
igita
l inp
ut 2
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[7
][1]
0
409
2508
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
a d
igita
l inp
ut 1
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[7
][2]
7
410
2509
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
a d
igita
l out
put 3
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[7
][2]
6
411
2510
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
a d
igita
l out
put 2
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[7
][2]
5
412
2511
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
a d
igita
l out
put 1
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[7
][2]
4
413
2512
Res
erve
dst
atus
_rtu
_pum
p_pr
esen
t[7][2
]3
414
2513
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
a S
CA
DA
lock
out f
ault
bein
g P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[7
][2]
2
415
2514
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
a lo
w fl
ow w
arni
ng fa
ult b
eing
PR
ES
EN
and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_pr
esen
t[7][2
]1
416
2515
Res
erve
dst
atus
_rtu
_pum
p_pr
esen
t[7][2
]0
417
2600
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
any
faul
t sho
wn
belo
w b
eing
PR
ES
EN
and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_pr
esen
t[8][0
]7
418
2601
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
an
unde
r cur
rent
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[8
][0]
6
419
2602
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
an
over
cur
rent
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[8
][0]
5
420
2603
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
a th
erm
al a
larm
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[8
][0]
4
Pag
e 16
Inpu
t Sta
tus
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Sta
tus:
Sin
gle
bit d
igita
l (re
ad o
nly)
* Th
e m
irror
ed in
put r
egis
ter o
ffest
nee
ds to
be
adde
d to
the
conf
igur
ed "M
irror
Bas
e" o
f the
Pro
con
V to
get
act
ual r
egis
ter n
umbe
r. In
dex
Mirr
ored
Inpu
t Reg
iste
rD
escr
iptio
nM
ultit
rode
Cro
ss-R
efer
ence
Offs
et *
Bit
Varia
ble
Bit
421
2604
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
a p
hase
fail
faul
t bei
ng P
RE
SE
NT
and
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[8
][0]
3
422
2605
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
a p
hase
rota
tion
alar
m fa
ult b
ein
PR
ES
EN
T an
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[8
][0]
2
423
2606
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
an
earth
faul
t bei
ng P
RE
SE
NT
and
is lo
othe
rwis
est
atus
_rtu
_pum
p_pr
esen
t[8][0
]1
424
2607
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
an
insu
latio
n te
st fa
ult b
eing
PR
ES
EN
and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_pr
esen
t[8][0
]0
425
2608
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
a lo
w fl
ow fa
ult b
eing
PR
ES
EN
T an
d is
loot
herw
ise
stat
us_r
tu_p
ump_
pres
ent[8
][1]
7
426
2609
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
an
anal
og in
put 2
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[8
][1]
6
427
2610
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
an
anal
og in
put 1
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[8
][1]
5
428
2611
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
a d
igita
l inp
ut 6
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[8
][1]
4
429
2612
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
a d
igita
l inp
ut 5
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[8
][1]
3
430
2613
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
a d
igita
l inp
ut 4
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[8
][1]
2
431
2614
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
a d
igita
l inp
ut 3
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[8
][1]
1
432
2615
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
a d
igita
l inp
ut 2
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[8
][1]
0
433
2700
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
a d
igita
l inp
ut 1
faul
t bei
ng P
RE
SE
NT
anis
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[8
][2]
7
434
2701
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
a d
igita
l out
put 3
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[8
][2]
6
435
2702
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
a d
igita
l out
put 2
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[8
][2]
5
436
2703
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
a d
igita
l out
put 1
faul
t bei
ng P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[8
][2]
4
437
2704
Res
erve
dst
atus
_rtu
_pum
p_pr
esen
t[8][2
]3
438
2705
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
a S
CA
DA
lock
out f
ault
bein
g P
RE
SE
Nan
d is
low
oth
erw
ise
stat
us_r
tu_p
ump_
pres
ent[8
][2]
2
439
2706
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
a lo
w fl
ow w
arni
ng fa
ult b
eing
PR
ES
EN
and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_pr
esen
t[8][2
]1
440
2707
Res
erve
dst
atus
_rtu
_pum
p_pr
esen
t[8][2
]0
441
2708
Res
erve
dst
atus
_rtu
_pum
p_un
ackd
[0][0
]7
442
2709
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
an
unde
r cur
rent
faul
t whi
ch h
as b
e eU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[0][0
]6
443
2710
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
an
over
cur
rent
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[0][0
]5
Pag
e 17
Inpu
t Sta
tus
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Sta
tus:
Sin
gle
bit d
igita
l (re
ad o
nly)
* Th
e m
irror
ed in
put r
egis
ter o
ffest
nee
ds to
be
adde
d to
the
conf
igur
ed "M
irror
Bas
e" o
f the
Pro
con
V to
get
act
ual r
egis
ter n
umbe
r. In
dex
Mirr
ored
Inpu
t Reg
iste
rD
escr
iptio
nM
ultit
rode
Cro
ss-R
efer
ence
Offs
et *
Bit
Varia
ble
Bit
444
2711
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
a th
erm
al a
larm
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[0][0
]4
445
2712
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
a p
hase
fail
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[0][0
]3
446
2713
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
a p
hase
rota
tion
alar
m fa
ult w
hich
has
be
en U
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
e
stat
us_r
tu_p
ump_
unac
kd[0
][0]
2
447
2714
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
an
earth
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[0][0
]1
448
2715
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
an
insu
latio
n te
st fa
ult w
hich
has
bee
UN
AC
KN
OW
LED
GE
D (f
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ack
now
ledg
ed) a
nd is
low
oth
erw
ise
stat
us_r
tu_p
ump_
unac
kd[0
][0]
0
449
2800
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
a lo
w fl
ow fa
ult w
hich
has
bee
UN
AC
KN
OW
LED
GE
D (f
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ack
now
ledg
ed) a
nd is
low
oth
erw
ise
stat
us_r
tu_p
ump_
unac
kd[0
][1]
7
450
2801
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
an
anal
og in
put 2
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[0][1
]6
451
2802
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
an
anal
og in
put 1
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[0][1
]5
452
2803
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
a d
igita
l inp
ut 6
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[0][1
]4
453
2804
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
a d
igita
l inp
ut 5
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[0][1
]3
454
2805
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
a d
igita
l inp
ut 4
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[0][1
]2
455
2806
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
a d
igita
l inp
ut 3
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[0][1
]1
456
2807
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
a d
igita
l inp
ut 2
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[0][1
]0
457
2808
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
a d
igita
l inp
ut 1
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[0][2
]7
458
2809
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
a d
igita
l out
put 3
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[0][2
]6
459
2810
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
a d
igita
l out
put 2
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[0][2
]5
460
2811
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
a d
igita
l out
put 1
faul
t whi
ch h
as b
e eU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[0][2
]4
461
2812
Res
erve
dst
atus
_rtu
_pum
p_un
ackd
[0][2
]3
462
2813
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
a S
CA
DA
lock
out f
ault
whi
ch h
as b
e eU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[0][2
]2
463
2814
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
1 du
e to
a lo
w fl
ow w
arni
ng fa
ult w
hich
has
be e
UN
AC
KN
OW
LED
GE
D (f
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ack
now
ledg
ed) a
nd is
low
oth
erw
ise
stat
us_r
tu_p
ump_
unac
kd[0
][2]
1
464
2815
Res
erve
dst
atus
_rtu
_pum
p_un
ackd
[0][2
]0
465
2900
Res
erve
dst
atus
_rtu
_pum
p_un
ackd
[1][0
]7
466
2901
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
an
unde
r cur
rent
faul
t whi
ch h
as b
e eU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[1][0
]6
Pag
e 18
Inpu
t Sta
tus
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Sta
tus:
Sin
gle
bit d
igita
l (re
ad o
nly)
* Th
e m
irror
ed in
put r
egis
ter o
ffest
nee
ds to
be
adde
d to
the
conf
igur
ed "M
irror
Bas
e" o
f the
Pro
con
V to
get
act
ual r
egis
ter n
umbe
r. In
dex
Mirr
ored
Inpu
t Reg
iste
rD
escr
iptio
nM
ultit
rode
Cro
ss-R
efer
ence
Offs
et *
Bit
Varia
ble
Bit
467
2902
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
an
over
cur
rent
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[1][0
]5
468
2903
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
a th
erm
al a
larm
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[1][0
]4
469
2904
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
a p
hase
fail
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[1][0
]3
470
2905
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
a p
hase
rota
tion
alar
m fa
ult w
hich
has
be
en U
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
e
stat
us_r
tu_p
ump_
unac
kd[1
][0]
2
471
2906
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
an
earth
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[1][0
]1
472
2907
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
an
insu
latio
n te
st fa
ult w
hich
has
bee
UN
AC
KN
OW
LED
GE
D (f
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ack
now
ledg
ed) a
nd is
low
oth
erw
ise
stat
us_r
tu_p
ump_
unac
kd[1
][0]
0
473
2908
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
a lo
w fl
ow fa
ult w
hich
has
bee
UN
AC
KN
OW
LED
GE
D (f
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ack
now
ledg
ed) a
nd is
low
oth
erw
ise
stat
us_r
tu_p
ump_
unac
kd[1
][1]
7
474
2909
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
an
anal
og in
put 2
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[1][1
]6
475
2910
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
an
anal
og in
put 1
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[1][1
]5
476
2911
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
a d
igita
l inp
ut 6
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[1][1
]4
477
2912
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
a d
igita
l inp
ut 5
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[1][1
]3
478
2913
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
a d
igita
l inp
ut 4
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[1][1
]2
479
2914
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
a d
igita
l inp
ut 3
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[1][1
]1
480
2915
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
a d
igita
l inp
ut 2
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[1][1
]0
481
3000
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
a d
igita
l inp
ut 1
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[1][2
]7
482
3001
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
a d
igita
l out
put 3
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[1][2
]6
483
3002
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
a d
igita
l out
put 2
faul
t whi
ch h
as b
e eU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[1][2
]5
484
3003
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
a d
igita
l out
put 1
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[1][2
]4
485
3004
Res
erve
dst
atus
_rtu
_pum
p_un
ackd
[1][2
]3
486
3005
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
a S
CA
DA
lock
out f
ault
whi
ch h
as b
e eU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[1][2
]2
487
3006
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
2 du
e to
a lo
w fl
ow w
arni
ng fa
ult w
hich
has
bee
UN
AC
KN
OW
LED
GE
D (f
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ack
now
ledg
ed) a
nd is
low
oth
erw
ise
stat
us_r
tu_p
ump_
unac
kd[1
][2]
1
488
3007
Res
erve
dst
atus
_rtu
_pum
p_un
ackd
[1][2
]0
489
3008
Res
erve
dst
atus
_rtu
_pum
p_un
ackd
[2][0
]7
Pag
e 19
Inpu
t Sta
tus
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Sta
tus:
Sin
gle
bit d
igita
l (re
ad o
nly)
* Th
e m
irror
ed in
put r
egis
ter o
ffest
nee
ds to
be
adde
d to
the
conf
igur
ed "M
irror
Bas
e" o
f the
Pro
con
V to
get
act
ual r
egis
ter n
umbe
r. In
dex
Mirr
ored
Inpu
t Reg
iste
rD
escr
iptio
nM
ultit
rode
Cro
ss-R
efer
ence
Offs
et *
Bit
Varia
ble
Bit
490
3009
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
an
unde
r cur
rent
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[2][0
]6
491
3010
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
an
over
cur
rent
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[2][0
]5
492
3011
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
a th
erm
al a
larm
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[2][0
]4
493
3012
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
a p
hase
fail
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[2][0
]3
494
3013
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
a p
hase
rota
tion
alar
m fa
ult w
hich
has
be
en U
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
e
stat
us_r
tu_p
ump_
unac
kd[2
][0]
2
495
3014
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
an
earth
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[2][0
]1
496
3015
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
an
insu
latio
n te
st fa
ult w
hich
has
bee
UN
AC
KN
OW
LED
GE
D (f
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ack
now
ledg
ed) a
nd is
low
oth
erw
ise
stat
us_r
tu_p
ump_
unac
kd[2
][0]
0
497
3100
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
a lo
w fl
ow fa
ult w
hich
has
bee
UN
AC
KN
OW
LED
GE
D (f
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ack
now
ledg
ed) a
nd is
low
oth
erw
ise
stat
us_r
tu_p
ump_
unac
kd[2
][1]
7
498
3101
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
an
anal
og in
put 2
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[2][1
]6
499
3102
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
an
anal
og in
put 1
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[2][1
]5
500
3103
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
a d
igita
l inp
ut 6
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[2][1
]4
501
3104
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
a d
igita
l inp
ut 5
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[2][1
]3
502
3105
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
a d
igita
l inp
ut 4
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[2][1
]2
503
3106
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
a d
igita
l inp
ut 3
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[2][1
]1
504
3107
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
a d
igita
l inp
ut 2
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[2][1
]0
505
3108
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
a d
igita
l inp
ut 1
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[2][2
]7
506
3109
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
a d
igita
l out
put 3
faul
t whi
ch h
as b
e eU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[2][2
]6
507
3110
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
a d
igita
l out
put 2
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[2][2
]5
508
3111
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
a d
igita
l out
put 1
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[2][2
]4
509
3112
Res
erve
dst
atus
_rtu
_pum
p_un
ackd
[2][2
]3
510
3113
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
a S
CA
DA
lock
out f
ault
whi
ch h
as b
e eU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[2][2
]2
511
3114
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
3 du
e to
a lo
w fl
ow w
arni
ng fa
ult w
hich
has
bee
UN
AC
KN
OW
LED
GE
D (f
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ack
now
ledg
ed) a
nd is
low
oth
erw
ise
stat
us_r
tu_p
ump_
unac
kd[2
][2]
1
Pag
e 20
Inpu
t Sta
tus
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Sta
tus:
Sin
gle
bit d
igita
l (re
ad o
nly)
* Th
e m
irror
ed in
put r
egis
ter o
ffest
nee
ds to
be
adde
d to
the
conf
igur
ed "M
irror
Bas
e" o
f the
Pro
con
V to
get
act
ual r
egis
ter n
umbe
r. In
dex
Mirr
ored
Inpu
t Reg
iste
rD
escr
iptio
nM
ultit
rode
Cro
ss-R
efer
ence
Offs
et *
Bit
Varia
ble
Bit
512
3115
Res
erve
dst
atus
_rtu
_pum
p_un
ackd
[2][2
]0
513
3200
Res
erve
dst
atus
_rtu
_pum
p_un
ackd
[3][0
]7
514
3201
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
an
unde
r cur
rent
faul
t whi
ch h
as b
e eU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[3][0
]6
515
3202
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
an
over
cur
rent
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[3][0
]5
516
3203
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
a th
erm
al a
larm
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[3][0
]4
517
3204
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
a p
hase
fail
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[3][0
]3
518
3205
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
a p
hase
rota
tion
alar
m fa
ult w
hich
has
be
en U
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
e
stat
us_r
tu_p
ump_
unac
kd[3
][0]
2
519
3206
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
an
earth
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[3][0
]1
520
3207
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
an
insu
latio
n te
st fa
ult w
hich
has
bee
UN
AC
KN
OW
LED
GE
D (f
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ack
now
ledg
ed) a
nd is
low
oth
erw
ise
stat
us_r
tu_p
ump_
unac
kd[3
][0]
0
521
3208
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
a lo
w fl
ow fa
ult w
hich
has
bee
UN
AC
KN
OW
LED
GE
D (f
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ack
now
ledg
ed) a
nd is
low
oth
erw
ise
stat
us_r
tu_p
ump_
unac
kd[3
][1]
7
522
3209
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
an
anal
og in
put 2
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[3][1
]6
523
3210
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
an
anal
og in
put 1
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[3][1
]5
524
3211
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
a d
igita
l inp
ut 6
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[3][1
]4
525
3212
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
a d
igita
l inp
ut 5
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[3][1
]3
526
3213
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
a d
igita
l inp
ut 4
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[3][1
]2
527
3214
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
a d
igita
l inp
ut 3
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[3][1
]1
528
3215
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
a d
igita
l inp
ut 2
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[3][1
]0
529
3300
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
a d
igita
l inp
ut 1
faul
t whi
ch h
as b
e eU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[3][2
]7
530
3301
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
a d
igita
l out
put 3
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[3][2
]6
531
3302
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
a d
igita
l out
put 2
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[3][2
]5
532
3303
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
a d
igita
l out
put 1
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[3][2
]4
533
3304
Res
erve
dst
atus
_rtu
_pum
p_un
ackd
[3][2
]3
534
3305
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
a S
CA
DA
lock
out f
ault
whi
ch h
as b
e eU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[3][2
]2
Pag
e 21
Inpu
t Sta
tus
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Sta
tus:
Sin
gle
bit d
igita
l (re
ad o
nly)
* Th
e m
irror
ed in
put r
egis
ter o
ffest
nee
ds to
be
adde
d to
the
conf
igur
ed "M
irror
Bas
e" o
f the
Pro
con
V to
get
act
ual r
egis
ter n
umbe
r. In
dex
Mirr
ored
Inpu
t Reg
iste
rD
escr
iptio
nM
ultit
rode
Cro
ss-R
efer
ence
Offs
et *
Bit
Varia
ble
Bit
535
3306
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
4 du
e to
a lo
w fl
ow w
arni
ng fa
ult w
hich
has
bee
UN
AC
KN
OW
LED
GE
D (f
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ack
now
ledg
ed) a
nd is
low
oth
erw
ise
stat
us_r
tu_p
ump_
unac
kd[3
][2]
1
536
3307
Res
erve
dst
atus
_rtu
_pum
p_un
ackd
[3][2
]0
537
3308
Res
erve
dst
atus
_rtu
_pum
p_un
ackd
[4][0
]7
538
3309
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
an
unde
r cur
rent
faul
t whi
ch h
as b
e eU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[4][0
]6
539
3310
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
an
over
cur
rent
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[4][0
]5
540
3311
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
a th
erm
al a
larm
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[4][0
]4
541
3312
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
a p
hase
fail
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[4][0
]3
542
3313
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
a p
hase
rota
tion
alar
m fa
ult w
hich
has
be
en U
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
e
stat
us_r
tu_p
ump_
unac
kd[4
][0]
2
543
3314
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
an
earth
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[4][0
]1
544
3315
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
an
insu
latio
n te
st fa
ult w
hich
has
bee
UN
AC
KN
OW
LED
GE
D (f
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ack
now
ledg
ed) a
nd is
low
oth
erw
ise
stat
us_r
tu_p
ump_
unac
kd[4
][0]
0
545
3400
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
a lo
w fl
ow fa
ult w
hich
has
bee
UN
AC
KN
OW
LED
GE
D (f
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ack
now
ledg
ed) a
nd is
low
oth
erw
ise
stat
us_r
tu_p
ump_
unac
kd[4
][1]
7
546
3401
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
an
anal
og in
put 2
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[4][1
]6
547
3402
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
an
anal
og in
put 1
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[4][1
]5
548
3403
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
a d
igita
l inp
ut 6
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[4][1
]4
549
3404
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
a d
igita
l inp
ut 5
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[4][1
]3
550
3405
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
a d
igita
l inp
ut 4
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[4][1
]2
551
3406
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
a d
igita
l inp
ut 3
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[4][1
]1
552
3407
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
a d
igita
l inp
ut 2
faul
t whi
ch h
as b
e eU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[4][1
]0
553
3408
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
a d
igita
l inp
ut 1
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[4][2
]7
554
3409
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
a d
igita
l out
put 3
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[4][2
]6
555
3410
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
a d
igita
l out
put 2
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[4][2
]5
556
3411
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
a d
igita
l out
put 1
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[4][2
]4
557
3412
Res
erve
dst
atus
_rtu
_pum
p_un
ackd
[4][2
]3
Pag
e 22
Inpu
t Sta
tus
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Sta
tus:
Sin
gle
bit d
igita
l (re
ad o
nly)
* Th
e m
irror
ed in
put r
egis
ter o
ffest
nee
ds to
be
adde
d to
the
conf
igur
ed "M
irror
Bas
e" o
f the
Pro
con
V to
get
act
ual r
egis
ter n
umbe
r. In
dex
Mirr
ored
Inpu
t Reg
iste
rD
escr
iptio
nM
ultit
rode
Cro
ss-R
efer
ence
Offs
et *
Bit
Varia
ble
Bit
558
3413
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
a S
CA
DA
lock
out f
ault
whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[4][2
]2
559
3414
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
5 du
e to
a lo
w fl
ow w
arni
ng fa
ult w
hich
has
bee
UN
AC
KN
OW
LED
GE
D (f
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ack
now
ledg
ed) a
nd is
low
oth
erw
ise
stat
us_r
tu_p
ump_
unac
kd[4
][2]
1
560
3415
Res
erve
dst
atus
_rtu
_pum
p_un
ackd
[4][2
]0
561
3500
Res
erve
dst
atus
_rtu
_pum
p_un
ackd
[5][0
]7
562
3501
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
an
unde
r cur
rent
faul
t whi
ch h
as b
e eU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[5][0
]6
563
3502
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
an
over
cur
rent
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[5][0
]5
564
3503
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
a th
erm
al a
larm
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[5][0
]4
565
3504
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
a p
hase
fail
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[5][0
]3
566
3505
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
a p
hase
rota
tion
alar
m fa
ult w
hich
has
be
en U
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
e
stat
us_r
tu_p
ump_
unac
kd[5
][0]
2
567
3506
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
an
earth
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[5][0
]1
568
3507
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
an
insu
latio
n te
st fa
ult w
hich
has
bee
UN
AC
KN
OW
LED
GE
D (f
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ack
now
ledg
ed) a
nd is
low
oth
erw
ise
stat
us_r
tu_p
ump_
unac
kd[5
][0]
0
569
3508
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
a lo
w fl
ow fa
ult w
hich
has
bee
UN
AC
KN
OW
LED
GE
D (f
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ack
now
ledg
ed) a
nd is
low
oth
erw
ise
stat
us_r
tu_p
ump_
unac
kd[5
][1]
7
570
3509
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
an
anal
og in
put 2
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[5][1
]6
571
3510
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
an
anal
og in
put 1
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[5][1
]5
572
3511
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
a d
igita
l inp
ut 6
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[5][1
]4
573
3512
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
a d
igita
l inp
ut 5
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[5][1
]3
574
3513
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
a d
igita
l inp
ut 4
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[5][1
]2
575
3514
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
a d
igita
l inp
ut 3
faul
t whi
ch h
as b
e eU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[5][1
]1
576
3515
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
a d
igita
l inp
ut 2
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[5][1
]0
577
3600
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
a d
igita
l inp
ut 1
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[5][2
]7
578
3601
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
a d
igita
l out
put 3
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[5][2
]6
579
3602
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
a d
igita
l out
put 2
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[5][2
]5
Pag
e 23
Inpu
t Sta
tus
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Sta
tus:
Sin
gle
bit d
igita
l (re
ad o
nly)
* Th
e m
irror
ed in
put r
egis
ter o
ffest
nee
ds to
be
adde
d to
the
conf
igur
ed "M
irror
Bas
e" o
f the
Pro
con
V to
get
act
ual r
egis
ter n
umbe
r. In
dex
Mirr
ored
Inpu
t Reg
iste
rD
escr
iptio
nM
ultit
rode
Cro
ss-R
efer
ence
Offs
et *
Bit
Varia
ble
Bit
580
3603
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
a d
igita
l out
put 1
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[5][2
]4
581
3604
Res
erve
dst
atus
_rtu
_pum
p_un
ackd
[5][2
]3
582
3605
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
a S
CA
DA
lock
out f
ault
whi
ch h
as b
e eU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[5][2
]2
583
3606
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
6 du
e to
a lo
w fl
ow w
arni
ng fa
ult w
hich
has
bee
UN
AC
KN
OW
LED
GE
D (f
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ack
now
ledg
ed) a
nd is
low
oth
erw
ise
stat
us_r
tu_p
ump_
unac
kd[5
][2]
1
584
3607
Res
erve
dst
atus
_rtu
_pum
p_un
ackd
[5][2
]0
585
3608
Res
erve
dst
atus
_rtu
_pum
p_un
ackd
[6][0
]7
586
3609
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
an
unde
r cur
rent
faul
t whi
ch h
as b
e eU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[6][0
]6
587
3610
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
an
over
cur
rent
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[6][0
]5
588
3611
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
a th
erm
al a
larm
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[6][0
]4
589
3612
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
a p
hase
fail
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[6][0
]3
590
3613
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
a p
hase
rota
tion
alar
m fa
ult w
hich
has
be
en U
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
e
stat
us_r
tu_p
ump_
unac
kd[6
][0]
2
591
3614
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
an
earth
faul
t whi
ch h
as b
e eU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[6][0
]1
592
3615
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
an
insu
latio
n te
st fa
ult w
hich
has
bee
UN
AC
KN
OW
LED
GE
D (f
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ack
now
ledg
ed) a
nd is
low
oth
erw
ise
stat
us_r
tu_p
ump_
unac
kd[6
][0]
0
593
3700
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
a lo
w fl
ow fa
ult w
hich
has
bee
UN
AC
KN
OW
LED
GE
D (f
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ack
now
ledg
ed) a
nd is
low
oth
erw
ise
stat
us_r
tu_p
ump_
unac
kd[6
][1]
7
594
3701
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
an
anal
og in
put 2
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[6][1
]6
595
3702
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
an
anal
og in
put 1
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[6][1
]5
596
3703
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
a d
igita
l inp
ut 6
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[6][1
]4
597
3704
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
a d
igita
l inp
ut 5
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[6][1
]3
598
3705
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
a d
igita
l inp
ut 4
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[6][1
]2
599
3706
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
a d
igita
l inp
ut 3
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[6][1
]1
600
3707
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
a d
igita
l inp
ut 2
faul
t whi
ch h
as b
e eU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[6][1
]0
601
3708
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
a d
igita
l inp
ut 1
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[6][2
]7
602
3709
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
a d
igita
l out
put 3
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[6][2
]6
Pag
e 24
Inpu
t Sta
tus
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Sta
tus:
Sin
gle
bit d
igita
l (re
ad o
nly)
* Th
e m
irror
ed in
put r
egis
ter o
ffest
nee
ds to
be
adde
d to
the
conf
igur
ed "M
irror
Bas
e" o
f the
Pro
con
V to
get
act
ual r
egis
ter n
umbe
r. In
dex
Mirr
ored
Inpu
t Reg
iste
rD
escr
iptio
nM
ultit
rode
Cro
ss-R
efer
ence
Offs
et *
Bit
Varia
ble
Bit
603
3710
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
a d
igita
l out
put 2
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[6][2
]5
604
3711
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
a d
igita
l out
put 1
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[6][2
]4
605
3712
Res
erve
dst
atus
_rtu
_pum
p_un
ackd
[6][2
]3
606
3713
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
a S
CA
DA
lock
out f
ault
whi
ch h
as b
e eU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[6][2
]2
607
3714
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
7 du
e to
a lo
w fl
ow w
arni
ng fa
ult w
hich
has
bee
UN
AC
KN
OW
LED
GE
D (f
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ack
now
ledg
ed) a
nd is
low
oth
erw
ise
stat
us_r
tu_p
ump_
unac
kd[6
][2]
1
608
3715
Res
erve
dst
atus
_rtu
_pum
p_un
ackd
[6][2
]0
609
3800
Res
erve
dst
atus
_rtu
_pum
p_un
ackd
[7][0
]7
610
3801
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
an
unde
r cur
rent
faul
t whi
ch h
as b
e eU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[7][0
]6
611
3802
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
an
over
cur
rent
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[7][0
]5
612
3803
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
a th
erm
al a
larm
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[7][0
]4
613
3804
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
a p
hase
fail
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[7][0
]3
614
3805
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
a p
hase
rota
tion
alar
m fa
ult w
hich
has
be
en U
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
e
stat
us_r
tu_p
ump_
unac
kd[7
][0]
2
615
3806
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
an
earth
faul
t whi
ch h
as b
e eU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[7][0
]1
616
3807
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
an
insu
latio
n te
st fa
ult w
hich
has
bee
UN
AC
KN
OW
LED
GE
D (f
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ack
now
ledg
ed) a
nd is
low
oth
erw
ise
stat
us_r
tu_p
ump_
unac
kd[7
][0]
0
617
3808
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
a lo
w fl
ow fa
ult w
hich
has
bee
UN
AC
KN
OW
LED
GE
D (f
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ack
now
ledg
ed) a
nd is
low
oth
erw
ise
stat
us_r
tu_p
ump_
unac
kd[7
][1]
7
618
3809
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
an
anal
og in
put 2
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[7][1
]6
619
3810
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
an
anal
og in
put 1
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[7][1
]5
620
3811
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
a d
igita
l inp
ut 6
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[7][1
]4
621
3812
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
a d
igita
l inp
ut 5
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[7][1
]3
622
3813
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
a d
igita
l inp
ut 4
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[7][1
]2
623
3814
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
a d
igita
l inp
ut 3
faul
t whi
ch h
as b
e eU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[7][1
]1
624
3815
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
a d
igita
l inp
ut 2
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[7][1
]0
625
3900
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
a d
igita
l inp
ut 1
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[7][2
]7
Pag
e 25
Inpu
t Sta
tus
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Sta
tus:
Sin
gle
bit d
igita
l (re
ad o
nly)
* Th
e m
irror
ed in
put r
egis
ter o
ffest
nee
ds to
be
adde
d to
the
conf
igur
ed "M
irror
Bas
e" o
f the
Pro
con
V to
get
act
ual r
egis
ter n
umbe
r. In
dex
Mirr
ored
Inpu
t Reg
iste
rD
escr
iptio
nM
ultit
rode
Cro
ss-R
efer
ence
Offs
et *
Bit
Varia
ble
Bit
626
3901
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
a d
igita
l out
put 3
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[7][2
]6
627
3902
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
a d
igita
l out
put 2
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[7][2
]5
628
3903
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
a d
igita
l out
put 1
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[7][2
]4
629
3904
Res
erve
dst
atus
_rtu
_pum
p_un
ackd
[7][2
]3
630
3905
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
a S
CA
DA
lock
out f
ault
whi
ch h
as b
e eU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[7][2
]2
631
3906
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
8 du
e to
a lo
w fl
ow w
arni
ng fa
ult w
hich
has
bee
UN
AC
KN
OW
LED
GE
D (f
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ack
now
ledg
ed) a
nd is
low
oth
erw
ise
stat
us_r
tu_p
ump_
unac
kd[7
][2]
1
632
3907
Res
erve
dst
atus
_rtu
_pum
p_un
ackd
[7][2
]0
633
3908
Res
erve
dst
atus
_rtu
_pum
p_un
ackd
[8][0
]7
634
3909
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
an
unde
r cur
rent
faul
t whi
ch h
as b
e eU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[8][0
]6
635
3910
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
an
over
cur
rent
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[8][0
]5
636
3911
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
a th
erm
al a
larm
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[8][0
]4
637
3912
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
a p
hase
fail
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[8][0
]3
638
3913
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
a p
hase
rota
tion
alar
m fa
ult w
hich
has
be
en U
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
e
stat
us_r
tu_p
ump_
unac
kd[8
][0]
2
639
3914
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
an
earth
faul
t whi
ch h
as b
e eU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[8][0
]1
640
3915
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
an
insu
latio
n te
st fa
ult w
hich
has
bee
UN
AC
KN
OW
LED
GE
D (f
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ack
now
ledg
ed) a
nd is
low
oth
erw
ise
stat
us_r
tu_p
ump_
unac
kd[8
][0]
0
641
4000
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
a lo
w fl
ow fa
ult w
hich
has
bee
UN
AC
KN
OW
LED
GE
D (f
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ack
now
ledg
ed) a
nd is
low
oth
erw
ise
stat
us_r
tu_p
ump_
unac
kd[8
][1]
7
642
4001
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
an
anal
og in
put 2
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[8][1
]6
643
4002
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
an
anal
og in
put 1
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[8][1
]5
644
4003
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
a d
igita
l inp
ut 6
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[8][1
]4
645
4004
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
a d
igita
l inp
ut 5
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[8][1
]3
646
4005
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
a d
igita
l inp
ut 4
faul
t whi
ch h
as b
e eU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[8][1
]2
647
4006
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
a d
igita
l inp
ut 3
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[8][1
]1
648
4007
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
a d
igita
l inp
ut 2
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[8][1
]0
Pag
e 26
Inpu
t Sta
tus
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Sta
tus:
Sin
gle
bit d
igita
l (re
ad o
nly)
* Th
e m
irror
ed in
put r
egis
ter o
ffest
nee
ds to
be
adde
d to
the
conf
igur
ed "M
irror
Bas
e" o
f the
Pro
con
V to
get
act
ual r
egis
ter n
umbe
r. In
dex
Mirr
ored
Inpu
t Reg
iste
rD
escr
iptio
nM
ultit
rode
Cro
ss-R
efer
ence
Offs
et *
Bit
Varia
ble
Bit
649
4008
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
a d
igita
l inp
ut 1
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[8][2
]7
650
4009
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
a d
igita
l out
put 3
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[8][2
]6
651
4010
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
a d
igita
l out
put 2
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[8][2
]5
652
4011
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
a d
igita
l out
put 1
faul
t whi
ch h
as b
eeU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[8][2
]4
653
4012
Res
erve
dst
atus
_rtu
_pum
p_un
ackd
[8][2
]3
654
4013
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
a S
CA
DA
lock
out f
ault
whi
ch h
as b
e eU
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
) and
is lo
w o
ther
wis
est
atus
_rtu
_pum
p_un
ackd
[8][2
]2
655
4014
This
bit
will
be
high
if th
e M
aste
r Mon
itorP
RO
has
a fa
ulte
d pu
mp
9 du
e to
a lo
w fl
ow w
arni
ng fa
ult w
hich
has
bee
UN
AC
KN
OW
LED
GE
D (f
ault
is N
OT
pres
ent b
ut h
as N
OT
been
ack
now
ledg
ed) a
nd is
low
oth
erw
ise
stat
us_r
tu_p
ump_
unac
kd[8
][2]
1
656
4015
Res
erve
dst
atus
_rtu
_pum
p_un
ackd
[8][2
]0
657
4100
Res
erve
dst
atus
_rtu
_cnt
rlr_p
rese
nt[0
]7
658
4101
Ala
rm p
rese
nt o
n M
onito
rPR
O. T
his
alar
m is
act
ivat
ed b
y th
e m
aste
r Mon
itorP
RO
and
indi
cate
s ba
ttery
pow
er h
faile
dst
atus
_rtu
_cnt
rlr_p
rese
nt[0
]6
659
4102
Ala
rm p
rese
nt o
n M
onito
rPR
O. T
his
alar
m is
act
ivat
ed b
y th
e m
aste
r Mon
itorP
RO
and
indi
cate
s co
mm
unic
atio
ns h
faile
d be
twee
n th
e m
aste
r Mon
itorP
RO
and
the
othe
r sla
ve u
nits
stat
us_r
tu_c
ntrlr
_pre
sent
[0]
5
660
4103
Res
erve
dst
atus
_rtu
_cnt
rlr_p
rese
nt[0
]4
661
4104
Ala
rm p
rese
nt o
n M
onito
rPR
O. T
his
alar
m is
act
ivat
ed b
y th
e m
aste
r Mon
itorP
RO
and
indi
cate
s an
und
er v
olta
ge h
been
det
ecte
d by
the
mas
ter M
onito
rPR
Ost
atus
_rtu
_cnt
rlr_p
rese
nt[0
]3
662
4105
Ala
rm p
rese
nt o
n M
onito
rPR
O. T
his
alar
m is
act
ivat
ed b
y th
e m
aste
r Mon
itorP
RO
and
indi
cate
s an
ove
r vol
tage
hbe
en d
etec
ted
by th
e m
aste
r Mon
itorP
RO
stat
us_r
tu_c
ntrlr
_pre
sent
[0]
2
663
4106
Leve
l 2 a
larm
pre
sent
on
Mon
itorP
RO
stat
us_r
tu_c
ntrlr
_pre
sent
[0]
166
441
07Le
vel 1
ala
rm p
rese
nt o
n M
onito
rPR
Ost
atus
_rtu
_cnt
rlr_p
rese
nt[0
]0
665
4108
Res
erve
dst
atus
_rtu
_cnt
rlr_p
rese
nt[1
]7
666
4109
Res
erve
dst
atus
_rtu
_cnt
rlr_p
rese
nt[1
]6
667
4110
Res
erve
dst
atus
_rtu
_cnt
rlr_p
rese
nt[1
]5
668
4111
Res
erve
dst
atus
_rtu
_cnt
rlr_p
rese
nt[1
]4
669
4112
Res
erve
dst
atus
_rtu
_cnt
rlr_p
rese
nt[1
]3
670
4113
Res
erve
dst
atus
_rtu
_cnt
rlr_p
rese
nt[1
]2
671
4114
Res
erve
dst
atus
_rtu
_cnt
rlr_p
rese
nt[1
]1
672
4115
Res
erve
dst
atus
_rtu
_cnt
rlr_p
rese
nt[1
]0
673
4200
Res
erve
dst
atus
_rtu
_cnt
rlr_p
rese
nt[2
]7
674
4201
Res
erve
dst
atus
_rtu
_cnt
rlr_p
rese
nt[2
]6
675
4202
Res
erve
dst
atus
_rtu
_cnt
rlr_p
rese
nt[2
]5
676
4203
Res
erve
dst
atus
_rtu
_cnt
rlr_p
rese
nt[2
]4
677
4204
Res
erve
dst
atus
_rtu
_cnt
rlr_p
rese
nt[2
]3
678
4205
Res
erve
dst
atus
_rtu
_cnt
rlr_p
rese
nt[2
]2
679
4206
Res
erve
dst
atus
_rtu
_cnt
rlr_p
rese
nt[2
]1
680
4207
Res
erve
dst
atus
_rtu
_cnt
rlr_p
rese
nt[2
]0
681
4208
Res
erve
dst
atus
_rtu
_cnt
rlr_u
nack
d[0]
7
Pag
e 27
Inpu
t Sta
tus
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Sta
tus:
Sin
gle
bit d
igita
l (re
ad o
nly)
* Th
e m
irror
ed in
put r
egis
ter o
ffest
nee
ds to
be
adde
d to
the
conf
igur
ed "M
irror
Bas
e" o
f the
Pro
con
V to
get
act
ual r
egis
ter n
umbe
r. In
dex
Mirr
ored
Inpu
t Reg
iste
rD
escr
iptio
nM
ultit
rode
Cro
ss-R
efer
ence
Offs
et *
Bit
Varia
ble
Bit
682
4209
Ala
rm U
NA
CK
NO
WLE
DG
ED
on
Mon
itorP
RO
. Thi
s al
arm
is a
ctiv
ated
by
the
mas
ter M
onito
rPR
O a
nd in
dica
teba
ttery
pow
er fa
ult i
s cl
ear b
ut h
as n
ot b
een
ackn
owle
dged
stat
us_r
tu_c
ntrlr
_una
ckd[
0]6
683
4210
Ala
rm U
NA
CK
NO
WLE
DG
ED
on
Mon
itorP
RO
. Thi
s al
arm
is a
ctiv
ated
by
the
mas
ter M
onito
rPR
O a
nd in
dica
teco
mm
unic
atio
ns h
as b
een
rest
ored
but
has
not
bee
n ac
know
ledg
edst
atus
_rtu
_cnt
rlr_u
nack
d[0]
5
684
4211
Res
erve
dst
atus
_rtu
_cnt
rlr_u
nack
d[0]
468
542
12A
larm
UN
AC
KN
OW
LED
GE
D o
n M
onito
rPR
O. T
his
alar
m is
act
ivat
ed b
y th
e m
aste
r Mon
itorP
RO
and
indi
cate
s th
unde
r vol
tage
faul
t is
clea
r but
has
not
bee
n ac
know
ledg
edst
atus
_rtu
_cnt
rlr_u
nack
d[0]
3
686
4213
Ala
rm U
NA
CK
NO
WLE
DG
ED
on
Mon
itorP
RO
. Thi
s al
arm
is a
ctiv
ated
by
the
mas
ter M
onito
rPR
O a
nd in
dica
tes
thov
er v
olta
ge fa
ult i
s cl
ear b
ut h
as n
ot b
een
ackn
owle
dged
stat
us_r
tu_c
ntrlr
_una
ckd[
0]2
687
4214
Leve
l 2 a
larm
on
Mon
itorP
RO
is U
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
)st
atus
_rtu
_cnt
rlr_u
nack
d[0]
1
688
4215
Leve
l 1 a
larm
on
Mon
itorP
RO
is U
NA
CK
NO
WLE
DG
ED
(fau
lt is
NO
T pr
esen
t but
has
NO
T be
en a
ckno
wle
dged
)st
atus
_rtu
_cnt
rlr_u
nack
d[0]
0
689
4300
Res
erve
dst
atus
_rtu
_cnt
rlr_u
nack
d[1]
769
043
01R
eser
ved
stat
us_r
tu_c
ntrlr
_una
ckd[
1]6
691
4302
Res
erve
dst
atus
_rtu
_cnt
rlr_u
nack
d[1]
569
243
03R
eser
ved
stat
us_r
tu_c
ntrlr
_una
ckd[
1]4
693
4304
Res
erve
dst
atus
_rtu
_cnt
rlr_u
nack
d[1]
369
443
05R
eser
ved
stat
us_r
tu_c
ntrlr
_una
ckd[
1]2
695
4306
Res
erve
dst
atus
_rtu
_cnt
rlr_u
nack
d[1]
169
643
07R
eser
ved
stat
us_r
tu_c
ntrlr
_una
ckd[
1]0
697
4308
Res
erve
dst
atus
_rtu
_cnt
rlr_u
nack
d[2]
769
843
09R
eser
ved
stat
us_r
tu_c
ntrlr
_una
ckd[
2]6
699
4310
Res
erve
dst
atus
_rtu
_cnt
rlr_u
nack
d[2]
570
043
11R
eser
ved
stat
us_r
tu_c
ntrlr
_una
ckd[
2]4
701
4312
Res
erve
dst
atus
_rtu
_cnt
rlr_u
nack
d[2]
370
243
13R
eser
ved
stat
us_r
tu_c
ntrlr
_una
ckd[
2]2
703
4314
Res
erve
dst
atus
_rtu
_cnt
rlr_u
nack
d[2]
170
443
15R
eser
ved
stat
us_r
tu_c
ntrlr
_una
ckd[
2]0
705
4400
This
bit
is h
igh
if di
gita
l inp
ut 6
from
mas
ter M
onito
rPR
O is
act
ive
and
low
oth
erw
ise
stat
us_d
ig[0
][0]
770
644
01Th
is b
it is
hig
h if
digi
tal i
nput
5 fr
om m
aste
r Mon
itorP
RO
is a
ctiv
e an
d lo
w o
ther
wis
est
atus
_dig
[0][0
]6
707
4402
This
bit
is h
igh
if di
gita
l inp
ut 4
from
mas
ter M
onito
rPR
O is
act
ive
and
low
oth
erw
ise
stat
us_d
ig[0
][0]
570
844
03Th
is b
it is
hig
h if
digi
tal i
nput
3 fr
om m
aste
r Mon
itorP
RO
is a
ctiv
e an
d lo
w o
ther
wis
est
atus
_dig
[0][0
]4
709
4404
This
bit
is h
igh
if di
gita
l inp
ut 2
from
mas
ter M
onito
rPR
O is
act
ive
and
low
oth
erw
ise
stat
us_d
ig[0
][0]
371
044
05Th
is b
it is
hig
h if
digi
tal i
nput
1 fr
om m
aste
r Mon
itorP
RO
is a
ctiv
e an
d lo
w o
ther
wis
est
atus
_dig
[0][0
]2
711
4406
This
bit
is h
igh
if di
gita
l out
put 3
from
mas
ter M
onito
rPR
O is
act
ive
and
low
oth
erw
ise
stat
us_d
ig[0
][0]
171
244
07Th
is b
it is
hig
h if
digi
tal o
utpu
t 2 fr
om m
aste
r Mon
itorP
RO
is a
ctiv
e an
d lo
w o
ther
wis
est
atus
_dig
[0][0
]0
713
4408
This
bit
is h
igh
if di
gita
l out
put 1
from
mas
ter M
onito
rPR
O is
act
ive
and
low
oth
erw
ise
stat
us_d
ig[0
][1]
771
444
09R
eser
ved
stat
us_d
ig[0
][1]
671
544
10R
eser
ved
stat
us_d
ig[0
][1]
571
644
11R
eser
ved
stat
us_d
ig[0
][1]
471
744
12R
eser
ved
stat
us_d
ig[0
][1]
371
844
13R
eser
ved
stat
us_d
ig[0
][1]
271
944
14R
eser
ved
stat
us_d
ig[0
][1]
1
Pag
e 28
Inpu
t Sta
tus
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Sta
tus:
Sin
gle
bit d
igita
l (re
ad o
nly)
* Th
e m
irror
ed in
put r
egis
ter o
ffest
nee
ds to
be
adde
d to
the
conf
igur
ed "M
irror
Bas
e" o
f the
Pro
con
V to
get
act
ual r
egis
ter n
umbe
r. In
dex
Mirr
ored
Inpu
t Reg
iste
rD
escr
iptio
nM
ultit
rode
Cro
ss-R
efer
ence
Offs
et *
Bit
Varia
ble
Bit
720
4415
Res
erve
dst
atus
_dig
[0][1
]0
721
4500
Res
erve
dst
atus
_dig
[0][2
]7
722
4501
Res
erve
dst
atus
_dig
[0][2
]6
723
4502
Res
erve
dst
atus
_dig
[0][2
]5
724
4503
Res
erve
dst
atus
_dig
[0][2
]4
725
4504
Res
erve
dst
atus
_dig
[0][2
]3
726
4505
Res
erve
dst
atus
_dig
[0][2
]2
727
4506
Res
erve
dst
atus
_dig
[0][2
]1
728
4507
Res
erve
dst
atus
_dig
[0][2
]0
729
4508
Res
erve
dst
atus
_dig
[1][0
]7
730
4509
Res
erve
dst
atus
_dig
[1][0
]6
731
4510
Res
erve
dst
atus
_dig
[1][0
]5
732
4511
Res
erve
dst
atus
_dig
[1][0
]4
733
4512
Res
erve
dst
atus
_dig
[1][0
]3
734
4513
Res
erve
dst
atus
_dig
[1][0
]2
735
4514
Res
erve
dst
atus
_dig
[1][0
]1
736
4515
Res
erve
dst
atus
_dig
[1][0
]0
737
4600
Res
erve
dst
atus
_dig
[1][1
]7
738
4601
Res
erve
dst
atus
_dig
[1][1
]6
739
4602
Res
erve
dst
atus
_dig
[1][1
]5
740
4603
Res
erve
dst
atus
_dig
[1][1
]4
741
4604
Res
erve
dst
atus
_dig
[1][1
]3
742
4605
Res
erve
dst
atus
_dig
[1][1
]2
743
4606
Res
erve
dst
atus
_dig
[1][1
]1
744
4607
Res
erve
dst
atus
_dig
[1][1
]0
745
4608
Res
erve
dst
atus
_dig
[1][2
]7
746
4609
Res
erve
dst
atus
_dig
[1][2
]6
747
4610
Res
erve
dst
atus
_dig
[1][2
]5
748
4611
Res
erve
dst
atus
_dig
[1][2
]4
749
4612
Res
erve
dst
atus
_dig
[1][2
]3
750
4613
Res
erve
dst
atus
_dig
[1][2
]2
751
4614
Res
erve
dst
atus
_dig
[1][2
]1
752
4615
Res
erve
dst
atus
_dig
[1][2
]0
753
4700
Res
erve
dst
atus
_dig
[2][0
]7
754
4701
Res
erve
dst
atus
_dig
[2][0
]6
755
4702
Res
erve
dst
atus
_dig
[2][0
]5
756
4703
Res
erve
dst
atus
_dig
[2][0
]4
757
4704
Res
erve
dst
atus
_dig
[2][0
]3
758
4705
Res
erve
dst
atus
_dig
[2][0
]2
759
4706
Res
erve
dst
atus
_dig
[2][0
]1
760
4707
Res
erve
dst
atus
_dig
[2][0
]0
761
4708
Res
erve
dst
atus
_dig
[2][1
]7
762
4709
Res
erve
dst
atus
_dig
[2][1
]6
763
4710
Res
erve
dst
atus
_dig
[2][1
]5
Pag
e 29
Inpu
t Sta
tus
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Sta
tus:
Sin
gle
bit d
igita
l (re
ad o
nly)
* Th
e m
irror
ed in
put r
egis
ter o
ffest
nee
ds to
be
adde
d to
the
conf
igur
ed "M
irror
Bas
e" o
f the
Pro
con
V to
get
act
ual r
egis
ter n
umbe
r. In
dex
Mirr
ored
Inpu
t Reg
iste
rD
escr
iptio
nM
ultit
rode
Cro
ss-R
efer
ence
Offs
et *
Bit
Varia
ble
Bit
764
4711
Res
erve
dst
atus
_dig
[2][1
]4
765
4712
Res
erve
dst
atus
_dig
[2][1
]3
766
4713
Res
erve
dst
atus
_dig
[2][1
]2
767
4714
Res
erve
dst
atus
_dig
[2][1
]1
768
4715
Res
erve
dst
atus
_dig
[2][1
]0
769
4800
Res
erve
dst
atus
_dig
[2][2
]7
770
4801
Res
erve
dst
atus
_dig
[2][2
]6
771
4802
Res
erve
dst
atus
_dig
[2][2
]5
772
4803
Res
erve
dst
atus
_dig
[2][2
]4
773
4804
Res
erve
dst
atus
_dig
[2][2
]3
774
4805
Res
erve
dst
atus
_dig
[2][2
]2
775
4806
Res
erve
dst
atus
_dig
[2][2
]1
776
4807
Res
erve
dst
atus
_dig
[2][2
]0
777
4808
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[0
]7
778
4809
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[0
]6
779
4810
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[0
]5
780
4811
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[0
]4
781
4812
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[0
]3
782
4813
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[0
]2
783
4814
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[0
]1
784
4815
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[0
]0
785
4900
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[1
]7
786
4901
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[1
]6
787
4902
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[1
]5
788
4903
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[1
]4
789
4904
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[1
]3
790
4905
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[1
]2
791
4906
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[1
]1
792
4907
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[1
]0
793
4908
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[2
]7
794
4909
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[2
]6
795
4910
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[2
]5
796
4911
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[2
]4
797
4912
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[2
]3
798
4913
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[2
]2
799
4914
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[2
]1
800
4915
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[2
]0
801
5000
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[3
]7
802
5001
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[3
]6
803
5002
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[3
]5
804
5003
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[3
]4
805
5004
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[3
]3
806
5005
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[3
]2
807
5006
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[3
]1
Pag
e 30
Inpu
t Sta
tus
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Sta
tus:
Sin
gle
bit d
igita
l (re
ad o
nly)
* Th
e m
irror
ed in
put r
egis
ter o
ffest
nee
ds to
be
adde
d to
the
conf
igur
ed "M
irror
Bas
e" o
f the
Pro
con
V to
get
act
ual r
egis
ter n
umbe
r. In
dex
Mirr
ored
Inpu
t Reg
iste
rD
escr
iptio
nM
ultit
rode
Cro
ss-R
efer
ence
Offs
et *
Bit
Varia
ble
Bit
808
5007
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[3
]0
809
5008
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[4
]7
810
5009
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[4
]6
811
5010
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[4
]5
812
5011
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[4
]4
813
5012
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[4
]3
814
5013
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[4
]2
815
5014
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[4
]1
816
5015
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[4
]0
817
5100
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[5
]7
818
5101
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[5
]6
819
5102
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[5
]5
820
5103
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[5
]4
821
5104
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[5
]3
822
5105
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[5
]2
823
5106
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[5
]1
824
5107
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[5
]0
825
5108
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[6
]7
826
5109
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[6
]6
827
5110
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[6
]5
828
5111
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[6
]4
829
5112
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[6
]3
830
5113
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[6
]2
831
5114
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[6
]1
832
5115
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[6
]0
833
5200
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[7
]7
834
5201
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[7
]6
835
5202
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[7
]5
836
5203
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[7
]4
837
5204
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[7
]3
838
5205
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[7
]2
839
5206
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[7
]1
840
5207
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[7
]0
841
5208
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[8
]7
842
5209
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[8
]6
843
5210
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[8
]5
844
5211
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[8
]4
845
5212
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[8
]3
846
5213
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[8
]2
847
5214
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[8
]1
848
5215
Res
erve
dst
atus
_una
ckd_
pum
p_co
unte
rs[8
]0
849
5300
Res
erve
dst
atus
_una
ckd_
rtu_c
ount
er7
850
5301
Res
erve
dst
atus
_una
ckd_
rtu_c
ount
er6
851
5302
Res
erve
dst
atus
_una
ckd_
rtu_c
ount
er5
Pag
e 31
Inpu
t Sta
tus
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Sta
tus:
Sin
gle
bit d
igita
l (re
ad o
nly)
* Th
e m
irror
ed in
put r
egis
ter o
ffest
nee
ds to
be
adde
d to
the
conf
igur
ed "M
irror
Bas
e" o
f the
Pro
con
V to
get
act
ual r
egis
ter n
umbe
r. In
dex
Mirr
ored
Inpu
t Reg
iste
rD
escr
iptio
nM
ultit
rode
Cro
ss-R
efer
ence
Offs
et *
Bit
Varia
ble
Bit
852
5303
Res
erve
dst
atus
_una
ckd_
rtu_c
ount
er4
853
5304
Res
erve
dst
atus
_una
ckd_
rtu_c
ount
er3
854
5305
Res
erve
dst
atus
_una
ckd_
rtu_c
ount
er2
855
5306
Res
erve
dst
atus
_una
ckd_
rtu_c
ount
er1
856
5307
Res
erve
dst
atus
_una
ckd_
rtu_c
ount
er0
857
5308
Res
erve
dst
atus
_rtu
_com
ms_
fail[
0]7
858
5309
Res
erve
dst
atus
_rtu
_com
ms_
fail[
0]6
859
5310
Res
erve
dst
atus
_rtu
_com
ms_
fail[
0]5
860
5311
Res
erve
dst
atus
_rtu
_com
ms_
fail[
0]4
861
5312
Res
erve
dst
atus
_rtu
_com
ms_
fail[
0]3
862
5313
Res
erve
dst
atus
_rtu
_com
ms_
fail[
0]2
863
5314
Res
erve
dst
atus
_rtu
_com
ms_
fail[
0]1
864
5315
Res
erve
dst
atus
_rtu
_com
ms_
fail[
0]0
865
5400
Res
erve
dst
atus
_rtu
_com
ms_
fail[
1]0
866
5401
Res
erve
dst
atus
_rtu
_com
ms_
fail[
2]0
867
5402
Ove
rflow
faul
t pre
sent
from
mas
ter M
onito
rPR
OS
tatu
s_rtu
_cnt
rlr_p
rese
nt2[
0]1
868
5403
Res
erve
dS
tatu
s_rtu
_cnt
rlr_p
rese
nt2[
0]0
869
5404
Res
erve
dS
tatu
s_rtu
_cnt
rlr_p
rese
nt2[
1]1
870
5405
Res
erve
dS
tatu
s_rtu
_cnt
rlr_p
rese
nt2[
1]0
871
5406
Res
erve
dS
tatu
s_rtu
_cnt
rlr_p
rese
nt2[
2]1
872
5407
Res
erve
dS
tatu
s_rtu
_cnt
rlr_p
rese
nt2[
2]0
873
5408
Res
erve
dS
tatu
s_rtu
_cnt
rlr_u
nack
d2[0
]1
874
5409
Res
erve
dS
tatu
s_rtu
_cnt
rlr_u
nack
d2[0
]0
875
5410
Res
erve
dS
tatu
s_rtu
_cnt
rlr_u
nack
d2[1
]1
876
5411
Res
erve
dS
tatu
s_rtu
_cnt
rlr_u
nack
d2[1
]0
877
5412
Res
erve
dS
tatu
s_rtu
_cnt
rlr_u
nack
d2[2
]1
878
5413
Res
erve
dS
tatu
s_rtu
_cnt
rlr_u
nack
d2[2
]0
879
5414
Sta
tus
from
mas
ter p
ump
cont
rolle
r: S
tatu
s of
sen
sor p
robe
inpu
t 10
(bot
tom
pro
be)
MTx
PC
Ctrl
Sta
tus[
0][2
]7
880
5415
Sta
tus
from
mas
ter p
ump
cont
rolle
r: S
tatu
s of
sen
sor p
robe
inpu
t 9M
TxP
CC
trlS
tatu
s[0]
[2]
688
155
00S
tatu
s fro
m m
aste
r pum
p co
ntro
ller:
Sta
tus
of s
enso
r pro
be in
put 8
MTx
PC
Ctrl
Sta
tus[
0][2
]5
882
5501
Sta
tus
from
mas
ter p
ump
cont
rolle
r: S
tatu
s of
sen
sor p
robe
inpu
t 7M
TxP
CC
trlS
tatu
s[0]
[2]
488
355
02S
tatu
s fro
m m
aste
r pum
p co
ntro
ller:
Sta
tus
of s
enso
r pro
be in
put 6
MTx
PC
Ctrl
Sta
tus[
0][2
]3
884
5503
Sta
tus
from
mas
ter p
ump
cont
rolle
r: S
tatu
s of
sen
sor p
robe
inpu
t 5M
TxP
CC
trlS
tatu
s[0]
[2]
288
555
04S
tatu
s fro
m m
aste
r pum
p co
ntro
ller:
Sta
tus
of s
enso
r pro
be in
put 4
MTx
PC
Ctrl
Sta
tus[
0][2
]1
886
5505
Sta
tus
from
mas
ter p
ump
cont
rolle
r: S
tatu
s of
sen
sor p
robe
inpu
t 3M
TxP
CC
trlS
tatu
s[0]
[2]
088
755
06S
tatu
s fro
m m
aste
r pum
p co
ntro
ller:
Sta
tus
of s
enso
r pro
be in
put 2
MTx
PC
Ctrl
Sta
tus[
0][3
]1
888
5507
Sta
tus
from
mas
ter p
ump
cont
rolle
r: S
tatu
s of
sen
sor p
robe
inpu
t 1 (t
op p
robe
)M
TxP
CC
trlS
tatu
s[0]
[3]
088
955
08S
tatu
s fro
m m
aste
r pum
p co
ntro
ller:
Sta
tus
of d
igita
l out
put 1
MTx
PC
Ctrl
Sta
tus[
0][7
]0
890
5509
Sta
tus
from
mas
ter p
ump
cont
rolle
r: S
tatu
s of
dig
ital o
utpu
t 2M
TxP
CC
trlS
tatu
s[0]
[7]
189
155
10S
tatu
s fro
m m
aste
r pum
p co
ntro
ller:
Sta
tus
of d
igita
l out
put 3
MTx
PC
Ctrl
Sta
tus[
0][7
]2
892
5511
Sta
tus
from
mas
ter p
ump
cont
rolle
r: S
tatu
s of
dig
ital o
utpu
t 4M
TxP
CC
trlS
tatu
s[0]
[7]
389
355
12S
tatu
s fro
m m
aste
r pum
p co
ntro
ller:
Sta
tus
of d
igita
l out
put 5
MTx
PC
Ctrl
Sta
tus[
0][7
]4
894
5513
Sta
tus
from
mas
ter p
ump
cont
rolle
r: A
larm
1 P
RE
SE
NT
MTx
PC
Ctrl
Sta
tus[
0][8
]0
895
5514
Sta
tus
from
mas
ter p
ump
cont
rolle
r: A
larm
1 U
NA
CK
NO
WLE
DG
ED
MTx
PC
Ctrl
Sta
tus[
0][8
]1
Pag
e 32
Inpu
t Sta
tus
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Sta
tus:
Sin
gle
bit d
igita
l (re
ad o
nly)
* Th
e m
irror
ed in
put r
egis
ter o
ffest
nee
ds to
be
adde
d to
the
conf
igur
ed "M
irror
Bas
e" o
f the
Pro
con
V to
get
act
ual r
egis
ter n
umbe
r. In
dex
Mirr
ored
Inpu
t Reg
iste
rD
escr
iptio
nM
ultit
rode
Cro
ss-R
efer
ence
Offs
et *
Bit
Varia
ble
Bit
896
5515
Sta
tus
from
mas
ter p
ump
cont
rolle
r: A
larm
1 M
uted
MTx
PC
Ctrl
Sta
tus[
0][8
]2
897
5600
Sta
tus
from
mas
ter p
ump
cont
rolle
r: A
larm
2 P
RE
SE
NT
MTx
PC
Ctrl
Sta
tus[
0][8
]3
898
5601
Sta
tus
from
mas
ter p
ump
cont
rolle
r: A
larm
2 U
NA
CK
NO
WLE
DG
ED
MTx
PC
Ctrl
Sta
tus[
0][8
]4
899
5602
Sta
tus
from
mas
ter p
ump
cont
rolle
r: A
larm
2 M
uted
MTx
PC
Ctrl
Sta
tus[
0][8
]5
900
5603
Sta
tus
from
mas
ter p
ump
cont
rolle
r: Le
ak le
vel s
tatu
sM
TxP
CC
trlS
tatu
s[0]
[9]
490
156
04S
tatu
s fro
m m
aste
r pum
p co
ntro
ller:
Spe
cial
inpu
t sta
tus
MTx
PC
Ctrl
Sta
tus[
0][9
]5
902
5605
Sta
tus
from
sla
ve 1
con
trolle
r: S
tatu
s of
sen
sor p
robe
inpu
t 10
(bot
tom
pro
be)
MTx
PC
Ctrl
Sta
tus[
1][2
]7
903
5606
Sta
tus
from
sla
ve 1
con
trolle
r: S
tatu
s of
sen
sor p
robe
inpu
t 9M
TxP
CC
trlS
tatu
s[1]
[2]
690
456
07S
tatu
s fro
m s
lave
1 c
ontro
ller:
Sta
tus
of s
enso
r pro
be in
put 8
MTx
PC
Ctrl
Sta
tus[
1][2
]5
905
5608
Sta
tus
from
sla
ve 1
con
trolle
r: S
tatu
s of
sen
sor p
robe
inpu
t 7M
TxP
CC
trlS
tatu
s[1]
[2]
490
656
09S
tatu
s fro
m s
lave
1 c
ontro
ller:
Sta
tus
of s
enso
r pro
be in
put 6
MTx
PC
Ctrl
Sta
tus[
1][2
]3
907
5610
Sta
tus
from
sla
ve 1
con
trolle
r: S
tatu
s of
sen
sor p
robe
inpu
t 5M
TxP
CC
trlS
tatu
s[1]
[2]
290
856
11S
tatu
s fro
m s
lave
1 c
ontro
ller:
Sta
tus
of s
enso
r pro
be in
put 4
MTx
PC
Ctrl
Sta
tus[
1][2
]1
909
5612
Sta
tus
from
sla
ve 1
con
trolle
r: S
tatu
s of
sen
sor p
robe
inpu
t 3M
TxP
CC
trlS
tatu
s[1]
[2]
091
056
13S
tatu
s fro
m s
lave
1 c
ontro
ller:
Sta
tus
of s
enso
r pro
be in
put 2
MTx
PC
Ctrl
Sta
tus[
1][3
]1
911
5614
Sta
tus
from
sla
ve 1
con
trolle
r: S
tatu
s of
sen
sor p
robe
inpu
t 1 (t
op p
robe
)M
TxP
CC
trlS
tatu
s[1]
[3]
091
256
15S
tatu
s fro
m s
lave
1 c
ontro
ller:
Sta
tus
of d
igita
l out
put 1
MTx
PC
Ctrl
Sta
tus[
1][7
]0
913
5700
Sta
tus
from
sla
ve 1
con
trolle
r: S
tatu
s of
dig
ital o
utpu
t 2M
TxP
CC
trlS
tatu
s[1]
[7]
191
457
01S
tatu
s fro
m s
lave
1 c
ontro
ller:
Sta
tus
of d
igita
l out
put 3
MTx
PC
Ctrl
Sta
tus[
1][7
]2
915
5702
Sta
tus
from
sla
ve 1
con
trolle
r: S
tatu
s of
dig
ital o
utpu
t 4M
TxP
CC
trlS
tatu
s[1]
[7]
391
657
03S
tatu
s fro
m s
lave
1 c
ontro
ller:
Sta
tus
of d
igita
l out
put 5
MTx
PC
Ctrl
Sta
tus[
1][7
]4
917
5704
Sta
tus
from
sla
ve 1
con
trolle
r: A
larm
1 P
RE
SE
NT
MTx
PC
Ctrl
Sta
tus[
1][8
]0
918
5705
Sta
tus
from
sla
ve 1
con
trolle
r: A
larm
1 U
NA
CK
NO
WLE
DG
ED
MTx
PC
Ctrl
Sta
tus[
1][8
]1
919
5706
Sta
tus
from
sla
ve 1
con
trolle
r: A
larm
1 M
uted
MTx
PC
Ctrl
Sta
tus[
1][8
]2
920
5707
Sta
tus
from
sla
ve 1
con
trolle
r: A
larm
2 P
RE
SE
NT
MTx
PC
Ctrl
Sta
tus[
1][8
]3
921
5708
Sta
tus
from
sla
ve 1
con
trolle
r: A
larm
2 U
NA
CK
NO
WLE
DG
ED
MTx
PC
Ctrl
Sta
tus[
1][8
]4
922
5709
Sta
tus
from
sla
ve 1
con
trolle
r: A
larm
2 M
uted
MTx
PC
Ctrl
Sta
tus[
1][8
]5
923
5710
Sta
tus
from
sla
ve 1
con
trolle
r: Le
ak le
vel s
tatu
sM
TxP
CC
trlS
tatu
s[1]
[9]
492
457
11S
tatu
s fro
m s
lave
1 c
ontro
ller:
Spe
cial
inpu
t sta
tus
MTx
PC
Ctrl
Sta
tus[
1][9
]5
925
5712
Sta
tus
from
sla
ve 2
con
trolle
r: S
tatu
s of
sen
sor p
robe
inpu
t 10
(bot
tom
pro
be)
MTx
PC
Ctrl
Sta
tus[
2][2
]7
926
5713
Sta
tus
from
sla
ve 2
con
trolle
r: S
tatu
s of
sen
sor p
robe
inpu
t 9M
TxP
CC
trlS
tatu
s[2]
[2]
692
757
14S
tatu
s fro
m s
lave
2 c
ontro
ller:
Sta
tus
of s
enso
r pro
be in
put 8
MTx
PC
Ctrl
Sta
tus[
2][2
]5
928
5715
Sta
tus
from
sla
ve 2
con
trolle
r: S
tatu
s of
sen
sor p
robe
inpu
t 7M
TxP
CC
trlS
tatu
s[2]
[2]
492
958
00S
tatu
s fro
m s
lave
2 c
ontro
ller:
Sta
tus
of s
enso
r pro
be in
put 6
MTx
PC
Ctrl
Sta
tus[
2][2
]3
930
5801
Sta
tus
from
sla
ve 2
con
trolle
r: S
tatu
s of
sen
sor p
robe
inpu
t 5M
TxP
CC
trlS
tatu
s[2]
[2]
293
158
02S
tatu
s fro
m s
lave
2 c
ontro
ller:
Sta
tus
of s
enso
r pro
be in
put 4
MTx
PC
Ctrl
Sta
tus[
2][2
]1
932
5803
Sta
tus
from
sla
ve 2
con
trolle
r: S
tatu
s of
sen
sor p
robe
inpu
t 3M
TxP
CC
trlS
tatu
s[2]
[2]
093
358
04S
tatu
s fro
m s
lave
2 c
ontro
ller:
Sta
tus
of s
enso
r pro
be in
put 2
MTx
PC
Ctrl
Sta
tus[
2][3
]1
934
5805
Sta
tus
from
sla
ve 2
con
trolle
r: S
tatu
s of
sen
sor p
robe
inpu
t 1 (t
op p
robe
)M
TxP
CC
trlS
tatu
s[2]
[3]
093
558
06S
tatu
s fro
m s
lave
2 c
ontro
ller:
Sta
tus
of d
igita
l out
put 1
MTx
PC
Ctrl
Sta
tus[
2][7
]0
936
5807
Sta
tus
from
sla
ve 2
con
trolle
r: S
tatu
s of
dig
ital o
utpu
t 2M
TxP
CC
trlS
tatu
s[2]
[7]
193
758
08S
tatu
s fro
m s
lave
2 c
ontro
ller:
Sta
tus
of d
igita
l out
put 3
MTx
PC
Ctrl
Sta
tus[
2][7
]2
938
5809
Sta
tus
from
sla
ve 2
con
trolle
r: S
tatu
s of
dig
ital o
utpu
t 4M
TxP
CC
trlS
tatu
s[2]
[7]
393
958
10S
tatu
s fro
m s
lave
2 c
ontro
ller:
Sta
tus
of d
igita
l out
put 5
MTx
PC
Ctrl
Sta
tus[
2][7
]4
Pag
e 33
Inpu
t Sta
tus
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Sta
tus:
Sin
gle
bit d
igita
l (re
ad o
nly)
* Th
e m
irror
ed in
put r
egis
ter o
ffest
nee
ds to
be
adde
d to
the
conf
igur
ed "M
irror
Bas
e" o
f the
Pro
con
V to
get
act
ual r
egis
ter n
umbe
r. In
dex
Mirr
ored
Inpu
t Reg
iste
rD
escr
iptio
nM
ultit
rode
Cro
ss-R
efer
ence
Offs
et *
Bit
Varia
ble
Bit
940
5811
Sta
tus
from
sla
ve 2
con
trolle
r: A
larm
1 P
RE
SE
NT
MTx
PC
Ctrl
Sta
tus[
2][8
]0
941
5812
Sta
tus
from
sla
ve 2
con
trolle
r: A
larm
1 U
NA
CK
NO
WLE
DG
ED
MTx
PC
Ctrl
Sta
tus[
2][8
]1
942
5813
Sta
tus
from
sla
ve 2
con
trolle
r: A
larm
1 M
uted
MTx
PC
Ctrl
Sta
tus[
2][8
]2
943
5814
Sta
tus
from
sla
ve 2
con
trolle
r: A
larm
2 P
RE
SE
NT
MTx
PC
Ctrl
Sta
tus[
2][8
]3
944
5815
Sta
tus
from
sla
ve 2
con
trolle
r: A
larm
2 U
NA
CK
NO
WLE
DG
ED
MTx
PC
Ctrl
Sta
tus[
2][8
]4
945
5900
Sta
tus
from
sla
ve 2
con
trolle
r: A
larm
2 M
uted
MTx
PC
Ctrl
Sta
tus[
2][8
]5
946
5901
Sta
tus
from
sla
ve 2
con
trolle
r: Le
ak le
vel s
tatu
sM
TxP
CC
trlS
tatu
s[2]
[9]
494
759
02S
tatu
s fro
m s
lave
2 c
ontro
ller:
Spe
cial
inpu
t sta
tus
MTx
PC
Ctrl
Sta
tus[
2][9
]5
948
5903
This
inpu
t rep
rese
nts
the
loca
l dig
ital i
nput
1 o
f the
Pro
con
VN
/A94
959
04Th
is in
put r
epre
sent
s th
e lo
cal d
igita
l inp
ut 2
of t
he P
roco
n V
N/A
950
5905
This
inpu
t rep
rese
nts
the
loca
l dig
ital i
nput
3 o
f the
Pro
con
VN
/A95
159
06Th
is in
put r
epre
sent
s th
e lo
cal d
igita
l inp
ut 4
of t
he P
roco
n V
N/A
952
5907
This
inpu
t rep
rese
nts
the
loca
l dig
ital i
nput
5 o
f the
Pro
con
VN
/A95
359
08Th
is in
put r
epre
sent
s th
e lo
cal d
igita
l inp
ut 6
of t
he P
roco
n V
N/A
954
5909
Res
erve
dN
/A95
559
10R
eser
ved
N/A
956
5911
This
bit
is h
igh
if co
mm
unic
atio
n is
lost
bet
wee
n th
e P
roco
n V
and
the
mas
ter M
onito
rPR
O a
nd lo
w o
ther
wis
eN
/A
957
5912
This
bit
is h
igh
if th
e in
form
atio
n is
old
er th
an a
sel
ecta
ble
amou
nt o
f tim
e an
d lo
w o
ther
wis
e. T
he s
elec
tabl
e pe
riod
of
time
for s
tale
dat
a, is
con
figur
able
und
er th
e P
roco
n V
con
figur
atio
n m
enu.
N/A
958
5913
Mas
ter T
elem
etry
Inpu
t AC
Sta
tus_
mit_
ekim
[21]
095
959
14M
aste
r Tel
emet
ry In
put A
NS
tatu
s_m
it_ek
im[2
1]1
960
5915
Mas
ter T
elem
etry
Inpu
t AD
Sta
tus_
mit_
ekim
[21]
296
160
00M
aste
r Tel
emet
ry In
put A
SS
tatu
s_m
it_ek
im[2
1]3
962
6001
Mas
ter T
elem
etry
Inpu
t BC
Sta
tus_
mit_
ekim
[21]
496
360
02M
aste
r Tel
emet
ry In
put B
NS
tatu
s_m
it_ek
im[2
1]5
964
6003
Mas
ter T
elem
etry
Inpu
t BD
Sta
tus_
mit_
ekim
[21]
696
560
04M
aste
r Tel
emet
ry In
put B
SS
tatu
s_m
it_ek
im[2
1]7
966
6005
Mas
ter T
elem
etry
Inpu
t CC
Sta
tus_
mit_
ekim
[22]
096
760
06M
aste
r Tel
emet
ry In
put C
NS
tatu
s_m
it_ek
im[2
2]1
968
6007
Mas
ter T
elem
etry
Inpu
t CD
Sta
tus_
mit_
ekim
[22]
296
960
08M
aste
r Tel
emet
ry In
put C
SS
tatu
s_m
it_ek
im[2
2]3
970
6009
Mas
ter T
elem
etry
Inpu
t PL
Sta
tus_
mit_
ekim
[22]
497
160
10M
aste
r Tel
emet
ry In
put P
FS
tatu
s_m
it_ek
im[2
2]5
972
6011
Mas
ter T
elem
etry
Inpu
t PS
Sta
tus_
mit_
ekim
[22]
697
360
12M
aste
r Tel
emet
ry In
put K
LS
tatu
s_m
it_ek
im[2
2]7
974
6013
Sla
ve 1
Tel
emet
ry In
put A
CS
tatu
s_m
it_ek
im[2
3]0
975
6014
Sla
ve 1
Tel
emet
ry In
put A
NS
tatu
s_m
it_ek
im[2
3]1
976
6015
Sla
ve 1
Tel
emet
ry In
put A
DS
tatu
s_m
it_ek
im[2
3]2
977
6100
Sla
ve 1
Tel
emet
ry In
put A
SS
tatu
s_m
it_ek
im[2
3]3
978
6101
Sla
ve 1
Tel
emet
ry In
put B
CS
tatu
s_m
it_ek
im[2
3]4
979
6102
Sla
ve 1
Tel
emet
ry In
put B
NS
tatu
s_m
it_ek
im[2
3]5
980
6103
Sla
ve 1
Tel
emet
ry In
put B
DS
tatu
s_m
it_ek
im[2
3]6
981
6104
Sla
ve 1
Tel
emet
ry In
put B
SS
tatu
s_m
it_ek
im[2
3]7
Pag
e 34
Inpu
t Sta
tus
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Sta
tus:
Sin
gle
bit d
igita
l (re
ad o
nly)
* Th
e m
irror
ed in
put r
egis
ter o
ffest
nee
ds to
be
adde
d to
the
conf
igur
ed "M
irror
Bas
e" o
f the
Pro
con
V to
get
act
ual r
egis
ter n
umbe
r. In
dex
Mirr
ored
Inpu
t Reg
iste
rD
escr
iptio
nM
ultit
rode
Cro
ss-R
efer
ence
Offs
et *
Bit
Varia
ble
Bit
982
6105
Sla
ve 1
Tel
emet
ry In
put C
CS
tatu
s_m
it_ek
im[2
4]0
983
6106
Sla
ve 1
Tel
emet
ry In
put C
NS
tatu
s_m
it_ek
im[2
4]1
984
6107
Sla
ve 1
Tel
emet
ry In
put C
DS
tatu
s_m
it_ek
im[2
4]2
985
6108
Sla
ve 1
Tel
emet
ry In
put C
SS
tatu
s_m
it_ek
im[2
4]3
986
6109
Sla
ve 1
Tel
emet
ry In
put P
LS
tatu
s_m
it_ek
im[2
4]4
987
6110
Sla
ve 1
Tel
emet
ry In
put P
FS
tatu
s_m
it_ek
im[2
4]5
988
6111
Sla
ve 1
Tel
emet
ry In
put P
SS
tatu
s_m
it_ek
im[2
4]6
989
6112
Sla
ve 1
Tel
emet
ry In
put K
LS
tatu
s_m
it_ek
im[2
4]7
990
6113
Sla
ve 2
Tel
emet
ry In
put A
CS
tatu
s_m
it_ek
im[2
5]0
991
6114
Sla
ve 2
Tel
emet
ry In
put A
NS
tatu
s_m
it_ek
im[2
5]1
992
6115
Sla
ve 2
Tel
emet
ry In
put A
DS
tatu
s_m
it_ek
im[2
5]2
993
6200
Sla
ve 2
Tel
emet
ry In
put A
SS
tatu
s_m
it_ek
im[2
5]3
994
6201
Sla
ve 2
Tel
emet
ry In
put B
CS
tatu
s_m
it_ek
im[2
5]4
995
6202
Sla
ve 2
Tel
emet
ry In
put B
NS
tatu
s_m
it_ek
im[2
5]5
996
6203
Sla
ve 2
Tel
emet
ry In
put B
DS
tatu
s_m
it_ek
im[2
5]6
997
6204
Sla
ve 2
Tel
emet
ry In
put B
SS
tatu
s_m
it_ek
im[2
5]7
998
6205
Sla
ve 2
Tel
emet
ry In
put C
CS
tatu
s_m
it_ek
im[2
6]0
999
6206
Sla
ve 2
Tel
emet
ry In
put C
NS
tatu
s_m
it_ek
im[2
6]1
1000
6207
Sla
ve 2
Tel
emet
ry In
put C
DS
tatu
s_m
it_ek
im[2
6]2
1001
6208
Sla
ve 2
Tel
emet
ry In
put C
SS
tatu
s_m
it_ek
im[2
6]3
1002
6209
Sla
ve 2
Tel
emet
ry In
put P
LS
tatu
s_m
it_ek
im[2
6]4
1003
6210
Sla
ve 2
Tel
emet
ry In
put P
FS
tatu
s_m
it_ek
im[2
6]5
1004
6211
Sla
ve 2
Tel
emet
ry In
put P
SS
tatu
s_m
it_ek
im[2
6]6
1005
6212
Sla
ve 2
Tel
emet
ry In
put K
LS
tatu
s_m
it_ek
im[2
6]7
1006
6213
Spa
reS
tatu
s_m
it_ek
im[2
7]0
1007
6214
Spa
reS
tatu
s_m
it_ek
im[2
7]1
1008
6215
Spa
reS
tatu
s_m
it_ek
im[2
7]2
1009
6300
Spa
reS
tatu
s_m
it_ek
im[2
7]3
1010
6301
Spa
reS
tatu
s_m
it_ek
im[2
7]4
1011
6302
Spa
reS
tatu
s_m
it_ek
im[2
7]5
1012
6303
Spa
reS
tatu
s_m
it_ek
im[2
7]6
1013
6304
Spa
reS
tatu
s_m
it_ek
im[2
7]7
1014
6305
Not
use
d (e
xist
s to
mak
e nu
mbe
r of i
nput
sta
tuse
s di
visi
ble
by 1
6 - s
ee re
leas
e no
tes
v1.0
5)N
/A10
1563
06N
ot u
sed
(exi
sts
to m
ake
num
ber o
f inp
ut s
tatu
ses
divi
sibl
e by
16
- see
rele
ase
note
s v1
.05)
N/A
1016
6307
Not
use
d (e
xist
s to
mak
e nu
mbe
r of i
nput
sta
tuse
s di
visi
ble
by 1
6 - s
ee re
leas
e no
tes
v1.0
5)N
/A10
1763
08N
ot u
sed
(exi
sts
to m
ake
num
ber o
f inp
ut s
tatu
ses
divi
sibl
e by
16
- see
rele
ase
note
s v1
.05)
N/A
1018
6309
Not
use
d (e
xist
s to
mak
e nu
mbe
r of i
nput
sta
tuse
s di
visi
ble
by 1
6 - s
ee re
leas
e no
tes
v1.0
5)N
/A10
1963
10N
ot u
sed
(exi
sts
to m
ake
num
ber o
f inp
ut s
tatu
ses
divi
sibl
e by
16
- see
rele
ase
note
s v1
.05)
N/A
1020
6311
Not
use
d (e
xist
s to
mak
e nu
mbe
r of i
nput
sta
tuse
s di
visi
ble
by 1
6 - s
ee re
leas
e no
tes
v1.0
5)N
/A10
2163
12N
ot u
sed
(exi
sts
to m
ake
num
ber o
f inp
ut s
tatu
ses
divi
sibl
e by
16
- see
rele
ase
note
s v1
.05)
N/A
1022
6313
Not
use
d (e
xist
s to
mak
e nu
mbe
r of i
nput
sta
tuse
s di
visi
ble
by 1
6 - s
ee re
leas
e no
tes
v1.0
5)N
/A10
2363
14N
ot u
sed
(exi
sts
to m
ake
num
ber o
f inp
ut s
tatu
ses
divi
sibl
e by
16
- see
rele
ase
note
s v1
.05)
N/A
1024
6315
Not
use
d (e
xist
s to
mak
e nu
mbe
r of i
nput
sta
tuse
s di
visi
ble
by 1
6 - s
ee re
leas
e no
tes
v1.0
5)N
/A
Pag
e 35
Inpu
t Sta
tus
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Out
put C
oils
: Sin
gle
bit d
igita
l (re
ad /
writ
e)N
ote:
[A],
[B] a
nd [C
] rep
rese
nt th
e th
ree
slav
e gr
oup/
unit
num
bers
from
the
Pro
con
V c
onfig
urat
ion
men
u.In
dex
Des
crip
tion
Mul
titro
de c
omm
and
for c
ontr
ol o
pera
tion
On
(1)
Off
(0)
1Th
is c
ontro
l rel
ates
to th
e m
aste
r Mon
itorP
RO
. Whe
n re
ad, t
his
cont
rol r
efle
cts
the
stat
us o
f Bin
ary
Inpu
t 712
(O
bj 0
1, In
dex
712)
. Tur
ning
the
cont
rol o
n w
ill e
nerg
ise
rela
y 1.
Tur
ning
the
cont
rol o
ff w
ill d
e-en
ergi
se re
lay
1.0x
3C 0
x00
0x3C
0x3C
0x1
1 0x
3C
2Th
is c
ontro
l rel
ates
to th
e m
aste
r Mon
itorP
RO
. Whe
n re
ad, t
his
cont
rol r
efle
cts
the
stat
us o
f Bin
ary
Inpu
t 711
(O
bj 0
1, In
dex
711)
. Tur
ning
the
cont
rol o
n w
ill e
nerg
ise
rela
y 2.
Tur
ning
the
cont
rol o
ff w
ill d
e-en
ergi
se re
lay
2.0x
3C 0
x02
0x3C
0x3C
0x2
2 0x
3C
3Th
is c
ontro
l rel
ates
to th
e m
aste
r Mon
itorP
RO
. Whe
n re
ad, t
his
cont
rol r
efle
cts
the
stat
us o
f Bin
ary
Inpu
t 710
(O
bj 0
1, In
dex
710)
. Tur
ning
the
cont
rol o
n w
ill e
nerg
ise
rela
y 3.
Tur
ning
the
cont
rol o
ff w
ill d
e-en
ergi
se re
lay
3.0x
3C 0
x03
0x3C
0x3C
0x3
3 0x
3C
4Th
is c
ontro
l rel
ates
to th
e m
aste
r pum
p co
ntro
ller.
Whe
n re
ad, t
his
cont
rol r
efle
cts
the
stat
us o
f Bin
ary
Inpu
t 88
8 (O
bj 0
1, In
dex
888)
. Tur
ning
the
cont
rol o
n w
ill e
nerg
ise
rela
y 1.
Tur
ning
the
cont
rol o
ff w
ill d
e-en
ergi
se
rela
y 1.
0x80
[A] 0
x00
0x00
0x8
0 0x
80 [A
] 0x0
0 0x
00 0
x80
5Th
is c
ontro
l rel
ates
to th
e m
aste
r pum
p co
ntro
ller.
Whe
n re
ad, t
his
cont
rol r
efle
cts
the
stat
us o
f Bin
ary
Inpu
t 88
9 (O
bj 0
1, In
dex
889)
. Tur
ning
the
cont
rol o
n w
ill e
nerg
ise
rela
y 2.
Tur
ning
the
cont
rol o
ff w
ill d
e-en
ergi
se
rela
y 2.
0x80
[A] 0
x02
0x00
0x8
0 0x
80 [A
] 0x0
2 0x
02 0
x80
6Th
is c
ontro
l rel
ates
to th
e m
aste
r pum
p co
ntro
ller.
Whe
n re
ad, t
his
cont
rol r
efle
cts
the
stat
us o
f Bin
ary
Inpu
t 89
0 (O
bj 0
1, In
dex
890)
. Tur
ning
the
cont
rol o
n w
ill e
nerg
ise
rela
y 3.
Tur
ning
the
cont
rol o
ff w
ill d
e-en
ergi
se
rela
y 3.
0x80
[A] 0
x04
0x00
0x8
0 0x
80 [A
] 0x0
4 0x
04 0
x80
7Th
is c
ontro
l rel
ates
to th
e m
aste
r pum
p co
ntro
ller.
Whe
n re
ad, t
his
cont
rol r
efle
cts
the
stat
us o
f Bin
ary
Inpu
t 89
1 (O
bj 0
1, In
dex
891)
. Tur
ning
the
cont
rol o
n w
ill e
nerg
ise
rela
y 4.
Tur
ning
the
cont
rol o
ff w
ill d
e-en
ergi
se
rela
y 4.
0x80
[A] 0
x08
0x00
0x8
0 0x
80 [A
] 0x0
8 0x
08 0
x80
8Th
is c
ontro
l rel
ates
to th
e m
aste
r pum
p co
ntro
ller.
Whe
n re
ad, t
his
cont
rol r
efle
cts
the
stat
us o
f Bin
ary
Inpu
t 89
2 (O
bj 0
1, In
dex
892)
. Tur
ning
the
cont
rol o
n w
ill e
nerg
ise
rela
y 5.
Tur
ning
the
cont
rol o
ff w
ill d
e-en
ergi
se
rela
y 5.
0x80
[A] 0
x10
0x00
0x8
0 0x
80 [A
] 0x1
0 0x
10 0
x80
9R
eser
ved
0x80
[B] 0
x00
0x00
0x8
0 0x
80 [B
] 0x0
0 0x
00 0
x80
10R
eser
ved
0x80
[B] 0
x02
0x00
0x8
0 0x
80 [B
] 0x0
2 0x
02 0
x80
11R
eser
ved
0x80
[B] 0
x04
0x00
0x8
0 0x
80 [B
] 0x0
4 0x
04 0
x80
12R
eser
ved
0x80
[B] 0
x08
0x00
0x8
0 0x
80 [B
] 0x0
8 0x
08 0
x80
13R
eser
ved
0x80
[B] 0
x10
0x00
0x8
0 0x
80 [B
] 0x1
0 0x
10 0
x80
14R
eser
ved
0x80
[C] 0
x00
0x00
0x8
0 0x
80 [C
] 0x0
0 0x
00 0
x80
15R
eser
ved
0x80
[C] 0
x02
0x00
0x8
0 0x
80 [C
] 0x0
2 0x
02 0
x80
16R
eser
ved
0x80
[C] 0
x04
0x00
0x8
0 0x
80 [C
] 0x0
4 0x
04 0
x80
17R
eser
ved
0x80
[C] 0
x08
0x00
0x8
0 0x
80 [C
] 0x0
8 0x
08 0
x80
Pag
e 36
Out
put C
oils
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Out
put C
oils
: Sin
gle
bit d
igita
l (re
ad /
writ
e)N
ote:
[A],
[B] a
nd [C
] rep
rese
nt th
e th
ree
slav
e gr
oup/
unit
num
bers
from
the
Pro
con
V c
onfig
urat
ion
men
u.In
dex
Des
crip
tion
Mul
titro
de c
omm
and
for c
ontr
ol o
pera
tion
On
(1)
Off
(0)
18R
eser
ved
0x80
[C] 0
x10
0x00
0x8
0 0x
80 [C
] 0x1
0 0x
10 0
x80
19Th
is c
ontro
l rel
ates
to th
e fir
st g
roup
of p
umps
onl
y. W
hen
read
, the
last
con
trol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on
). Tu
rnin
g th
e co
ntro
l on
will
faul
t pum
p 1
of g
roup
1. T
urni
ng th
e co
ntro
l off
will
rem
ove
the
pum
p fa
ult
cond
ition
but
not
rese
t the
indi
catio
n on
the
unit.
ie. T
he fa
ult w
ill b
e un
ackn
owle
ged
(to re
set t
he in
dica
tion
see
bina
ry o
utpu
t 45
belo
w).
0x83
[A] 0
x00
0x00
0x8
30x
83 [A
] 0x0
0 0x
01 0
x83
20Th
is c
ontro
l rel
ates
to th
e fir
st g
roup
of p
umps
onl
y. W
hen
read
, the
last
con
trol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on
). Tu
rnin
g th
e co
ntro
l on
will
faul
t pum
p 2
of g
roup
1. T
urni
ng th
e co
ntro
l off
will
rem
ove
the
pum
p fa
ult
cond
ition
but
not
rese
t the
indi
catio
n on
the
unit.
ie. T
he fa
ult w
ill b
e un
ackn
owle
ged
(to re
set t
he in
dica
tion
see
bina
ry o
utpu
t 46
belo
w).
0x83
[A] 0
x01
0x00
0x8
30x
83 [A
] 0x0
1 0x
01 0
x83
21Th
is c
ontro
l rel
ates
to th
e fir
st g
roup
of p
umps
onl
y. W
hen
read
, the
last
con
trol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on
). Tu
rnin
g th
e co
ntro
l on
will
faul
t pum
p 3
of g
roup
1. T
urni
ng th
e co
ntro
l off
will
rem
ove
the
pum
p fa
ult
cond
ition
but
not
rese
t the
indi
catio
n on
the
unit.
ie. T
he fa
ult w
ill b
e un
ackn
owle
ged
(to re
set t
he in
dica
tion
see
bina
ry o
utpu
t 47
belo
w).
0x83
[A] 0
x02
0x00
0x8
30x
83 [A
] 0x0
2 0x
01 0
x83
22Th
is c
ontro
l rel
ates
to th
e fir
st g
roup
of p
umps
onl
y. W
hen
read
, the
last
con
trol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on
). Tu
rnin
g th
e co
ntro
l on
will
faul
t pum
p 4
of g
roup
1. T
urni
ng th
e co
ntro
l off
will
rem
ove
the
pum
p fa
ult
cond
ition
but
not
rese
t the
indi
catio
n on
the
unit.
ie. T
he fa
ult w
ill b
e un
ackn
owle
ged
(to re
set t
he in
dica
tion
see
bina
ry o
utpu
t 48
belo
w).
0x83
[A] 0
x03
0x00
0x8
30x
83 [A
] 0x0
3 0x
01 0
x83
23Th
is c
ontro
l rel
ates
to th
e fir
st g
roup
of p
umps
onl
y. W
hen
read
, the
last
con
trol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on
). Tu
rnin
g th
e co
ntro
l on
will
faul
t pum
p 5
of g
roup
1. T
urni
ng th
e co
ntro
l off
will
rem
ove
the
pum
p fa
ult
cond
ition
but
not
rese
t the
indi
catio
n on
the
unit.
ie. T
he fa
ult w
ill b
e un
ackn
owle
ged
(to re
set t
he in
dica
tion
see
bina
ry o
utpu
t 49
belo
w).
0x83
[A] 0
x04
0x00
0x8
30x
83 [A
] 0x0
4 0x
01 0
x83
24Th
is c
ontro
l rel
ates
to th
e fir
st g
roup
of p
umps
onl
y. W
hen
read
, the
last
con
trol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on
). Tu
rnin
g th
e co
ntro
l on
will
faul
t pum
p 6
of g
roup
1. T
urni
ng th
e co
ntro
l off
will
rem
ove
the
pum
p fa
ult
cond
ition
but
not
rese
t the
indi
catio
n on
the
unit.
ie. T
he fa
ult w
ill b
e un
ackn
owle
ged
(to re
set t
he in
dica
tion
see
bina
ry o
utpu
t 50
belo
w).
0x83
[A] 0
x05
0x00
0x8
30x
83 [A
] 0x0
5 0x
01 0
x83
25Th
is c
ontro
l rel
ates
to th
e fir
st g
roup
of p
umps
onl
y. W
hen
read
, the
last
con
trol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on
). Tu
rnin
g th
e co
ntro
l on
will
faul
t pum
p 7
of g
roup
1. T
urni
ng th
e co
ntro
l off
will
rem
ove
the
pum
p fa
ult
cond
ition
but
not
rese
t the
indi
catio
n on
the
unit.
ie. T
he fa
ult w
ill b
e un
ackn
owle
ged
(to re
set t
he in
dica
tion
see
bina
ry o
utpu
t 51
belo
w).
0x83
[A] 0
x06
0x00
0x8
30x
83 [A
] 0x0
6 0x
01 0
x83
26Th
is c
ontro
l rel
ates
to th
e fir
st g
roup
of p
umps
onl
y. W
hen
read
, the
last
con
trol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on
). Tu
rnin
g th
e co
ntro
l on
will
faul
t pum
p 8
of g
roup
1. T
urni
ng th
e co
ntro
l off
will
rem
ove
the
pum
p fa
ult
cond
ition
but
not
rese
t the
indi
catio
n on
the
unit.
ie. T
he fa
ult w
ill b
e un
ackn
owle
ged
(to re
set t
he in
dica
tion
see
bina
ry o
utpu
t 52
belo
w).
0x83
[A] 0
x07
0x00
0x8
30x
83 [A
] 0x0
7 0x
01 0
x83
27Th
is c
ontro
l rel
ates
to th
e fir
st g
roup
of p
umps
onl
y. W
hen
read
, the
last
con
trol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on
). Tu
rnin
g th
e co
ntro
l on
will
faul
t pum
p 9
of g
roup
1. T
urni
ng th
e co
ntro
l off
will
rem
ove
the
pum
p fa
ult
cond
ition
but
not
rese
t the
indi
catio
n on
the
unit.
ie. T
he fa
ult w
ill b
e un
ackn
owle
ged
(to re
set t
he in
dica
tion
see
bina
ry o
utpu
t 53
belo
w).
0x83
[A] 0
x08
0x00
0x8
30x
83 [A
] 0x0
8 0x
01 0
x83
28R
eser
ved
0x83
[B] 0
x00
0x00
0x8
30x
83 [B
] 0x0
0 0x
01 0
x83
29R
eser
ved
0x83
[B] 0
x01
0x00
0x8
30x
83 [B
] 0x0
1 0x
01 0
x83
30R
eser
ved
0x83
[B] 0
x02
0x00
0x8
30x
83 [B
] 0x0
2 0x
01 0
x83
31R
eser
ved
0x83
[B] 0
x03
0x00
0x8
30x
83 [B
] 0x0
3 0x
01 0
x83
Pag
e 37
Out
put C
oils
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Out
put C
oils
: Sin
gle
bit d
igita
l (re
ad /
writ
e)N
ote:
[A],
[B] a
nd [C
] rep
rese
nt th
e th
ree
slav
e gr
oup/
unit
num
bers
from
the
Pro
con
V c
onfig
urat
ion
men
u.In
dex
Des
crip
tion
Mul
titro
de c
omm
and
for c
ontr
ol o
pera
tion
On
(1)
Off
(0)
32R
eser
ved
0x83
[B] 0
x04
0x00
0x8
30x
83 [B
] 0x0
4 0x
01 0
x83
33R
eser
ved
0x83
[B] 0
x05
0x00
0x8
30x
83 [B
] 0x0
5 0x
01 0
x83
34R
eser
ved
0x83
[B] 0
x06
0x00
0x8
30x
83 [B
] 0x0
6 0x
01 0
x83
35R
eser
ved
0x83
[B] 0
x07
0x00
0x8
30x
83 [B
] 0x0
7 0x
01 0
x83
36R
eser
ved
0x83
[B] 0
x08
0x00
0x8
30x
83 [B
] 0x0
8 0x
01 0
x83
37R
eser
ved
0x83
[C] 0
x00
0x00
0x8
30x
83 [C
] 0x0
0 0x
01 0
x83
38R
eser
ved
0x83
[C] 0
x01
0x00
0x8
30x
83 [C
] 0x0
1 0x
01 0
x83
39R
eser
ved
0x83
[C] 0
x02
0x00
0x8
30x
83 [C
] 0x0
2 0x
01 0
x83
40R
eser
ved
0x83
[C] 0
x03
0x00
0x8
30x
83 [C
] 0x0
3 0x
01 0
x83
41R
eser
ved
0x83
[C] 0
x04
0x00
0x8
30x
83 [C
] 0x0
4 0x
01 0
x83
42R
eser
ved
0x83
[C] 0
x05
0x00
0x8
30x
83 [C
] 0x0
5 0x
01 0
x83
43R
eser
ved
0x83
[C] 0
x06
0x00
0x8
30x
83 [C
] 0x0
6 0x
01 0
x83
44R
eser
ved
0x83
[C] 0
x07
0x00
0x8
30x
83 [C
] 0x0
7 0x
01 0
x83
45R
eser
ved
0x83
[C] 0
x08
0x00
0x8
30x
83 [C
] 0x0
8 0x
01 0
x83
46Th
is c
ontro
l rel
ates
to th
e fir
st g
roup
of p
umps
onl
y. W
hen
read
, the
last
con
trol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on
). Tu
rnin
g th
e co
ntro
l on
will
ack
now
ledg
e pu
mp
1 fa
ult.
Turn
ing
the
cont
rol o
ff ha
s no
act
ion.
No
Act
ion
0x85
[A] 0
x00
0x85
47Th
is c
ontro
l rel
ates
to th
e fir
st g
roup
of p
umps
onl
y. W
hen
read
, the
last
con
trol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on
). Tu
rnin
g th
e co
ntro
l on
will
ack
now
ledg
e pu
mp
2 fa
ult.
Turn
ing
the
cont
rol o
ff ha
s no
act
ion.
No
Act
ion
0x85
[A] 0
x01
0x85
48Th
is c
ontro
l rel
ates
to th
e fir
st g
roup
of p
umps
onl
y. W
hen
read
, the
last
con
trol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on
). Tu
rnin
g th
e co
ntro
l on
will
ack
now
ledg
e pu
mp
3 fa
ult.
Turn
ing
the
cont
rol o
ff ha
s no
act
ion.
No
Act
ion
0x85
[A] 0
x02
0x85
49Th
is c
ontro
l rel
ates
to th
e fir
st g
roup
of p
umps
onl
y. W
hen
read
, the
last
con
trol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on
). Tu
rnin
g th
e co
ntro
l on
will
ack
now
ledg
e pu
mp
4 fa
ult.
Turn
ing
the
cont
rol o
ff ha
s no
act
ion.
No
Act
ion
0x85
[A] 0
x03
0x85
50Th
is c
ontro
l rel
ates
to th
e fir
st g
roup
of p
umps
onl
y. W
hen
read
, the
last
con
trol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on
). Tu
rnin
g th
e co
ntro
l on
will
ack
now
ledg
e pu
mp
5 fa
ult.
Turn
ing
the
cont
rol o
ff ha
s no
act
ion.
No
Act
ion
0x85
[A] 0
x04
0x85
51Th
is c
ontro
l rel
ates
to th
e fir
st g
roup
of p
umps
onl
y. W
hen
read
, the
last
con
trol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on
). Tu
rnin
g th
e co
ntro
l on
will
ack
now
ledg
e pu
mp
6 fa
ult.
Turn
ing
the
cont
rol o
ff ha
s no
act
ion.
No
Act
ion
0x85
[A] 0
x05
0x85
52Th
is c
ontro
l rel
ates
to th
e fir
st g
roup
of p
umps
onl
y. W
hen
read
, the
last
con
trol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on
). Tu
rnin
g th
e co
ntro
l on
will
ack
now
ledg
e pu
mp
7 fa
ult.
Turn
ing
the
cont
rol o
ff ha
s no
act
ion.
No
Act
ion
0x85
[A] 0
x06
0x85
53Th
is c
ontro
l rel
ates
to th
e fir
st g
roup
of p
umps
onl
y. W
hen
read
, the
last
con
trol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on
). Tu
rnin
g th
e co
ntro
l on
will
ack
now
ledg
e pu
mp
8 fa
ult.
Turn
ing
the
cont
rol o
ff ha
s no
act
ion.
No
Act
ion
0x85
[A] 0
x07
0x85
54Th
is c
ontro
l rel
ates
to th
e fir
st g
roup
of p
umps
onl
y. W
hen
read
, the
last
con
trol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on
). Tu
rnin
g th
e co
ntro
l on
will
ack
now
ledg
e pu
mp
9 fa
ult.
Turn
ing
the
cont
rol o
ff ha
s no
act
ion.
No
Act
ion
0x85
[A] 0
x08
0x85
55R
eser
ved
No
Act
ion
0x85
[B] 0
x00
0x85
Pag
e 38
Out
put C
oils
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Out
put C
oils
: Sin
gle
bit d
igita
l (re
ad /
writ
e)N
ote:
[A],
[B] a
nd [C
] rep
rese
nt th
e th
ree
slav
e gr
oup/
unit
num
bers
from
the
Pro
con
V c
onfig
urat
ion
men
u.In
dex
Des
crip
tion
Mul
titro
de c
omm
and
for c
ontr
ol o
pera
tion
On
(1)
Off
(0)
56R
eser
ved
No
Act
ion
0x85
[B] 0
x01
0x85
57R
eser
ved
No
Act
ion
0x85
[B] 0
x02
0x85
58R
eser
ved
No
Act
ion
0x85
[B] 0
x03
0x85
59R
eser
ved
No
Act
ion
0x85
[B] 0
x04
0x85
60R
eser
ved
No
Act
ion
0x85
[B] 0
x05
0x85
61R
eser
ved
No
Act
ion
0x85
[B] 0
x06
0x85
62R
eser
ved
No
Act
ion
0x85
[B] 0
x07
0x85
63R
eser
ved
No
Act
ion
0x85
[B] 0
x08
0x85
64R
eser
ved
No
Act
ion
0x85
[C] 0
x00
0x85
65R
eser
ved
No
Act
ion
0x85
[C] 0
x01
0x85
66R
eser
ved
No
Act
ion
0x85
[C] 0
x02
0x85
67R
eser
ved
No
Act
ion
0x85
[C] 0
x03
0x85
68R
eser
ved
No
Act
ion
0x85
[C] 0
x04
0x85
69R
eser
ved
No
Act
ion
0x85
[C] 0
x05
0x85
70R
eser
ved
No
Act
ion
0x85
[C] 0
x06
0x85
71R
eser
ved
No
Act
ion
0x85
[C] 0
x07
0x85
72R
eser
ved
No
Act
ion
0x85
[C] 0
x08
0x85
73Tu
rnin
g th
e co
ntro
l on
will
cau
se p
ump
1 to
sw
itch
OFF
and
the
OFF
LE
D w
ill fl
ash
on th
e un
it. T
urni
ng th
e co
ntro
l off
has
no a
ctio
n. W
hen
read
, the
last
con
trol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on)
.N
o ac
tion
0x86
[A] 0
x00
0x01
0x8
6
74Tu
rnin
g th
e co
ntro
l on
will
cau
se p
ump
1 to
sw
itch
to A
UTO
mod
e an
d th
e A
UTO
mod
e LE
D w
ill il
lum
inat
e on
th
e un
it. T
urni
ng th
e co
ntro
l off
has
no a
ctio
n. W
hen
read
, the
last
con
trol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on)
.N
o ac
tion
0x86
[A] 0
x00
0x00
0x8
6
75Tu
rnin
g th
e co
ntro
l on
will
cau
se p
ump
1 to
sw
itch
to M
AN
UA
L m
ode
and
the
MA
NU
AL/
HA
ND
LE
D w
ill
illum
inat
e on
the
unit.
Tur
ning
the
cont
rol o
ff ha
s no
act
ion.
Whe
n re
ad, t
he la
st c
ontro
l atte
mpt
is re
turn
ed (0
=
off,
1 =
on).
No
actio
n0x
86 [A
] 0x0
0 0x
03 0
x86
76Tu
rnin
g th
e co
ntro
l on
will
cau
se p
ump
2 to
sw
itch
OFF
and
the
OFF
LE
D w
ill fl
ash
on th
e un
it. T
urni
ng th
e co
ntro
l off
has
no a
ctio
n. W
hen
read
, the
last
con
trol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on)
.N
o ac
tion
0x86
[A] 0
x01
0x01
0x8
6
77Tu
rnin
g th
e co
ntro
l on
will
cau
se p
ump
2 to
sw
itch
OFF
and
the
OFF
LE
D w
ill fl
ash
on th
e un
it. T
urni
ng th
e co
ntro
l off
has
no a
ctio
n. W
hen
read
, the
last
con
trol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on)
.N
o ac
tion
0x86
[A] 0
x01
0x00
0x8
6
78Tu
rnin
g th
e co
ntro
l on
will
cau
se p
ump
2 to
sw
itch
OFF
and
the
OFF
LE
D w
ill fl
ash
on th
e un
it. T
urni
ng th
e co
ntro
l off
has
no a
ctio
n. W
hen
read
, the
last
con
trol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on)
.N
o ac
tion
0x86
[A] 0
x01
0x03
0x8
6
79Tu
rnin
g th
e co
ntro
l on
will
cau
se p
ump
3 to
sw
itch
OFF
and
the
OFF
LE
D w
ill fl
ash
on th
e un
it. T
urni
ng th
e co
ntro
l off
has
no a
ctio
n. W
hen
read
, the
last
con
trol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on)
.N
o ac
tion
0x86
[A] 0
x02
0x01
0x8
6
80Tu
rnin
g th
e co
ntro
l on
will
cau
se p
ump
3 to
sw
itch
to A
UTO
mod
e an
d th
e A
UTO
mod
e LE
D w
ill il
lum
inat
e on
th
e un
it. T
urni
ng th
e co
ntro
l off
has
no a
ctio
n. W
hen
read
, the
last
con
trol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on)
.N
o ac
tion
0x86
[A] 0
x02
0x00
0x8
6
81Tu
rnin
g th
e co
ntro
l on
will
cau
se p
ump
3 to
sw
itch
to M
AN
UA
L m
ode
and
the
MA
NU
AL/
HA
ND
LE
D w
ill
illum
inat
e on
the
unit.
Tur
ning
the
cont
rol o
ff ha
s no
act
ion.
Whe
n re
ad, t
he la
st c
ontro
l atte
mpt
is re
turn
ed (0
=
off,
1 =
on).
No
actio
n0x
86 [A
] 0x0
2 0x
03 0
x86
82Tu
rnin
g th
e co
ntro
l on
will
cau
se p
ump
4 to
sw
itch
OFF
and
the
OFF
LE
D w
ill fl
ash
on th
e un
it. T
urni
ng th
e co
ntro
l off
has
no a
ctio
n. W
hen
read
, the
last
con
trol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on)
.N
o ac
tion
0x86
[A] 0
x03
0x01
0x8
6
Pag
e 39
Out
put C
oils
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Out
put C
oils
: Sin
gle
bit d
igita
l (re
ad /
writ
e)N
ote:
[A],
[B] a
nd [C
] rep
rese
nt th
e th
ree
slav
e gr
oup/
unit
num
bers
from
the
Pro
con
V c
onfig
urat
ion
men
u.In
dex
Des
crip
tion
Mul
titro
de c
omm
and
for c
ontr
ol o
pera
tion
On
(1)
Off
(0)
83Tu
rnin
g th
e co
ntro
l on
will
cau
se p
ump
4 to
sw
itch
to A
UTO
mod
e an
d th
e A
UTO
mod
e LE
D w
ill il
lum
inat
e on
th
e un
it. T
urni
ng th
e co
ntro
l off
has
no a
ctio
n. W
hen
read
, the
last
con
trol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on)
.N
o ac
tion
0x86
[A] 0
x03
0x00
0x8
6
84Tu
rnin
g th
e co
ntro
l on
will
cau
se p
ump
4 to
sw
itch
to M
AN
UA
L m
ode
and
the
MA
NU
AL/
HA
ND
LE
D w
ill
illum
inat
e on
the
unit.
Tur
ning
the
cont
rol o
ff ha
s no
act
ion.
Whe
n re
ad, t
he la
st c
ontro
l atte
mpt
is re
turn
ed (0
=
off,
1 =
on).
No
actio
n0x
86 [A
] 0x0
3 0x
03 0
x86
85Tu
rnin
g th
e co
ntro
l on
will
cau
se p
ump
5 to
sw
itch
OFF
and
the
OFF
LE
D w
ill fl
ash
on th
e un
it. T
urni
ng th
e co
ntro
l off
has
no a
ctio
n. W
hen
read
, the
last
con
trol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on)
.N
o ac
tion
0x86
[A] 0
x04
0x01
0x8
6
86Tu
rnin
g th
e co
ntro
l on
will
cau
se p
ump
5 to
sw
itch
to A
UTO
mod
e an
d th
e A
UTO
mod
e LE
D w
ill il
lum
inat
e on
th
e un
it. T
urni
ng th
e co
ntro
l off
has
no a
ctio
n. W
hen
read
, the
last
con
trol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on)
.N
o ac
tion
0x86
[A] 0
x04
0x00
0x8
6
87Tu
rnin
g th
e co
ntro
l on
will
cau
se p
ump
5 to
sw
itch
to M
AN
UA
L m
ode
and
the
MA
NU
AL/
HA
ND
LE
D w
ill
illum
inat
e on
the
unit.
Tur
ning
the
cont
rol o
ff ha
s no
act
ion.
Whe
n re
ad, t
he la
st c
ontro
l atte
mpt
is re
turn
ed (0
=
off,
1 =
on).
No
actio
n0x
86 [A
] 0x0
4 0x
03 0
x86
88Tu
rnin
g th
e co
ntro
l on
will
cau
se p
ump
6 to
sw
itch
OFF
and
the
OFF
LE
D w
ill fl
ash
on th
e un
it. T
urni
ng th
e co
ntro
l off
has
no a
ctio
n. W
hen
read
, the
last
con
trol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on)
.N
o ac
tion
0x86
[A] 0
x05
0x01
0x8
6
89Tu
rnin
g th
e co
ntro
l on
will
cau
se p
ump
6 to
sw
itch
to A
UTO
mod
e an
d th
e A
UTO
mod
e LE
D w
ill il
lum
inat
e on
th
e un
it. T
urni
ng th
e co
ntro
l off
has
no a
ctio
n. W
hen
read
, the
last
con
trol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on)
.N
o ac
tion
0x86
[A] 0
x05
0x00
0x8
6
90Tu
rnin
g th
e co
ntro
l on
will
cau
se p
ump
6 to
sw
itch
to M
AN
UA
L m
ode
and
the
MA
NU
AL/
HA
ND
LE
D w
ill
illum
inat
e on
the
unit.
Tur
ning
the
cont
rol o
ff ha
s no
act
ion.
Whe
n re
ad, t
he la
st c
ontro
l atte
mpt
is re
turn
ed (0
=
off,
1 =
on).
No
actio
n0x
86 [A
] 0x0
5 0x
03 0
x86
91Tu
rnin
g th
e co
ntro
l on
will
cau
se p
ump
7 to
sw
itch
OFF
and
the
OFF
LE
D w
ill fl
ash
on th
e un
it. T
urni
ng th
e co
ntro
l off
has
no a
ctio
n. W
hen
read
, the
last
con
trol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on)
.N
o ac
tion
0x86
[A] 0
x06
0x01
0x8
6
92Tu
rnin
g th
e co
ntro
l on
will
cau
se p
ump
7 to
sw
itch
to A
UTO
mod
e an
d th
e A
UTO
mod
e LE
D w
ill il
lum
inat
e on
th
e un
it. T
urni
ng th
e co
ntro
l off
has
no a
ctio
n. W
hen
read
, the
last
con
trol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on)
.N
o ac
tion
0x86
[A] 0
x06
0x00
0x8
6
93Tu
rnin
g th
e co
ntro
l on
will
cau
se p
ump
7 to
sw
itch
to M
AN
UA
L m
ode
and
the
MA
NU
AL/
HA
ND
LE
D w
ill
illum
inat
e on
the
unit.
Tur
ning
the
cont
rol o
ff ha
s no
act
ion.
Whe
n re
ad, t
he la
st c
ontro
l atte
mpt
is re
turn
ed (0
=
off,
1 =
on).
No
actio
n0x
86 [A
] 0x0
6 0x
03 0
x86
94Tu
rnin
g th
e co
ntro
l on
will
cau
se p
ump
8 to
sw
itch
OFF
and
the
OFF
LE
D w
ill fl
ash
on th
e un
it. T
urni
ng th
e co
ntro
l off
has
no a
ctio
n. W
hen
read
, the
last
con
trol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on)
.N
o ac
tion
0x86
[A] 0
x07
0x01
0x8
6
95Tu
rnin
g th
e co
ntro
l on
will
cau
se p
ump
8 to
sw
itch
to A
UTO
mod
e an
d th
e A
UTO
mod
e LE
D w
ill il
lum
inat
e on
th
e un
it. T
urni
ng th
e co
ntro
l off
has
no a
ctio
n. W
hen
read
, the
last
con
trol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on)
.N
o ac
tion
0x86
[A] 0
x07
0x00
0x8
6
96Tu
rnin
g th
e co
ntro
l on
will
cau
se p
ump
8 to
sw
itch
to M
AN
UA
L m
ode
and
the
MA
NU
AL/
HA
ND
LE
D w
ill
illum
inat
e on
the
unit.
Tur
ning
the
cont
rol o
ff ha
s no
act
ion.
Whe
n re
ad, t
he la
st c
ontro
l atte
mpt
is re
turn
ed (0
=
off,
1 =
on).
No
actio
n0x
86 [A
] 0x0
7 0x
03 0
x86
97Tu
rnin
g th
e co
ntro
l on
will
cau
se p
ump
9 to
sw
itch
OFF
and
the
OFF
LE
D w
ill fl
ash
on th
e un
it. T
urni
ng th
e co
ntro
l off
has
no a
ctio
n. W
hen
read
, the
last
con
trol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on)
.N
o ac
tion
0x86
[A] 0
x08
0x01
0x8
6
Pag
e 40
Out
put C
oils
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Out
put C
oils
: Sin
gle
bit d
igita
l (re
ad /
writ
e)N
ote:
[A],
[B] a
nd [C
] rep
rese
nt th
e th
ree
slav
e gr
oup/
unit
num
bers
from
the
Pro
con
V c
onfig
urat
ion
men
u.In
dex
Des
crip
tion
Mul
titro
de c
omm
and
for c
ontr
ol o
pera
tion
On
(1)
Off
(0)
98Tu
rnin
g th
e co
ntro
l on
will
cau
se p
ump
9 to
sw
itch
to A
UTO
mod
e an
d th
e A
UTO
mod
e LE
D w
ill il
lum
inat
e on
th
e un
it. T
urni
ng th
e co
ntro
l off
has
no a
ctio
n. W
hen
read
, the
last
con
trol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on)
.N
o ac
tion
0x86
[A] 0
x08
0x00
0x8
6
99Tu
rnin
g th
e co
ntro
l on
will
cau
se p
ump
9 to
sw
itch
to M
AN
UA
L m
ode
and
the
MA
NU
AL/
HA
ND
LE
D w
ill
illum
inat
e on
the
unit.
Tur
ning
the
cont
rol o
ff ha
s no
act
ion.
Whe
n re
ad, t
he la
st c
ontro
l atte
mpt
is re
turn
ed (0
=
off,
1 =
on).
No
actio
n0x
86 [A
] 0x0
8 0x
03 0
x86
100
Res
erve
dN
o ac
tion
0x86
[B] 0
x00
0x01
0x8
610
1R
eser
ved
No
actio
n0x
86 [B
] 0x0
0 0x
00 0
x86
102
Res
erve
dN
o ac
tion
0x86
[B] 0
x00
0x03
0x8
610
3R
eser
ved
No
actio
n0x
86 [B
] 0x0
1 0x
01 0
x86
104
Res
erve
dN
o ac
tion
0x86
[B] 0
x01
0x00
0x8
610
5R
eser
ved
No
actio
n0x
86 [B
] 0x0
1 0x
03 0
x86
106
Res
erve
dN
o ac
tion
0x86
[B] 0
x02
0x01
0x8
610
7R
eser
ved
No
actio
n0x
86 [B
] 0x0
2 0x
00 0
x86
108
Res
erve
dN
o ac
tion
0x86
[B] 0
x02
0x03
0x8
610
9R
eser
ved
No
actio
n0x
86 [B
] 0x0
3 0x
01 0
x86
110
Res
erve
dN
o ac
tion
0x86
[B] 0
x03
0x00
0x8
611
1R
eser
ved
No
actio
n0x
86 [B
] 0x0
3 0x
03 0
x86
112
Res
erve
dN
o ac
tion
0x86
[B] 0
x04
0x01
0x8
611
3R
eser
ved
No
actio
n0x
86 [B
] 0x0
4 0x
00 0
x86
114
Res
erve
dN
o ac
tion
0x86
[B] 0
x04
0x03
0x8
611
5R
eser
ved
No
actio
n0x
86 [B
] 0x0
5 0x
01 0
x86
116
Res
erve
dN
o ac
tion
0x86
[B] 0
x05
0x00
0x8
611
7R
eser
ved
No
actio
n0x
86 [B
] 0x0
5 0x
03 0
x86
118
Res
erve
dN
o ac
tion
0x86
[B] 0
x06
0x01
0x8
611
9R
eser
ved
No
actio
n0x
86 [B
] 0x0
6 0x
00 0
x86
120
Res
erve
dN
o ac
tion
0x86
[B] 0
x06
0x03
0x8
612
1R
eser
ved
No
actio
n0x
86 [B
] 0x0
7 0x
01 0
x86
122
Res
erve
dN
o ac
tion
0x86
[B] 0
x07
0x00
0x8
612
3R
eser
ved
No
actio
n0x
86 [B
] 0x0
7 0x
03 0
x86
124
Res
erve
dN
o ac
tion
0x86
[B] 0
x08
0x01
0x8
612
5R
eser
ved
No
actio
n0x
86 [B
] 0x0
8 0x
00 0
x86
126
Res
erve
dN
o ac
tion
0x86
[B] 0
x08
0x03
0x8
612
7R
eser
ved
No
actio
n0x
86 [C
] 0x0
0 0x
01 0
x86
128
Res
erve
dN
o ac
tion
0x86
[C] 0
x00
0x00
0x8
612
9R
eser
ved
No
actio
n0x
86 [C
] 0x0
0 0x
03 0
x86
130
Res
erve
dN
o ac
tion
0x86
[C] 0
x01
0x01
0x8
613
1R
eser
ved
No
actio
n0x
86 [C
] 0x0
1 0x
00 0
x86
132
Res
erve
dN
o ac
tion
0x86
[C] 0
x01
0x03
0x8
613
3R
eser
ved
No
actio
n0x
86 [C
] 0x0
2 0x
01 0
x86
134
Res
erve
dN
o ac
tion
0x86
[C] 0
x02
0x00
0x8
613
5R
eser
ved
No
actio
n0x
86 [C
] 0x0
2 0x
03 0
x86
Pag
e 41
Out
put C
oils
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Out
put C
oils
: Sin
gle
bit d
igita
l (re
ad /
writ
e)N
ote:
[A],
[B] a
nd [C
] rep
rese
nt th
e th
ree
slav
e gr
oup/
unit
num
bers
from
the
Pro
con
V c
onfig
urat
ion
men
u.In
dex
Des
crip
tion
Mul
titro
de c
omm
and
for c
ontr
ol o
pera
tion
On
(1)
Off
(0)
136
Res
erve
dN
o ac
tion
0x86
[C] 0
x03
0x01
0x8
613
7R
eser
ved
No
actio
n0x
86 [C
] 0x0
3 0x
00 0
x86
138
Res
erve
dN
o ac
tion
0x86
[C] 0
x03
0x03
0x8
613
9R
eser
ved
No
actio
n0x
86 [C
] 0x0
4 0x
01 0
x86
140
Res
erve
dN
o ac
tion
0x86
[C] 0
x04
0x00
0x8
614
1R
eser
ved
No
actio
n0x
86 [C
] 0x0
4 0x
03 0
x86
142
Res
erve
dN
o ac
tion
0x86
[C] 0
x05
0x01
0x8
614
3R
eser
ved
No
actio
n0x
86 [C
] 0x0
5 0x
00 0
x86
144
Res
erve
dN
o ac
tion
0x86
[C] 0
x05
0x03
0x8
614
5R
eser
ved
No
actio
n0x
86 [C
] 0x0
6 0x
01 0
x86
146
Res
erve
dN
o ac
tion
0x86
[C] 0
x06
0x00
0x8
614
7R
eser
ved
No
actio
n0x
86 [C
] 0x0
6 0x
03 0
x86
148
Res
erve
dN
o ac
tion
0x86
[C] 0
x07
0x01
0x8
614
9R
eser
ved
No
actio
n0x
86 [C
] 0x0
7 0x
00 0
x86
150
Res
erve
dN
o ac
tion
0x86
[C] 0
x07
0x03
0x8
615
1R
eser
ved
No
actio
n0x
86 [C
] 0x0
8 0x
01 0
x86
152
Res
erve
dN
o ac
tion
0x86
[C] 0
x08
0x00
0x8
615
3R
eser
ved
No
actio
n0x
86 [C
] 0x0
8 0x
03 0
x86
154
Turn
ing
the
cont
rol o
n w
ill c
ause
gro
up 1
uni
ts to
be
plac
ed in
to P
EA
K L
EV
EL
mod
e. T
urni
ng th
e co
ntro
l off
wre
turn
the
grou
p ba
ck to
nor
mal
con
trol.
Whe
n re
ad, t
he la
st c
ontro
l atte
mpt
is re
turn
ed (0
= o
ff, 1
= o
n).
0x87
[A] 0
x00
0x87
0x87
[A] 0
x00
0x87
155
Res
erve
d0x
87 [B
] 0x0
0 0x
870x
87 [A
] 0x0
0 0x
8715
6R
eser
ved
0x87
[C] 0
x00
0x87
0x87
[A] 0
x00
0x87
157
Turn
ing
the
cont
rol o
n w
ill c
ause
all
pum
ps in
gro
up 1
to b
e sw
itche
d O
FF (s
et in
HO
LD O
UT
mod
e) a
nd th
e av
aila
ble
LED
will
flas
h. T
urni
ng th
e co
ntro
l off
will
rem
ove
the
HO
LD O
UT
cond
ition
and
retu
rn a
ll pu
mps
to
norm
al o
pera
tion.
Whe
n re
ad, t
he la
st c
ontro
l atte
mpt
is re
turn
ed (0
= o
ff, 1
= o
n).
0x88
[A] 0
x00
0x88
0x88
[A] 0
x00
0x88
158
Res
erve
d0x
88 [B
] 0x0
0 0x
880x
88 [A
] 0x0
0 0x
8815
9R
eser
ved
0x88
[C] 0
x00
0x88
0x88
[A] 0
x00
0x88
160
Turn
ing
the
cont
rol o
n w
ill c
ause
one
pum
p in
gro
up 1
to s
tart.
The
pum
p to
sta
rt w
ill b
e th
e "n
ext t
o st
art"
pum
in th
e se
t seq
uenc
e. F
or th
e pu
mp
to s
tart,
the
deac
tivat
ion
leve
l has
to b
e co
vere
d an
d th
e pu
mps
will
sto
p on
ce th
e de
activ
atio
n le
vel h
as b
een
clea
red.
Tur
ning
the
cont
rol o
ff ha
s no
effe
ct. W
hen
read
, the
last
con
trol
atte
mpt
is re
turn
ed (0
= o
ff, 1
= o
n).
No
actio
n0x
89 [A
] 0x0
0 0x
89
161
Turn
ing
the
cont
rol o
n w
ill c
ause
two
pum
ps in
gro
up 1
to s
tart.
The
pum
ps to
sta
rt w
ill b
e th
e "n
ext t
o st
art"
pum
ps in
the
set s
eque
nce.
For
the
pum
ps to
sta
rt, th
e de
activ
atio
n le
vel h
as to
be
cove
red
and
the
pum
ps w
ill
stop
onc
e th
e de
activ
atio
n le
vel h
as b
een
clea
red.
Tur
ning
the
cont
rol o
ff ha
s no
effe
ct. W
hen
read
, the
last
co
ntro
l atte
mpt
is re
turn
ed (0
= o
ff, 1
= o
n).
No
actio
n0x
89 [A
] 0x0
2 0x
89
162
Turn
ing
the
cont
rol o
n w
ill c
ause
thre
e pu
mps
in g
roup
1 to
sta
rt. T
he p
umps
to s
tart
will
be
the
"nex
t to
star
t" pu
mps
in th
e se
t seq
uenc
e. F
or th
e pu
mps
to s
tart,
the
deac
tivat
ion
leve
l has
to b
e co
vere
d an
d th
e pu
mps
will
st
op o
nce
the
deac
tivat
ion
leve
l has
bee
n cl
eare
d. T
urni
ng th
e co
ntro
l off
has
no e
ffect
. Whe
n re
ad, t
he la
st
cont
rol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on)
.
No
actio
n0x
89 [A
] 0x0
3 0x
89
Pag
e 42
Out
put C
oils
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Out
put C
oils
: Sin
gle
bit d
igita
l (re
ad /
writ
e)N
ote:
[A],
[B] a
nd [C
] rep
rese
nt th
e th
ree
slav
e gr
oup/
unit
num
bers
from
the
Pro
con
V c
onfig
urat
ion
men
u.In
dex
Des
crip
tion
Mul
titro
de c
omm
and
for c
ontr
ol o
pera
tion
On
(1)
Off
(0)
163
Turn
ing
the
cont
rol o
n w
ill c
ause
four
pum
ps in
gro
up 1
to s
tart.
The
pum
ps to
sta
rt w
ill b
e th
e "n
ext t
o st
art"
pum
ps in
the
set s
eque
nce.
For
the
pum
ps to
sta
rt, th
e de
activ
atio
n le
vel h
as to
be
cove
red
and
the
pum
ps w
ill
stop
onc
e th
e de
activ
atio
n le
vel h
as b
een
clea
red.
Tur
ning
the
cont
rol o
ff ha
s no
effe
ct. W
hen
read
, the
last
co
ntro
l atte
mpt
is re
turn
ed (0
= o
ff, 1
= o
n).
No
actio
n0x
89 [A
] 0x0
4 0x
89
164
Turn
ing
the
cont
rol o
n w
ill c
ause
five
pum
ps in
gro
up 1
to s
tart.
The
pum
ps to
sta
rt w
ill b
e th
e "n
ext t
o st
art"
pum
ps in
the
set s
eque
nce.
For
the
pum
ps to
sta
rt, th
e de
activ
atio
n le
vel h
as to
be
cove
red
and
the
pum
ps w
ill
stop
onc
e th
e de
activ
atio
n le
vel h
as b
een
clea
red.
Tur
ning
the
cont
rol o
ff ha
s no
effe
ct. W
hen
read
, the
last
co
ntro
l atte
mpt
is re
turn
ed (0
= o
ff, 1
= o
n).
No
actio
n0x
89 [A
] 0x0
5 0x
89
165
Turn
ing
the
cont
rol o
n w
ill c
ause
six
pum
ps in
gro
up 1
to s
tart.
The
pum
ps to
sta
rt w
ill b
e th
e "n
ext t
o st
art"
pum
ps in
the
set s
eque
nce.
For
the
pum
ps to
sta
rt, th
e de
activ
atio
n le
vel h
as to
be
cove
red
and
the
pum
ps w
ill
stop
onc
e th
e de
activ
atio
n le
vel h
as b
een
clea
red.
Tur
ning
the
cont
rol o
ff ha
s no
effe
ct. W
hen
read
, the
last
co
ntro
l atte
mpt
is re
turn
ed (0
= o
ff, 1
= o
n).
No
actio
n0x
89 [A
] 0x0
6 0x
89
166
Turn
ing
the
cont
rol o
n w
ill c
ause
sev
en p
umps
in g
roup
1 to
sta
rt. T
he p
umps
to s
tart
will
be
the
"nex
t to
star
t" pu
mps
in th
e se
t seq
uenc
e. F
or th
e pu
mps
to s
tart,
the
deac
tivat
ion
leve
l has
to b
e co
vere
d an
d th
e pu
mps
will
st
op o
nce
the
deac
tivat
ion
leve
l has
bee
n cl
eare
d. T
urni
ng th
e co
ntro
l off
has
no e
ffect
. Whe
n re
ad, t
he la
st
cont
rol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on)
.
No
actio
n0x
89 [A
] 0x0
7 0x
89
167
Turn
ing
the
cont
rol o
n w
ill c
ause
eig
ht p
umps
in g
roup
1 to
sta
rt. T
he p
umps
to s
tart
will
be
the
"nex
t to
star
t" pu
mps
in th
e se
t seq
uenc
e. F
or th
e pu
mps
to s
tart,
the
deac
tivat
ion
leve
l has
to b
e co
vere
d an
d th
e pu
mps
will
st
op o
nce
the
deac
tivat
ion
leve
l has
bee
n cl
eare
d. T
urni
ng th
e co
ntro
l off
has
no e
ffect
. Whe
n re
ad, t
he la
st
cont
rol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on)
.
No
actio
n0x
89 [A
] 0x0
8 0x
89
168
Turn
ing
the
cont
rol o
n w
ill c
ause
nin
e pu
mps
in g
roup
1 to
sta
rt. T
he p
umps
to s
tart
will
be
the
"nex
t to
star
t" pu
mps
in th
e se
t seq
uenc
e. F
or th
e pu
mps
to s
tart,
the
deac
tivat
ion
leve
l has
to b
e co
vere
d an
d th
e pu
mps
will
st
op o
nce
the
deac
tivat
ion
leve
l has
bee
n cl
eare
d. T
urni
ng th
e co
ntro
l off
has
no e
ffect
. Whe
n re
ad, t
he la
st
cont
rol a
ttem
pt is
retu
rned
(0 =
off,
1 =
on)
.
No
actio
n0x
89 [A
] 0x0
9 0x
89
169
Res
erve
dN
o ac
tion
0x89
[B] 0
x00
0x89
170
Res
erve
dN
o ac
tion
0x89
[B] 0
x02
0x89
171
Res
erve
dN
o ac
tion
0x89
[B] 0
x03
0x89
172
Res
erve
dN
o ac
tion
0x89
[B] 0
x04
0x89
173
Res
erve
dN
o ac
tion
0x89
[B] 0
x05
0x89
174
Res
erve
dN
o ac
tion
0x89
[B] 0
x06
0x89
175
Res
erve
dN
o ac
tion
0x89
[B] 0
x07
0x89
176
Res
erve
dN
o ac
tion
0x89
[B] 0
x08
0x89
177
Res
erve
dN
o ac
tion
0x89
[B] 0
x09
0x89
178
Res
erve
dN
o ac
tion
0x89
[C] 0
x00
0x89
179
Res
erve
dN
o ac
tion
0x89
[C] 0
x02
0x89
180
Res
erve
dN
o ac
tion
0x89
[C] 0
x03
0x89
181
Res
erve
dN
o ac
tion
0x89
[C] 0
x04
0x89
182
Res
erve
dN
o ac
tion
0x89
[C] 0
x05
0x89
183
Res
erve
dN
o ac
tion
0x89
[C] 0
x06
0x89
184
Res
erve
dN
o ac
tion
0x89
[C] 0
x07
0x89
185
Res
erve
dN
o ac
tion
0x89
[C] 0
x08
0x89
186
Res
erve
dN
o ac
tion
0x89
[C] 0
x09
0x89
Pag
e 43
Out
put C
oils
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Out
put C
oils
: Sin
gle
bit d
igita
l (re
ad /
writ
e)N
ote:
[A],
[B] a
nd [C
] rep
rese
nt th
e th
ree
slav
e gr
oup/
unit
num
bers
from
the
Pro
con
V c
onfig
urat
ion
men
u.In
dex
Des
crip
tion
Mul
titro
de c
omm
and
for c
ontr
ol o
pera
tion
On
(1)
Off
(0)
187
Cle
ar la
tche
d in
put 1
. Tur
ning
this
con
trol o
n w
ill fo
rce
the
Pro
con
V D
igita
l Inp
ut 1
(Obj
ect 0
1, In
dex
947)
to th
stat
e of
the
asso
ciat
ed p
hysi
cal i
nput
. Tur
ning
this
con
trol o
ff ha
s no
effe
ct. W
hen
read
, the
last
con
trol a
ttem
pt
is re
turn
ed (0
= o
ff, 1
= o
n).
N/A
N/A
188
Cle
ar la
tche
d in
put 1
. Tur
ning
this
con
trol o
n w
ill fo
rce
the
Pro
con
V D
igita
l Inp
ut 1
(Obj
ect 0
1, In
dex
948)
to t h
stat
e of
the
asso
ciat
ed p
hysi
cal i
nput
. Tur
ning
this
con
trol o
ff ha
s no
effe
ct. W
hen
read
, the
last
con
trol a
ttem
pt
is re
turn
ed (0
= o
ff, 1
= o
n).
N/A
N/A
189
Cle
ar la
tche
d in
put 1
. Tur
ning
this
con
trol o
n w
ill fo
rce
the
Pro
con
V D
igita
l Inp
ut 1
(Obj
ect 0
1, In
dex
949)
to t h
stat
e of
the
asso
ciat
ed p
hysi
cal i
nput
. Tur
ning
this
con
trol o
ff ha
s no
effe
ct. W
hen
read
, the
last
con
trol a
ttem
pt
is re
turn
ed (0
= o
ff, 1
= o
n).
N/A
N/A
190
Cle
ar la
tche
d in
put 1
. Tur
ning
this
con
trol o
n w
ill fo
rce
the
Pro
con
V D
igita
l Inp
ut 1
(Obj
ect 0
1, In
dex
950)
to t h
stat
e of
the
asso
ciat
ed p
hysi
cal i
nput
. Tur
ning
this
con
trol o
ff ha
s no
effe
ct. W
hen
read
, the
last
con
trol a
ttem
pt
is re
turn
ed (0
= o
ff, 1
= o
n).
N/A
N/A
191
Cle
ar la
tche
d in
put 1
. Tur
ning
this
con
trol o
n w
ill fo
rce
the
Pro
con
V D
igita
l Inp
ut 1
(Obj
ect 0
1, In
dex
951)
to t h
stat
e of
the
asso
ciat
ed p
hysi
cal i
nput
. Tur
ning
this
con
trol o
ff ha
s no
effe
ct. W
hen
read
, the
last
con
trol a
ttem
pt
is re
turn
ed (0
= o
ff, 1
= o
n).
N/A
N/A
192
Cle
ar la
tche
d in
put 1
. Tur
ning
this
con
trol o
n w
ill fo
rce
the
Pro
con
V D
igita
l Inp
ut 1
(Obj
ect 0
1, In
dex
952)
to t h
stat
e of
the
asso
ciat
ed p
hysi
cal i
nput
. Tur
ning
this
con
trol o
ff ha
s no
effe
ct. W
hen
read
, the
last
con
trol a
ttem
pt
is re
turn
ed (0
= o
ff, 1
= o
n).
N/A
N/A
193
Res
erve
d19
4R
eser
ved
195
Pro
con
Res
et. T
urni
ng th
is o
n w
ill fo
rce
the
Pro
con
V p
roto
col c
onve
rter t
o re
star
t.N
/AN
/A
Pag
e 44
Out
put C
oils
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Reg
iste
r: 1
6 bi
t reg
sist
er (r
ead
only
)In
dex
Des
crip
tion
Mul
titro
de C
ross
-Ref
eren
ceVa
riabl
e
1R
eser
vevd
Mem
ory:
0x0
002
2C
urre
nt li
quid
leve
l as
an A
SC
II va
lue
betw
een
0 an
d 20
0 (0
0hex
to C
8hex
).st
atus
_qui
ck[0
]3
Cur
rent
val
ue o
f mas
ter M
onito
rPR
O's
ana
log
inpu
t 1. T
his
valu
e is
sca
led
to b
e be
twee
n 0
and
200
(00
hex
to C
8 he
x). T
he v
alue
is li
mite
d to
20
mA
ie. 2
00 (C
8 he
x).
stat
us_a
na[0
][0]
4C
urre
nt v
alue
of m
aste
r Mon
itorP
RO
's a
nalo
g in
put 2
. Thi
s va
lue
is s
cale
d to
be
betw
een
0 an
d 20
0 (0
0 he
x to
C8
hex)
. The
val
ue is
lim
ited
to 2
0 m
A ie
. 200
(C8
hex)
.st
atus
_ana
[0][1
]
5C
urre
nt v
alue
of m
aste
r Mon
itorP
RO
's in
com
ing
DC
sup
ply
volta
ge. T
his
valu
e is
sca
led
to b
e be
twee
n 0
and
200
(00
hex
to C
8 he
x). T
he v
alue
is li
mite
d to
20
mA
ie
. 200
(C8
hex)
.st
atus
_ana
[0][2
]
6C
urre
nt v
alue
of m
aste
r Mon
itorP
RO
's in
com
ing
DC
sup
ply
volta
ge. T
his
valu
e is
sca
led
to b
e be
twee
n 0
and
200
(00
hex
to C
8 he
x). W
hen
the
Mon
itorP
RO
's
anal
og o
utpu
tis c
onfig
ured
to tr
ansm
it th
e "c
urre
nt le
vel"
then
zer
o le
vel w
ill b
e 4m
A a
nd th
is p
oint
will
sho
w 4
0 (2
8 he
x) w
hile
100
% le
vel w
ould
be
20m
A a
nd s
how
10
0 (C
8 he
x).
stat
us_a
na[0
][3]
7R
eser
ved
stat
us_a
na[0
][4]
8C
urre
nt R
AW
val
ue o
f mas
ter M
onito
rPR
O's
ana
log
inpu
t 1. T
his
valu
e is
NO
T sc
aled
to b
e be
twee
n 0
and
6553
5 (0
000
hex
to F
FFF
hex)
. The
val
ue is
lim
ited
to
21.1
mA
ie. (
FF00
hex
) whe
re 3
30 c
ount
s =
0.1
mA
.st
atus
_ana
[0][5
]
9C
urre
nt R
AW
val
ue o
f mas
ter M
onito
rPR
O's
ana
log
inpu
t 2. T
his
valu
e is
NO
T sc
aled
to b
e be
twee
n 0
and
6553
5 (0
000
hex
to F
FFF
hex)
. The
val
ue is
lim
ited
to
21.1
mA
ie. (
FF00
hex
) whe
re 3
30 c
ount
s =
0.1
mA
.st
atus
_ana
[0][6
]
10C
urre
nt v
alue
of s
lave
1 M
onito
rPR
O's
ana
log
inpu
t 1. T
his
valu
e is
sca
led
to b
e be
twee
n 0
and
200
(00
hex
to C
8 he
x). T
he v
alue
is li
mite
d to
20
mA
ie. 2
00 (C
8 he
x).
stat
us_a
na[1
][0]
11C
urre
nt v
alue
of s
lave
1 M
onito
rPR
O's
ana
log
inpu
t 2. T
his
valu
e is
sca
led
to b
e be
twee
n 0
and
200
(00
hex
to C
8 he
x). T
he v
alue
is li
mite
d to
20
mA
ie. 2
00 (C
8 he
x).
stat
us_a
na[1
][1]
12C
urre
nt v
alue
of s
lave
1 M
onito
rPR
O's
inco
min
g D
C s
uppl
y vo
ltage
. Thi
s va
lue
is s
cale
d to
be
betw
een
0 an
d 20
0 (0
0 he
x to
C8
hex)
. The
val
ue is
lim
ited
to 2
0 m
A
ie. 2
00 (C
8 he
x).
stat
us_a
na[1
][2]
13C
urre
nt v
alue
of s
lave
1 M
onito
rPR
O's
inco
min
g D
C s
uppl
y vo
ltage
. Thi
s va
lue
is s
cale
d to
be
betw
een
0 an
d 20
0 (0
0 he
x to
C8
hex)
. Whe
n th
e M
onito
rPR
O's
an
alog
out
putis
con
figur
ed to
tran
smit
the
"cur
rent
leve
l" th
en z
ero
leve
l will
be
4mA
and
this
poi
nt w
ill s
how
40
(28
hex)
whi
le 1
00%
leve
l wou
ld b
e 20
mA
and
sho
w
100
(C8
hex)
.
stat
us_a
na[1
][3]
14R
eser
ved
stat
us_a
na[1
][4]
15C
urre
nt R
AW
val
ue o
f sla
ve 1
Mon
itorP
RO
's a
nalo
g in
put 1
. Thi
s va
lue
is N
OT
scal
ed to
be
betw
een
0 an
d 65
535
(000
0 he
x to
FFF
F he
x). T
he v
alue
is li
mite
d to
21
.1 m
A ie
. (FF
00 h
ex) w
here
330
cou
nts
= 0.
1 m
A.
stat
us_a
na[1
][5]
16C
urre
nt R
AW
val
ue o
f sla
ve 1
Mon
itorP
RO
's a
nalo
g in
put 2
. Thi
s va
lue
is N
OT
scal
ed to
be
betw
een
0 an
d 65
535
(000
0 he
x to
FFF
F he
x). T
he v
alue
is li
mite
d to
21
.1 m
A ie
. (FF
00 h
ex) w
here
330
cou
nts
= 0.
1 m
A.
stat
us_a
na[1
][6]
17C
urre
nt v
alue
of s
lave
2 M
onito
rPR
O's
ana
log
inpu
t 1. T
his
valu
e is
sca
led
to b
e be
twee
n 0
and
200
(00
hex
to C
8 he
x). T
he v
alue
is li
mite
d to
20
mA
ie. 2
00 (C
8 he
x).
stat
us_a
na[2
][0]
18C
urre
nt v
alue
of s
lave
2 M
onito
rPR
O's
ana
log
inpu
t 2. T
his
valu
e is
sca
led
to b
e be
twee
n 0
and
200
(00
hex
to C
8 he
x). T
he v
alue
is li
mite
d to
20
mA
ie. 2
00 (C
8 he
x).
stat
us_a
na[2
][1]
19C
urre
nt v
alue
of s
lave
2 M
onito
rPR
O's
inco
min
g D
C s
uppl
y vo
ltage
. Thi
s va
lue
is s
cale
d to
be
betw
een
0 an
d 20
0 (0
0 he
x to
C8
hex)
. The
val
ue is
lim
ited
to 2
0 m
A
ie. 2
00 (C
8 he
x).
stat
us_a
na[2
][2]
20C
urre
nt v
alue
of s
lave
2 M
onito
rPR
O's
inco
min
g D
C s
uppl
y vo
ltage
. Thi
s va
lue
is s
cale
d to
be
betw
een
0 an
d 20
0 (0
0 he
x to
C8
hex)
. Whe
n th
e M
onito
rPR
O's
an
alog
out
putis
con
figur
ed to
tran
smit
the
"cur
rent
leve
l" th
en z
ero
leve
l will
be
4mA
and
this
poi
nt w
ill s
how
40
(28
hex)
whi
le 1
00%
leve
l wou
ld b
e 20
mA
and
sho
w
100
(C8
hex)
.
stat
us_a
na[2
][3]
21R
eser
ved
stat
us_a
na[2
][4]
22C
urre
nt R
AW
val
ue o
f sla
ve 2
Mon
itorP
RO
's a
nalo
g in
put 1
. Thi
s va
lue
is N
OT
scal
ed to
be
betw
een
0 an
d 65
535
(000
0 he
x to
FFF
F he
x). T
he v
alue
is li
mite
d to
21
.1 m
A ie
. (FF
00 h
ex) w
here
330
cou
nts
= 0.
1 m
A.
stat
us_a
na[2
][5]
Pag
e 45
Inpu
t Reg
iste
rs
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Reg
iste
r: 1
6 bi
t reg
sist
er (r
ead
only
)In
dex
Des
crip
tion
Mul
titro
de C
ross
-Ref
eren
ceVa
riabl
e
23C
urre
nt R
AW
val
ue o
f sla
ve 2
Mon
itorP
RO
's a
nalo
g in
put 2
. Thi
s va
lue
is N
OT
scal
ed to
be
betw
een
0 an
d 65
535
(000
0 he
x to
FFF
F he
x). T
he v
alue
is li
mite
d to
21
.1 m
A ie
. (FF
00 h
ex) w
here
330
cou
nts
= 0.
1 m
A.
stat
us_a
na[2
][6]
24P
rese
nt v
alue
of c
urre
nt o
n re
d [L
1] p
hase
of p
ump
1. S
calin
g is
0.1
A p
er b
it co
unt (
eg. 0
00A
hex
= 1
.0A
, 000
B h
ex =
1.1
A).
Sta
tus_
num
eric
[0][0
]25
Pre
sent
val
ue o
f cur
rent
on
whi
te [L
2] p
hase
of p
ump
1. S
calin
g is
0.1
A p
er b
it co
unt (
eg. 0
00A
hex
= 1
.0A
, 000
B h
ex =
1.1
A).
Sta
tus_
num
eric
[0][1
]26
Pre
sent
val
ue o
f cur
rent
on
blue
[L3]
pha
se o
f pum
p 1.
Sca
ling
is 0
.1A
per
bit
coun
t (eg
. 000
A h
ex =
1.0
A, 0
00B
hex
= 1
.1A
).S
tatu
s_nu
mer
ic[0
][2]
27A
vera
ge v
alue
of c
urre
nt o
n al
l 3 p
hase
s of
pum
p 1.
Sca
ling
is 0
.1A
per
bit
coun
t (eg
. 000
A h
ex =
1.0
A, 0
00B
hex
= 1
.1A
).S
tatu
s_nu
mer
ic[0
][3]
28To
tal f
low
vol
ume
of p
ump
1. S
calin
g is
100
0 lit
ers
per b
it co
unt (
eg. 0
00A
hex
= 1
0kL,
000
B h
ex =
11k
L).
Sta
tus_
num
eric
[0][4
]29
Last
flow
vol
ume
of p
ump
1. S
calin
g is
1 li
ter p
er b
it co
unt (
eg. 0
00A
hex
= 1
0L, 0
00B
hex
= 1
1L).
Sta
tus_
num
eric
[0][5
]30
Res
erve
dS
tatu
s_nu
mer
ic[0
][6]
31H
ours
last
run
of p
ump
1. S
calin
g is
0.1
lite
r per
bit
coun
t (eg
. 000
A h
ex =
1m
in, 0
00B
hex
= 1
.1m
in).
Sta
tus_
num
eric
[0][7
]32
Sta
rts p
er h
our o
f pum
p 1.
Sca
ling
is 1
sta
rt pe
r 10
bit c
ount
s (e
g. 0
00A
hex
= 1
star
t/hou
r, 00
0B h
ex =
not
pos
sibl
e).
Sta
tus_
num
eric
[0][8
]33
Last
flow
rate
of p
ump
1. S
calin
g is
sec
onds
per
litre
(eg.
000
A h
ex =
10
L/s,
000
B h
ex =
11L
/s).
Sta
tus_
num
eric
[0][9
]34
Insu
latio
n re
sist
ance
of p
ump
1. S
calin
g is
0.1
Moh
m p
er b
it co
unt (
eg. 0
00A
hex
= 1
Moh
m, 0
00B
hex
= 1
.1 M
ohm
).S
tatu
s_nu
mer
ic[0
][10]
35P
hase
vol
tage
of p
ump
1. S
calin
g is
0.1
vol
ts p
er b
it co
unt (
eg. 0
00A
hex
= 1
VA
C, 0
00B
hex
= 1
.1 V
AC
).S
tatu
s_nu
mer
ic[0
][11]
36A
vera
ge p
hase
vol
tage
of p
ump
1. S
calin
g is
0.1
vol
ts p
er b
it co
unt (
eg. 0
00A
hex
= 1
VA
C, 0
00B
hex
= 1
.1 V
AC
).S
tatu
s_nu
mer
ic[0
][12]
37P
rese
nt v
alue
of c
urre
nt o
n re
d [L
1] p
hase
of p
ump
1. S
calin
g is
0.1
A p
er b
it co
unt (
eg. 0
00A
hex
= 1
.0A
, 000
B h
ex =
1.1
A).
Sta
tus_
num
eric
[1][0
]38
Pre
sent
val
ue o
f cur
rent
on
whi
te [L
2] p
hase
of p
ump
1. S
calin
g is
0.1
A p
er b
it co
unt (
eg. 0
00A
hex
= 1
.0A
, 000
B h
ex =
1.1
A).
Sta
tus_
num
eric
[1][1
]39
Pre
sent
val
ue o
f cur
rent
on
blue
[L3]
pha
se o
f pum
p 2.
Sca
ling
is 0
.1A
per
bit
coun
t (eg
. 000
A h
ex =
1.0
A, 0
00B
hex
= 1
.1A
).S
tatu
s_nu
mer
ic[1
][2]
40A
vera
ge v
alue
of c
urre
nt o
n al
l 3 p
hase
s of
pum
p 2.
Sca
ling
is 0
.1A
per
bit
coun
t (eg
. 000
A h
ex =
1.0
A, 0
00B
hex
= 1
.1A
).S
tatu
s_nu
mer
ic[1
][3]
41To
tal f
low
vol
ume
of p
ump
2. S
calin
g is
100
0 lit
ers
per b
it co
unt (
eg. 0
00A
hex
= 1
0kL,
000
B h
ex =
11k
L).
Sta
tus_
num
eric
[1][4
]42
Last
flow
vol
ume
of p
ump
2. S
calin
g is
1 li
ter p
er b
it co
unt (
eg. 0
00A
hex
= 1
0L, 0
00B
hex
= 1
1L).
Sta
tus_
num
eric
[1][5
]43
Res
erve
dS
tatu
s_nu
mer
ic[1
][6]
44H
ours
last
run
of p
ump
2. S
calin
g is
0.1
lite
r per
bit
coun
t (eg
. 000
A h
ex =
1m
in, 0
00B
hex
= 1
.1m
in).
Sta
tus_
num
eric
[1][7
]45
Sta
rts p
er h
our o
f pum
p 2.
Sca
ling
is 1
sta
rt pe
r 10
bit c
ount
s (e
g. 0
00A
hex
= 1
star
t/hou
r, 00
0B h
ex =
not
pos
sibl
e).
Sta
tus_
num
eric
[1][8
]46
Last
flow
rate
of p
ump
2. S
calin
g is
sec
onds
per
litre
(eg.
000
A h
ex =
10
L/s,
000
B h
ex =
11L
/s).
Sta
tus_
num
eric
[1][9
]47
Insu
latio
n re
sist
ance
of p
ump
2. S
calin
g is
0.1
Moh
m p
er b
it co
unt (
eg. 0
00A
hex
= 1
Moh
m, 0
00B
hex
= 1
.1 M
ohm
).S
tatu
s_nu
mer
ic[1
][10]
48P
hase
vol
tage
of p
ump
2. S
calin
g is
0.1
vol
ts p
er b
it co
unt (
eg. 0
00A
hex
= 1
VA
C, 0
00B
hex
= 1
.1 V
AC
).S
tatu
s_nu
mer
ic[1
][11]
49A
vera
ge p
hase
vol
tage
of p
ump
2. S
calin
g is
0.1
vol
ts p
er b
it co
unt (
eg. 0
00A
hex
= 1
VA
C, 0
00B
hex
= 1
.1 V
AC
).S
tatu
s_nu
mer
ic[1
][12]
50P
rese
nt v
alue
of c
urre
nt o
n re
d [L
1] p
hase
of p
ump
3. S
calin
g is
0.1
A p
er b
it co
unt (
eg. 0
00A
hex
= 1
.0A
, 000
B h
ex =
1.1
A).
Sta
tus_
num
eric
[2][0
]51
Pre
sent
val
ue o
f cur
rent
on
whi
te [L
2] p
hase
of p
ump
3. S
calin
g is
0.1
A p
er b
it co
unt (
eg. 0
00A
hex
= 1
.0A
, 000
B h
ex =
1.1
A).
Sta
tus_
num
eric
[2][1
]52
Pre
sent
val
ue o
f cur
rent
on
blue
[L3]
pha
se o
f pum
p 3.
Sca
ling
is 0
.1A
per
bit
coun
t (eg
. 000
A h
ex =
1.0
A, 0
00B
hex
= 1
.1A
).S
tatu
s_nu
mer
ic[2
][2]
53A
vera
ge v
alue
of c
urre
nt o
n al
l 3 p
hase
s of
pum
p 3.
Sca
ling
is 0
.1A
per
bit
coun
t (eg
. 000
A h
ex =
1.0
A, 0
00B
hex
= 1
.1A
).S
tatu
s_nu
mer
ic[2
][3]
54To
tal f
low
vol
ume
of p
ump
3. S
calin
g is
100
0 lit
ers
per b
it co
unt (
eg. 0
00A
hex
= 1
0kL,
000
B h
ex =
11k
L).
Sta
tus_
num
eric
[2][4
]55
Last
flow
vol
ume
of p
ump
3. S
calin
g is
1 li
ter p
er b
it co
unt (
eg. 0
00A
hex
= 1
0L, 0
00B
hex
= 1
1L).
Sta
tus_
num
eric
[2][5
]56
Res
erve
dS
tatu
s_nu
mer
ic[2
][6]
57H
ours
last
run
of p
ump
3. S
calin
g is
0.1
lite
r per
bit
coun
t (eg
. 000
A h
ex =
1m
in, 0
00B
hex
= 1
.1m
in).
Sta
tus_
num
eric
[2][7
]58
Sta
rts p
er h
our o
f pum
p 3.
Sca
ling
is 1
sta
rt pe
r 10
bit c
ount
s (e
g. 0
00A
hex
= 1
star
t/hou
r, 00
0B h
ex =
not
pos
sibl
e).
Sta
tus_
num
eric
[2][8
]59
Last
flow
rate
of p
ump
3. S
calin
g is
sec
onds
per
litre
(eg.
000
A h
ex =
10
L/s,
000
B h
ex =
11L
/s).
Sta
tus_
num
eric
[2][9
]60
Insu
latio
n re
sist
ance
of p
ump
3. S
calin
g is
0.1
Moh
m p
er b
it co
unt (
eg. 0
00A
hex
= 1
Moh
m, 0
00B
hex
= 1
.1 M
ohm
).S
tatu
s_nu
mer
ic[2
][10]
61P
hase
vol
tage
of p
ump
3. S
calin
g is
0.1
vol
ts p
er b
it co
unt (
eg. 0
00A
hex
= 1
VA
C, 0
00B
hex
= 1
.1 V
AC
).S
tatu
s_nu
mer
ic[2
][11]
62A
vera
ge p
hase
vol
tage
of p
ump
3. S
calin
g is
0.1
vol
ts p
er b
it co
unt (
eg. 0
00A
hex
= 1
VA
C, 0
00B
hex
= 1
.1 V
AC
).S
tatu
s_nu
mer
ic[2
][12]
63P
rese
nt v
alue
of c
urre
nt o
n re
d [L
1] p
hase
of p
ump
4. S
calin
g is
0.1
A p
er b
it co
unt (
eg. 0
00A
hex
= 1
.0A
, 000
B h
ex =
1.1
A).
Sta
tus_
num
eric
[3][0
]
Pag
e 46
Inpu
t Reg
iste
rs
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Reg
iste
r: 1
6 bi
t reg
sist
er (r
ead
only
)In
dex
Des
crip
tion
Mul
titro
de C
ross
-Ref
eren
ceVa
riabl
e
64P
rese
nt v
alue
of c
urre
nt o
n w
hite
[L2]
pha
se o
f pum
p 4.
Sca
ling
is 0
.1A
per
bit
coun
t (eg
. 000
A h
ex =
1.0
A, 0
00B
hex
= 1
.1A
).S
tatu
s_nu
mer
ic[3
][1]
65P
rese
nt v
alue
of c
urre
nt o
n bl
ue [L
3] p
hase
of p
ump
4. S
calin
g is
0.1
A p
er b
it co
unt (
eg. 0
00A
hex
= 1
.0A
, 000
B h
ex =
1.1
A).
Sta
tus_
num
eric
[3][2
]66
Ave
rage
val
ue o
f cur
rent
on
all 3
pha
ses
of p
ump
4. S
calin
g is
0.1
A p
er b
it co
unt (
eg. 0
00A
hex
= 1
.0A
, 000
B h
ex =
1.1
A).
Sta
tus_
num
eric
[3][3
]67
Tota
l flo
w v
olum
e of
pum
p 4.
Sca
ling
is 1
000
liter
s pe
r bit
coun
t (eg
. 000
A h
ex =
10k
L, 0
00B
hex
= 1
1kL)
.S
tatu
s_nu
mer
ic[3
][4]
68La
st fl
ow v
olum
e of
pum
p 4.
Sca
ling
is 1
lite
r per
bit
coun
t (eg
. 000
A h
ex =
10L
, 000
B h
ex =
11L
).S
tatu
s_nu
mer
ic[3
][5]
69R
eser
ved
Sta
tus_
num
eric
[3][6
]70
Hou
rs la
st ru
n of
pum
p 4.
Sca
ling
is 0
.1 li
ter p
er b
it co
unt (
eg. 0
00A
hex
= 1
min
, 000
B h
ex =
1.1
min
).S
tatu
s_nu
mer
ic[3
][7]
71S
tarts
per
hou
r of p
ump
4. S
calin
g is
1 s
tart
per 1
0 bi
t cou
nts
(eg.
000
A h
ex =
1st
art/h
our,
000B
hex
= n
ot p
ossi
ble)
.S
tatu
s_nu
mer
ic[3
][8]
72La
st fl
ow ra
te o
f pum
p 4.
Sca
ling
is s
econ
ds p
er li
tre (e
g. 0
00A
hex
= 1
0 L/
s, 0
00B
hex
= 1
1L/s
).S
tatu
s_nu
mer
ic[3
][9]
73In
sula
tion
resi
stan
ce o
f pum
p 4.
Sca
ling
is 0
.1 M
ohm
per
bit
coun
t (eg
. 000
A h
ex =
1 M
ohm
, 000
B h
ex =
1.1
Moh
m).
Sta
tus_
num
eric
[3][1
0]74
Pha
se v
olta
ge o
f pum
p 4.
Sca
ling
is 0
.1 v
olts
per
bit
coun
t (eg
. 000
A h
ex =
1 V
AC
, 000
B h
ex =
1.1
VA
C).
Sta
tus_
num
eric
[3][1
1]75
Ave
rage
pha
se v
olta
ge o
f pum
p 4.
Sca
ling
is 0
.1 v
olts
per
bit
coun
t (eg
. 000
A h
ex =
1 V
AC
, 000
B h
ex =
1.1
VA
C).
Sta
tus_
num
eric
[3][1
2]76
Pre
sent
val
ue o
f cur
rent
on
red
[L1]
pha
se o
f pum
p 5.
Sca
ling
is 0
.1A
per
bit
coun
t (eg
. 000
A h
ex =
1.0
A, 0
00B
hex
= 1
.1A
).S
tatu
s_nu
mer
ic[4
][0]
77P
rese
nt v
alue
of c
urre
nt o
n w
hite
[L2]
pha
se o
f pum
p 5.
Sca
ling
is 0
.1A
per
bit
coun
t (eg
. 000
A h
ex =
1.0
A, 0
00B
hex
= 1
.1A
).S
tatu
s_nu
mer
ic[4
][1]
78P
rese
nt v
alue
of c
urre
nt o
n bl
ue [L
3] p
hase
of p
ump
5. S
calin
g is
0.1
A p
er b
it co
unt (
eg. 0
00A
hex
= 1
.0A
, 000
B h
ex =
1.1
A).
Sta
tus_
num
eric
[4][2
]79
Ave
rage
val
ue o
f cur
rent
on
all 3
pha
ses
of p
ump
5. S
calin
g is
0.1
A p
er b
it co
unt (
eg. 0
00A
hex
= 1
.0A
, 000
B h
ex =
1.1
A).
Sta
tus_
num
eric
[4][3
]80
Tota
l flo
w v
olum
e of
pum
p 5.
Sca
ling
is 1
000
liter
s pe
r bit
coun
t (eg
. 000
A h
ex =
10k
L, 0
00B
hex
= 1
1kL)
.S
tatu
s_nu
mer
ic[4
][4]
81La
st fl
ow v
olum
e of
pum
p 5.
Sca
ling
is 1
lite
r per
bit
coun
t (eg
. 000
A h
ex =
10L
, 000
B h
ex =
11L
).S
tatu
s_nu
mer
ic[4
][5]
82R
eser
ved
Sta
tus_
num
eric
[4][6
]83
Hou
rs la
st ru
n of
pum
p 5.
Sca
ling
is 0
.1 li
ter p
er b
it co
unt (
eg. 0
00A
hex
= 1
min
, 000
B h
ex =
1.1
min
).S
tatu
s_nu
mer
ic[4
][7]
84S
tarts
per
hou
r of p
ump
5. S
calin
g is
1 s
tart
per 1
0 bi
t cou
nts
(eg.
000
A h
ex =
1st
art/h
our,
000B
hex
= n
ot p
ossi
ble)
.S
tatu
s_nu
mer
ic[4
][8]
85La
st fl
ow ra
te o
f pum
p 5.
Sca
ling
is s
econ
ds p
er li
tre (e
g. 0
00A
hex
= 1
0 L/
s, 0
00B
hex
= 1
1L/s
).S
tatu
s_nu
mer
ic[4
][9]
86In
sula
tion
resi
stan
ce o
f pum
p 5.
Sca
ling
is 0
.1 M
ohm
per
bit
coun
t (eg
. 000
A h
ex =
1 M
ohm
, 000
B h
ex =
1.1
Moh
m).
Sta
tus_
num
eric
[4][1
0]87
Pha
se v
olta
ge o
f pum
p 5.
Sca
ling
is 0
.1 v
olts
per
bit
coun
t (eg
. 000
A h
ex =
1 V
AC
, 000
B h
ex =
1.1
VA
C).
Sta
tus_
num
eric
[4][1
1]88
Ave
rage
pha
se v
olta
ge o
f pum
p 5.
Sca
ling
is 0
.1 v
olts
per
bit
coun
t (eg
. 000
A h
ex =
1 V
AC
, 000
B h
ex =
1.1
VA
C).
Sta
tus_
num
eric
[4][1
2]89
Pre
sent
val
ue o
f cur
rent
on
red
[L1]
pha
se o
f pum
p 6.
Sca
ling
is 0
.1A
per
bit
coun
t (eg
. 000
A h
ex =
1.0
A, 0
00B
hex
= 1
.1A
).S
tatu
s_nu
mer
ic[5
][0]
90P
rese
nt v
alue
of c
urre
nt o
n w
hite
[L2]
pha
se o
f pum
p 6.
Sca
ling
is 0
.1A
per
bit
coun
t (eg
. 000
A h
ex =
1.0
A, 0
00B
hex
= 1
.1A
).S
tatu
s_nu
mer
ic[5
][1]
91P
rese
nt v
alue
of c
urre
nt o
n bl
ue [L
3] p
hase
of p
ump
6. S
calin
g is
0.1
A p
er b
it co
unt (
eg. 0
00A
hex
= 1
.0A
, 000
B h
ex =
1.1
A).
Sta
tus_
num
eric
[5][2
]92
Ave
rage
val
ue o
f cur
rent
on
all 3
pha
ses
of p
ump
6. S
calin
g is
0.1
A p
er b
it co
unt (
eg. 0
00A
hex
= 1
.0A
, 000
B h
ex =
1.1
A).
Sta
tus_
num
eric
[5][3
]93
Tota
l flo
w v
olum
e of
pum
p 6.
Sca
ling
is 1
000
liter
s pe
r bit
coun
t (eg
. 000
A h
ex =
10k
L, 0
00B
hex
= 1
1kL)
.S
tatu
s_nu
mer
ic[5
][4]
94La
st fl
ow v
olum
e of
pum
p 6.
Sca
ling
is 1
lite
r per
bit
coun
t (eg
. 000
A h
ex =
10L
, 000
B h
ex =
11L
).S
tatu
s_nu
mer
ic[5
][5]
95R
eser
ved
Sta
tus_
num
eric
[5][6
]96
Hou
rs la
st ru
n of
pum
p 6.
Sca
ling
is 0
.1 li
ter p
er b
it co
unt (
eg. 0
00A
hex
= 1
min
, 000
B h
ex =
1.1
min
).S
tatu
s_nu
mer
ic[5
][7]
97S
tarts
per
hou
r of p
ump
6. S
calin
g is
1 s
tart
per 1
0 bi
t cou
nts
(eg.
000
A h
ex =
1st
art/h
our,
000B
hex
= n
ot p
ossi
ble)
.S
tatu
s_nu
mer
ic[5
][8]
98La
st fl
ow ra
te o
f pum
p 6.
Sca
ling
is s
econ
ds p
er li
tre (e
g. 0
00A
hex
= 1
0 L/
s, 0
00B
hex
= 1
1L/s
).S
tatu
s_nu
mer
ic[5
][9]
99In
sula
tion
resi
stan
ce o
f pum
p 6.
Sca
ling
is 0
.1 M
ohm
per
bit
coun
t (eg
. 000
A h
ex =
1 M
ohm
, 000
B h
ex =
1.1
Moh
m).
Sta
tus_
num
eric
[5][1
0]10
0P
hase
vol
tage
of p
ump
6. S
calin
g is
0.1
vol
ts p
er b
it co
unt (
eg. 0
00A
hex
= 1
VA
C, 0
00B
hex
= 1
.1 V
AC
).S
tatu
s_nu
mer
ic[5
][11]
101
Ave
rage
pha
se v
olta
ge o
f pum
p 6.
Sca
ling
is 0
.1 v
olts
per
bit
coun
t (eg
. 000
A h
ex =
1 V
AC
, 000
B h
ex =
1.1
VA
C).
Sta
tus_
num
eric
[5][1
2]10
2P
rese
nt v
alue
of c
urre
nt o
n re
d [L
1] p
hase
of p
ump
7. S
calin
g is
0.1
A p
er b
it co
unt (
eg. 0
00A
hex
= 1
.0A
, 000
B h
ex =
1.1
A).
Sta
tus_
num
eric
[6][0
]10
3P
rese
nt v
alue
of c
urre
nt o
n w
hite
[L2]
pha
se o
f pum
p 7.
Sca
ling
is 0
.1A
per
bit
coun
t (eg
. 000
A h
ex =
1.0
A, 0
00B
hex
= 1
.1A
).S
tatu
s_nu
mer
ic[6
][1]
104
Pre
sent
val
ue o
f cur
rent
on
blue
[L3]
pha
se o
f pum
p 7.
Sca
ling
is 0
.1A
per
bit
coun
t (eg
. 000
A h
ex =
1.0
A, 0
00B
hex
= 1
.1A
).S
tatu
s_nu
mer
ic[6
][2]
105
Ave
rage
val
ue o
f cur
rent
on
all 3
pha
ses
of p
ump
7. S
calin
g is
0.1
A p
er b
it co
unt (
eg. 0
00A
hex
= 1
.0A
, 000
B h
ex =
1.1
A).
Sta
tus_
num
eric
[6][3
]
Pag
e 47
Inpu
t Reg
iste
rs
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Reg
iste
r: 1
6 bi
t reg
sist
er (r
ead
only
)In
dex
Des
crip
tion
Mul
titro
de C
ross
-Ref
eren
ceVa
riabl
e
106
Tota
l flo
w v
olum
e of
pum
p 7.
Sca
ling
is 1
000
liter
s pe
r bit
coun
t (eg
. 000
A h
ex =
10k
L, 0
00B
hex
= 1
1kL)
.S
tatu
s_nu
mer
ic[6
][4]
107
Last
flow
vol
ume
of p
ump
7. S
calin
g is
1 li
ter p
er b
it co
unt (
eg. 0
00A
hex
= 1
0L, 0
00B
hex
= 1
1L).
Sta
tus_
num
eric
[6][5
]10
8R
eser
ved
Sta
tus_
num
eric
[6][6
]10
9H
ours
last
run
of p
ump
7. S
calin
g is
0.1
lite
r per
bit
coun
t (eg
. 000
A h
ex =
1m
in, 0
00B
hex
= 1
.1m
in).
Sta
tus_
num
eric
[6][7
]11
0S
tarts
per
hou
r of p
ump
7. S
calin
g is
1 s
tart
per 1
0 bi
t cou
nts
(eg.
000
A h
ex =
1st
art/h
our,
000B
hex
= n
ot p
ossi
ble)
.S
tatu
s_nu
mer
ic[6
][8]
111
Last
flow
rate
of p
ump
7. S
calin
g is
sec
onds
per
litre
(eg.
000
A h
ex =
10
L/s,
000
B h
ex =
11L
/s).
Sta
tus_
num
eric
[6][9
]11
2In
sula
tion
resi
stan
ce o
f pum
p 7.
Sca
ling
is 0
.1 M
ohm
per
bit
coun
t (eg
. 000
A h
ex =
1 M
ohm
, 000
B h
ex =
1.1
Moh
m).
Sta
tus_
num
eric
[6][1
0]11
3P
hase
vol
tage
of p
ump
7. S
calin
g is
0.1
vol
ts p
er b
it co
unt (
eg. 0
00A
hex
= 1
VA
C, 0
00B
hex
= 1
.1 V
AC
).S
tatu
s_nu
mer
ic[6
][11]
114
Ave
rage
pha
se v
olta
ge o
f pum
p 7.
Sca
ling
is 0
.1 v
olts
per
bit
coun
t (eg
. 000
A h
ex =
1 V
AC
, 000
B h
ex =
1.1
VA
C).
Sta
tus_
num
eric
[6][1
2]11
5P
rese
nt v
alue
of c
urre
nt o
n re
d [L
1] p
hase
of p
ump
8. S
calin
g is
0.1
A p
er b
it co
unt (
eg. 0
00A
hex
= 1
.0A
, 000
B h
ex =
1.1
A).
Sta
tus_
num
eric
[7][0
]11
6P
rese
nt v
alue
of c
urre
nt o
n w
hite
[L2]
pha
se o
f pum
p 8.
Sca
ling
is 0
.1A
per
bit
coun
t (eg
. 000
A h
ex =
1.0
A, 0
00B
hex
= 1
.1A
).S
tatu
s_nu
mer
ic[7
][1]
117
Pre
sent
val
ue o
f cur
rent
on
blue
[L3]
pha
se o
f pum
p 8.
Sca
ling
is 0
.1A
per
bit
coun
t (eg
. 000
A h
ex =
1.0
A, 0
00B
hex
= 1
.1A
).S
tatu
s_nu
mer
ic[7
][2]
118
Ave
rage
val
ue o
f cur
rent
on
all 3
pha
ses
of p
ump
8. S
calin
g is
0.1
A p
er b
it co
unt (
eg. 0
00A
hex
= 1
.0A
, 000
B h
ex =
1.1
A).
Sta
tus_
num
eric
[7][3
]11
9To
tal f
low
vol
ume
of p
ump
8. S
calin
g is
100
0 lit
ers
per b
it co
unt (
eg. 0
00A
hex
= 1
0kL,
000
B h
ex =
11k
L).
Sta
tus_
num
eric
[7][4
]12
0La
st fl
ow v
olum
e of
pum
p 8.
Sca
ling
is 1
lite
r per
bit
coun
t (eg
. 000
A h
ex =
10L
, 000
B h
ex =
11L
).S
tatu
s_nu
mer
ic[7
][5]
121
Res
erve
dS
tatu
s_nu
mer
ic[7
][6]
122
Hou
rs la
st ru
n of
pum
p 8.
Sca
ling
is 0
.1 li
ter p
er b
it co
unt (
eg. 0
00A
hex
= 1
min
, 000
B h
ex =
1.1
min
).S
tatu
s_nu
mer
ic[7
][7]
123
Sta
rts p
er h
our o
f pum
p 8.
Sca
ling
is 1
sta
rt pe
r 10
bit c
ount
s (e
g. 0
00A
hex
= 1
star
t/hou
r, 00
0B h
ex =
not
pos
sibl
e).
Sta
tus_
num
eric
[7][8
]12
4La
st fl
ow ra
te o
f pum
p 8.
Sca
ling
is s
econ
ds p
er li
tre (e
g. 0
00A
hex
= 1
0 L/
s, 0
00B
hex
= 1
1L/s
).S
tatu
s_nu
mer
ic[7
][9]
125
Insu
latio
n re
sist
ance
of p
ump
8. S
calin
g is
0.1
Moh
m p
er b
it co
unt (
eg. 0
00A
hex
= 1
Moh
m, 0
00B
hex
= 1
.1 M
ohm
).S
tatu
s_nu
mer
ic[7
][10]
126
Pha
se v
olta
ge o
f pum
p 8.
Sca
ling
is 0
.1 v
olts
per
bit
coun
t (eg
. 000
A h
ex =
1 V
AC
, 000
B h
ex =
1.1
VA
C).
Sta
tus_
num
eric
[7][1
1]12
7A
vera
ge p
hase
vol
tage
of p
ump
8. S
calin
g is
0.1
vol
ts p
er b
it co
unt (
eg. 0
00A
hex
= 1
VA
C, 0
00B
hex
= 1
.1 V
AC
).S
tatu
s_nu
mer
ic[7
][12]
128
Pre
sent
val
ue o
f cur
rent
on
red
[L1]
pha
se o
f pum
p 9.
Sca
ling
is 0
.1A
per
bit
coun
t (eg
. 000
A h
ex =
1.0
A, 0
00B
hex
= 1
.1A
).S
tatu
s_nu
mer
ic[8
][0]
129
Pre
sent
val
ue o
f cur
rent
on
whi
te [L
2] p
hase
of p
ump
9. S
calin
g is
0.1
A p
er b
it co
unt (
eg. 0
00A
hex
= 1
.0A
, 000
B h
ex =
1.1
A).
Sta
tus_
num
eric
[8][1
]13
0P
rese
nt v
alue
of c
urre
nt o
n bl
ue [L
3] p
hase
of p
ump
9. S
calin
g is
0.1
A p
er b
it co
unt (
eg. 0
00A
hex
= 1
.0A
, 000
B h
ex =
1.1
A).
Sta
tus_
num
eric
[8][2
]13
1A
vera
ge v
alue
of c
urre
nt o
n al
l 3 p
hase
s of
pum
p 9.
Sca
ling
is 0
.1A
per
bit
coun
t (eg
. 000
A h
ex =
1.0
A, 0
00B
hex
= 1
.1A
).S
tatu
s_nu
mer
ic[8
][3]
132
Tota
l flo
w v
olum
e of
pum
p 9.
Sca
ling
is 1
000
liter
s pe
r bit
coun
t (eg
. 000
A h
ex =
10k
L, 0
00B
hex
= 1
1kL)
.S
tatu
s_nu
mer
ic[8
][4]
133
Last
flow
vol
ume
of p
ump
9. S
calin
g is
1 li
ter p
er b
it co
unt (
eg. 0
00A
hex
= 1
0L, 0
00B
hex
= 1
1L).
Sta
tus_
num
eric
[8][5
]13
4R
eser
ved
Sta
tus_
num
eric
[8][6
]13
5H
ours
last
run
of p
ump
9. S
calin
g is
0.1
lite
r per
bit
coun
t (eg
. 000
A h
ex =
1m
in, 0
00B
hex
= 1
.1m
in).
Sta
tus_
num
eric
[8][7
]13
6S
tarts
per
hou
r of p
ump
9. S
calin
g is
1 s
tart
per 1
0 bi
t cou
nts
(eg.
000
A h
ex =
1st
art/h
our,
000B
hex
= n
ot p
ossi
ble)
.S
tatu
s_nu
mer
ic[8
][8]
137
Last
flow
rate
of p
ump
9. S
calin
g is
sec
onds
per
litre
(eg.
000
A h
ex =
10
L/s,
000
B h
ex =
11L
/s).
Sta
tus_
num
eric
[8][9
]13
8In
sula
tion
resi
stan
ce o
f pum
p 9.
Sca
ling
is 0
.1 M
ohm
per
bit
coun
t (eg
. 000
A h
ex =
1 M
ohm
, 000
B h
ex =
1.1
Moh
m).
Sta
tus_
num
eric
[8][1
0]13
9P
hase
vol
tage
of p
ump
9. S
calin
g is
0.1
vol
ts p
er b
it co
unt (
eg. 0
00A
hex
= 1
VA
C, 0
00B
hex
= 1
.1 V
AC
).S
tatu
s_nu
mer
ic[8
][11]
140
Ave
rage
pha
se v
olta
ge o
f pum
p 9.
Sca
ling
is 0
.1 v
olts
per
bit
coun
t (eg
. 000
A h
ex =
1 V
AC
, 000
B h
ex =
1.1
VA
C).
Sta
tus_
num
eric
[8][1
2]14
1M
ost s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
tota
l fro
m d
igita
l inp
ut 1
of t
he m
aste
r Mon
itorP
RO
. Thi
s ac
cum
ulat
or n
eeds
to b
e en
able
d fo
r thi
s fe
atur
e.st
atus
_pul
sed[
0][0
] (16
:31)
142
Leas
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e to
tal f
rom
dig
ital i
nput
1 o
f the
mas
ter M
onito
rPR
O. T
his
accu
mul
ator
nee
ds to
be
enab
led
for t
his
feat
ure.
stat
us_p
ulse
d[0]
[0] (
0:15
)14
3M
ost s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
tota
l fro
m d
igita
l inp
ut 2
of t
he m
aste
r Mon
itorP
RO
. Thi
s ac
cum
ulat
or n
eeds
to b
e en
able
d fo
r thi
s fe
atur
e.st
atus
_pul
sed[
0][1
] (16
:31)
144
Leas
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e to
tal f
rom
dig
ital i
nput
2 o
f the
mas
ter M
onito
rPR
O. T
his
accu
mul
ator
nee
ds to
be
enab
led
for t
his
feat
ure.
stat
us_p
ulse
d[0]
[1] (
0:15
)14
5M
ost s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
tota
l fro
m d
igita
l inp
ut 3
of t
he m
aste
r Mon
itorP
RO
. Thi
s ac
cum
ulat
or n
eeds
to b
e en
able
d fo
r thi
s fe
atur
e.st
atus
_pul
sed[
0][2
] (16
:31)
146
Leas
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e to
tal f
rom
dig
ital i
nput
3 o
f the
mas
ter M
onito
rPR
O. T
his
accu
mul
ator
nee
ds to
be
enab
led
for t
his
feat
ure.
stat
us_p
ulse
d[0]
[2] (
0:15
)14
7M
ost s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
tota
l fro
m d
igita
l inp
ut 4
of t
he m
aste
r Mon
itorP
RO
. Thi
s ac
cum
ulat
or n
eeds
to b
e en
able
d fo
r thi
s fe
atur
e.st
atus
_pul
sed[
0][3
] (16
:31)
Pag
e 48
Inpu
t Reg
iste
rs
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Reg
iste
r: 1
6 bi
t reg
sist
er (r
ead
only
)In
dex
Des
crip
tion
Mul
titro
de C
ross
-Ref
eren
ceVa
riabl
e
148
Leas
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e to
tal f
rom
dig
ital i
nput
4 o
f the
mas
ter M
onito
rPR
O. T
his
accu
mul
ator
nee
ds to
be
enab
led
for t
his
feat
ure.
stat
us_p
ulse
d[0]
[3] (
0:15
)14
9M
ost s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
tota
l fro
m d
igita
l inp
ut 5
of t
he m
aste
r Mon
itorP
RO
. Thi
s ac
cum
ulat
or n
eeds
to b
e en
able
d fo
r thi
s fe
atur
e.st
atus
_pul
sed[
0][4
] (16
:31)
150
Leas
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e to
tal f
rom
dig
ital i
nput
5 o
f the
mas
ter M
onito
rPR
O. T
his
accu
mul
ator
nee
ds to
be
enab
led
for t
his
feat
ure.
stat
us_p
ulse
d[0]
[4] (
0:15
)15
1M
ost s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
tota
l fro
m d
igita
l inp
ut 6
of t
he m
aste
r Mon
itorP
RO
. Thi
s ac
cum
ulat
or n
eeds
to b
e en
able
d fo
r thi
s fe
atur
e.st
atus
_pul
sed[
0][5
] (16
:31)
152
Leas
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e to
tal f
rom
dig
ital i
nput
6 o
f the
mas
ter M
onito
rPR
O. T
his
accu
mul
ator
nee
ds to
be
enab
led
for t
his
feat
ure.
stat
us_p
ulse
d[0]
[5] (
0:15
)15
3M
ost s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
tota
l fro
m d
igita
l inp
ut 1
of t
he s
lave
1 M
onito
rPR
O. T
his
accu
mul
ator
nee
ds to
be
enab
led
for t
his
feat
ure.
stat
us_p
ulse
d[1]
[0] (
16:3
1)15
4Le
ast s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
tota
l fro
m d
igita
l inp
ut 1
of t
he s
lave
1 M
onito
rPR
O. T
his
accu
mul
ator
nee
ds to
be
enab
led
for t
his
feat
ure.
stat
us_p
ulse
d[1]
[0] (
0:15
)15
5M
ost s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
tota
l fro
m d
igita
l inp
ut 2
of t
he s
lave
1 M
onito
rPR
O. T
his
accu
mul
ator
nee
ds to
be
enab
led
for t
his
feat
ure.
stat
us_p
ulse
d[1]
[1] (
16:3
1)15
6Le
ast s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
tota
l fro
m d
igita
l inp
ut 2
of t
he s
lave
1 M
onito
rPR
O. T
his
accu
mul
ator
nee
ds to
be
enab
led
for t
his
feat
ure.
stat
us_p
ulse
d[1]
[1] (
0:15
)15
7M
ost s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
tota
l fro
m d
igita
l inp
ut 3
of t
he s
lave
1 M
onito
rPR
O. T
his
accu
mul
ator
nee
ds to
be
enab
led
for t
his
feat
ure.
stat
us_p
ulse
d[1]
[2] (
16:3
1)15
8Le
ast s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
tota
l fro
m d
igita
l inp
ut 3
of t
he s
lave
1 M
onito
rPR
O. T
his
accu
mul
ator
nee
ds to
be
enab
led
for t
his
feat
ure.
stat
us_p
ulse
d[1]
[2] (
0:15
)15
9M
ost s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
tota
l fro
m d
igita
l inp
ut 4
of t
he s
lave
1 M
onito
rPR
O. T
his
accu
mul
ator
nee
ds to
be
enab
led
for t
his
feat
ure.
stat
us_p
ulse
d[1]
[3] (
16:3
1)16
0Le
ast s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
tota
l fro
m d
igita
l inp
ut 4
of t
he s
lave
1 M
onito
rPR
O. T
his
accu
mul
ator
nee
ds to
be
enab
led
for t
his
feat
ure.
stat
us_p
ulse
d[1]
[3] (
0:15
)16
1M
ost s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
tota
l fro
m d
igita
l inp
ut 5
of t
he s
lave
1 M
onito
rPR
O. T
his
accu
mul
ator
nee
ds to
be
enab
led
for t
his
feat
ure.
stat
us_p
ulse
d[1]
[4] (
16:3
1)16
2Le
ast s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
tota
l fro
m d
igita
l inp
ut 5
of t
he s
lave
1 M
onito
rPR
O. T
his
accu
mul
ator
nee
ds to
be
enab
led
for t
his
feat
ure.
stat
us_p
ulse
d[1]
[4] (
0:15
)16
3M
ost s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
tota
l fro
m d
igita
l inp
ut 6
of t
he s
lave
1 M
onito
rPR
O. T
his
accu
mul
ator
nee
ds to
be
enab
led
for t
his
feat
ure.
stat
us_p
ulse
d[1]
[5] (
16:3
1)16
4Le
ast s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
tota
l fro
m d
igita
l inp
ut 6
of t
he s
lave
1 M
onito
rPR
O. T
his
accu
mul
ator
nee
ds to
be
enab
led
for t
his
feat
ure.
stat
us_p
ulse
d[1]
[5] (
0:15
)16
5M
ost s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
tota
l fro
m d
igita
l inp
ut 1
of t
he s
lave
2 M
onito
rPR
O. T
his
accu
mul
ator
nee
ds to
be
enab
led
for t
his
feat
ure.
stat
us_p
ulse
d[2]
[0] (
16:3
1)16
6Le
ast s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
tota
l fro
m d
igita
l inp
ut 1
of t
he s
lave
2 M
onito
rPR
O. T
his
accu
mul
ator
nee
ds to
be
enab
led
for t
his
feat
ure.
stat
us_p
ulse
d[2]
[0] (
0:15
)16
7M
ost s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
tota
l fro
m d
igita
l inp
ut 2
of t
he s
lave
2 M
onito
rPR
O. T
his
accu
mul
ator
nee
ds to
be
enab
led
for t
his
feat
ure.
stat
us_p
ulse
d[2]
[1] (
16:3
1)16
8Le
ast s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
tota
l fro
m d
igita
l inp
ut 2
of t
he s
lave
2 M
onito
rPR
O. T
his
accu
mul
ator
nee
ds to
be
enab
led
for t
his
feat
ure.
stat
us_p
ulse
d[2]
[1] (
0:15
)16
9M
ost s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
tota
l fro
m d
igita
l inp
ut 3
of t
he s
lave
2 M
onito
rPR
O. T
his
accu
mul
ator
nee
ds to
be
enab
led
for t
his
feat
ure.
stat
us_p
ulse
d[2]
[2] (
16:3
1)17
0Le
ast s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
tota
l fro
m d
igita
l inp
ut 3
of t
he s
lave
2 M
onito
rPR
O. T
his
accu
mul
ator
nee
ds to
be
enab
led
for t
his
feat
ure.
stat
us_p
ulse
d[2]
[2] (
0:15
)17
1M
ost s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
tota
l fro
m d
igita
l inp
ut 4
of t
he s
lave
2 M
onito
rPR
O. T
his
accu
mul
ator
nee
ds to
be
enab
led
for t
his
feat
ure.
stat
us_p
ulse
d[2]
[3] (
16:3
1)17
2Le
ast s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
tota
l fro
m d
igita
l inp
ut 4
of t
he s
lave
2 M
onito
rPR
O. T
his
accu
mul
ator
nee
ds to
be
enab
led
for t
his
feat
ure.
stat
us_p
ulse
d[2]
[3] (
0:15
)17
3M
ost s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
tota
l fro
m d
igita
l inp
ut 5
of t
he s
lave
2 M
onito
rPR
O. T
his
accu
mul
ator
nee
ds to
be
enab
led
for t
his
feat
ure.
stat
us_p
ulse
d[2]
[4] (
16:3
1)17
4Le
ast s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
tota
l fro
m d
igita
l inp
ut 5
of t
he s
lave
2 M
onito
rPR
O. T
his
accu
mul
ator
nee
ds to
be
enab
led
for t
his
feat
ure.
stat
us_p
ulse
d[2]
[4] (
0:15
)17
5M
ost s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
tota
l fro
m d
igita
l inp
ut 6
of t
he s
lave
2 M
onito
rPR
O. T
his
accu
mul
ator
nee
ds to
be
enab
led
for t
his
feat
ure.
stat
us_p
ulse
d[2]
[5] (
16:3
1)17
6Le
ast s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
tota
l fro
m d
igita
l inp
ut 6
of t
he s
lave
2 M
onito
rPR
O. T
his
accu
mul
ator
nee
ds to
be
enab
led
for t
his
feat
ure.
stat
us_p
ulse
d[2]
[5] (
0:15
)17
7M
ost s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
num
ber o
f fau
lts o
n pu
mp
1st
atus
_fau
lt_ac
cum
ulat
or[0
] (16
:31)
178
Leas
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e nu
mbe
r of f
aults
on
pum
p 1
stat
us_f
ault_
accu
mul
ator
[0] (
0:15
)17
9M
ost s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
num
ber o
f fau
lts o
n pu
mp
2st
atus
_fau
lt_ac
cum
ulat
or[1
] (16
:31)
180
Leas
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e nu
mbe
r of f
aults
on
pum
p 2
stat
us_f
ault_
accu
mul
ator
[1] (
0:15
)18
1M
ost s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
num
ber o
f fau
lts o
n pu
mp
3st
atus
_fau
lt_ac
cum
ulat
or[2
] (16
:31)
182
Leas
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e nu
mbe
r of f
aults
on
pum
p 3
stat
us_f
ault_
accu
mul
ator
[2] (
0:15
)18
3M
ost s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
num
ber o
f fau
lts o
n pu
mp
4st
atus
_fau
lt_ac
cum
ulat
or[3
] (16
:31)
184
Leas
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e nu
mbe
r of f
aults
on
pum
p 4
stat
us_f
ault_
accu
mul
ator
[3] (
0:15
)18
5M
ost s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
num
ber o
f fau
lts o
n pu
mp
5st
atus
_fau
lt_ac
cum
ulat
or[4
] (16
:31)
186
Leas
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e nu
mbe
r of f
aults
on
pum
p 5
stat
us_f
ault_
accu
mul
ator
[4] (
0:15
)18
7M
ost s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
num
ber o
f fau
lts o
n pu
mp
6st
atus
_fau
lt_ac
cum
ulat
or[5
] (16
:31)
188
Leas
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e nu
mbe
r of f
aults
on
pum
p 6
stat
us_f
ault_
accu
mul
ator
[5] (
0:15
)18
9M
ost s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
num
ber o
f fau
lts o
n pu
mp
7st
atus
_fau
lt_ac
cum
ulat
or[6
] (16
:31)
Pag
e 49
Inpu
t Reg
iste
rs
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Reg
iste
r: 1
6 bi
t reg
sist
er (r
ead
only
)In
dex
Des
crip
tion
Mul
titro
de C
ross
-Ref
eren
ceVa
riabl
e
190
Leas
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e nu
mbe
r of f
aults
on
pum
p 7
stat
us_f
ault_
accu
mul
ator
[6] (
0:15
)19
1M
ost s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
num
ber o
f fau
lts o
n pu
mp
8st
atus
_fau
lt_ac
cum
ulat
or[7
] (16
:31)
192
Leas
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e nu
mbe
r of f
aults
on
pum
p 8
stat
us_f
ault_
accu
mul
ator
[7] (
0:15
)19
3M
ost s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
num
ber o
f fau
lts o
n pu
mp
9st
atus
_fau
lt_ac
cum
ulat
or[8
] (16
:31)
194
Leas
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e nu
mbe
r of f
aults
on
pum
p 9
stat
us_f
ault_
accu
mul
ator
[8] (
0:15
)19
5M
ost s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
num
ber o
f hou
rs ru
n on
pum
p 1.
Sca
ling
is 0
.1 h
ours
per
cou
nt (i
e 00
0A h
ex =
1 h
our,
000B
hex
= 1
.1 h
ours
).st
atus
_hrs
_run
[0] (
16:3
1)
196
Leas
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e nu
mbe
r of h
ours
run
on p
ump
1. S
calin
g is
0.1
hou
rs p
er c
ount
(ie
000A
hex
= 1
hou
r, 00
0B h
ex =
1.1
hou
rs).
stat
us_h
rs_r
un[0
] (0:
15)
197
Mos
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e nu
mbe
r of h
ours
run
on p
ump
2. S
calin
g is
0.1
hou
rs p
er c
ount
(ie
000A
hex
= 1
hou
r, 00
0B h
ex =
1.1
hou
rs).
stat
us_h
rs_r
un[1
] (16
:31)
198
Leas
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e nu
mbe
r of h
ours
run
on p
ump
2. S
calin
g is
0.1
hou
rs p
er c
ount
(ie
000A
hex
= 1
hou
r, 00
0B h
ex =
1.1
hou
rs).
stat
us_h
rs_r
un[1
] (0:
15)
199
Mos
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e nu
mbe
r of h
ours
run
on p
ump
3. S
calin
g is
0.1
hou
rs p
er c
ount
(ie
000A
hex
= 1
hou
r, 00
0B h
ex =
1.1
hou
rs).
stat
us_h
rs_r
un[2
] (16
:31)
200
Leas
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e nu
mbe
r of h
ours
run
on p
ump
3. S
calin
g is
0.1
hou
rs p
er c
ount
(ie
000A
hex
= 1
hou
r, 00
0B h
ex =
1.1
hou
rs).
stat
us_h
rs_r
un[2
] (0:
15)
201
Mos
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e nu
mbe
r of h
ours
run
on p
ump
4. S
calin
g is
0.1
hou
rs p
er c
ount
(ie
000A
hex
= 1
hou
r, 00
0B h
ex =
1.1
hou
rs).
stat
us_h
rs_r
un[3
] (16
:31)
202
Leas
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e nu
mbe
r of h
ours
run
on p
ump
4. S
calin
g is
0.1
hou
rs p
er c
ount
(ie
000A
hex
= 1
hou
r, 00
0B h
ex =
1.1
hou
rs).
stat
us_h
rs_r
un[3
] (0:
15)
203
Mos
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e nu
mbe
r of h
ours
run
on p
ump
5. S
calin
g is
0.1
hou
rs p
er c
ount
(ie
000A
hex
= 1
hou
r, 00
0B h
ex =
1.1
hou
rs).
stat
us_h
rs_r
un[4
] (16
:31)
204
Leas
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e nu
mbe
r of h
ours
run
on p
ump
5. S
calin
g is
0.1
hou
rs p
er c
ount
(ie
000A
hex
= 1
hou
r, 00
0B h
ex =
1.1
hou
rs).
stat
us_h
rs_r
un[4
] (0:
15)
205
Mos
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e nu
mbe
r of h
ours
run
on p
ump
6. S
calin
g is
0.1
hou
rs p
er c
ount
(ie
000A
hex
= 1
hou
r, 00
0B h
ex =
1.1
hou
rs).
stat
us_h
rs_r
un[5
] (16
:31)
206
Leas
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e nu
mbe
r of h
ours
run
on p
ump
6. S
calin
g is
0.1
hou
rs p
er c
ount
(ie
000A
hex
= 1
hou
r, 00
0B h
ex =
1.1
hou
rs).
stat
us_h
rs_r
un[5
] (0:
15)
207
Mos
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e nu
mbe
r of h
ours
run
on p
ump
7. S
calin
g is
0.1
hou
rs p
er c
ount
(ie
000A
hex
= 1
hou
r, 00
0B h
ex =
1.1
hou
rs).
stat
us_h
rs_r
un[6
] (16
:31)
208
Leas
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e nu
mbe
r of h
ours
run
on p
ump
7. S
calin
g is
0.1
hou
rs p
er c
ount
(ie
000A
hex
= 1
hou
r, 00
0B h
ex =
1.1
hou
rs).
stat
us_h
rs_r
un[6
] (0:
15)
209
Mos
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e nu
mbe
r of h
ours
run
on p
ump
8. S
calin
g is
0.1
hou
rs p
er c
ount
(ie
000A
hex
= 1
hou
r, 00
0B h
ex =
1.1
hou
rs).
stat
us_h
rs_r
un[7
] (16
:31)
210
Leas
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e nu
mbe
r of h
ours
run
on p
ump
8. S
calin
g is
0.1
hou
rs p
er c
ount
(ie
000A
hex
= 1
hou
r, 00
0B h
ex =
1.1
hou
rs).
stat
us_h
rs_r
un[7
] (0:
15)
211
Mos
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e nu
mbe
r of h
ours
run
on p
ump
9. S
calin
g is
0.1
hou
rs p
er c
ount
(ie
000A
hex
= 1
hou
r, 00
0B h
ex =
1.1
hou
rs).
stat
us_h
rs_r
un[8
] (16
:31)
212
Leas
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e nu
mbe
r of h
ours
run
on p
ump
9. S
calin
g is
0.1
hou
rs p
er c
ount
(ie
000A
hex
= 1
hou
r, 00
0B h
ex =
1.1
hou
rs).
stat
us_h
rs_r
un[8
] (0:
15)
213
Mos
t sig
nific
ant 1
6 bi
ts o
f 32
bit l
ast f
low
vol
ume
on p
ump
1. S
calin
g is
1 li
tre p
er c
ount
(ie
000A
hex
= 1
0 L,
000
B h
ex =
11
L).
stat
usLa
stV
olum
e[0]
(16:
31)
Pag
e 50
Inpu
t Reg
iste
rs
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Reg
iste
r: 1
6 bi
t reg
sist
er (r
ead
only
)In
dex
Des
crip
tion
Mul
titro
de C
ross
-Ref
eren
ceVa
riabl
e
214
Leas
t sig
nific
ant 1
6 bi
ts o
f 32
bit l
ast f
low
vol
ume
on p
ump
1. S
calin
g is
1 li
tre p
er c
ount
(ie
000A
hex
= 1
0 L,
000
B h
ex =
11
L).
stat
usLa
stV
olum
e[0]
(0:1
5)21
5M
ost s
igni
fican
t 16
bits
of 3
2 bi
t las
t flo
w v
olum
e on
pum
p 2.
Sca
ling
is 1
litre
per
cou
nt (i
e 00
0A h
ex =
10
L, 0
00B
hex
= 1
1 L)
.st
atus
Last
Vol
ume[
1] (1
6:31
)21
6Le
ast s
igni
fican
t 16
bits
of 3
2 bi
t las
t flo
w v
olum
e on
pum
p 2.
Sca
ling
is 1
litre
per
cou
nt (i
e 00
0A h
ex =
10
L, 0
00B
hex
= 1
1 L)
.st
atus
Last
Vol
ume[
1] (0
:15)
217
Mos
t sig
nific
ant 1
6 bi
ts o
f 32
bit l
ast
flow
vol
ume
on p
ump
3. S
calin
g is
1 li
tre p
er c
ount
(ie
000A
hex
= 1
0 L,
000
B h
ex =
11
L).
stat
usLa
stV
olum
e[2]
(16:
31)
218
Leas
t sig
nific
ant 1
6 bi
ts o
f 32
bit l
ast
flow
vol
ume
on p
ump
3. S
calin
g is
1 li
tre p
er c
ount
(ie
000A
hex
= 1
0 L,
000
B h
ex =
11
L).
stat
usLa
stV
olum
e[2]
(0:1
5)21
9M
ost s
igni
fican
t 16
bits
of 3
2 bi
t las
t flo
w v
olum
e on
pum
p 4.
Sca
ling
is 1
litre
per
cou
nt (i
e 00
0A h
ex =
10
L, 0
00B
hex
= 1
1 L)
.st
atus
Last
Vol
ume[
3] (1
6:31
)22
0Le
ast s
igni
fican
t 16
bits
of 3
2 bi
t las
t flo
w v
olum
e on
pum
p 4.
Sca
ling
is 1
litre
per
cou
nt (i
e 00
0A h
ex =
10
L, 0
00B
hex
= 1
1 L)
.st
atus
Last
Vol
ume[
3] (0
:15)
221
Mos
t sig
nific
ant 1
6 bi
ts o
f 32
bit l
ast
flow
vol
ume
on p
ump
5. S
calin
g is
1 li
tre p
er c
ount
(ie
000A
hex
= 1
0 L,
000
B h
ex =
11
L).
stat
usLa
stV
olum
e[4]
(16:
31)
222
Leas
t sig
nific
ant 1
6 bi
ts o
f 32
bit l
ast
flow
vol
ume
on p
ump
5. S
calin
g is
1 li
tre p
er c
ount
(ie
000A
hex
= 1
0 L,
000
B h
ex =
11
L).
stat
usLa
stV
olum
e[4]
(0:1
5)22
3M
ost s
igni
fican
t 16
bits
of 3
2 bi
t las
t flo
w v
olum
e on
pum
p 6.
Sca
ling
is 1
litre
per
cou
nt (i
e 00
0A h
ex =
10
L, 0
00B
hex
= 1
1 L)
.st
atus
Last
Vol
ume[
5] (1
6:31
)22
4Le
ast s
igni
fican
t 16
bits
of 3
2 bi
t las
t flo
w v
olum
e on
pum
p 6.
Sca
ling
is 1
litre
per
cou
nt (i
e 00
0A h
ex =
10
L, 0
00B
hex
= 1
1 L)
.st
atus
Last
Vol
ume[
5] (0
:15)
225
Mos
t sig
nific
ant 1
6 bi
ts o
f 32
bit l
ast
flow
vol
ume
on p
ump
7. S
calin
g is
1 li
tre p
er c
ount
(ie
000A
hex
= 1
0 L,
000
B h
ex =
11
L).
stat
usLa
stV
olum
e[6]
(16:
31)
226
Leas
t sig
nific
ant 1
6 bi
ts o
f 32
bit l
ast
flow
vol
ume
on p
ump
7. S
calin
g is
1 li
tre p
er c
ount
(ie
000A
hex
= 1
0 L,
000
B h
ex =
11
L).
stat
usLa
stV
olum
e[6]
(0:1
5)22
7M
ost s
igni
fican
t 16
bits
of 3
2 bi
t las
t flo
w v
olum
e on
pum
p 8.
Sca
ling
is 1
litre
per
cou
nt (i
e 00
0A h
ex =
10
L, 0
00B
hex
= 1
1 L)
.st
atus
Last
Vol
ume[
7] (1
6:31
)22
8Le
ast s
igni
fican
t 16
bits
of 3
2 bi
t las
t flo
w v
olum
e on
pum
p 8.
Sca
ling
is 1
litre
per
cou
nt (i
e 00
0A h
ex =
10
L, 0
00B
hex
= 1
1 L)
.st
atus
Last
Vol
ume[
7] (0
:15)
229
Mos
t sig
nific
ant 1
6 bi
ts o
f 32
bit l
ast
flow
vol
ume
on p
ump
9. S
calin
g is
1 li
tre p
er c
ount
(ie
000A
hex
= 1
0 L,
000
B h
ex =
11
L).
stat
usLa
stV
olum
e[8]
(16:
31)
230
Leas
t sig
nific
ant 1
6 bi
ts o
f 32
bit l
ast
flow
vol
ume
on p
ump
9. S
calin
g is
1 li
tre p
er c
ount
(ie
000A
hex
= 1
0 L,
000
B h
ex =
11
L).
stat
usLa
stV
olum
e[8]
(0:1
5)23
1M
ost s
igni
fican
t 16
bits
of 3
2 bi
t tot
al v
olum
e pu
mpe
d fo
r the
sta
tion.
stat
usS
tatio
nTot
alFl
ow (1
6:31
)23
2Le
ast s
igni
fican
t 16
bits
of 3
2 bi
t tot
al v
olum
e pu
mpe
d fo
r the
sta
tion.
stat
usS
tatio
nTot
alFl
ow (0
:15)
233
Sta
tion
inflo
w ra
te. S
calin
g is
in li
tres
per s
econ
d.st
atus
Sta
tionF
low
Rat
es[0
]23
4S
tatio
n ou
tflow
rate
. Sca
ling
is in
litre
s pe
r sec
ond.
stat
usS
tatio
nFlo
wR
ates
[1]
235
Mos
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e st
arts
for p
ump
1st
atus
_sta
rts_p
ump[
0] (1
6:31
)23
6Le
ast s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
star
ts fo
r pum
p 1
stat
us_s
tarts
_pum
p[0]
(0:1
5)23
7M
ost s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
star
ts fo
r pum
p 2
stat
us_s
tarts
_pum
p[1]
(16:
31)
238
Leas
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e st
arts
for p
ump
2st
atus
_sta
rts_p
ump[
1] (0
:15)
239
Mos
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e st
arts
for p
ump
3st
atus
_sta
rts_p
ump[
2] (1
6:31
)24
0Le
ast s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
star
ts fo
r pum
p 3
stat
us_s
tarts
_pum
p[2]
(0:1
5)24
1M
ost s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
star
ts fo
r pum
p 4
stat
us_s
tarts
_pum
p[3]
(16:
31)
242
Leas
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e st
arts
for p
ump
4st
atus
_sta
rts_p
ump[
3] (0
:15)
243
Mos
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e st
arts
for p
ump
5st
atus
_sta
rts_p
ump[
4] (1
6:31
)24
4Le
ast s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
star
ts fo
r pum
p 5
stat
us_s
tarts
_pum
p[4]
(0:1
5)24
5M
ost s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
star
ts fo
r pum
p 6
stat
us_s
tarts
_pum
p[5]
(16:
31)
246
Leas
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e st
arts
for p
ump
6st
atus
_sta
rts_p
ump[
5] (0
:15)
247
Mos
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e st
arts
for p
ump
7st
atus
_sta
rts_p
ump[
6] (1
6:31
)24
8Le
ast s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
star
ts fo
r pum
p 7
stat
us_s
tarts
_pum
p[6]
(0:1
5)24
9M
ost s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
star
ts fo
r pum
p 8
stat
us_s
tarts
_pum
p[7]
(16:
31)
250
Leas
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e st
arts
for p
ump
8st
atus
_sta
rts_p
ump[
7] (0
:15)
251
Mos
t sig
nific
ant 1
6 bi
ts o
f 32
bit c
umul
ativ
e st
arts
for p
ump
9st
atus
_sta
rts_p
ump[
8] (1
6:31
)25
2Le
ast s
igni
fican
t 16
bits
of 3
2 bi
t cum
ulat
ive
star
ts fo
r pum
p 9
stat
us_s
tarts
_pum
p[8]
(0:1
5)25
3D
ay o
f las
t ove
r flo
wS
tatu
sDat
eLas
tOflo
w[0
]25
4M
onth
of l
ast o
ver f
low
Sta
tusD
ateL
astO
flow
[1]
255
Yea
r of l
ast o
ver f
low
Sta
tusD
ateL
astO
flow
[2]
Pag
e 51
Inpu
t Reg
iste
rs
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Reg
iste
r: 1
6 bi
t reg
sist
er (r
ead
only
)In
dex
Des
crip
tion
Mul
titro
de C
ross
-Ref
eren
ceVa
riabl
e
256
Hou
r of l
ast o
ver f
low
Sta
tusT
imeL
astO
flow
[0]
257
Min
ute
of la
st o
ver f
low
Sta
tusT
imeL
astO
flow
[1]
258
Sec
ond
of la
st o
ver f
low
Sta
tusT
imeL
astO
flow
[2]
259
Mos
t sig
nific
ant 1
6 bi
ts o
f 32
bit d
urat
ion
of la
st o
verfl
ow. S
calin
g is
in 0
.1 m
inut
es p
er c
ount
(eg.
000
A h
ex =
1 m
in, 0
00B
hex
= 1
.1 m
in).
Sta
tusD
urat
ionL
astO
flow
(16:
31)
260
Leas
t sig
nific
ant 1
6 bi
ts o
f 32
bit d
urat
ion
of la
st o
verfl
ow. S
calin
g is
in 0
.1 m
inut
es p
er c
ount
(eg.
000
A h
ex =
1 m
in, 0
00B
hex
= 1
.1 m
in).
Sta
tusD
urat
ionL
astO
flow
(0:1
5)26
1M
ost s
igni
fican
t 16
bits
of 3
2 bi
t tot
al n
umbe
r of o
verfl
ows
Sta
tusT
otal
Num
berO
flow
s (1
6:31
)26
2Le
ast s
igni
fican
t 16
bits
of 3
2 bi
t tot
al n
umbe
r of o
verfl
ows
Sta
tusT
otal
Num
berO
flow
s (0
:15)
263
Num
ber o
f day
s of
ove
r flo
wS
tatu
sTot
alO
flow
Tim
e[0]
264
Num
ber o
f hou
rs o
f ove
r flo
wS
tatu
sTot
alO
flow
Tim
e[1]
265
Num
ber o
f min
utes
of o
ver f
low
Sta
tusT
otal
Oflo
wTi
me[
2]26
6N
umbe
r of s
econ
ds o
f ove
r flo
wS
tatu
sTot
alO
flow
Tim
e[3]
267
Mos
t sig
nific
ant 1
6 bi
ts o
f 32
bit l
ast o
verfl
ow v
olum
e. S
calin
g is
1 li
tre p
er c
ount
.S
tatu
sLas
tOflo
wV
olum
e (1
6:31
)26
8Le
ast s
igni
fican
t 16
bits
of 3
2 bi
t las
t ove
rflow
vol
ume.
Sca
ling
is 1
litre
per
cou
nt.
Sta
tusL
astO
flow
Vol
ume
(0:1
5)26
9M
ost s
igni
fican
t 16
bits
of 3
2 bi
t tot
al o
verfl
ow v
olum
e. S
calin
g is
100
0 lit
res
per c
ount
.S
tatu
sTot
alO
flow
Vol
ume
(16:
31)
270
Leas
t sig
nific
ant 1
6 bi
ts o
f 32
bit t
otal
ove
rflow
vol
ume.
Sca
ling
is 1
000
litre
s pe
r cou
nt.
Sta
tusT
otal
Oflo
wV
olum
e (0
:15)
271
Cur
rent
leve
l val
ue b
eing
use
d by
the
mas
ter p
ump
cont
rolle
r. S
calin
g is
as
an A
SC
II va
lue
betw
een
0 an
d 20
0.M
TxP
CC
trlS
tatu
s[0]
[0]
272
Cur
rent
pro
be le
vel v
alue
bei
ng u
sed
by th
e m
aste
r pum
p co
ntro
ller.
Sca
ling
is a
s an
AS
CII
valu
e be
twee
n 0
and
200.
MTx
PC
Ctrl
Sta
tus[
0][1
]27
3C
urre
nt v
alue
of a
nalo
g in
put 1
of t
he m
aste
r pum
p co
ntro
ller.
Sca
ling
is a
s an
AS
CII
valu
e be
twee
n 0
and
200.
MTx
PC
Ctrl
Sta
tus[
0][4
]27
4C
urre
nt v
alue
of a
nalo
g in
put 2
of t
he m
aste
r pum
p co
ntro
ller.
Sca
ling
is a
s an
AS
CII
valu
e be
twee
n 0
and
200.
MTx
PC
Ctrl
Sta
tus[
0][5
]27
5C
urre
nt v
alue
of a
nalo
g ou
tput
1 o
f the
mas
ter p
ump
cont
rolle
r. S
calin
g is
as
an A
SC
II va
lue
betw
een
0 an
d 20
0.M
TxP
CC
trlS
tatu
s[0]
[6]
276
Cur
rent
I/P
dev
ice
chos
en. L
evel
inpu
t dev
ice:
01
hex
= st
anda
rd m
ultit
rode
pro
be, 0
2 he
x =
anal
og s
enso
r onl
y, 0
3 he
x =
anal
og s
enso
r with
pro
be s
enso
r ove
rrid
e,
04 h
ex =
via
tele
met
ry.
MTx
PC
Ctrl
Sta
tus[
0][9
] bits
0-3
277
Key
lock
inpu
t: 00
hex
= o
ff, 0
1 he
x =
parti
al, 0
2 he
x =
full.
MTx
PC
Ctrl
Sta
tus[
0][9
] bits
6-7
278
Res
erve
dM
TxP
CC
trlS
tatu
s[1]
[0]
279
Res
erve
dM
TxP
CC
trlS
tatu
s[1]
[1]
280
Res
erve
dM
TxP
CC
trlS
tatu
s[1]
[4]
281
Res
erve
dM
TxP
CC
trlS
tatu
s[1]
[5]
282
Res
erve
dM
TxP
CC
trlS
tatu
s[1]
[6]
283
Res
erve
dM
TxP
CC
trlS
tatu
s[1]
[9] b
its 0
-328
4R
eser
ved
MTx
PC
Ctrl
Sta
tus[
1][9
] bits
6-7
285
Res
erve
dM
TxP
CC
trlS
tatu
s[2]
[0]
286
Res
erve
dM
TxP
CC
trlS
tatu
s[2]
[1]
287
Res
erve
dM
TxP
CC
trlS
tatu
s[2]
[4]
288
Res
erve
dM
TxP
CC
trlS
tatu
s[2]
[5]
289
Res
erve
dM
TxP
CC
trlS
tatu
s[2]
[6]
290
Res
erve
dM
TxP
CC
trlS
tatu
s[2]
[9] b
its 0
-329
1R
eser
ved
MTx
PC
Ctrl
Sta
tus[
2][9
] bits
6-7
292
Vol
tage
on
the
red
[L1]
pha
se. S
calin
g is
0.1
vol
ts p
er c
ount
(eg.
000
A h
ex =
1 V
AC
, 000
B =
1.1
VA
C)
stat
us_r
tu_p
hase
volts
[0][0
]29
3V
olta
ge o
n th
e w
hite
[L2]
pha
se. S
calin
g is
0.1
vol
ts p
er c
ount
(eg.
000
A h
ex =
1 V
AC
, 000
B =
1.1
VA
C)
stat
us_r
tu_p
hase
volts
[0][1
]29
4V
olta
ge o
n th
e bl
ue [L
3] p
hase
. Sca
ling
is 0
.1 v
olts
per
cou
nt (e
g. 0
00A
hex
= 1
VA
C, 0
00B
= 1
.1 V
AC
)st
atus
_rtu
_pha
sevo
lts[0
][2]
295
Res
erve
dst
atus
_rtu
_pha
sevo
lts[1
][0]
296
Res
erve
dst
atus
_rtu
_pha
sevo
lts[1
][1]
Pag
e 52
Inpu
t Reg
iste
rs
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Inpu
t Reg
iste
r: 1
6 bi
t reg
sist
er (r
ead
only
)In
dex
Des
crip
tion
Mul
titro
de C
ross
-Ref
eren
ceVa
riabl
e
297
Res
erve
dst
atus
_rtu
_pha
sevo
lts[1
][2]
298
Res
erve
dst
atus
_rtu
_pha
sevo
lts[2
][0]
299
Res
erve
dst
atus
_rtu
_pha
sevo
lts[2
][1]
300
Res
erve
dst
atus
_rtu
_pha
sevo
lts[2
][2]
301
Res
erve
dN
/A (N
umbe
r of p
endi
ng c
omm
ands
i nP
roco
n V
com
man
d qu
eue)
302
Sca
led
valu
e of
Pro
con
V a
nalo
g in
put 1
. Ran
ge a
nd c
alib
ratio
n is
set
via
the
Pro
con
V c
onfig
urat
ion
men
u.N
/A (F
rom
Pro
con
V h
ardw
are)
303
Sca
led
valu
e of
Pro
con
V a
nalo
g in
put 2
. Ran
ge a
nd c
alib
ratio
n is
set
via
the
Pro
con
V c
onfig
urat
ion
men
u.N
/A (F
rom
Pro
con
V h
ardw
are)
304
Res
erve
dN
/A (F
rom
Pro
con
V h
ardw
are)
305
Res
erve
dN
/A (F
rom
Pro
con
V h
ardw
are)
306
Res
erve
dN
/A (F
rom
Pro
con
V h
ardw
are)
307
Res
erve
dN
/A (F
rom
Pro
con
V h
ardw
are)
308
Res
erve
dN
/A (F
rom
Pro
con
V h
ardw
are)
309
Res
erve
dN
/A (F
rom
Pro
con
V h
ardw
are)
310
Res
erve
dN
/A (N
umbe
r of R
TUs
spec
ified
in
last
Ass
embl
ed S
tatu
s R
espo
nse)
311
Res
erve
dN
/A (N
umbe
r of p
umps
spe
cifie
d in
la
st A
ssem
bled
Sta
tus
Res
pons
e)31
2G
ucpW
orki
ngO
rder
[0][0
]S
tatu
s_m
it_ek
im[0
]31
3G
ucpW
orki
ngO
rder
[0][1
]S
tatu
s_m
it_ek
im[1
]31
4G
ucpW
orki
ngO
rder
[0][2
]S
tatu
s_m
it_ek
im[2
]31
5G
ucpW
orki
ngO
rder
[0][3
]S
tatu
s_m
it_ek
im[3
]31
6G
ucpW
orki
ngO
rder
[0][4
]S
tatu
s_m
it_ek
im[4
]31
7G
ucpW
orki
ngO
rder
[0][5
]S
tatu
s_m
it_ek
im[5
]31
8G
ucpW
orki
ngO
rder
[0][6
]S
tatu
s_m
it_ek
im[6
]31
9G
ucpW
orki
ngO
rder
[0][7
]S
tatu
s_m
it_ek
im[7
]32
0G
ucpW
orki
ngO
rder
[0][8
]S
tatu
s_m
it_ek
im[8
]32
1G
ucpW
orki
ngO
rder
[1][0
]S
tatu
s_m
it_ek
im[9
]32
2G
ucpW
orki
ngO
rder
[1][1
]S
tatu
s_m
it_ek
im[1
0]32
3G
ucpW
orki
ngO
rder
[1][2
]S
tatu
s_m
it_ek
im[1
1]32
4G
ucpW
orki
ngO
rder
[1][3
]S
tatu
s_m
it_ek
im[1
2]32
5G
ucpW
orki
ngO
rder
[1][4
]S
tatu
s_m
it_ek
im[1
3]32
6G
ucpW
orki
ngO
rder
[1][5
]S
tatu
s_m
it_ek
im[1
4]32
7G
ucpW
orki
ngO
rder
[1][6
]S
tatu
s_m
it_ek
im[1
5]32
8G
ucpW
orki
ngO
rder
[1][7
]S
tatu
s_m
it_ek
im[1
6]32
9G
ucpW
orki
ngO
rder
[1][8
]S
tatu
s_m
it_ek
im[1
7]33
0G
ucpW
orki
ngG
roup
[0]
Sta
tus_
mit_
ekim
[18]
331
Guc
pWor
king
Gro
up[1
]S
tatu
s_m
it_ek
im[1
9]33
2G
ucN
TSS
tatu
s_m
it_ek
im[2
0]
Pag
e 53
Inpu
t Reg
iste
rs
Pro
con
V M
odbu
s D
evic
e P
rofil
e D
ata
Dic
tiona
ry
Hol
ding
Reg
iste
r: 1
6 bi
t reg
iste
r (re
ad /
writ
e)In
dex
Des
crip
tion
Mul
titro
de c
omm
and
whe
n w
ritte
n
1W
hen
read
, thi
s re
gist
er w
ill re
turn
the
curr
ent a
nalo
gue
outp
ut v
alue
. W
rittin
g to
this
regi
ster
will
set
the
anal
ogue
ou
tput
of t
he M
aste
r Mon
itorP
RO
to th
e va
lue
writ
ten.
0x81
[A] [
VA
LUE
] 0x8
1
2R
eser
ved
0x81
[B] [
VA
LUE
] 0x8
13
Res
erve
d0x
81 [C
] [V
ALU
E] 0
x81
4W
hen
read
, thi
s re
gist
er w
ill re
turn
the
curr
ent l
evel
of t
he M
aste
r Pum
p C
ontro
ller.
Whe
n w
ritte
n to
, thi
s by
te w
ill s
et
the
curr
ent l
evel
of t
he m
aste
r lev
el in
put d
evic
e. H
owev
er, t
he le
vel c
an o
nly
be m
odifi
ed if
the
mas
ter l
evel
inpu
t de
vice
has
bee
n co
nfig
ured
to a
llow
"Com
mun
icat
ions
Lev
el" t
o be
use
d (i.
e. E
DS
5 s
et to
7).
0x82
[A] [
VA
LUE
] 0x8
2
5R
eser
ved
0x82
[B] [
VA
LUE
] 0x8
26
Res
erve
d0x
82 [C
] [V
ALU
E] 0
x82
7W
hen
read
this
byt
e w
ill re
turn
the
last
writ
ten
valu
e. W
hen
writ
ten
to w
ith a
ny v
alue
all
leve
l ala
rms
will
be
rese
t on
units
with
-in th
e gr
oup.
0x84
[A] [
VA
LUE
] 0x8
4
8R
eser
ved
0x84
[B] [
VA
LUE
] 0x8
49
Res
erve
d0x
84 [C
] [V
ALU
E] 0
x84
10D
ay o
f cur
rent
dat
e on
the
site
.0x
53 [D
AY
] [M
ON
TH] [
YE
AR
-HI]
[YE
AR
-LO
] [H
OU
R] [
MIN
UTE
] [S
EC
ON
D] 0
x53
11M
onth
of c
urre
nt d
ate
on th
e si
te.
0x53
[DA
Y] [
MO
NTH
] [Y
EA
R-H
I] [Y
EA
R-L
O] [
HO
UR
] [M
INU
TE] [
SE
CO
ND
] 0x5
312
Yea
r of c
urre
nt d
ate
on th
e si
te.
0x53
[DA
Y] [
MO
NTH
] [Y
EA
R-H
I] [Y
EA
R-L
O] [
HO
UR
] [M
INU
TE] [
SE
CO
ND
] 0x5
313
Hou
r of c
urre
nt ti
me
on th
e si
te0x
53 [D
AY
] [M
ON
TH] [
YE
AR
-HI]
[YE
AR
-LO
] [H
OU
R] [
MIN
UTE
] [S
EC
ON
D] 0
x53
14M
inut
e of
cur
rent
tim
e on
the
site
0x53
[DA
Y] [
MO
NTH
] [Y
EA
R-H
I] [Y
EA
R-L
O] [
HO
UR
] [M
INU
TE] [
SE
CO
ND
] 0x5
315
Sec
ond
of c
urre
nt ti
me
on th
e si
te0x
53 [D
AY
] [M
ON
TH] [
YE
AR
-HI]
[YE
AR
-LO
] [H
OU
R] [
MIN
UTE
] [S
EC
ON
D] 0
x53
16M
ost s
igni
fican
t 16
bits
of t
he 3
2 bi
t Pro
con
V d
igita
l inp
ut 1
acc
umul
ator
.17
Leas
t sig
nific
ant 1
6 bi
ts o
f the
32
bit P
roco
n V
dig
ital i
nput
1 a
ccum
ulat
or.
18M
ost s
igni
fican
t 16
bits
of t
he 3
2 bi
t Pro
con
V d
igita
l inp
ut 2
acc
umul
ator
.19
Leas
t sig
nific
ant 1
6 bi
ts o
f the
32
bit P
roco
n V
dig
ital i
nput
2 a
ccum
ulat
or.
20M
ost s
igni
fican
t 16
bits
of t
he 3
2 bi
t Pro
con
V d
igita
l inp
ut 3
acc
umul
ator
.21
Leas
t sig
nific
ant 1
6 bi
ts o
f the
32
bit P
roco
n V
dig
ital i
nput
3 a
ccum
ulat
or.
22M
ost s
igni
fican
t 16
bits
of t
he 3
2 bi
t Pro
con
V d
igita
l inp
ut 4
acc
umul
ator
.23
Leas
t sig
nific
ant 1
6 bi
ts o
f the
32
bit P
roco
n V
dig
ital i
nput
4 a
ccum
ulat
or.
24M
ost s
igni
fican
t 16
bits
of t
he 3
2 bi
t Pro
con
V d
igita
l inp
ut 5
acc
umul
ator
.25
Leas
t sig
nific
ant 1
6 bi
ts o
f the
32
bit P
roco
n V
dig
ital i
nput
5 a
ccum
ulat
or.
26M
ost s
igni
fican
t 16
bits
of t
he 3
2 bi
t Pro
con
V d
igita
l inp
ut 6
acc
umul
ator
.27
Leas
t sig
nific
ant 1
6 bi
ts o
f the
32
bit P
roco
n V
dig
ital i
nput
6 a
ccum
ulat
or.
28re
serv
ed29
rese
rved
30re
serv
ed31
rese
rved
Hol
ding
Reg
iste
rsP
age
54