Proposal of an ASIC CMOS for Sliding Mode Control of ... · Proposal of an ASIC CMOS for Sliding...

Proposal of an ASIC CMOS for Sliding Mode Control of SwitchedReluctance Aerogenerators

BRUNO C. DIASUniversidade Federal do ABC

Av. dos Estados, 5001, Sto. Andre - SPBRAZIL

[email protected]

EVANDRO BOLZANUniversidade Federal do ABC

Av. dos Estados, 5001, Sto. Andre - SPBRAZIL

[email protected]

JOSE A. TORRICO ALTUNAUniversidade Federal do ABC

Av. dos Estados, 5001, Sto. AndreBRAZIL

[email protected]

ALFEU J. SGUAREZI FILHOUniversidade Federal do ABC


[email protected]

CARLOS E. CAPOVILLAUniversidade Federal do ABC


[email protected]

Abstract: This paper proposes an ASIC CMOS for sliding mode control (direct power one) applied to switchedreluctance aerogenerators. The topology of the circuit is designed in order to carry out, in the most optimal way, themathematical function which processing directly the power error and supply the turn-off angle to the power systemconverter. The specifications and simulation performance are in close agreement, which validate the proposedcompact design. The ASIC final layout is also presented.

Key–Words: ASIC; CMOS; SRG; sliding mode control; wind energy.

1 IntroductionThe growing demand for energy sources as an alterna-tive to fossil fuels becomes renewable energy a greatarea of research, which has been explored by manycountries around the world. Among these alternatives,the wind energy is one of most important and mostenvironmentally-friendly [1].

For this purpose, the Switched Reluctance Ma-chine (SRM) is a type of device that can be usedin wind generation for micro-grids or isolated sys-tems with relatively low loads, due to it can oper-ate at variable speed with high efficiency and lowcost [2, 3, 4]. In the Figure 1 is presented a visual dia-gram of a possible wind generation system connectedto the grid system using a Switched Reluctance Gen-erator (SRG).

There are several academic papers that discusstechniques to control the SRG [5, 6, 3]. In [7], theauthor proposes a control strategy for the SRG con-nected to the power grid based on sliding mode con-trol. This strategy proposes the control acts directlyon the generated power.

In the other way, the steady growth of the CMOS(Complementary Metal-Oxide-Semiconductor) tech-nology to implement integrated circuit has beenshown as a trend in the design of new devices tocater the increasing demand for analog and digital

ASIC (Application Specific Integrated Circuit) sys-tems. These ICs (Integrated Circuits) are customizedfor a particular use, rather than ICs for general pur-pose utilization [8].

Wind

Turbine

Wind

Turbine

SRGn1

n2Controller

Power GridPower Grid

Converter

and

Converter

and

Figure 1: Wind generation system connected to thepower grid using an SRG.

In this context, this paper presents the design ofan analog integrated circuit for sliding mode control.It is implemented by dedicated CMOS OperationalAmplifiers, which perform the direct power control ofSRG. This topology is a full ASIC circuit to be used asan alternative to traditional control implementationsby programmable processors [9]. The ASIC designuses the 0.35μm CMOS process models from AMS(Austriamicrosystems) foundry [10].

WSEAS TRANSACTIONS on CIRCUITS and SYSTEMSBruno C. Dias, Evandro Bolzan, Jose A. Torrico Altuna, Alfeu J. Sguarezi Filho, Carlos E. Capovilla

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2 SRG and the Direct Power Control

SRG operation is based on the reluctance variation ofits rotor magnetic circuit [11]. The inductance in anSRM is related to the reluctance, and it presents alinear variation in accordance with the poles’ align-ment position of rotor and stator, having a maximuminductance when the poles are fully aligned and a min-imum inductance when the poles are completely mis-aligned. To operate as a generator, the SRM musthave their phase excited during degrowth of its induc-tance [11, 4].

There are several power converters for activatingSRG, however the configuration commonly used isthe HBC (Half-Bridge Converter), which is presentedin Figure 2 [12]. Its operation is in two steps: 1) Ex-citation step, which both SRG switches of each phaseare activated, making the bus voltage Vdc to energizethe stage, causing an increase in current flow throughthe coil and transferring energy to its magnetic fieldand; 2) Generation step, which both switches areturned off (open switches) and the current starts toflow by the diodes to load [13].

Ph

ase

b

Ph

ase a

Ph

ase

d

Vdc

C

+

-

Ph

ase

c

Figure 2: Power HBC.

As strategy control, in this paper has adopted theSM-DPC (Sliding Mode - Direct Power Control) tech-nique, previously reported in [7]. In this one, the windgeneration system is based on the control of two sep-arate converters, in which the HBC connected to theSRG regulates the extraction of the maximum electri-cal power generated by the wind system, and a secondconverter connected directly to the power grid is re-sponsible for regulating the continuous voltage Vdc,allowing that the energy generated by SRG has beensent to the power grid [14]. The switching surface ofthe HBC is defined by the processing of the error be-tween a reference power value, Pref , and the instanta-neous power value generated by the system, P , wherethis value is calculated from the measured values ofvoltage and current of the SRG. An expression thatrepresents this error is given by:

ep = Pref − P (1)

The set S of the switching surface is givenby: [14]:

S = s1 = ep+ kddep

dt(2)

where: kd is a constant that represents the deriva-tive gain defined in accordance to desired system re-sponse.

The sliding mode system controls the power ofthe SRG by the actuation at the turn-off angle θoffof the HBC. The turn-on angle θon is kept at a fixedvalue. The control law that reproduces this behavioris given by [14]:

θoff =

(

kp+ki

s

)

eval(s1) (3)

where: ki and kp are the PI controller gains, and theeval function is responsible for determining the reac-tion of the control system, acting linearly with satura-tion limits, as can be seen in (4).

eval (s1) =

⎧

⎪

⎨

⎪

⎩

s1ke if lmin < x < lmax,lmax if x > lmax,lmin if x < lmin.

(4)

where: ke is a constant that represents the eval func-tion gain and lmin and lmax represent the minimumand maximum limits, respectively.

The Figure 3 shows the block diagram of theDPC-SM for the SRG, where can be observed that theerror processing is carried out by comparing of thePref signal with the P signal and the switching sur-face S is calculated from equation (2). Thus, the turn-off angle θoff , presented by equation (3), is foundthrough the action of the PI controller applied to theswitching surface S, and processed by the eval func-tion.

Figure 3: Block diagram of the SM - DPC adopted.

3 ASIC - Basic Block - OperationalAmplifier

3.1 CMOS Operational Amplifier Architec-ture

The CMOS technology is widely used in the designof operational amplifiers (opamps) [15, 16] and, as arule, a designer must accomplish the most of the re-quired functions using only MOS transistors and small


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capacitors [8, 17]. The Figure 4 presents the completeschematic of the opamp adopted as the core of theproposed ASIC. The opamp is composed by a rail-to-rail input stage with two complementary folded-cascode circuits and a rail-to-rail output stage biasedin Class-AB. For easily visualization of the schematic,the bias circuit was omitted in the schematic. This oneis formed by MOS voltage dividers, which provide thebiasing voltages Vb1-Vb4.

The rail-to-rail input stage is implemented withtwo complementary circuits (PMOS differential pair),MP3 and MP5, connected in parallel with an NMOSdifferential pair, MN4 and MN6 [18, 19]. The firstcircuit is composed by PMOS transistors, MP1, MP3and MP5, and by NMOS transistors, MN8, MN10,MN12 and MN14. The second circuit is composed byNMOS transistors, MN2, MN4, MN6, and by PMOStransistors, MP7, MP9, MP11 and MP13. The differ-ential pairs are biasing by MP1 and MN2 transistors,which operate as current sources, providing a biasingcurrent to the circuit [20].

The MP7-MN10 transistors are current mirrorsand, together with the MP11-MN14 transistors, rep-resent a summing circuit that adds the signals fromthe input stage and aid to improve the voltage gainachieved by the input differential pairs. They are bias-ing by a floating current source formed by MP15 andMN16 transistors [21, 22].

Each of the differential pairs leads the input signalby a different path and generates an independent AV P

(Voltage Gain). The ones of PMOS and NMOS differ-ential pairs can be found by (5) and (6), respectively,and the input stage gain is given by (7) [23].

AV P ≈ − gm5

(gd5 + gd10).(gm14 + gmb14 + gd14)

gd14(5)

AV N ≈ − gm6

(gd6 + gd9).(gm13 + gd13)

gd13(6)

AV 1 = AV P .AV N (7)

gm = KP.W

L.(|VGS | − |Vth|) (8)

gd =Id

(

1λ + VDS

) (9)

gmb = gm.

⎛

⎝

γ

2√

|2φf |+ VSB

⎞

⎠ (10)

where: KP is the transistor transconductance, W isthe transistor channel width, L is the transistor chan-nel length, Vth is the threshold voltage, Id is the tran-sistor drain current, λ is the transistor channel-lengthmodulation, γ is the transistor body factor and φf isthe fermi potential.

The Class-AB rail-to-rail output stage is imple-mented by complementary transistors pairs, MP19and MN20, by transistors, MP17 and MN18 (floatingvoltage source) which biasing the output transistors,and also function as a DC level shifter. It couples theinput signals to the MP19 and MN20 gate terminals.

The MP21-MN24 transistors form two translin-ear loops with the output transistors pairs, MP19 andMN20, and the transistors pairs of the DC level shifter.The MP17 and MN18 directly control the quiescentbiasing current of the output stage, according to (11)and (12). The output stage gain can be given by (13),and the circuit total gain is given by (14), where, RLis a resistive load [20, 24].

VGS19 + VGS17 = VGS23 + VGS21 (11)

VGS20 + VGS18 = VGS22 + VGS24 (12)

AV 2 =gm19 + gm20

gd19 + gd20 +1RL

(13)

AV T = AV 1.AV 2 (14)

3.2 Design and OptimizationThe opamp design has used a voltage supply of +/-1.65V. The adopted biasing currents were the follow-ing: 20μA for the current mirror and differential inputstage, resulting in a current of 10μA for each arm;10μA to the summing circuit, MP11-MN14; 5μAfor the floating current source, MP15-MN16, and DClevel shifter, MP17-MN18; and Idq = 60μA to thequiescent current of the output stage transistors. TheMOS transistors must be biased in the saturation re-gion to operate as amplifiers and (15) gives the (W/L)ratio required to bias correctly the transistors in thisregion [25, 26].

(W/L) =2.Id

KP.(VGS − Vth)2. (1− λVDS)

(15)

The VGS and VDS voltages of each transistor wereset to operate in the saturation region, obtaining thebest possible response to the opamp and the (W/L)ratios of all transistors were calculated by (15).

For the output stage, it is fixed a maximum outputvoltage excursion Vout = ±1.55V . The maximum


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VDD

VSS

Mp1Vb1

Vp+Vp+ Mp3 Mp5

Mn4 Mn6

Vb2

Mn2

Vn-

Mp7 Mp9

Mp11

Vb3

Mp13

Vb4

Mn8 Mn10

Mn12 Mn14

Mp15 Mn16Mp 81 Mp 71

Mp19

Mn20

Mn22

Mn24

Mn26

Mp21

Mp23

Mp25

MPCNCcN

CcPMPCP

Vout

Figure 4: Full opamp schematic.

output current was calculated considering a resistiveload of 500Ω connected to the circuit output, reach-ing a value of Idmax = (+1.65V/500Ω) = 3.3mA.Considering the moment of peak output voltage, thePMOS transistor MPS1 will be driving and operatingin the linear region, while the MNS2 transistor willbe cut. Thus, the MPS1 transistor must be biased inaccordance with the equation (16).

Imax =1

2(W/L) (2 (VGS − Vthp)− VDS)VDS

(16)Adopting a VGS = −3.3V and VDS = −0.1V ,

the (W/L) ratio of the MP19 transistor can be foundfrom (16). Similarly, adopting a VGS = +3.3V andVDS = +0.1V , the (W/L) ratio of the MN20 transis-tor can also be found from (16).

The (W/L) ratios, optimized by simulations, andthe main values of transistors biasing are summarizedin the Table 1.

To maintain the circuit stability in the closed loopfeedback, it is important an appropriate frequencycompensation design. In this topology, the Miller fre-quency compensation is performed by two loops. Thefirst one is formed by MPCN transistor in series withthe CcN capacitor, and the second one is formed byMPCP transistor in series with the CcP capacitor.Each of the folded-cascode circuits present two mainpoles that can affect your open-loop gain.

In small signal analysis, the DC level shifter canbe replaced by a short, and for this condition, both

frequency compensation loops operate as if they wereconnected in parallel. Considering that the resistorsand capacitors have the same values, the two loopsare equivalent to a single loop compensation providedby the capacitor Cc and resistor Rc, and the followingrelationships can be expressed by:

Rc =Rp

2=

Rn

2(17)

Cc = 2CcP = 2CcN (18)

where: Rp and Rn represents the resistance value ofthe MPCP and MPCN transistors, respectively.

The positions of the two poles of the PMOS inputdifferential pair are shown by (19) and (20). The po-sitions of the two poles of the NMOS differential paircan be found in the analogous way.

Wp1P ≈ 1

C2

(

1gd5+gd10

)(

gm14+gmb14+gd14gd14

) (19)

Wp2P ≈ 1

C1P

(

1gm14+gmb14+gd14+gd5+gd10

) (20)

where: C1P represents the gate-source capacitance ofMN14 transistor and C2 is the output impedance ofthe differential pairs, multiplied by the gains of MP13and MN14 transistors.


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Table 1: Summary of opamp values.

Opamp ID VGS VDS L WTransistors (μA) (V ) (V ) (μm) (μm)

MP1 20 -1.00 -0.61 2 19.95MN2 10 1.00 0.60 2 2.75MP3 10 -1.04 -2.09 4 14.25MN4 10 1.05 2.10 4 5.10MP5 10 -1.04 -2.09 4 14.25MN6 10 1.05 2.10 4 5.10MP7 20 -1.15 -0.60 2 8.55MN8 20 1.00 0.60 2 2.95MP9 20 -1.15 -0.60 2 8.55

MN10 20 1.00 0.60 2 2.95MP11 10 -0.84 -0.55 2 32.10MN12 10 0.90 0.40 2 13.60MP13 10 -0.84 -0.55 2 32.10MN14 10 0.90 0.40 2 13.60MN15 5 -0.85 -1.15 2 18.90MN16 5 1.00 1.15 2 2.00MP17 5 -0.85 -1.15 2 18.90MN18 5 1.00 1.15 2 2.00MP19 10 -1.15 -1.65 2 438MN20 10 1.00 1.65 2 155MP21 5 1.22 1.22 2 165MN22 5 1.00 1.00 2 2.00MP23 5 -0.85 -1.15 2 18.90MN24 5 1.00 1.15 2 2.00MP25 20 -1.00 -1.30 2 19.95MN26 20 1.00 1.30 2 2.75MPCN - -2.15 - 2 5.50MPCP - -1 - 2 23.65

The insertion of the capacitor changes the polespositions and also adds a zero on the right side of thecomplex plane. This zero increases the gain and de-creases the phase, so it can lead to instability [27]. Thezero value is given by:

WZ ≈ 1

Cc(

1gm19+gm20

− 1gc

) (21)

An option to eliminate this zero is to adopt RC =1/(gm19 + gm20), in this way, moving the zero toinfinity, according to (22). The circuit has adopteda compensation capacitor CcN = CcP = 1pF(Cc = 2pF ).

Rc =1

gc=

1

gm19 + gm20(22)

The (W/L) ratios of the two compensa-tion transistors can be calculated by (23), find-ing the value of (W/L)MPCN=(5.5/2) and(W/L)MPCP=(23.65/2)

(W/L) =(1/2Rc)

K (VGS − Vthp)(23)

The main parameters analyzed are the Open-Loopfrequency response; Closed-Loop Bandwidth (CLB);Common Mode Rejection Ratio (CMRR); Outputswing (Vout±) and the Input (Rin) and Output (Rout)resistances. The Figure 5 shows the opamp Open-Loop frequency response. The main results of thesimulations are presented in Table 2.

1 10 100 1k 10k 100k 1M 10M 100M 1G-100

-50

0

50

100

150

200

Gai

n(dB

)

Frequency (Hz)

Gain dB Gain Phase

-100

-50

0

50

100

150

200

Gain(

o)

Figure 5: Opamp open-loop frequency response.

Table 2: Opamp - Simulation results

Parameters ValuesAvo 119.90dB

GBW 8.10MHzPM 77.10◦

CLB(−3dB) 4.70MHzCLB(PM) 124.60◦

CMRR 131dBVout± ±1.64VRin 1.16TΩRout 185Ω

In this simulation, the opamp output is connectedto a resistive load in parallel with a capacitor (10kΩand 10pF , respectively). The DC gain, Avo, haspresented 119.90dB. The gain bandwidth, GBW, is


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8.4MHz, and the phase margin is 77.10◦. These re-sults show that the circuit has the necessary stabilityfor a satisfactory operation.

The values of CMRR, CLB and output swinghave shown satisfactory results. The impedances val-ues are also satisfactory, with Rin much higher thanRout. In this way, the opamp has shown excellent per-formance, validating the circuit topology to be used inthe proposed analog controller.

4 ASIC - Analog Dedicated CircuitControl

Figure 6 presents the fully integrated ASIC schematic,which is implemented by an optimized arrangement ofopamps (only the capacitors are not integrated, due tothe large sizes and necessity of external control com-pensations). For this reason, the first design approachwas of the CMOS opamp. After the optimization ofthe opamp, the complete ASIC design can be accom-plished.

In Figure 6 can be highlight seven main blocks:1) Isolator input block, in which the Pref and P sig-nals are applied; 2) Power error calculation block;3) Power error derived calculation block, where thederivative gain kd is found through its output equa-tion (24); 4) Switching surface calculation (S) block;5) Anti-windup circuit block; 6) PI controller block,where the proportional (kd) and integrator (ki) gainsare found through their output equations (25) and (26),respectively; and 7) Gain adjustment block, whichprovides a final gain for optimized response of the cir-cuit.

Finally, the output circuit will provide the turn-off angle θoff acting in the power control of the windgeneration system.

V o(t) = −kd.dVE(t)

dt(24)

where: V o(t) corresponds to the output signal, kd isthe derivative gain given by (Rder.Cder), and VE cor-responds to the error signal.

V o = −kp.VE (25)

where: kp is the proportional gain given by(Rprop1/Rprop2).

V o(t) = −ki.

t∫

0

(VE(t)dt) (26)

where: ki is the integrator gain given by(1/Rint.Cint).

5 Simulation ResultsTo perform the simulations and to verify the ASICoperation was used as reference model an input sig-nal corresponding to Pref , a feedback power signal,P and their output signal resultant, corresponding tothe turn-off angle of the HBC switches, θoff . All sig-nals were obtained through of a mathematical modelsimulation, performed by Matlab/Simulink with theSimPowerSystems tool [7]. In this model, a signalPref was inserted, and the P and θoff values wereanalyzed.

The power reference Pref , which can be seenfrom Figure 7, has a step waveform with variations ofthe active power and the power factor according to thefollowing pattern: The active power starts at 2.5 kW.In the time instant of 0.4s, the one is changed to 5 kW.Again, in the time instant of 1s, the one is changed to2.5 kW. In the time instant of 1.5s, the one is changedto 3.75 kW. Finally, in the time instant of 2.0s, the onereturns to their initial values.

Figure 7: Reference model of the Pref and P signals.

The ASIC simulation was carried out by insertingthe same input signals Pref and P of Figure 7 (ref-erence model). The Figure 9 shows a comparison be-tween the turn-off angle of the ASIC and the referencemodel of Figure 8. The y-axis scale of Figure 9 corre-sponds to 10% of the same axis of Figure 8. The anal-ysis begins at 0.3s due to the time necessary to SRGcomplete its magnetization, as can be seen in Figure 7.It is possible to observe that the analog sliding modecontroller implemented by Opamp developed in thiswork (the proposal ASIC) converged to the same θoffoutput angle obtained in the mathematical model. Inthis way, the integrated circuit is totally operationaland the analysis of results shows a satisfactory perfor-mance of the proposed ASIC, validating the topology.In addition, this one can be used in an SRG real plantas an alternative to programmable processors.


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10k Ohm

10k Ohm

10k Ohm

10k Ohm

100 Ohm 100nF

1k Ohm

10k Ohm

10k Ohm

90 9 Ohm.

10k Ohm10k Ohm

10k Ohm3.30k Ohm

5k Ohm 60k Ohm10k Ohm

17k Ohm

100k Ohm

6 3k Ohm. 100k Ohm

10k Ohm

10k Ohm

4 k Ohm.60

2 k Ohm.4

T eta_offh

P

Pref

5k Ohm

-2.50V

IsolatorInputBlock

Power ErrorCalculation

Block

Power ErrorDerived

CalculationBlock

SwitchingSurface

CalculationBlock

Anti Windup-CircuitBlock

P I ControllerBlock

Gain Adjustment

Block

µ0.1 F

Figure 6: ASIC - Analog Slide Mode Controller.

Figure 8: Reference model of the turn-off angle θoff .

To complete the design, Figure 10 presents thelayout of the opamp (isolated) and Figure 11 presentsthe complete ASIC layout. To avoid offset problemsin the design of the amplifier components, the matchbetween them must be carefully done. The transistorsare placed as close as possible to decrease the gradi-ent, and then applied the common centroid configura-tion, which ensure that the gradient affect all transis-tors in the same way [8].

0,5 1,0 1,5 2,0 2,5

0,4

0,6

0,8

1,0

1,2

1,4

1,6

1,8

2,0

Theta

_off (

V)

T (s)ime

Analog Controller

Reference Model

Figure 9: Comparison of the turn-off angle θoff be-tween the ASIC and the reference model.

6 ConclusionsThis paper presented a proposal of an ASIC CMOSdesign for sliding mode direct power control appliedto SRG. Firstly, it was accomplish the design of adedicated CMOS opamp and several simulations wereperformed, demonstrating excellent results. The ana-


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Figure 10: Opamp layout (0.15 x 0.11 = 0.017 mm2).

Figure 11: ASIC - Analog controller circuit layout(1.63 x 1.28 = 2.09 mm2).

log sliding mode controller was implemented by a op-timized arrangement of these CMOS operational am-plifiers. Its simulation results demonstrated that thecircuit ones converged at the same turn-off angle θoffof the mathematical model used as the reference, con-firming its effectiveness. The obtained results of thethe analog sliding mode controller were extremely sat-isfactory, showing the feasibility of such device in0.35μm technology. Finally, the complete layout wasalso proposed.

Appendix

Gains values for the analog controller circuit:kd = 0.0001 (Rder = 1kΩ and Cder = 100nF );kp = 1.7 (Rprop1 = 17kΩ and Rprop2 = 10kΩ);ki = 100 (Rint = 100kΩ and Cint = 0.1uF ).

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