Properties of Digital Switching Currents in Fully CMOS Combinational Logic

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO. 12, DECEMBER 2010 1625

Properties of Digital Switching Currents in FullyCMOS Combinational Logic

Giorgio Boselli, Gabriella Trucco, and Valentino Liberali

Abstract—In this paper, we present a model to derive statisticalproperties of digital noise due to logic transitions of gates in a fullyCMOS combinational circuit. Switching activity of logic gates in adigital system is a deterministic process, depending on both circuitparameters and input signals. However, the huge number of logicblocks in a complex IC makes digital switching a cognitively sto-chastic process. For a combinational logic network, we can modeldigital switching currents as stationary shot noise processes, de-riving both their amplitude distributions and their power spectraldensities. From the spectra of digital currents, we can also calcu-late the spectral components and the rms value of disturbances in-jected into the on-chip power supply lines. The stochastic modelfor switching currents has been validated by comparing theoret-ical results with circuit simulations.

Index Terms—Digital switching noise, power spectral density,shot noise, stochastic processes.

I. INTRODUCTION

D igital switching noise is one of the major concerns in com-plex systems on chip (SoC). In fully CMOS logic circuits,

when gate outputs switch from 0 to 1 or from 1 to 0, the currentsdrawn from power supplies flow through the interconnections.Due to interconnection nonidealities, switching currents affectthe on-chip supply voltages. It is well known that parasitic in-ductances of bond wires and package, together with on-chip andoff-chip capacitances, can cause oscillations of supply voltages:this effect is known as “ground bounce” or “power supply ( )bounce” [1], [2].

Moreover, the integration of more and more complex systemsinto a single chip, which exploits the ever-increasing integra-tion density, has the drawback of worsening unwanted interac-tions between signals inside the chip. In a mixed-signal SoC,i.e., when analog and digital circuits are integrated on the samechip, performance limitations come mainly from the analog sec-tion that interfaces the digital processing core with the externalworld. In such ICs, the noise generated by digital switching ac-tivity propagates through parasitic elements due to interconnec-tions, package, and substrate, and interferes with the analog sec-tion, thus affecting the overall system performance [3]–[9].

Manuscript received October 22, 2008; revised February 27, 2009 andMay 28, 2009. First published September 22, 2009; current version publishedNovember 24, 2010.

G. Boselli was with the Department of Information Technologies, Universitàdegli Studi di Milano, I-26013 Crema, Italy. He is now with Live Reply, I-20141Milan, Italy (e-mail: [email protected]).

G. Trucco and V. Liberali are with the Department of Information Technolo-gies, Università degli Studi di Milano, I-26013 Crema, Italy (e-mail: [email protected]; [email protected]).

Digital Object Identifier 10.1109/TVLSI.2009.2025883

For this reason, the optimum “mixed-signal” design can bevery different from the optimum stand-alone design [10]. Thedesigner must choose the optimum circuit architecture, consid-ering robustness and crosstalk immunity. This involves the anal-ysis of noise generation, noise propagation, and effects on sen-sitive parts of the system.

Therefore, a correct design methodology should take the dig-ital switching noise into account from early stages of the de-sign process, and should require a fast and accurate analysis ofcurrent consumption during logic transitions [11], together withnoise propagation path toward analog blocks, in order to designsuitable protection structures.

As switching noise effects depend on total currents drawnfrom the positive and the negative supplies ( andrespectively) of the digital circuit, we are interested in esti-mating the current consumption of the overall digital circuit,instead of the consumption of individual logic gates. For thisreason, we must focus our attention on a method that providesaggregate information.

Although logic transitions are a completely deterministicphenomenon, their effects are complex. Noise effects dependon the values of currents and their time derivatives, and onpropagation mechanisms, which, in turn, are related to bothon-chip and off-chip interconnections, and substrate parasitics[6]. Then, for a large integrated system, we can assume thatlogic transitions are a cognitively stochastic process due to thehuge number of logic blocks. For these reasons, a stochasticmodel of switching activity is needed to evaluate effects on thewhole integrated system.

An example of stochastic approach is provided in [12], wherethe authors use Markov chains to model the switching currentwaveform, in order to determine the most relevant characteris-tics of the substrate noise spectrum. This study is based on asimplified analytical model of the substrate noise generated bythe digital circuit.

Using a different approach, we are looking for a statisticaldistribution, which can model the overall switching current ofa large digital circuit. In this way, we can describe digital cur-rents by means of a stochastic model based on few statisticalparameters. The amplitude distribution and the power spectraldensity (p.s.d.) of the digital noise can be obtained from a the-oretical analysis. In this paper, we present a model suitable toobtain the stochastic properties of digital switching currents infully CMOS combinational circuits. The model for sequentialcircuits will be presented in a successive paper.

The paper is organized as follows. Section II presents anoverview of the approach. The hypotheses under which digitalswitching currents can be modeled as stochastic processes are

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1626 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO. 12, DECEMBER 2010

discussed in Section III. The model for currents in a combi-national digital circuit is presented in Section IV, and spectralcharacteristics of switching current are calculated in Section Vfor simple current pulses. The noise power superimposedto supply voltage is obtained by using a simple model forinterconnection parasitics, described in Section VI. Finally, tovalidate the proposed model, theoretical results are comparedwith circuit simulations in Section VII.

II. OVERVIEW OF THE PROPOSED APPROACH

As current consumption in a large digital system is a cog-nitively stochastic process, we aim at deriving its statisticalproperties (i.e., its amplitude density and p.s.d.) using a limitednumber of parameters.

Since power consumption in a combinational circuit dependson switching activity of input signals, we must assume an apriori knowledge of the time density of logic transitions at pri-mary inputs. From the circuit schematic and input transition sta-tistics, the switching activity of each internal node can be easilyestimated. Hence, the switching activity of the whole circuit canbe derived.

At this point, to obtain the statistical properties of theswitching noise starting from the logic transition activity, wehave to provide answers to the following questions.

1 Under which hypotheses digital switching currents are sta-tistically equivalent to some kind of noise?

2 Which noise model is more suitable to describe the overallswitching currents?

The target is to find answers to these questions in order to de-rive a simple model that, using few parameters and under someassumptions, allows to estimate digital switching noise with anacceptable level of approximation.

As explained in Section IV, when logic switching instantsoccur randomly over time, they can be modeled as a Poissonprocess. Switching currents may be regarded as a filteredPoisson process analogous to the shot noise in electronicdevices. Therefore, we can model the currents as a stationarystochastic process under some hypotheses.

From the statistical properties of the process, amplitude andfrequency distribution of the switching noise, i.e., the proba-bility density function and the p.s.d., can be calculated startingfrom a small number of parameters, namely, the time density oflogic transitions, the average switching charge, and the durationof switching interval. The time density of logic transitions re-quires the knowledge of the switching probability of each inputsignal. Hence, from the circuit schematic, we can estimate theswitching probability of each internal node on the basis of theBoolean function of the logic gate driving the considered node.The switching probability at the output of a logic gate is givenby the ratio between the total number of output transitions (01 and 1 0) when a single input bit changes, and the numberof possible changes in the input vector. The estimated time den-sity of logic transitions is good if the probabilities of zero andone logic values are similar throughout the whole circuit; on theother hand, a prevalence of logic zeros (or ones) in a part of thecircuit may lead to an overestimation of the switching activity,and hence of the switching noise. The duration of the switching

interval and the total charge transferred during switching can beobtained from circuit-level simulation of each logic gate.

The model has been validated through circuit-level simula-tion using Spectre (a SPICE-like electrical circuit simulator).Benchmark circuits have been synthesized using two differentlibraries of CMOS gates, to have circuits with different features,corresponding to different hypotheses of the model. In this way,the circuit set is general enough to represent an arbitrary combi-national circuit, provided that the number of logic gates is largeenough to allow a statistical modeling. Time-domain currentwaveforms obtained from simulations have been postprocessedto calculate their amplitude and frequency distributions, and re-sults were compared with the theoretical model.

III. DIGITAL SWITCHING CURRENT MODEL

In order to derive the stochastic properties of switching cur-rents, a model of transition activity is needed. To this end, westart from a simplified model obtained under some hypotheses.First of all, in this paper, we limit the analysis to combinationalcircuits. Moreover, we assume that input signals are mutually in-dependent with respect to both logic values and transition times.In other words, input signals are not structured as logic vectors.In the latter case, input vectors should be the output of registersdriven by a clock signal, and the whole circuit would behave as asequential network. This topic will be the subject of a followingpaper.

The hypotheses under which the model is valid follow.1) Independence of logic transitions: First of all, we as-

sume that the transition activity of a logic gate is inde-pendent of transitions of the other gates. Obviously, thisstatement is not true as the output of a logic gate drivesother cells; however, in a large system, the huge numberof logic gates makes each of them dependent on a verysmall number of neighboring cells. Therefore, we maysay that each logic transition is independent of almostall other transitions in the same system.

2) Input switching instants uniformly distributed in time: Inthis paper, we consider that the input switching instants,and as a consequence, the transition activity, occur atrandom instants with uniform distribution over time.

The assumptions 1) and 2) are similar to the ones used to de-rive the mathematical model of shot noise in electronic devices[13]. Shot noise in devices is due to electrons crossing a p-njunction independently at random instants. As all electrons havethe same charge and the same time transit through the junction,the model of shot noise is simpler than the statistical descriptionof switching currents in large digital circuit.

As a first step, we consider two additional assumptions inorder to adapt our model to the shot noise theory.

3) Logic gates with equal switching time: We assume thatall logic transitions require the same time, so all currentpulses have the same finite-time duration .

4) Logic gates with equal current consumption: We con-sider that the current consumption due to switching ac-tivity is equal for all logic cells.

In the next section, we derive a simplified model based onthe aforementioned four assumptions. Next, we present a moregeneral model, which does not require constraints 3) and 4).

BOSELLI et al.: PROPERTIES OF DIGITAL SWITCHING CURRENTS IN FULLY CMOS COMBINATIONAL LOGIC 1627

Fig. 1. Train of impulses filtered through a linear, time-invariant system.

IV. STOCHASTIC MODEL FOR SWITCHING NOISE IN

COMBINATIONAL CIRCUITS

A. Simplified Shot Noise Model

Let us consider a combinational network made up with iden-tical logic cells driving equal capacitive loads. This assumptionis useful to derive a simplified model. If all switching instantsare independent and randomly distributed in a uniform mannerover time, then the digital switching noise could be well approx-imated with a shot noise process. The instants when logic gatesstart switching can be considered as Poisson points.

Given the time interval , we define the random variableas the number of transitions of signals at logic gate outputs.

The probability to have exactly events in the consideredtime interval is given by

for (1)

The number of Poisson points in an interval of length is aPoisson distributed random variable with parameter ,where is the density of the points [14].

Let us consider the transition of a logic gate as a Dirac im-pulse. Therefore, the stochastic process , which representsthe logic transitions of the circuit, is a train of impulses taken atrandom instants given by

(2)

If the logic gates of the circuit are all equal, in the sense thatall gates have the same and current consumption, theconvolution between the train of impulses and the current drawnby the single logic gate is equal to the total current drawn by theentire digital circuit

(3)

where is the impulse response that represents the current ofa single gate in one logic transition. Fig. 1 illustrates the filteringof an impulse train with a linear, time-invariant system. For sim-plicity, only positive transitions are illustrated, and is thestochastic process that represents the switching current drawnby all logic gates from the positive supply. By substituting (2)into (3), we obtain

(4)

In a similar way, we can derive the current drawn from the neg-ative supply.

For a combinational circuit, can be obtained for each gateof the logic library by performing a transistor-level simulationfor both positive and negative output transitions.

The process described by (4) is known as shot noise, and it isbased on the statistical independence of the considered events[14], which are, in our case, the transitions of logic gates. If theimpulse density is uniform over time, the process is stationary.

It is worth pointing out that the shot noise model used todescribe digital switching currents is different from the well-known shot noise in electronic devices. Shot noise in devices isdue to the carrier transit through a p-n junction at random timeinstants. Since all carriers have the same elementary charge andvery short transit time , device shot noise can be modeled ina simple way, and has a white spectrum up to frequencies inthe gigahertz range [13]. On the other hand, the switching noisemodel must account for time-varying currents, different elec-trical charges transferred to capacitive output loads, and longertransition times compared to junction transit time.

The following sections describe the statistical properties ofdigital switching currents.

B. Amplitude Distribution of Switching Noise

The amplitude distribution of the total current drawn by thedigital circuit is represented by the probability density function(p.d.f.) of the stochastic process , which can be calculatedfrom the p.d.f. of the single current pulse .

Let us consider an arbitrary time instant . The total currentat time , , is a random variable, whose p.d.f. dependson both the number of Poisson impulses falling in the interval

and the p.d.f. of the single current pulse , asfollows.

If no impulse occurs in , then , and thep.d.f. is , with probability .

If a single impulse occurs in , then has ap.d.f. , with probability .

If two impulses occur in , then the p.d.f. of the sumof two current pulses is given by the convolution between thetwo p.d.f. of the pulses , with probability

.If exactly impulses occur in , then the p.d.f. of

the total current is

with probability .Of course, .The p.d.f. of the total current can be calculated by taking

the average sum

(5)


where

By using the Poisson probability (1) in (5), we obtain

(6)

If , i.e., the duration of current pulses is small com-pared to the average interval between Poisson impulses, thenwe have the low-density shot noise, and the p.d.f. of the totalcurrent can be obtained by adding just a few terms of the se-ries (6), since the general term vanishes quickly as increases.If , then we have the high-density shot noise, and thep.d.f. of the total current tends to be Gaussian.

C. Frequency Distribution of Switching Noise

By calculating the p.s.d. of the switching current , weobtain its frequency distribution.

The p.s.d. of the logic transition impulses is

(7)

and the p.s.d. of the stochastic process can be calcu-lated as [14]

(8)

where is the Fourier transform of the impulse response. As the Dirac’s impulse is zero for all , in (8),

we can replace with . Moreover,is the time-domain integral of the single current pulse given by

(9)

i.e., is the charge transferred during the completeswitching of a single logic gate. Therefore, the p.s.d. ofthe stochastic process is

(10)

The normalized power of the switching current is

(11)

where the term is the dc component of the digitalswitching power ( is the average value of the current drawnfrom the supply voltage), while the term isthe ac component of the switching power.

By using Parseval’s theorem

(12)

we simplify calculations as the function is real. Equation(11) can be written as

(13)

In the following section, we will see that, for all the impulseresponses , the normalized power can be written as

(14)

where is a “pulse shape” factor, which depends on the singlecurrent-pulse waveform in time domain, and is the time du-ration of the single current pulse.

D. Current Pulses With Different Duration

In order to obtain a more realistic estimation of digitalswitching currents, let us refine our model by removing theassumption 3) of Section III.

Let us consider a digital circuit made up of two differentparts, A and B. Each part is a combinational network made upof logic cells with the same current consumption and the sametime delay. In more detail, all gates of part A are characterizedby the digital switching current , which can be described asa shot noise with time density and impulse response .Analogously, gates of part B are characterized by the digitalswitching current , with time density and impulse re-sponse .

The total current drawn by the whole circuit is

(15)

which is the sum of two shot noise components with differenttime duration of current pulses.

The amplitude distribution of the total current is

(16)

The autocorrelation function of the process is

(17)

which is the sum of the autocorrelation functions of the singleprocesses, which are given by

(18)


Fig. 2. Switching currents for three different logic gates (inverter, two-inputNAND, two-input NOR).

Fig. 3. Amplitude density of the single switching current pulse.

and

(19)

and the cross-correlations and , which aregiven by

(20)

From (20), we can observe that the cross-correlationsand are independent of .

The p.s.d. is given by the sum of the p.s.d. of the singleprocesses and their cross-spectra

(21)

Since the cross-correlations and are constant,the cross-spectra and have a single componentat

(22)

As a consequence, at any frequency , the p.s.d. of thesum of shot noises is given by the sum of power spectral densi-ties of the single noise components.

E. Current Pulses With Different Amplitude

Now, we remove the assumption 4) of Section III to derive astochastic model for current pulses with different peak ampli-tude. Indeed, looking at the waveform in Fig. 2, representingthe current drawn by three different logic gates (inverter,two-input NAND, two-input NOR), we can see that current peakscan be different from each other due to differences in pull-downconductivity of different switching gates. Moreover, the areas

under current pulses may also differ due to different capacitiveloads. For these reasons, we must assume that the current pulsesdue to logic transitions may have different amplitudes.

A mathematical model to describe this situation can beachieved by considering Poisson impulses with different in-tensities proportional to the current drawn by logic gates.Therefore, we have a generalized Poisson process [14], whichis given by

(23)

where is a random variable representing the amplitude ofPoisson impulses, with mean and standard deviation .

In a practical situation, the values, and hence, and ,are obtained from the amplitudes of currents in different logicgates simulated at transistor level. Of course, in the calculationof mean and standard deviation, the current amplitudes mustbe weighted according to the number of instances of each gatewithin the whole circuit.

For simplicity, we assume that current peaks are uniformlydistributed within their range. Moreover, from Fig. 2, we ob-serve that some current pulses exhibit a low current ‘‘tail’’ atthe end of logic transitions. We can model the current amplitudedensity as shown in Fig. 3, where denotes the upper limit ofthe current ‘‘tail,’’ while and are the lower and the uppervalues of the current peak intensities.

To derive the p.s.d. of the generalized Poisson process ,we start from its mean , which is given by

(24)

and from its autocorrelation [14], which is given by

(25)

The p.s.d. is

(26)

By filtering the process through a linear, time-in-variant system, we obtain the stochastic process , whichrepresents the current consumption due to switching activity oflogic gates with different current intensities.

The p.s.d. is

(27)

where represents the average charge transferred during theswitching transitions (assuming ). From (27), it is ap-parent that the ac component of the power spectrum increasesas the variance of current peaks increases.

V. CURRENT-PULSE WAVEFORMS

In this section, we calculate both the amplitude distributionand the p.s.d. for the described model. For simplicity, we areusing the simplified model described in Section IV-A. However,


Fig. 4. (a) Triangular impulse response ��. (b) Corresponding p.s.d. � ��.

Fig. 5. (a) Erlangian impulse response ��. (b) Corresponding p.s.d. � ��.

it is worth pointing out that the approach holds for the moregeneral model in Section IV-D and IV-E also, by using (16),(21), and (22), and replacing with for the dc power and

with for the ac p.s.d.To calculate the amplitude distribution and the p.s.d. of the

current, we need to know the current pulse shape in timedomain. We are considering current pulse waveforms with tri-angular and Erlangian shape.

A. Triangular Current Pulse

For simplicity, let us assume that can be approximatedwith a triangular pulse with peak amplitude and duration

, as shown in Fig. 4(a).The Fourier transform of , , is

(28)

where and .The modulus of is

(29)

and from (10), we obtain the p.s.d. of the current

(30)

shown in Fig. 4(b). The normalized power is

(31)

Therefore, the shape factor is for the triangular currentpulse.

B. Erlangian Current Pulse

To obtain a model of current pulses, which takes into accountboth an exponential tail and a current rise starting with zero

derivative, let us assume that any logic transition from toor vice versa can be approximated with a linear ramp (at

least in its central part), so the input voltage of the logic gateis . When the logic gate starts switching, aMOS transistor in saturation region draws a current equals to

. Then the MOStransistor current rises proportionally to the square of the time

. Moreover, assuming that the MOS transistor in triode regionbehaves as a resistance, we can model the impulse responseas

(32)

where is the Heaviside unit step function and the factoris required to satisfy (9). The impulse response in

(32) is known as the third-order Erlang’s function1 [15].The current-pulse waveform, shown in Fig. 5(a), is in good

agreement with circuit-level simulations [16].The p.s.d. is

(33)

which is illustrated in Fig. 5(b), and the normalized power is

(34)

The impulse response in (32) becomes negligible aftereight time constants, i.e., for , so the correspondingfrequency is , and the normalized power becomes

(35)

with a shape factor .A double exponential has been used in [17] to model

switching currents as functions of time. Results are similar tothe ones shown in Fig. 5. However, we will not investigate fur-ther the double exponential function, since it has been proposedas a mathematical model of the envelope of switching currentsin sequential circuits driven by a clock signal.

C. Considerations on Current Pulse Shape

Considering the normalized power , we can observethat the dc component is the major contribution to the digitalswitching power if ; on the other hand, if , thenthe switching power is mainly due to the ac component. Since

is not much different from 1, we can conclude that the accomponent of the switching power is dominant when the digitaltransition rate is lower than the inverse of the transition time

.By comparing the normalized powers , given by (31) and

(35), and the power spectral densities in Figs. 4(b) and5(b), we can conclude that the noise current generated by theswitching activity of a combinational network is weakly depen-dent on the current-pulse waveform, and it can be described

1The �th-order Erlang’s function is given by �� .Note that the first-order Erlang’s function is just a decreasing exponential func-tion.


Fig. 6. Equivalent circuit for calculation of bond wire inductance effects.

by three parameters: the transition rate , the characteristic fre-quency (which is the inverse of the transition time ), andthe switching charge .

VI. EFFECTS OF PARASITICS ON ON-CHIP SUPPLY VOLTAGES

The results obtained in previous sections can be used to cal-culate the on-chip noise voltage, which is due both to digitalswitching currents and parasitic elements.

A. Bond Wire Parasitics

First of all, let us consider the simplified circuit shown inFig. 6, where the current generator models the digital switchingnoise source, and bond wire parasitics are modeled as seriesinductance and resistance . The bond wire impedance is

(36)

The on-chip power supply is affected by a noise voltagehaving the p.s.d.

(37)

The normalized power of the switching noise affectingthe on-chip voltage supply is

(38)

where we have used Parseval’s theorem, (12), for both andits time derivative

(39)

The first two terms in (38), and , arethe dc and ac components due to the voltage drop across theparasitic resistance . The last term, , is theac component due to the parasitic inductance .

Fig. 7. Voltage p.s.d. � �� due to resistive drop (dashed line) and inductivedrop (solid line) for the triangular current-pulse model.

By comparing the voltage spectral density and power in (37)and (38) with the current spectral density and power in (10)and (11), we can observe that the noise voltage terms due tothe parasitic resistance are similar to the noise current terms,since the resistance gives a proportional relationship betweencurrent and voltage. On the other hand, the last term in (37) and(38) accounts for the inductive voltage drop . Therefore,spectral characteristics of noise voltage are dependent on boththe impulse response and its time derivative .

Finally, we derive the rms value of the on-chip noise voltage,which is given by

(40)

In the following sections, we will calculate the voltage spec-tral density and power for the triangular current pulse and theErlangian pulse.

B. Triangular Current-Pulse Model

Assuming that switching currents may be approximated bytriangular pulses, the p.s.d. of the on-chip supply voltage ,

, is

(41)

Fig. 7 shows the resistive and inductive components of theon-chip supply voltage p.s.d. . The inductive term (solidline) has been calculated assuming , and it ex-hibits a peak at .

The normalized power of the switching noise is

(42)

By comparing the resistive and the inductive terms in (42),we observe that, using the triangular current-pulse model,switching noise effects are mostly due to bond wire inductancewhen .

Finally, the rms value of the noise voltage turns out to be

(43)


Fig. 8. Voltage p.s.d. � �� due to resistive drop (dashed line) and inductivedrop (solid line) for the Erlangian current-pulse model.

C. Erlangian Current-Pulse Model

Using the Erlangian current-pulse model, the p.s.d. of theon-chip supply voltage is

(44)

Fig. 8 shows the resistive and inductive components of thep.s.d. for . The inductive term exhibits apeak at .

The normalized power of the switching noise is

(45)

with switching noise effects mostly due to bond wire inductancewhen .

The rms value of the noise voltage is

(46)

By comparing (42) and (45), we can see that the result isstrongly dependent on the current pulse shape. The triangularcurrent pulse is a very simple model, and can be useful for im-mediate calculation of switching noise; however, it can lead toan underestimation of switching noise effects.

D. Resistive, Inductive, and Capacitive Parasitics

Now we suppose that besides bond wire parasitic inductanceand resistance , the n-well and p-substrate are providing

an additional ac path from the on-chip supply toward ground,modeled by the resistance and the capacitance , as shownin Fig. 9. The overall impedance is

(47)

Since the impedance formula (47) has a second-order denom-inator, oscillations may arise in the circuit in the underdampedcase; this occurs when

(48)

As an example, assuming and , the totalresistance value for critical damping is

(49)

Fig. 9. Equivalent circuit for calculation of bond wire and substrate parasiticeffects.

TABLE ILOGIC GATES IN THE EQUAL DELAY LIBRARY

For , current pulses due to digital switchingmake the on-chip voltage supply to oscillate, giving riseto the well known “VDD bounce.” The lower the ratio

, the longer the duration of the bouncing.

VII. MODEL VALIDATION

To validate the model of stationary shot noise for combina-tional digital circuits described in Section IV, we synthesized aset of logic circuits from the International Workshop on Logicand Synthesis 1993 (IWLS’93) benchmarks [18], and we simu-lated them at transistor level using Spectre.

First of all, we started by choosing combinational net-works from the considered set of benchmarks, made up of asufficiently great number of NOT, AND, and OR gates. We syn-thesized the chosen networks without optimization, obtainingtheir sum-of-products (SOPs) form computed using the toolEspresso for two-level Boolean minimization [19]. Then, wederived the logic networks by mapping the SOP forms usingtwo different cell libraries in a 180-nm CMOS technology withvoltage supply : 1) a minimal set of equal delaygates, namely, inverter, two-input NAND and two-input NOR,listed in Table I, all of them with rise and fall times equal to70 ps, to validate the model presented in Section IV-A and 2)the equal size gates listed in Table II, all of them with NMOStransistors having and PMOStransistors having , to have circuitswith different gate delays, according to the more general modelpresented in Section IV-D and IV-E. For both cell libraries, thetechnology mapping imposes the decomposition of a -inputgate into a logarithmic-deep tree: for the first library, a gatewith inputs is decomposed into a tree of two-inputgates; while for the second library, a gate with inputs isdecomposed into a tree of gates with two, three, or four inputs.

The transition times and the switching charges have beenobtained from Spectre simulations, assuming that each logicgate drives a load made of a single gate with CMOS transis-


TABLE IILOGIC GATES IN THE EQUAL SIZE LIBRARY

tors having an ‘‘average’’ size and . The transistor modelaccounts for internal capacitances (i.e., for both junction capac-itances and gate capacitances), but not for parasitic capacitancesdue to wires. The required CPU time for simulation is about 10 sfor each cell.

Since in the synthesized logic network, most of the logicgates have a fan-out equal to 1, the capacitive loads shown inTables I and II (calculated as the switching charges divided bythe voltage swing) describe the average behavior of each gatewith a sufficient accuracy.

The combinational logic functions listed in Table III havebeen chosen in order to have a set of networks with differentfeatures and sizes. For both cell libraries, Table III shows thenumber of logic gates for each circuit and the normalized powercalculated from transistor-level simulation in time domain. In-puts were driven with random digital signals; at any time, onlyone input bit can change its logic value. The values of and

currents, and of the on-chip and voltages were sam-pled at 2 ps intervals and stored for postprocessing. The normal-ized power has been calculated from the simulated currentsas

(50)

where the sum is taken over the number of current samples.As an example, to compare the theoretical model with sim-

ulation results, we use (31) to calculate the normalized powerfor the benchmark circuit “clip,” synthesized with the equaldelay cell library. The circuit contains 546 cells, namely, 123 in-verters, 212 NAND gates, and 211 NOR gates. The average logictransition rate at each input is for an overall tran-sition density . The average charge trans-ferred during a single logic transition is

, and the transition time is . Obviously, thetransition time is larger than the rise and fall times, since it en-compasses the whole output swing from 0 to , while the riseand fall times are conventionally estimated for the interval from

to . From (31), we obtain ,which differs from the simulated result by 10%.

In a similar way, we can estimate the power for the samebenchmark circuit “clip,” synthesized with the equal size cells,

TABLE IIISIMULATION RESULTS WITH NORMALIZED POWER OF SWITCHING CURRENTS

(IN �� )

obtaining an overall transition density , and anormalized power , which is lower thanthe figure obtained from simulation by about 11%.

The following sections present a comparison between theo-retical results and simulated results for the benchmark circuits“XOR5,” “clip,” and “rd84,” which are the circuit of the set withthe lower number of gates (“XOR5”), the one with the highernumber (“rd84”) and another one with an intermediate figure(“clip”), respectively. SPECTRE simulation times were 5 minfor the benchmark “XOR5,” 38 min for “clip,” and 68 min for“rd84,” on a 1600-MHz Pentium 4 workstation. Of course, theseCPU times are much larger than the time required to obtain theparameters of each logic cell.

As an example, Fig. 10 shows the simulated switchingcurrents and for the benchmark circuit “clip,” resultingfrom two different values of input transition density, labeled“low density” and “high density,” respectively, with idealvoltage supplies. The transition density of each input signal inFig. 10(a) is , while in Fig. 10(b), the transitiondensity is approximately ten times larger.

A. Amplitude Distribution

Current waveforms in Fig. 10(a) exhibit quasi-triangularpulses with different peak values. Therefore, the impulseresponse shown in Fig. 4(a) is suitable to derive frequencycharacteristics of the switching noise, while the amplitudedistribution can be calculated from the p.d.f. of the single pulse

, modeled as shown in Fig. 3. The amplitude densityis constant for intermediate values of the current ; for

low current values, i.e., for , the amplitudedensity is larger to account for pulse tails. Peak values of thesingle current pulse are assumed to be uniformly distributedbetween and .

Fig. 11 shows the amplitude distribution of the positivesupply currents for the benchmark circuit “clip,” for thelow-density [Fig. 11(a)] and the high-density [Fig. 11(b)]transition conditions, respectively. Histograms, labeled with(s) in Fig. 11, were obtained from transistor-level simulations,while continuous curves, labeled with (t), have been calculatedfrom (6). The peak-at-zero amplitude in Fig. 11(a) is due to the


Fig. 10. Digital switching currents � and � for the circuit “clip”: (a) low density of logic transitions and (b) high density of logic transitions.

Fig. 11. Relative amplitude density of the � switching current, for (a) low density of logic transitions and (b) high density of logic transitions: histogram of thesimulated current (s); theoretical curve (t).

Fig. 12. Relative amplitude density of the � switching current for (a) the “XOR5” and (b) the “rd84” benchmarks.

return to zero of the current when the logic transition density islow. This peak vanishes if the switching activity increases.

Theoretical results are in excellent agreement with simula-tions.

All benchmark circuits exhibit similar amplitude distributionsof currents. As a further example, Fig. 12 shows current his-tograms for benchmarks “XOR5” [Fig. 12(a)] and “rd84” [Fig.12(b)].

B. Frequency Distribution of Switching Current

The p.s.d. of the currents can be obtained by calculating theautocorrelation , and then, by taking the Fourier transform

(51)

The CPU time required for postprocessing is about 30 min,mostly due to the calculation of the autocorrelation .


Fig. 13. Simulated p.s.d. of the � switching current for the circuit “clip.” (a) Low density of logic transitions. (b) High density of logic transitions.

Fig. 13 shows the p.s.d. of the positive supply currents inthe benchmark circuit “clip” for the low-density [Fig. 13(a)]and high-density [Fig. 13(b)] transition conditions, respectively.The p.s.d. exhibits notches at multiples of the characteristic fre-quency , which corresponds to the finite cur-rent-pulse duration .

To explain the presence of notches at multiples of, we observe that the “clip” benchmark has been syn-

thesized with 123 inverters, 212 two-input NAND gates, and 211two-input NOR gates. Both inverters and NAND gates have a pos-itive current-pulse duration , while NOR gates ex-hibit current pulses with duration (assuming thatall gates have a unitary fan-out). Therefore, inverters contributeto the positive switching activity by 37%, NAND gates by 31.5%and NOR gates by 31.5%. Then, about 68.5% of positive tran-sitions have a finite duration of 200 ps, which motivates thenotches at multiples of .

Fig. 14 shows the theoretical p.s.d. for the “clip” circuit, cal-culated using: 1) (30) for the triangular current pulse model;2) (33) for the Erlangian pulse model; and 3) a combinationof triangular and Erlangian equations. We can note that the tri-angular current-pulse model achieves a good agreement withsimulated results in Fig. 13. A better agreement can be ob-tained considering a superposition of triangular and Erlangianmodels. A similar result can be obtained considering only the tri-angular current-pulse model by combining several current p.s.d.(30) with different characteristic frequencies , as explained inSection IV-D.

Power spectral densities have been calculated for all bench-mark circuits listed in Table III. Fig. 15 shows the power spectraldensities of switching currents for the “XOR5” [Fig. 15(a)] andthe “rd84” [Fig. 15(b)] benchmark circuits. The plots for theother benchmark circuits are not shown because they are verysimilar to the ones presented in this section, the only differencebeing the spectrum level on the vertical axis.

Fig. 16 shows the p.s.d. of switching currents for the “rd84”benchmark circuit synthesized with the equal size library. Asthis circuit is made with logic gate with different transition timesand there is no prevalence of one kind of gates with respect tothe others, the current p.s.d. does not exhibit notches at mul-tiples of a characteristic frequency. For the other benchmarkssynthesized with the equal size library, the p.s.d. plots look sim-

Fig. 14. Theoretical p.s.d. of the � switching current for the “clip” bench-mark.

ilar to the ones shown in Figs. 13–15, since circuits have alower number of logic gates, with a prevalence of inverters andtwo-input gates, which have similar durations of switching cur-rents.

C. On-Chip Supply Voltages

In the previous sections, we have verified that the shot noisemodel for the digital switching currents leads to theoretical re-sults that agree with simulations.

Now we aim at deriving the on-chip noise voltages. From (43)and (46), we can estimate the rms value of the on-chip supplynoise. As an example, let us consider the switching currents inFig. 10(a), which have the following parameters:(i.e., ), , and .Moreover, let us consider the bond wire model in Fig. 6, with

and . With these parameters, the maincontribution to switching noise is due to the inductance. From(43), we obtain for the triangular current pulse,while (46) gives for the Erlangian pulse.

To simulate the effects of switching currents on supply volt-ages, we consider a network of parasitic elements similar to theone shown in Fig. 9, including interconnection parasitics to ex-ternal supplies and , and main parasitics due to the sub-strate, modeled as a resistance and a capacitance , whichaccounts for the substrate resistance and the well-to-substrate


Fig. 15. Simulated p.s.d. of the � switching current for (a) the “XOR5” and (b) the “rd84” benchmarks.

Fig. 16. Simulated p.s.d. of the � switching current for the benchmark circuit“rd84” synthesized with the equal size library (low density of logic transitions).

junction. As discussed in Section VI-D, the network givesrise to oscillations, which affect supply voltages and currents.

Figs. 17 and 18 show the simulated currents and on-chipvoltage supply waveforms, respectively, with low density oflogic transitions. Simulation results were obtained by addingthe parasitic network shown in Fig. 9 to the supply,and series resistance and inductance to the supply.Comparing Fig. 17 with Fig. 10(a), we can note that bondwire inductances have a twofold effect: current peaks becomelarger and supply currents do not return to zero after the digitaltransitions. From Fig. 18, it is apparent that on-chip supplyvoltages exhibit a bouncing effect, with rms values of 63 mVfor and 80 mV for , and peak values up to 400 mV.The rms values of on-chip voltages are in good agreement withtheoretical results.

The p.s.d. of the current and the on-chip supply areillustrated in Figs. 19 and 20, respectively. A peak at the res-onance frequency ( 1 GHz) can be observed. Moreover, thecharacteristic frequency previously observed in Fig. 13 disap-pears in Fig. 19 due to voltage bouncing effects.

Fig. 21 shows the theoretical p.s.d. of the on-chip voltagesupply, calculated as the ac component of

(52)

Fig. 17. Simulated digital switching currents � and � , with bonding in-ductance (low density of logic transitions).

Fig. 18. Simulated on-chip voltage supply waveforms (low density of logictransitions).

using: 1) (30) for the triangular current pulse model and 2) (33)for the Erlangian pulse model, together with the impedance for-mula (47).

By comparing the simulated and the calculated voltage p.s.d.in Figs. 20 and 21, we may conclude that the Erlangian cur-rent-pulse model gives the best approximation since it does notassume a finite current-pulse duration.


Fig. 19. Simulated p.s.d. of the � current, with bonding inductance (lowdensity of logic transitions).

Fig. 20. Simulated p.s.d. of the on-chip � supply (low density of logic tran-sitions).

Fig. 21. Theoretical p.s.d. of the on-chip � supply.

VIII. CONCLUSION

Digital switching currents can be modeled using a statisticalapproach. By considering switching activity of logic gates as astochastic process, with transition instants randomly and uni-formly distributed in time, we can model digital switching cur-rents as a stationary shot noise process, described with few pa-rameters: digital switching rate, duration of switching currentpulses, and average charge transferred during logic transitions.

The time duration of current pulses and the charge transferredduring logic switching may be obtained from transistor-levelsimulation of each logic gate of the library in time domain. This

kind of analysis requires few seconds of CPU time per logicgate.

The overall switching rate of the circuit can be estimatedfrom the time density of input logic transitions and the circuitschematic by calculating the switching probability of each node.The accuracy of the estimation is good if input bits are suffi-ciently random, and logic values 0 and 1 have equal probabilitywithin the circuit.

The amplitude distribution and the p.s.d. of the digitalswitching currents have been derived from the current-pulsewaveforms of single logic cells, and they can be calculatedfrom the parameters of the stochastic process.

Moreover, the effects of interconnections have been con-sidered. A resonant network, made of both off-chip andon-chip parasitics due to interconnections and substrate, leadsto peaks in the noise spectrum. Results can be exploited ina small-signal analysis to study switching noise propagationand its effects in different circuit nodes, thus obtaining a goodestimation of digital switching noise power and rms voltage.

The model of stationary shot noise for digital circuits has beenvalidated by comparing theoretical results with circuit simula-tions.

In sequential circuits driven by a clock signal, switching cur-rents can be described as a cyclostationary shot noise process.This will be the subject of a future paper.

ACKNOWLEDGMENT

The authors wish to thank three anonymous reviewers fortheir helpful comments.

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Giorgio Boselli received the Laurea and Ph.D.degrees in computer science from the University ofMilan, Milan, Italy, in 2003 and 2008, respectively.

From 2003 to 2007, he was a Research Assistantin the Department of Information Technologies,University of Milan. Since 2008, he has been aConsultant in the multichannel value-added services(VAS) area at Live Reply, Milan. He is also involvedin scouting and software development activities onset-top boxes (STBs) at Pirelli Broadband Solutions,Milan, where he deals with analysis and evaluation

of innovative technologies for STB, middleware porting, and with setup ofdemonstration sets. His current research interests include digital processing

of video signal, simulation and analysis of mixed-signal ICs, and models fordigital switching noise.

Gabriella Trucco received the Laurea and Ph.D.degrees in computer science from the University ofMilan, Milan, Italy, in 2002 and 2005, respectively.

During 2006, she was an Assistant Professorin the Department of Information Technologies,University of Milan, where she is currently aLecturer of the Web technologies course. Her re-search interests include the following: in the fieldof bioinformatics, the development of algorithmsand software for genome analysis, phylogeneticanalysis and haplotype inference; and in the VLSI

field, the development of power-aware logic synthesis and testing techniques,together with methodologies, models, and algorithms for the analysis, and thesimulation of crosstalk effects in mixed A/D CMOS ICs.

Valentino Liberali received the Laurea degree inelectronic engineering from the University of Pavia,Pavia, Italy, in 1986.

In 1986, he was granted a one-year scholarshipfrom SGS (now part of STMicroelectronics). From1987 to 1990, he was with the Italian NuclearPhysics Institute (INFN), where he was engaged inthe development and characterization of low-noiseelectronics for particle detectors. From 1990 to 2000,he was an Assistant Professor in the Department ofElectronics, University of Pavia. He is currently an

Associate Professor in the Department of Information Technologies, Universityof Milan, Milan. His research interests include the design of mixed-signalcircuits, A/D interfaces, sensor interfaces, computer-aided design for analogand mixed-signal ICs, mixed-signal testing, and radiation-tolerant IC design.

Properties of Digital Switching Currents in Fully CMOS Combinational Logic

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