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![Page 1: Promising Directions in Hardware Design Verification Shaz Qadeer Serdar Tasiran Compaq Systems Research Center.](https://reader038.fdocuments.in/reader038/viewer/2022110319/56649c765503460f9492ac70/html5/thumbnails/1.jpg)
Promising Directions in Hardware Design
VerificationShaz Qadeer
Serdar TasiranCompaq Systems Research
Center
![Page 2: Promising Directions in Hardware Design Verification Shaz Qadeer Serdar Tasiran Compaq Systems Research Center.](https://reader038.fdocuments.in/reader038/viewer/2022110319/56649c765503460f9492ac70/html5/thumbnails/2.jpg)
Hardware design verification
• Verification consumes more than 70% of resources– compute cycles – human cycles
• Time to market affected• Bugs remain undetected• Conventional simulation inadequate• Better approaches needed
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Design verification
• Check that RTL conforms to Spec
• Catch design errors early
Req/Spec
RTL
Netlist
Silicon
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What can be done?
Exhaustive Automatic Scalable
Simulation Model checking Compositional model checking
Coverage-guided simulation
Part1
Part2
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Formal design verification
Checker
RTL
Formal Spec
Yes
No
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Model checking
init bad
Clarke-Emerson 81, Queille-Sifakis 81Bryant 86, McMillan 92, …
Problem : State space explosion !
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Compositional model checking
• Abstraction followed by divide and conquer
• Case studies– STARI chip (Tasiran-Brayton 97)– Tomasulo’s algorithm (McMillan 97,
Henzinger-Qadeer-Rajamani 98)– Coherence protocol processor (Eiriksson 98)– VGI parallel DSP (Henzinger-Liu-Qadeer-
Rajamani 99)– Microarchitecture (Jhala-McMillan 01)
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regs
op
src
dst
P1 P2
FETCH EXECUTE WRITE-BACK
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regs
op
src
dst
opr res
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Opr Res
Ctrl
RegsPipeline =
Regs || Opr || Res || Ctrl
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isaRegs
op
src
dst
ISA
Correctness condition :P1.op = NOP P2.op = NOP regs = isaRegs
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Verification problem
Pipeline || ISA = Regs || Opr || Res || Ctrl || ISA
satisfies the invariant
I: P1.op = NOP P2.op = NOP regs = isaRegs
1. Abstraction2. Divide and conquer
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opr
res
isaRegs
op
src
dst
P1.dstP1.op
Opr’
Res’
Abstraction
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Abstraction
Regs || Opr || Res || Ctrl || ISA Opr’ || Res’
Regs || Opr’ || Res’ || Ctrl || ISA satisfies I
Regs || Opr || Res || Ctrl || ISA satisfies I
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Assume-guarantee reasoning
Regs || Opr || Res || Ctrl || ISA Opr’ || Res’
Regs || Opr’ || Res || Ctrl || ISA Res’
Regs || Opr || Res’ || Ctrl || ISA Opr’
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But…• Compositional techniques require
– manual effort– design+verification methodology
• Validation relies heavily on simulation– hand-written tests– random inputs
• Validation quality – hard to quantify– difficult to improve
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Coverage-guided simulation
Simulation
Coverageanalysis
Inputgeneration
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Coverage FSMState-Space
fabs
Implementation State-Space
fabs : Abstraction
mappingfabs
Non-covered state in
coverage module
Coverage-guided simulation
Path to be covered
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Coverage-guided simulation
Coverage FSMState-Space
Implementation State-Space
fabs : Abstraction
mappingfabs fabs
Path to be covered
One corresponding path in
implementation
Uncovered state
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Coverage module for pipeline
• Recommended practice: construct coverage modules along with design
P1.op = NOTP2.op = NOPsrc = P2.dst
P1.op = NOTP2.op = NOTsrc = P2.dst
P1.op = NOTP2.op = NOPsrc != P2.dst
P1.op = NOTP2.op = NOTsrc != P2.dst
P1.op = NOPP2.op = NOPsrc != P2.dst
P1.op = NOPP2.op = NOTsrc != P2.dst
P1.op = NOPP2.op = NOPsrc = P2.dst
P1.op = NOPP2.op = NOTsrc = P2.dst
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Coverage-guided simulation
Simulation
Coverageanalysis
Inputgeneration
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• Difficult SAT problem• Environment constraints
on implementation inputs: – Combinational: e.g. input to
processor must be legal instruction
– Sequential: e.g. branch delay slots
Input sequence generation
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Applications• DEC/Compaq
– Kantrowitz-Noack 96
• IBM – Benjamin et al. 99
• Intel– Ur-Yadin 99
• Synopsys– Ho et al. 00
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Conclusions• Ideally
– design+verification– compositional model checking– exhaustive and scalable
• Really– unstructured non-hierarchical designs– compositional reasoning difficult– make simulation smarter