Electrical and Computer EngineeringECE-C302

I. FPGA embedded Block RAM

Problem Statement Implement Random Access Memory as a block RAM generated by Core Generator tool.

Objective To study and implement embedded block RAM.

DeliverableDemonstrate a working RAM with interfaces to the FPGA board switches, button and LEDs.

Steps

1. Create new ISE project. Make sure that in Design Properties, Preferred Language is VHDL (not Verilog).

2. Add new source as Core Generator type (as opposed to vhdl module or UCF) name it “ram4_16”. Core Generator window will start.

3. In Core GeneratorFollow the generator selection windows, generate single-port 16X4 RAM, that is, 16 locations or depth = 16 (4-bit address) and 4-bit data or width = 4. Choose options that generate registered output, no reset, no initial data, no error flags.3.1 Detailed InstructionsPage 1: Select Native Next, Page 2: Select Minimum area Next, Page 3:

Page 4: next, Page 5: next and arrive at

Select generate

3.3 View HDL Instantiation TemplateTake a look at what are in the template file

4. Create new source, an entity called “my_ram”. It will contain ram4_16 as a component. The code is shown below.

In the UCF; connect din (data in), wea (write enable), addra (address) to switches and, douta to LEDs. Use wea<0> since it’s an std_logic_vector(0 downto 0); an example on some FPGA board

5. Implement and test my_ram.

II. Design and Implementation Exercise using RAM

Design a 4x16 RAM with a redundant unit storing a backup copy of the data. Connect LEDs to the outputs of the two 4x16 RAMs (they should be identical else errors have occurred). The entity declaration is the same as my_ram but with additional outputs, douta2: out std_logic_vector(3 downto 0); which are connected to LEDs.

III. FIFO (First-In First-Out) Queue

Problem Statement Implement a FIFO generated by Core Generator.Objective To study and implement a FIFO.DeliverableDemonstrate a working FIFO with interfaces to the S3 board switches, button and LEDs.Steps1. Create new ISE project2. Add new source from Core Generator called “fifo_416” (4-bit data, queue depth = 16)3. With Core Generator application generate a FIFO3.1 FIFO Generator Select Native3.2 Select Common Clock and next3.3 Select First-Word Fall-Through Write Width = 4 Write Depth = 16

3.4 Page 4 next page 5 select synchronous reset and next, page 6 select Next and arrive at a summary

Select Generate

3.5 View HDL Instantiation Template

4. Add new source, entity called “myfifo” (the code is shown below). In UCF connect din (data in), wr_en (write enable, rd_en (read enable), rst (reset) to switches; b1, b2 (single-step buttons); and dout (data out), full, empty (flags) to LEDs. Implement and test fifo. Note the latency (3 clock cycles or 3 single steps) before the empty flag goes low and the data appears at dout LEDs. Verify the FIFO functions.

5. Implementation

5.1 When start Empty is high?5.2 Set wr_en high, rd_en low, write until full is high “0001”, “0010”, … “1111”, “0001”, “0010”, “0011”, (It seems to have depth = 18).5.3 Set wr_en low, rd_en high, read until empty justify the values of dout and the depth of the queue.5.4 What is the FIFO latency? Answer: Three cycles before first write is valid at the output.

IV. A design exercise with FIFO (First-In First-Out) queue

Modify the FIFO design in previous section such that when user writes into the FIFO until the full flag is high, the contents are automatically read off at one second interval until the FIFO is empty.