PROJECT:CMX VME Testboard · st31 st32 st33 st34 r51 r52 r53 r54 st39 st40 st41 st42 r47 r48 r49...

15
VME J1/P1 VME ADDRESS BUFFER - USE 74LVT574WM DIR=0;DATA B TO A P3V3 VME DATA BUFFER BUFFER P3V3 P3V3 VME CONTROL (P2) (P6) GND JUMPERS FOR PROBE LAST_MODIFIED=Wed May 23 16:20:51 2012 Project file:cmx_vme_vat.cpm SYSTEM: SPB 16.3 1/15 MODULE:cmx_vme_vat 1/15 DATE: 11/04/2012 PCB by: <PCB_BY> Design by: Y. Ermoline PROJECT:CMX VME Testboard EDA-02515-V1-0 12 13 14 15 16 17 18 19 1 9 8 7 6 5 4 3 2 11 IC33 12 13 14 15 16 17 18 19 1 9 8 7 6 5 4 3 2 11 IC34 19 1 11 12 13 14 15 16 17 18 9 8 7 6 5 4 3 2 IC32 19 1 11 12 13 14 15 16 17 18 9 8 7 6 5 4 3 2 IC31 A14 D32 D1 C12 C10 A10 B22 B21 Z29 Z31 D8 D5 D21 D19 Z27 Z25 Z23 Z21 Z19 Z17 D25 D23 Z15 Z13 Z11 D4 D3 D7 D6 Z5 Z1 Z7 Z9 Z3 C13 D29 D27 B24 B25 B26 B27 B28 B29 B30 A22 A21 A20 D9 D17 D15 D13 D11 D10 A16 A12 A13 C8 C7 C6 C5 C4 C3 C2 C1 A8 A7 A6 A5 A4 A3 A2 A1 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 C11 B2 B1 A18 C14 A23 B19 B18 B17 B16 B3 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 A24 A25 A26 A27 A28 A29 A30 B31 P1 19 1 11 12 13 14 15 16 17 18 9 8 7 6 5 4 3 2 IC30 12 13 14 15 16 17 18 19 1 9 8 7 6 5 4 3 2 11 IC35 ST49 ST48 ST67 ST29 C26 C25 C24 C23 C22 C21 TP15 TP16 TP17 TP23 TP22 TP21 TP20 TP18 TP19 VCC=P5V VCC=P3V3 VCC=P3V3 VCC=P3V3 VCC=P3V3 VCC=P3V3 VCC=P3V3 02 01 160 2101 VMEADDR<23..1> 100NF 18 21 23 100NF 100NF 16 SOIC 100NF 100NF 14 10 100NF P3V3 A16 D08 MM74HC574WM 13 DS0* DS1* 1 2 3 4 6 7 8 A01 9 11 12 15 A09 A10 A11 A12 A13 A14 A16 17 19 20 22 A17 A18 A19 A21 A22 A23 5 6 D04 D05 D06 D07 74LVT245WM D00 D01 D02 BRDSEL_L D08 D09 8 9 10 11 12 13 3 D06 D07 DTACK* AS* A10 SOIC A20 MM74HC574WM D09 A11 A13 A21 AM4 AM3 D04 A09 AM1 AM0 A23 A22 A20 A19 A18 A17 A15 A14 A12 A08 A07 A06 A05 A04 A03 A02 A01 D15 D14 D13 D12 D11 D10 D05 D03 D02 D00 IACK* VMEDS 2 0 SOIC D03 SOIC AM5 VMERST_L VMEWR_L VMEDS1_L VMEDS0_L WRITE* D01 LWORD* BERR* SYSRESET* A07 A06 A05 A04 A03 A02 MM74HC574WM SOIC VMEDATA<15..0> 74LVT245WM 15 14 1 SOIC 7 74LVT245WM 4 D10 D11 D12 D13 D14 D15 A15 5 A08

Transcript of PROJECT:CMX VME Testboard · st31 st32 st33 st34 r51 r52 r53 r54 st39 st40 st41 st42 r47 r48 r49...

  • VME J1/P1

    VME ADDRESS BUFFER - USE 74LVT574WM

    DIR=0;DATA B TO A

    P3V3

    VME DATA BUFFER

    BUFFER

    P3V3

    P3V3

    VME CONTROL

    (P2)

    (P6)

    GND JUMPERS FOR PROBE

    LAST_MODIFIED=Wed May 23 16:20:51 2012

    Project file:cmx_vme_vat.cpm SYSTEM: SPB 16.3

    1/15MODULE:cmx_vme_vat 1/15

    DATE: 11/04/2012PCB by: Design by: Y. Ermoline

    PROJECT:CMX VME TestboardEDA-02515-V1-0

    1213141516171819

    1

    98765432

    11 IC33

    1213141516171819

    1

    98765432

    11 IC34

    19 1

    1112131415161718

    98765432

    IC32

    19 1

    1112131415161718

    98765432

    IC31

    A14

    D32D1

    C12C10A10

    B22B21

    Z29Z31

    D8D5

    D21D19Z27Z25Z23Z21Z19Z17

    D25D23

    Z15Z13

    Z11

    D4D3

    D7D6

    Z5

    Z1

    Z7Z9

    Z3

    C13

    D29D27

    B24B25B26B27B28B29B30

    A22A21A20

    D9

    D17D15D13D11D10

    A16

    A12A13

    C8C7C6C5C4C3C2C1A8A7A6A5A4A3A2A1

    B15B14B13B12

    B11B10B9B8B7B6B5B4

    C11

    B2B1

    A18

    C14A23B19B18B17B16

    B3

    C15C16C17C18C19C20C21C22C23C24C25C26C27C28C29C30A24A25A26A27A28A29A30

    B31

    P1

    19 1

    1112131415161718

    98765432

    IC30

    1213141516171819

    1

    98765432

    11 IC35

    ST49

    ST48

    ST67

    ST29

    C26

    C25

    C24

    C23

    C22

    C21

    TP15

    TP16

    TP17

    TP23

    TP22

    TP21

    TP20

    TP18

    TP19

    VCC=P5V

    VCC=P3V3

    VCC=P3V3VCC=P3V3

    VCC=P3V3

    VCC=P3V3

    VCC=P3V3

    02 01 160 2101

    VMEADDR

    100NF

    18

    21

    23

    100NF

    100NF

    16

    SOIC

    100NF

    100NF

    14

    10 100NF

    P3V3

    A16

    D08MM74HC574WM

    13

    DS0*DS1*

    1234

    678

    A01

    9

    1112

    15

    A09A10A11A12A13A14

    A16

    17

    1920

    22

    A17A18A19

    A21A22A23

    56

    D04D05D06D07

    74LVT245WM

    D00D01D02

    BRDSEL_L

    D08D09

    89

    10111213

    3

    D06D07

    DTACK*AS*

    A10

    SOIC

    A20

    MM74HC574WM

    D09

    A11

    A13

    A21

    AM4AM3

    D04

    A09

    AM1AM0A23A22

    A20A19A18A17

    A15A14

    A12

    A08A07A06A05A04A03A02A01D15D14D13D12D11D10

    D05

    D03D02

    D00

    IACK*

    VMEDS

    2

    0

    SOIC

    D03

    SOIC

    AM5

    VMERST_LVMEWR_L

    VMEDS1_LVMEDS0_L

    WRITE*

    D01

    LWORD*BERR*SYSRESET*

    A07A06A05A04A03A02

    MM74HC574WM

    SOIC

    VMEDATA74LVT245WM

    15141

    SOIC

    7

    74LVT245WM

    4

    D10D11D12D13D14D15

    A15

    5

    A08

    4 3

    A

    B

    D

    C

    E

    4 3 2 1

    B

    D

    C

    A

    E

    12

    TS/DEM

    SWITZERLAND1211 GENEVA 23for Nuclear ResearchEuropean Organization Project:

    Sheet:Module:

    GNDGND

    GND

    GND

    GND

    CPOE*

    D[0]

    D[7]D[6]

    D[1]D[2]

    D[5]D[4]D[3]

    Q[7]

    Q[0]Q[1]

    Q[6]Q[5]

    Q[2]Q[3]Q[4]

    CPOE*

    D[0]

    D[7]D[6]

    D[1]D[2]

    D[5]D[4]D[3]

    Q[7]

    Q[0]Q[1]

    Q[6]Q[5]

    Q[2]Q[3]Q[4]

    A4

    BBB

    TS

    01

    4567

    0123

    567 AAAA

    AAA

    DIR

    BB

    B

    E

    BB

    23

    A4

    BBB

    TS

    01

    4567

    0123

    567 AAAA

    AAA

    DIR

    BB

    B

    E

    BB

    23

    P1CONVME64X

    BBSY

    ACFAIL

    BG0OUT

    BCLR

    BG0IN

    BG1IN

    BG3OUT

    BG2OUT

    BG1OUT

    BG3IN

    BG2IN

    SYSCLK

    BERRLWORD

    IACKIN

    WRITE

    IACKAS

    DTACK

    MPRMCLK

    SERBSERA

    MSD

    RESPSBB

    MCTLMMD

    SBA

    GA1GA2

    GAPGA0

    GA3

    RSVULI/O

    GA4LI/I

    RSVB

    +V1

    VPC

    -V2-V1+V2

    5VSTDBY

    SYSRESETSYSFAIL

    IACKOUT

    D00D01

    D05D04D03D02

    D06

    D10D09D08D07

    D11

    D15D14D13D12

    A01

    A05A04A03A02

    A06

    A10A09A08A07

    A11

    A15A14A13A12

    A16

    A20A19A18A17

    A21

    AM2AM1AM0A23A22

    DS1DS0AM5AM4AM3

    BR0

    IRQ1BR3BR2BR1

    IRQ2

    IRQ6IRQ5IRQ4IRQ3

    IRQ7

    VPC

    RSVU

    RSVBRSVBRSVBRSVBRSVBRSVBRSVBRSVBRSVBRSVBRSVB

    A4

    BBB

    TS

    01

    4567

    0123

    567 AAAA

    AAA

    DIR

    BB

    B

    E

    BB

    23

    CPOE*

    D[0]

    D[7]D[6]

    D[1]D[2]

    D[5]D[4]D[3]

    Q[7]

    Q[0]Q[1]

    Q[6]Q[5]

    Q[2]Q[3]Q[4]

  • BOARD POWER ON RESET

    CLOCK

    (P1)

    (P1)

    DS GENERATION

    (VMM LOGIC)DETECTORLWORD & IACKILLEGAL AM CODES

    (P1)

    (P1)

    (MAKE NEW DELAY!)

    (74LCX157)

    (P1)

    BOARD

    (P9)

    (P6)

    (P6) (P1)

    TTC/XTL

    LAST_MODIFIED=Wed May 23 16:20:52 2012

    Project file:cmx_vme_vat.cpm

    MODULE:cmx_vme_vat 2/152/15

    DATE: 11/04/2012PCB by: Design by: Y. Ermoline

    EDA-02515-V1-0

    SYSTEM: SPB 16.3

    PROJECT:CMX VME Testboard

    C132

    1113

    12

    IC24

    65

    IC27

    89

    IC27

    1011

    IC27

    1213

    IC27

    43

    IC276

    5

    4

    2

    3

    1

    IC26

    12

    1

    13

    14

    15

    IC39

    810

    9

    IC24

    8

    1211654321

    IC28

    TP25

    TP24

    1 34

    IC47

    C79

    4

    1 3

    2

    QZ1

    4

    5

    2

    1

    IC23

    4

    5

    2

    1

    IC21

    C40

    ST65

    R18

    C34

    C36

    C37

    C81

    C39

    C35

    C32

    C33

    C38

    TP12

    TP11

    ST35

    ST36

    ST37

    ST38

    R55

    R56

    R57

    R58

    ST31

    ST32

    ST33

    ST34

    R51

    R52

    R53

    R54

    ST40

    ST39

    ST41

    ST42

    R48

    R47

    R50

    R49

    53627

    1

    IC22

    ST55ST56ST57ST58ST59

    ST2

    ST3

    ST4

    R43

    R45

    R44

    R46

    ST1

    53627

    1

    IC25

    ST64ST63ST62ST61ST60

    SW1

    ST50ST51ST52ST53ST54

    53627

    1

    IC20

    P3V3

    VCC=P3V3

    TPS3825-33DBVT

    SN74LS157D

    VCC=P5V

    VCC=P3V3

    SN74LS04D74ABT74D

    CD74HC30M

    4.7K

    4.7K

    4

    GEOADDR

    GEOADDR0

    P3V3

    VMEDS0_L

    VMEDS1_L

    VMEDS

    SOIC

    DS1100LZ-25+

    VCC=P3V3

    VMEDS_L

    AM4IACK*

    LWORD*AM0AM3

    AM5

    VCC=P5V

    4

    100NF

    P3V3

    P3V3

    100NF

    100NF

    SOICVCC=P5V

    SN74LS04D

    SN74LS04D

    VCC=P5V

    SN74LS04DSN74LS04D

    AM1

    SOIC

    CLK40SG_310_SCF40.0MHZ

    4.7K

    VCC=P3V3

    BRDDS

    PONRST

    DS1100LZ-25+

    4.7K

    CLOCK40DES1

    10

    4.7K

    4.7K

    7

    100NF

    100NF

    0

    100NF

    4.7K

    4.7K

    321

    4.7K

    4.7K

    56

    4.7K

    98

    4.7K

    4.7K

    4.7K

    65

    4.7K

    100NF

    100NF

    100NF

    100NF

    100NF

    100NF

    11

    4.7K

    4.7K

    P3V3

    MODID_L

    BERR*

    SOT23-5VDD=P3V3

    BERR_LED*VCC=P5V

    P5V

    VCC=P5VVCC=P5V

    DS1100LZ-25+

    VCC=P5V

    74HC38D

    74HC38D

    DTACK*

    AS*

    4 3

    A

    B

    D

    C

    E

    4 3 2 1

    B

    D

    C

    A

    E

    12

    TS/DEM

    SWITZERLAND1211 GENEVA 23for Nuclear ResearchEuropean Organization Project:

    Sheet:Module:

    IN

    TAP5TAP4TAP3TAP2TAP1

    IN

    TAP5TAP4TAP3TAP2TAP1

    IN

    TAP5TAP4TAP3TAP2TAP1

    GND

    GND

    OC

    GNDGNDGND

    GND

    Q

    CL

    D

    Q

    PR

    I1

    I0

    SE

    Y

    MUX

    OC

    Y*

    AB

    EDC

    GF

    H

    P2V5

    RESETRESET*MR*

    GND

    ST OUT

    VCC

    VCC

    NC7SZ00A

    BY

    VCC

    NC7SZ00A

    BY

    GND

    GNDGND

  • P3V3

    TTCDECS2

    TTC OPTICAL

    P3V3

    TTCDECS1

    P5V

    P3V3

    RECEIVER

    CLOCK BUFFER

    P5V

    DIR=0;DATA B TO A

    (P6)

    BLM21PG331SN1

    INDUCTOR

    LAST_MODIFIED=Wed May 23 16:20:53 2012

    Project file:cmx_vme_vat.cpm

    PROJECT:CMX VME TestboardSYSTEM: SPB 16.3

    PCB by: DATE: 11/04/2012

    3/153/15

    EDA-02515-V1-0

    Design by: Y. Ermoline

    MODULE:cmx_vme_vat

    19 1

    1112131415161718

    98765432

    IC43

    4

    13

    1

    2

    315

    14IC17

    R36

    R37

    R35

    R38

    C31

    C84

    4

    5

    2

    1

    IC18

    21L1

    C30

    R25

    R24

    R12 C7

    C129

    C130

    R20

    R19

    R21

    R22

    C1

    C2

    C3

    C128

    605958575655545352515049484746454443424140393837363534333231302928272625242322212019181716151413121110987654321

    J4

    605958575655545352515049484746454443424140393837363534333231302928272625242322212019181716151413121110987654321

    J3

    11

    201

    1213

    1516

    1819

    7

    4

    14

    17

    1098

    65

    32

    IC42

    654

    1514

    98

    23

    IC40

    10UF220K

    P5V

    CLK40DES2

    82

    74LVT245WM

    VCC=P3V3

    100NF

    P3V3

    BRCSTSTR2

    CLK40DES1P1

    CLK40DES1FBCLK40DES2P1

    CLK40DES2FB

    CLOCK40DES1

    L1ACCEPT

    BCNTRSTBRCST6BRCST7

    BRCST5BRCST4BRCST3BRCST2BRCSTSTR1

    QSH-030-01-X-D-A

    P3V3

    100NF

    IN_BIN

    DOUT2

    SUBADDR4

    P5V

    BLM21PG221SN1D

    100NF

    100NF

    P3V3

    CLK40DES2FB

    TTCCLKSE

    DOUT4

    100NF

    P3V3

    CLK40DES1CLK40DES1FB

    TTCRST_L

    RESET_B

    SOIC

    TTCSCL

    DQ1

    SUBADDR3

    SUBADDR7130

    P5V

    SN74LS123D

    SOIC

    STATUS1

    CLK40DES1P1

    CLK40DES2P1

    130

    130

    DOUTSTR

    SUBADDR1

    DOUT0

    00

    100NF

    TTCSDA

    DQ2

    100NF

    P5VP3V3

    IN_B

    10UF

    100NF

    130

    82

    82

    DQ0DQ3

    SUBADDR0SUBADDR2

    SUBADDR6

    DOUT5

    SUBADDR5

    IN

    00

    82

    RESET_B

    DOUT6

    TTCPD

    STATUS2

    DOUT7

    DOUT3DOUT1

    QSH-030-01-X-D-A

    4 3

    A

    B

    D

    C

    E

    4 3 2 1

    B

    D

    C

    A

    E

    12

    TS/DEM

    SWITZERLAND1211 GENEVA 23for Nuclear ResearchEuropean Organization Project:

    Sheet:Module:

    GND

    GND

    GND GND

    GND

    A4

    BBB

    TS

    01

    4567

    0123

    567 AAAA

    AAA

    DIR

    BB

    B

    E

    BB

    23

    C/R C

    Q

    QCL

    GND

    VCC

    A

    BY

    NC7SZ08

    GND

    12108

    3634323028

    4644424038

    48

    56545250

    5860

    1

    131197

    2523

    35

    27293133

    4543413937

    47

    55535149

    5759

    53

    1820

    262422

    141615

    21

    1719

    642

    12108

    3634323028

    4644424038

    48

    56545250

    5860

    1

    131197

    2523

    35

    27293133

    4543413937

    47

    55535149

    5759

    53

    1820

    262422

    141615

    21

    1719

    642

    PECL LVPECLMC100LVEL92

    VCCVCCQ0Q0

    Q1Q1

    LVCC

    Q2Q2

    VCC

    LVCC

    PVBB

    D0D0

    D1D1

    GND

    PVBBD2D2

    SDSD

    DD

    VCC

    HFBR2119TRX

  • P3V3

    USE 74LVT244WM

    HARDWIRED ID AND

    AFTER RESETMASTERMODE BITS

    DIR=0;DATA B TO A

    P3V3

    P3V3

    3V3

    3V3

    P3V3

    LAST_MODIFIED=Wed May 23 16:20:53 2012

    PCB by:

    4/15

    DATE: 11/04/2012

    4/15

    Project file:cmx_vme_vat.cpm SYSTEM: SPB 16.3

    Design by: Y. Ermoline

    EDA-02515-V1-0

    MODULE:cmx_vme_vat

    PROJECT:CMX VME Testboard

    ST5

    ST6

    ST7

    ST14ST15ST16

    ST8

    ST9ST10ST11ST12ST13

    12

    14

    16

    18

    1

    8

    6

    4

    2

    IC4

    19 1

    1112131415161718

    98765432

    IC5

    19 1

    1112131415161718

    98765432

    IC6

    19 1

    1112131415161718

    98765432

    IC3

    19 1

    1112131415161718

    98765432

    IC2

    3

    5

    7

    9

    1917

    15

    13

    11

    IC4

    TP13TP14

    TP1

    C75

    C77

    C74

    C73

    C76

    R76

    R74

    R72

    R70

    R68

    R66

    R82

    R80

    R78

    R64

    R62

    R60

    R77

    R63

    R61

    R59

    R67

    R65

    R81

    R79

    R69

    R71

    R73

    R75

    P3V3

    4.7K

    4.7K

    4.7K

    4.7K

    4.7K

    4.7K

    4.7K

    4.7K

    GND

    4.7K

    4.7K

    4.7K

    4.7K

    4.7K

    6

    DOUT3

    DOUT5DOUT4

    DOUT1

    4.7K

    4.7K

    4.7K

    4.7K

    4.7K

    4.7K

    P3V3

    DOUT2

    DOUT0

    SUBADDR5

    SUBADDR6

    SUBADDR7

    100NF

    100NF

    4.7K

    4.7K

    100NF

    100NF

    100NF

    4

    GEOADDR

    TTCRDY

    SUBADDR4

    SUBADDR1

    SUBADDR0

    SUBADDR2

    5 SUBADDR3

    GEOADDR1

    GEOADDR0

    DOUT7DOUT6

    4.7K

    4.7K

    VCC=P3V3

    VCC=P3V3

    74HCT244D

    GEOADDR2

    GEOADDR3

    74HCT244D

    4.7K

    10

    234

    67

    5

    74LVT245WM VCC=P3V3

    TTCSADDR

    SUBADDR7SUBADDR6SUBADDR5SUBADDR4SUBADDR3SUBADDR2SUBADDR1SUBADDR0

    32

    4567

    74LVT245WM VCC=P3V3

    TTCBRCST

    TTCBSTR2TTCBSTR1

    BRCST7BRCST6BRCST5BRCST4BRCST3BRCST2BRCSTSTR2BRCSTSTR1

    01234567

    SOIC

    VCC=P3V374LVT245WM

    TTCDOUT

    DOUT7DOUT6DOUT5DOUT4DOUT3DOUT2DOUT1DOUT0

    10

    23

    SOIC

    VCC=P3V374LVT245WM

    TTCDQ

    TTCBCRTTCL1ATTCRDY

    TTCDOSTR

    DQ3DQ2DQ1DQ0BCNTRSTL1ACCEPTSTATUS1DOUTSTR

    4 3

    A

    B

    D

    C

    E

    4 3 2 1

    B

    D

    C

    A

    E

    12

    TS/DEM

    SWITZERLAND1211 GENEVA 23for Nuclear ResearchEuropean Organization Project:

    Sheet:Module:

    GND

    GND

    GND

    Y1

    A2

    A

    Y

    3

    0

    3

    A

    Y

    2

    1

    Y

    OE

    A

    0

    A4

    BBB

    TS

    01

    4567

    0123

    567 AAAA

    AAA

    DIR

    BB

    B

    E

    BB

    23

    A4

    BBB

    TS

    01

    4567

    0123

    567 AAAA

    AAA

    DIR

    BB

    B

    E

    BB

    23

    A4

    BBB

    TS

    01

    4567

    0123

    567 AAAA

    AAA

    DIR

    BB

    B

    E

    BB

    23

    A4

    BBB

    TS

    01

    4567

    0123

    567 AAAA

    AAA

    DIR

    BB

    B

    E

    BB

    23

    Y1

    A2

    A

    Y

    3

    0

    3

    A

    Y

    2

    1

    Y

    OE

    A

    0

    GND

  • V6P3V3

    DIR=0;DATA B TO A

    TDOTDI

    TCKTMS

    JTAG

    J5

    P3V3

    P2V5

    P3V3

    VIRTEX 6

    P3V3

    J10

    J1 J6

    J7

    J8 J9

    VAT/ACE JTAG CHAIN PCB PATTERN

    J6

    J7

    J8

    J9

    J10J5

    J4

    J3

    J2

    J1

    J4J3

    J2

    LAST_MODIFIED=Wed May 23 16:20:54 2012

    Project file:cmx_vme_vat.cpm

    5/15

    EDA-02515-V1-0

    5/15

    DATE: 11/04/2012

    LAST_MODIFIED=Thu Jan 26 17:43:19 2012

    Design by: Y. Ermoline

    SYSTEM: SPB 16.3

    PROJECT:CMX VME TestboardMODULE:cmx_vme_vat

    PCB by:

    C140

    C138

    C142

    C147

    C148

    C149

    C144

    C139

    C145

    C151

    C146

    C143

    C137

    C136

    C150

    C141

    C127

    19 1

    1112131415161718

    98765432

    IC1

    C135

    R34

    R33

    R31

    R32

    R30

    R29

    C152

    R28

    24

    3642

    40

    33

    3813

    41

    44

    37

    9

    35

    34

    43

    501

    65432

    3130292827494847

    232221

    39

    32

    7

    2526

    4546

    810111214151617181920

    R94

    ST66

    4

    1 3

    2

    QZ2

    IC44

    9897

    102101

    8582

    8180

    IC44

    95

    33

    74

    72108

    7677

    41

    47484950515253565859606162636566

    42

    39

    43444567686970

    96

    93

    131140

    133

    3

    123

    79

    8978

    888786

    11811611410710512117

    117115113106104

    865

    138

    119

    13103

    121125130132134135137139141142

    4

    IC44

    ST22ST17

    ST23ST18

    ST26

    ST25

    ST21

    ST24ST20

    R83

    ST19

    R86

    R85

    R84

    1413121110987654321

    J2

    ACERST_L

    4.7K

    P3V3

    1KP3V3

    CFGMODECFGINIT_L

    CFGADDR

    12

    0

    ACECLK

    100NF

    SG_310_SCF20.0MHZ

    P3V3

    CFGTDICFGTCKCFGTMSCFGTDOACETDO

    ACETMSACETCKACETDI

    P3V3

    P3V3

    VCC=P3V3

    74LVT245WM1K

    P3V3

    MOLEX_87833

    100NF

    P3V3

    1K1K

    1K

    VATTDOACETDI

    TCK

    P3V3

    100NF

    100NF

    100NF

    100NF

    100NF

    100NF

    100NF

    100NF

    100NF

    100NF

    100NF

    100NF

    100NF

    100NF

    100NF

    100NF

    XCCACE-TQG144I

    TMS

    SOIC

    TDO

    MOLEX_55358-5029_EJECTOR

    6543210

    0123456789

    11

    1312

    10

    1K1K

    100NF

    1K1K1K1K

    XCCACE-TQG144I

    XCCACE-TQG144I

    VATTMS

    VATTDI

    VATTDO ACETDO

    ACETCK

    ACETMS

    TDI

    MPBRDY

    MPOE_L

    MPCE_L

    ACECLK

    MPDATA

    MPADDR

    14

    ACETDI

    VATTCK

    ERRLED_L

    15

    MPIRQ

    PONRST

    MPWE_L

    STATLED_L

    4 3

    A

    B

    D

    C

    E

    4 3 2 1

    B

    D

    C

    A

    E

    12

    TS/DEM

    SWITZERLAND1211 GENEVA 23for Nuclear ResearchEuropean Organization Project:

    Sheet:Module:

    GND

    P2V5

    GND

    A4

    BBB

    TS

    01

    4567

    0123

    567 AAAA

    AAA

    DIR

    BB

    B

    E

    BB

    23

    P2V5

    GND

    GND

    GND

    A01A00

    D15

    A03

    GND2GND1VCC2VCC1

    CSEL*

    CD2*CD1*OE*

    WAIT*WE*

    CE2*REG*CE1*

    A08A07

    A05A04

    A02

    A06

    D14

    D11D12D13

    D09D10

    DO6DO7D08

    DO4DO5

    DO3D02D01D00

    IOWR*

    IORD*

    VS1*RDY/BSYVS2*INPACK*BVD2BVD1

    WP

    A10A09

    RESET

    GND

    GND

    GND

    ST OUT

    VCC

    ACE

    GNDVCCLVCCH

    ACE

    CFGTDOCFGTMSCFGTCK

    TSTTDITSTTCKTSTTMS

    CFGTDI

    TSTTDO

    ACEMPA00

    MPA02MPA01

    MPA03

    MPA05MPA04

    MPD00

    MPA06

    MPD01MPD02

    MPD05

    MPD03MPD04

    MPD06MPD07MPD08

    MPD10MPD09

    MPD11MPD12

    MPD15

    MPD13MPD14

    CLKRESET*MPCE*MPWE*

    POR_RESETP0R_BYPASS

    MPOE*

    MPIRQ

    POR_TEST

    MPBRDY

    STATLED*

    ERRLED*

    CFD00CFD01CFD02CFD03

    CFD05CFD04

    CFD06

    CFD08CFD07

    CFD09CFD10CFD11CFD12CFD13

    CFD15CFD14

    CFA01CFA00

    CFA02CFA03CFA04CFA05CFA06CFA07CFA08CFA09CFA10

    CFCE1*CFREG*CFCE2*

    CFWAIT*CFWE*

    CFOE*CFCD1*CFCD2*CFRSVDCFGADDR0CFGADDR1CFGADDR2CFGMODEPINCFGINIT*CFGPROG*

    131197531

    42

    6

    108

    1214

  • (1V2)

    (3V3)

    6/15LAST_MODIFIED=Wed May 23 16:20:52 2012

    EDA-02515-V1-0

    Project file:cmx_vme_vat.cpm

    PROJECT:CMX VME TestboardMODULE:cmx_vme_vat

    Design by: Y. Ermoline

    6/15

    DATE: 11/04/2012PCB by:

    SYSTEM: SPB 16.3

    C66

    C44

    C48

    C60

    C72

    C56

    C57

    C58

    C53

    C52

    C54

    LD5

    R5

    4

    5

    2

    IC11

    K8

    K10J9

    H8

    G9

    G7

    M6

    L12

    F5

    E11

    B2

    B16B1A15

    A2

    T16

    T1

    R6

    R10

    P3

    P14

    M5

    M12

    L15

    L11

    K9

    K7

    K2

    J8H9

    G8

    G15

    G10

    F6

    F2

    E5

    E12

    C3

    C14

    B7

    B11

    A16

    A1

    T15

    IC13

    100NF

    VATTMS

    BGA

    VATPROG_B

    VATTDIVATTCK VATTDO

    XC3S200A-FTG256

    100NF

    16V

    GND

    GND

    220

    HSMG-C170

    100NF

    100NF

    100NF

    100NF

    100NF

    100NF

    100NF

    100NF

    100NF

    S3_VCCAUX

    S3_VCCINT

    S3_VCCAUX

    S3_VCCAUX

    4 3

    A

    B

    D

    C

    E

    4 3 2 1

    B

    D

    C

    A

    E

    12

    TS/DEM

    SWITZERLAND1211 GENEVA 23for Nuclear ResearchEuropean Organization Project:

    Sheet:Module:

    Y

    VCC

    NC7S14

    A

    GND

    GND

    GND

    VCCINT_K10

    GND_T16GND_A16GND_L15GND_G15GND_P14GND_C14GND_M12GND_E12GND_L11GND_B11GND_R10GND_G10GND_K9GND_H9GND_J8GND_G8GND_K7GND_B7GND_R6GND_F6GND_M5GND_E5GND_P3GND_C3GND_K2GND_F2GND_T1GND_A1

    VCCINT_J9VCCINT_G9VCCINT_K8VCCINT_H8VCCINT_G7

    VCCAUX_L12VCCAUX_E11VCCAUX_M6VCCAUX_F5

    TMS

    TDOTDITCK

    PROG_BDONE

  • (2V5)

    LAST_MODIFIED=Wed May 23 16:20:55 20127/15

    PCB by: DATE: 11/04/2012

    7/15

    SYSTEM: SPB 16.3

    Design by: Y. Ermoline

    MODULE:cmx_vme_vat

    PROJECT:CMX VME TestboardProject file:cmx_vme_vat.cpm

    EDA-02515-V1-0

    R42

    R41

    TP10

    TP9

    C67

    C65

    C64

    C62

    E8B9

    B5

    B13

    F9F7

    F10

    E6D6

    D12

    E9

    C4D5A3B3A4B4A5C5D7C6A6B6F8E7A7C7A8B8C8D8C9A9

    C10D9

    B10A10C11A11D10E10B12A12A14A13C12D11B15B14D13C13

    IC13

    CLK40

    130

    MODID_L

    VMEWR_L

    82

    P3V3

    S3_VCCO

    VMEADDR

    100NF

    100NF

    100NF

    100NF

    CMMDONEGEOADDR0

    GEOADDR

    ACECLK

    VMEDS_LPUDC_B

    CMMSDONE

    10

    11

    VMERST_L

    XC3S200A-FTG256

    BGA

    3

    2

    1

    0

    7

    6

    54

    98

    141513

    111210

    976

    6

    54

    4

    1

    2

    19

    21202322

    161718

    3

    8

    5

    4 3

    A

    B

    D

    C

    E

    4 3 2 1

    B

    D

    C

    A

    E

    12

    TS/DEM

    SWITZERLAND1211 GENEVA 23for Nuclear ResearchEuropean Organization Project:

    Sheet:Module:

    GND

    GND

    BANK 0

    IO_L01P_0IO_L01N_0

    IO_L02N_0IO_L02P_0/VREF_0IO_L03N_0IO_L03P_0IO_L04N_0IO_L04P_0IO_L05N_0IO_L05P_0IO_L06N_0/VREF_0IO_L06P_0IO_L07N_0IO_L07P_0IO_L08N_0IO_L08P_0IO_L09N_0/GCLK5IO_L09P_0/GCLK4IO_L10N_0/GCLK7IO_L10P_0/GCLK6IO_L11N_0/GCLK9IO_L11P_0/GCLK8IO_L12N_0/GCLK11IO_L12P_0/GCLK10IO_L13N_0IO_L13P_0IO_L14N_0/VREF_0IO_L14P_0IO_L15N_0IO_L15P_0IO_L16N_0IO_L16P_0IO_L17N_0IO_L17P_0IO_L18N_0IO_L18P_0IO_L19N_0IO_L19P_0IO_L20N_0/PUDC_BIO_L20P_0/VREF_0IP_0_D12IP_0_F10IP_0_F9IP_0_F7IP_0_D6IP_0_E6IP_0/VREF_0

    VCCO_0_B5VCCO_0_E8VCCO_0_B9VCCO_0_B13

  • (2V5)

    LAST_MODIFIED=Wed May 23 16:20:56 20128/15

    PCB by: DATE: 11/04/2012

    8/15

    Design by: Y. Ermoline

    Project file:cmx_vme_vat.cpm

    EDA-02515-V1-0

    SYSTEM: SPB 16.3

    MODULE:cmx_vme_vat

    PROJECT:CMX VME Testboard

    C49

    C55

    C63

    C59

    N15J15

    H12E15

    R16F12F11G12G11H10H11J10J11K11K12C16C15E13D14D16D15E14F13G13F14E16F15H13G14G16F16H15H16J14H14K16J16K15K14J12J13L14L16M15M16L13K13M13M14P16N16R15P15N13N14

    IC13

    S3_VCCO

    SP2V5IO

    BRDRST_LCMMSLDLLCMMRFEF

    SPCORE

    SPSERV

    CMMLDLLCMMPECNZCMMSDFEF

    TTCDQ

    TTCSADDR

    100NF

    100NF

    100NF

    100NF

    TTCBRCST

    TTCDOUT

    TTCRDY

    01

    21

    0

    0

    XC3S200A-FTG256

    BGA

    DLLRST_LCMMRFFF

    CMMSRFFFCMMDFEF

    TTCBSTR1

    CLRPEPLYBKEN

    TTCBSTR2

    CMMSDFFFCMMDFFFCMMSRFEF

    TTCDOSTR

    1

    23

    4

    5

    6

    7

    GND

    76

    54

    1

    03

    2

    7

    1

    32

    0

    6

    5

    4

    3

    2

    4 3

    A

    B

    D

    C

    E

    4 3 2 1

    B

    D

    C

    A

    E

    12

    TS/DEM

    SWITZERLAND1211 GENEVA 23for Nuclear ResearchEuropean Organization Project:

    Sheet:Module:

    GND

    BANK 1

    IP_L21P_1/VREF_1

    VCCO_1_N15VCCO_1_J15VCCO_1_E15VCCO_1_H12

    SUSPENDIP_L25P_1/VREF_1IP_L25N_1

    IP_L21N_1IP_L13P_1IP_L13N_1IP_L09P_1/VREF_1IP_L09N_1IP_L04P_1IP_L04N_1/VREF_1IO_L24P_1/A24IO_L24N_1/A25IO_L23P_1/A22IO_L23N_1/A23IO_L22P_1/A20IO_L22N_1/A21IO_L20P_1/A18IO_L20N_1/A19IO_L19P_1/A16IO_L19N_1/A17IO_L18P_1/A14IO_L18N_1/A15IO_L17P_1/A12IO_L17N_1/A13IO_L16P_1/A10IO_L16N_1/A11IO_L15P_1/IRDY1/RHCLK6IO_L15N_1/RHCLK7IO_L14P_1/RHCLK4IO_L14N_1/RHCLK5IO_L12P_1/RHCLK2IO_L12N_1/TRDY1/RHCLK3IO_L11P_1/RHCLK0IO_L11N_1/RHCLK1IO_L10P_1/A8IO_L10N_1/A9IO_L08P_1/A6IO_L08N_1/A7IO_L07P_1/A4IO_L07N_1/A5IO_L06P_1/A2IO_L06N_1/A3IO_L05P_1IO_L05N_1/VREF_1IO_L03P_1/A0IO_L03N_1/A1IO_L02P_1/LDC1IO_L02N_1/LDC0

    IO_L01N_1/LDC2IO_L01P_1/HDC

  • (3V3)

    M2M1M0

    VS2

    (3V3)

    (2V5)

    VS0VS1

    EDA-02515-V1-0

    Project file:cmx_vme_vat.cpm

    LAST_MODIFIED=Wed May 23 16:20:52 2012

    PCB by: DATE: 11/04/2012

    9/15

    SYSTEM: SPB 16.3

    Design by: Y. Ermoline

    MODULE:cmx_vme_vat

    PROJECT:CMX VME Testboard9/15

    C68

    C69

    C71

    C70

    4

    5

    2

    IC10

    R4

    LD4

    4

    5

    2

    IC9

    R3

    LD3

    4

    5

    2

    IC7

    R1

    LD1

    LD2

    R2

    4

    5

    2

    IC8

    TP3TP4

    TP5

    R40

    R39

    TP6TP7

    TP8

    TP2

    R8R4

    R12M9

    L8L7

    N5

    M8M7

    M11

    L9L10

    T14R14N12P13T13R13T12P12P11N11T11R11T10P10N10M10R9T9N9P9P8T8R7T7P7N8N7P6T5T6T4R5N6P5R3T3R2T2N4P4

    IC13

    3 2 1

    ST30

    C47

    C46

    C45

    C43

    S3_VCCAUX

    S3_VCCAUX

    100NF

    220XC3S200A-FTG256

    S3_VCCO

    S3_VCCAUX

    LEDS

    SP2V5IN

    100NF

    VMEDATA

    100NF

    100NF

    100NF

    GND

    CANIRQ

    TTCCLKSE

    01

    23

    765432102301

    4.7K

    4.7K

    GND

    100NF

    100NF

    100NF

    CANRST_LCANRD_L

    BGA

    TTCRST_LTTCPD

    TTCSDATTCSCLBRDSEL_L

    INIT_B

    BRDDS

    12

    0

    2

    3

    7

    6

    54

    1

    151413

    1110

    9

    8

    3

    1

    0

    220

    HSMY-C170

    220

    HSMY-C170

    HSMY-C170

    220

    HSMY-C170

    2

    4 3

    A

    B

    D

    C

    E

    4 3 2 1

    B

    D

    C

    A

    E

    12

    TS/DEM

    SWITZERLAND1211 GENEVA 23for Nuclear ResearchEuropean Organization Project:

    Sheet:Module:

    GND

    Y

    VCC

    NC7S14

    A

    Y

    VCC

    NC7S14

    A

    Y

    VCC

    NC7S14

    A

    Y

    VCC

    NC7S14

    A

    GND

    BANK 2

    IO_L03P_2/RDWR_BIO_L04N_2/VS0IO_L04P_2/VS1IO_L05N_2IO_L05P_2IO_L06N_2/D6IO_L06P_2/D7IO_L07N_2IO_L07P_2IO_L08N_2/D4IO_L08P_2/D5IO_L09N_2/GCLK13IO_L09P_2/GCLK12IO_L10N_2/GCLK15IO_L10P_2/GCLK14IO_L11N_2/GCLK1IO_L11P_2/GCLK0IO_L12N_2/GCLK3IO_L12P_2/GCLK2IO_L13N_2IO_L13P_2IO_L14N_2/MOSI/CSI_BIO_L14P_2IO_L15N_2/DOUTIO_L15P_2/AWAKEIO_L16N_2IO_L16P_2IO_L17N_2/D3IO_L17P_2/INIT_BIO_L18N_2/D1IO_L18P_2/D2IO_L19N_2IO_L19P_2IO_L20N_2/CCLKIO_L20P_2/D0/DIN/MISOIP_2_L7IP_2_L8IP_2/VREF_2_N5IP_2/VREF_2_M7IP_2/VREF_2_M8IP_2/VREF_2_L9IP_2/VREF_2_L10IP_2/VREF_2_M11

    VCCO_2_R4VCCO_2_R8VCCO_2_M9VCCO_2_R12

    IO_L02P_2/M2IO_L03N_2/VS2

    IO_L02N_2/CSO_BIO_L01P_2/M1IO_L01N_2/M0

    2 13

    GND

  • (2V5)

    LAST_MODIFIED=Wed May 23 16:20:55 2012

    PCB by: DATE: 11/04/2012

    10/15

    SYSTEM: SPB 16.3

    Design by: Y. Ermoline

    MODULE:cmx_vme_vat

    PROJECT:CMX VME TestboardProject file:cmx_vme_vat.cpm

    EDA-02515-V1-0

    10/15

    C50

    C42

    C51

    C61

    M2J5

    H2D2

    L5L6K5K6H7J7G6G5E4F4N3M4R1P2N2P1M1N1M3L4K4L3J4J6L1L2K3K1J2J1H3J3G2H1H6H5G3H4F1G1F3G4E3E2D1E1D4D3C2C1

    IC13

    LASRDIS

    MPIRQ

    BGA

    XC3S200A-FTG256

    MPWE_L

    MPCE_LMPOE_LCFGMODEALLDONEACERST_LGLDRST_LGLRRST_LLASDDIS

    MPBRDY

    GLDRDYGLRRDY

    PONRST

    S3_VCCO

    SP2V5IO

    SP2V5IN 109811

    12

    100NF

    100NF

    100NF

    100NF

    GND

    3

    2

    67

    2

    0

    8

    1

    1

    1

    95

    0

    15

    MPDATA

    23

    60

    4

    MPADDR

    CFGADDR

    12345

    11121314

    10

    4

    4 3

    A

    B

    D

    C

    E

    4 3 2 1

    B

    D

    C

    A

    E

    12

    TS/DEM

    SWITZERLAND1211 GENEVA 23for Nuclear ResearchEuropean Organization Project:

    Sheet:Module:

    GND

    BANK 3

    IO_L01P_3IO_L01N_3

    IO_L02N_3IO_L02P_3IO_L03N_3IO_L03P_3IO_L05N_3IO_L05P_3IO_L07N_3IO_L07P_3IO_L08N_3/VREF_3IO_L08P_3IO_L09N_3IO_L09P_3IO_L10N_3IO_L10P_3IO_L11N_3/LHCLK1IO_L11P_3/LHCLK0IO_L12N_3/IRDY2/LHCLK3IO_L12P_3/LHCLK2IO_L14N_3/LHCLK5IO_L14P_3/LHCLK4IO_L15N_3/LHCLK7IO_L15P_3/TRDY2/LHCLK6IO_L16N_3IO_L16P_3/VREF_3IO_L17N_3IO_L17P_3IO_L18N_3IO_L18P_3IO_L19N_3IO_L19P_3IO_L20N_3IO_L20P_3IO_L22N_3IO_L22P_3IO_L23N_3IO_L23P_3IO_L24N_3IO_L24P_3IP_L04N_3/VREF_3IP_L04P_3IP_L06N_3/VREF_3IP_L06P_3IP_L13N_3IP_L13P_3IP_L21N_3IP_L21P_3IP_L25N_3/VREF_3IP_L25P_3

    VCCO_3_D2VCCO_3_H2VCCO_3_M2VCCO_3_J5

  • ASTGREEN RED

    AERGREENALL

    GREENSTAT

    GREENCL40

    P5V

    P5V

    P5V

    YELLOWBRDS

    REDBERR

    P5VP5V

    P5V

    P5V

    P5V

    P5V

    LAST_MODIFIED=Wed May 23 16:20:54 2012

    PCB by: DATE: 11/04/2012

    11/15

    SYSTEM: SPB 16.3

    11/15

    Design by: Y. Ermoline

    Project file:cmx_vme_vat.cpm

    MODULE:cmx_vme_vat

    PROJECT:CMX VME TestboardEDA-02515-V1-0

    C83

    C82

    C28

    C80

    C131

    C29

    C41

    C133

    C134

    4

    13

    1

    2

    315

    14

    IC37

    12

    5

    9

    1011

    7 6 IC17

    12

    5

    9

    10

    11

    7 6 IC37

    R6

    R26

    R27

    LD11 LD6LD12

    4

    5

    2

    IC12

    4

    5

    2

    1

    IC45

    4

    5

    2

    1

    IC46

    R23

    LD10

    4

    5

    2

    IC41

    LD9

    R14 C9

    4

    5

    2

    1

    IC38

    R16

    LD74

    5

    2

    IC16

    R13 C8

    4

    5

    2

    1

    IC15

    R11

    R15

    LD8

    4

    5

    2

    1

    IC36

    C10R17

    BRDDS

    STATUS2P3V3

    P3V3

    100NF

    100NF

    HSMG-C170HSMS-C170HSMG-C170

    220

    220

    220

    STATLED_L

    HSMG-C170HSMG-C170

    SN74LS123D

    220K10UF

    P5V

    CLK40

    ERRLED_LALLDONE

    100NF

    100NF

    SOIC

    100NF

    100NF

    300

    300

    SN74LS123D

    SN74LS123D

    HSMY-C170

    300

    10UF220K

    P5V

    HSMS-C170

    300

    10UF220K

    P5V

    100NF

    100NF

    SOIC

    SOICBERR_LED*

    100NF

    4 3

    A

    B

    D

    C

    E

    4 3 2 1

    B

    D

    C

    A

    E

    12

    TS/DEM

    SWITZERLAND1211 GENEVA 23for Nuclear ResearchEuropean Organization Project:

    Sheet:Module:

    GND

    GNDGND

    GND

    GND

    VCC

    A

    BY

    NC7SZ08

    GND

    GND

    C/R C

    Q

    QCL

    C/R C

    Q

    QCL

    C/R C

    Q

    QCL

    Y

    VCC

    NC7S14

    A

    VCC

    A

    BY

    NC7SZ08

    VCC

    A

    BY

    NC7SZ08

    Y

    VCC

    NC7S14

    A

    VCC

    A

    BY

    NC7SZ08

    Y

    VCC

    NC7S14

    A

    VCC

    A

    BY

    NC7SZ08

  • SN74CB3T16211 SN74CB3T16211

    P2V5P2V5

    LAST_MODIFIED=Wed May 23 16:20:54 2012

    Project file:cmx_vme_vat.cpm

    PROJECT:CMX VME TestboardEDA-02515-V1-0

    DATE: 11/04/2012

    MODULE:cmx_vme_vat

    Design by: Y. Ermoline

    12/1512/15

    PCB by:

    SYSTEM: SPB 16.3

    21

    R88

    21

    R90

    21

    R89

    21

    R87

    C100

    C101

    C88

    C110

    C102

    C115

    C111

    C116

    C112

    C113

    C27

    56

    55

    45

    32

    46

    33

    47

    34

    48

    35

    50

    36

    51

    37

    52

    39

    53

    40

    42

    29

    43

    30

    44

    31

    54

    41

    11

    25

    10

    24

    9

    23

    7

    22

    6

    21

    5

    20

    4

    18

    3

    16

    14

    28

    13

    27

    12

    26

    2

    15

    IC19

    C78

    56

    55

    45

    32

    46

    33

    47

    34

    48

    35

    50

    36

    51

    37

    52

    39

    53

    40

    42

    29

    43

    30

    44

    31

    54

    41

    11

    25

    10

    24

    9

    23

    7

    22

    6

    21

    5

    20

    4

    18

    3

    16

    14

    28

    13

    27

    12

    26

    2

    15

    IC29

    B14A14

    J15K15

    C14B13

    D13D12

    B11C11

    J16H15

    G14F14

    H16G16

    E13E14

    H14G13

    B12C13

    A17B17

    D16C16

    C15B16

    A11A12

    A15A16

    E15D15

    G12F12

    F16F15

    E12D11

    IC14

    H19G19

    A20A19

    E18F19

    D17E17

    B18B19

    G18H18

    C18D18

    J17J18

    G17F17

    F20F21

    H20G21

    B22B23

    E20D21

    A24A25

    K19J20

    B21C21

    C19C20

    A21A22

    D20E19

    K17K18

    IC14

    12

    130

    130

    8282

    CLK2

    47

    100NF

    15

    CLK1

    GLRRDY

    GLDRDYV6_L1A

    V6_BCR

    BGA

    XC6VLX240T-1FFG784C

    NO

    6

    22 TTCBCR

    V6_VD

    NONONONONONONONONO

    SP2V5IN

    12

    SP2V5IOLASDDIS

    GLDRST_L2

    13

    VMEWR_LBRDSEL_L

    BRDDS

    TTCL1ACLK40DES2CLK40DES1

    SN74CB3T16211DGG

    VMEADDR

    100NF

    14

    TSSOP

    100NF

    LASRDIS

    11

    1211

    98

    19

    XC6VLX240T-1FFG784C

    V6_VA

    CLK40

    V6_CLK GND

    VMEDATA

    1098

    0123765415

    1314

    12

    V6_BDSV6_VW_LV6_BS_L

    11

    100NF

    100NF

    100NF

    100NF

    100NF

    100NF

    100NF

    100NF

    VCC=P2V5VCC=P2V5

    1314

    1011

    BGA

    9

    1

    21

    7

    36

    5

    11

    10

    8

    20

    2

    1

    3

    5

    8

    9

    5

    TSSOP

    SN74CB3T16211DGG

    CLK1CLK2

    100NF

    17

    4567

    4

    6789

    123

    123

    10 10

    12

    1314

    16 1615

    21

    13

    GNDGND

    76

    4

    18 18

    5

    1110

    8

    3210

    1514

    12

    9

    1920

    2223 23

    15

    16

    21

    15

    4

    17

    9

    18

    210

    14

    17

    1213

    20

    19

    4

    3

    211

    V6_L1AV6_BCR

    2223

    4 3

    A

    B

    D

    C

    E

    4 3 2 1

    B

    D

    C

    A

    E

    12

    TS/DEM

    SWITZERLAND1211 GENEVA 23for Nuclear ResearchEuropean Organization Project:

    Sheet:Module:

    GND

    P2V5

    P2V5

    P2V5

    Bank 26

    VCCO_26[5..1]

    IO_L0P_26IO_L0N_26IO_L1P_26IO_L1N_26IO_L2P_26IO_L2N_26IO_L3P_26IO_L3N_26IO_L4P_26IO_L4N_VREF_26IO_L5P_26IO_L5N_26IO_L6P_26IO_L6N_26IO_L7P_26IO_L7N_26IO_L8P_SRCC_26IO_L8N_SRCC_26IO_L9P_MRCC_26IO_L9N_MRCC_26IO_L10P_MRCC_26IO_L10N_MRCC_26IO_L11P_SRCC_26IO_L11N_SRCC_26IO_L12P_VRN_26IO_L12N_VRP_26IO_L13P_26IO_L13N_26IO_L14P_26IO_L14N_VREF_26IO_L15P_26IO_L15N_26IO_L16P_26IO_L16N_26IO_L17P_26IO_L17N_26IO_L18P_26IO_L18N_26IO_L19P_26IO_L19N_26

    GND

    GND

    GND

    2OE

    2A9

    2A122A112A10

    2A82A72A62A52A42A32A22A1

    1OE1A12

    1A91A8

    1A111A10

    1A71A6

    2B122B112B102B92B82B72B62B52B4

    2B12B22B3

    1B121B111B101B91B8

    1B41B31B2

    1A51A41A31A21A1

    1B7

    1B51B6

    1B1

    GND

    P2V5

    GND GND

    2OE

    2A9

    2A122A112A10

    2A82A72A62A52A42A32A22A1

    1OE1A12

    1A91A8

    1A111A10

    1A71A6

    2B122B112B102B92B82B72B62B52B4

    2B12B22B3

    1B121B111B101B91B8

    1B41B31B2

    1A51A41A31A21A1

    1B7

    1B51B6

    1B1

    Bank 25

    VCCO_25[5..1]

    IO_L0P_25IO_L0N_25IO_L1P_25IO_L1N_25IO_L2P_25IO_L2N_25IO_L3P_25IO_L3N_25IO_L4P_25IO_L4N_VREF_25IO_L5P_25IO_L5N_25IO_L6P_25IO_L6N_25IO_L7P_25IO_L7N_25IO_L8P_SRCC_25IO_L8N_SRCC_25IO_L9P_MRCC_25IO_L9N_MRCC_25IO_L10P_MRCC_25IO_L10N_MRCC_25IO_L11P_SRCC_25IO_L11N_SRCC_25IO_L12P_25IO_L12N_25IO_L13P_25IO_L13N_25IO_L14P_25IO_L14N_VREF_25IO_L15P_25IO_L15N_25IO_L16P_VRN_25IO_L16N_VRP_25IO_L17P_25IO_L17N_25IO_L18P_GC_25IO_L18N_GC_25IO_L19P_GC_25IO_L19N_GC_25

  • TEMPERATURE

    JTAG

    VCC0VCCAUX

    FPGA DECOUPLING CAPSDIODE

    MONITORSYSTEM

    M[2:0]=101JTAG MODE

    SPARE BANK

    CANBUS CONNECTOR

    VCCINT

    CONFIGURATION BANK

    VCCINT

    LAST_MODIFIED=Wed May 23 16:20:53 2012

    DATE: 11/04/2012

    13/15

    SYSTEM: SPB 16.3

    EDA-02515-V1-0

    13/15

    Design by: Y. Ermoline PCB by:

    Project file:cmx_vme_vat.cpm

    MODULE:cmx_vme_vat

    PROJECT:CMX VME Testboard

    C5

    C85

    C86

    C97

    C87

    C94

    C95

    C99

    C98

    C105

    C106

    C107

    C108

    C109

    C96

    C93

    C92

    C91

    C90

    C4

    C89

    C6

    C126

    IC14

    C10C9C8C7C6C5C4C3C2C1

    B10B9B8B7B6B5B4B3B2B1

    A10A9A8A7A6A5A4A3A2A1

    J1

    AB11AA11

    W11W10

    AD11AC11

    AC8AB8

    AC10AD10

    AA9AB9

    AC9AD8

    AA7AB7

    Y10AA10

    AH11AG12

    AF10AE10

    AH9AH10

    AG7AG8

    AF12AE12

    AE9AF9

    AG9AH8

    AF7AE8

    AF11AG11

    AD7AE7

    W8Y9

    IC14

    C104

    L3

    C103

    L2

    ST27

    ST28

    R93

    R8

    R91

    R10

    R7R9R92

    R14

    P13

    P14

    R13

    AD6

    J6

    Y6

    Y7

    AA6

    AB6

    G6

    M7

    C6D6

    F6

    M6

    N7

    T14T13

    AF6

    L6

    H6

    AG6

    AH6

    N13N14

    IC14

    330UF

    100NF

    22UF

    XC6VLX240T-1FFG784C

    CFGTDO

    AVSS

    10NF

    DXPDXN

    100NF

    BLM18HK102SN1

    100NF

    470NF

    8

    110

    4

    5

    67

    5

    0

    12

    CFGTMSCFGTCKCFGTDI

    AVDD

    BGA

    22UF

    100NF

    0

    40

    CLRPE

    CMMRFFFPLYBKEN

    GEOADDR0

    BGA

    456

    01234567

    0123

    GEOADDR

    VMEDATA

    CANIRQ

    GEOADDR3GEOADDR2

    DXNDXP

    CANRST_LCANRD_L

    ERNI_424189P5VP3V3

    100NF

    XC6VLX240T-1FFG784C

    VATPROG_BGEOADDR0GEOADDR1

    XC6VLX240T-1FFG784C

    100NF

    100NF

    100NF

    100NF

    100NF

    100NF

    100NF

    100NF

    100NF

    4.7K

    4.7K

    4.7K

    4.7K

    36

    SP2V5IO

    4.7K

    1

    BRDRST_L

    SP2V5IN

    GEOADDR

    GLRRST_L

    CMMSDFEF

    SPSERV

    DLLRST_L

    SPCORE

    CMMRFEF

    CMMSDFFFCMMSRFEFCMMPECNZ

    CMMSLDLLCMMDFEFCMMLDLL

    CMMSRFFFCMMDFFF

    100NF

    100NF

    BLM18HK102SN1

    CMMDONECFGINIT_L

    330

    4.7K

    100NF

    100NF

    100NF

    100NF

    4 3

    A

    B

    D

    C

    E

    4 3 2 1

    B

    D

    C

    A

    E

    12

    TS/DEM

    SWITZERLAND1211 GENEVA 23for Nuclear ResearchEuropean Organization Project:

    Sheet:Module:

    P1V0P2V5

    A

    A

    789

    65

    1

    34

    2

    10

    C

    C

    789

    65

    1

    34

    2

    10

    B10

    B2

    43

    1

    9

    65

    87

    GND

    GND

    Bank 35

    VCCO_35[6..1]

    IO_L0P_35IO_L0N_35IO_L1P_35IO_L1N_35IO_L2P_SM0P_35IO_L2N_SM0N_35IO_L3P_SM1P_35IO_L3N_SM1N_35IO_L4P_35IO_L4N_VREF_35IO_L5P_SM2P_35IO_L5N_SM2N_35IO_L6P_SM3P_35IO_L6N_SM3N_35IO_L7P_SM4P_35IO_L7N_SM4N_35IO_L8P_SRCC_35IO_L8N_SRCC_35IO_L9P_MRCC_35IO_L9N_MRCC_35IO_L10P_MRCC_35IO_L10N_MRCC_35IO_L11P_SRCC_35IO_L11N_SRCC_35IO_L12P_SM5P_35IO_L12N_SM5N_35IO_L13P_SM6P_35IO_L13N_SM6N_35IO_L14P_35IO_L14N_VREF_35IO_L15P_SM7P_35IO_L15N_SM7N_35IO_L16P_VRN_35IO_L16N_VRP_35IO_L17P_35IO_L17N_35IO_L18P_GC_35IO_L18N_GC_35IO_L19P_GC_35IO_L19N_GC_35

    GND

    P2V5

    P1V0

    +

    GND

    P1V0

    GND

    P1V0P2V5

    GND

    Power

    GND[169..0]

    VCCAUX[12..0]VCCINT[40..0]

    MGTAVTT[8..0]MGTAVCC[9..0]

    GND

    Bank 0INIT_B_0DONE_0M1_0M2_0HSWAPEN_0PROGRAM_B_0M0_0AVSS_0AVDD_0VP_0VREFP_0VN_0VREFN_0DXP_0DXN_0VBATT_0DIN_0RDWR_B_0CSI_B_0DOUT_BUSY_0CCLK_0TDO_0TCK_0TMS_0TDI_0VFS_0

    VCCO_0[1..2]

  • VCCO BANK14

    VCCO BANK15

    Project file:cmx_vme_vat.cpm

    EDA-02515-V1-0

    LAST_MODIFIED=Wed May 23 16:20:55 2012

    PROJECT:CMX VME Testboard

    Design by: Y. Ermoline

    14/15MODULE:cmx_vme_vat

    SYSTEM: SPB 16.3

    14/15

    DATE: 11/04/2012PCB by:

    C120

    C121

    C123

    C124

    C125

    C114

    C117

    C119

    C118

    C122

    ST43ST44ST45ST46ST47

    F7G7

    D10C10

    E8F9

    G11F10

    D8E9

    H13J13

    A7B7

    A10A9

    B8C8

    K7L7

    K9K10

    J7J8

    J11J10

    H8H9

    D7E7

    G8G9

    B9C9

    J12K13

    H11H10

    F11E10 IC14

    AH15AH16

    Y13AA12

    AH13AH14

    AD13AE14

    AB14AC14

    AF14AG13

    AB13AA14

    W12Y12

    AB12AC13

    Y17AA17

    W16Y15

    AA16AB17

    AA15Y14

    AD16AE15

    AB16AC16

    AF16AG16

    AE17AD17

    AD15AC15

    AG14AF15

    AE13AD12 IC14

    AF26AG26

    AB27AB26

    AC25AD25

    AA24AA25

    AE28AE27

    AG27AH28

    AG28AF27

    AC28AB28

    AD28AD27

    AB22AA22

    AE23AD23

    AH23AG23

    AC24AB24

    AG24AH24

    AE24AF24

    AH26AH25

    AC26AD26

    AB23AC23

    AE25AF25

    AA26AA27 IC14

    Y23W23

    P21P22

    Y25Y24

    W27Y27

    Y28W28

    W26V26

    W25V25

    V28U28

    T27U27

    T21T22

    R22R23

    U22U21

    V24U24

    T24T25

    R20P20

    Y22W22

    R24R25

    V23U23

    U26T26

    R27R28 IC14

    K27L26

    L21L22

    J28K28

    M23M24

    K25J25

    L20M19

    J26J27

    K24J23

    H25H26

    N23P23

    N20N21

    P26P25

    N24N25

    N28M28

    L24L25

    P28P27

    M27L27

    M26N26

    M22M21

    K22K23 IC14

    B27B28

    J21J22

    A26A27

    E24D25

    E22F22

    D22C23

    B26C25

    H23G23

    B24C24

    G28H28

    D26C26

    G27G26

    F27E27

    F26F25

    E23D23

    D28E28

    H24G24

    D27C28

    E25F24

    G22H21 IC14

    AD21AC20

    AD20AE20

    AG21AF20

    Y18W18

    AA21AB21

    AF22AE22

    AG22AF21

    V20V19

    AD22AC21

    AH19AG19

    AG18AH18

    AH20AH21

    AB18AC18

    AC19AB19

    AD18AE18

    AG17AF17

    AA19Y19

    Y20AA20

    AF19AE19

    W21V21 IC14

    NONO

    NONONONONO

    NONONO

    100NF

    100NF

    3

    54

    TS<5..1>

    12

    ST<5..1>

    54321

    TS<5..1>

    XC6VLX240T-1FFG784C

    ST<5..1>

    2

    5

    5

    1

    4

    4

    3

    32

    1

    BGA

    4 3

    A

    B

    D

    C

    E

    4 3 2 1

    B

    D

    C

    A

    E

    12

    TS/DEM

    SWITZERLAND1211 GENEVA 23for Nuclear ResearchEuropean Organization Project:

    Sheet:Module:

    Bank 36

    VCCO_36[5..1]

    IO_L0P_36IO_L0N_36IO_L1P_36IO_L1N_36IO_L2P_36IO_L2N_36IO_L3P_36IO_L3N_36IO_L4P_36IO_L4N_VREF_36IO_L5P_36IO_L5N_36IO_L6P_36IO_L6N_36IO_L7P_36IO_L7N_36IO_L8P_SRCC_36IO_L8N_SRCC_36IO_L9P_MRCC_36IO_L9N_MRCC_36IO_L10P_MRCC_36IO_L10N_MRCC_36IO_L11P_SRCC_36IO_L11N_SRCC_36IO_L12P_VRN_36IO_L12N_VRP_36IO_L13P_36IO_L13N_36IO_L14P_36IO_L14N_VREF_36IO_L15P_36IO_L15N_36IO_L16P_36IO_L16N_36IO_L17P_36IO_L17N_36IO_L18P_36IO_L18N_36IO_L19P_36IO_L19N_36

    Bank 34

    VCCO_34[5..1]

    IO_L19N_VRP_34IO_L19P_VRN_34

    IO_L18P_A17_34IO_L18N_A16_34

    IO_L17N_A18_34IO_L17P_A19_34IO_L16N_A20_34

    IO_L15N_A22_34IO_L16P_A21_34

    IO_L15P_A23_34IO_L14N_VREF_A24_34IO_L14P_A25_34

    IO_L13P_A01_D17_34IO_L13N_A00_D16_34

    IO_L12N_A02_D18_34IO_L12P_A03_D19_34IO_L11N_SRCC_34

    IO_L10P_MRCC_34IO_L10N_MRCC_34IO_L11P_SRCC_34

    IO_L9P_MRCC_34IO_L9N_MRCC_34

    IO_L8N_SRCC_34IO_L8P_SRCC_34IO_L7N_A04_D20_34

    IO_L6N_A06_D22_34IO_L7P_A05_D21_34

    IO_L6P_A07_D23_34IO_L5N_A08_D24_34IO_L5P_A09_D25_34

    IO_L4P_A11_D27_34IO_L4N_VREF_A10_D26_34

    IO_L3N_A12_D28_34IO_L3P_A13_D29_34IO_L2N_A14_D30_34

    IO_L1N_GC_34IO_L2P_A15_D31_34

    IO_L1P_GC_34IO_L0N_GC_34IO_L0P_GC_34

    Bank 24

    VCCO_24[5..1]

    IO_L19P_24IO_L19N_24

    IO_L18P_24IO_L18N_24

    IO_L17N_VRP_24IO_L17P_VRN_24IO_L16N_CSO_B_24IO_L16P_RS0_24IO_L15N_RS1_24

    IO_L14N_VREF_FOE_B_MOSI_24IO_L15P_FWE_B_24

    IO_L14P_FCS_B_24

    IO_L13P_D1_FS1_24IO_L13N_D0_FS0_24

    IO_L12N_D2_FS2_24IO_L12P_D3_24IO_L11N_SRCC_24

    IO_L10P_MRCC_24IO_L10N_MRCC_24IO_L11P_SRCC_24

    IO_L9P_MRCC_24IO_L9N_MRCC_24

    IO_L8N_SRCC_24IO_L8P_SRCC_24IO_L7N_D4_24

    IO_L6N_D6_24IO_L7P_D5_24

    IO_L6P_D7_24IO_L5N_D8_24IO_L5P_D9_24

    IO_L4P_D11_24IO_L4N_VREF_D10_24

    IO_L3P_D13_24IO_L3N_D12_24

    IO_L2N_D14_24

    IO_L1N_GC_24IO_L2P_D15_24

    IO_L1P_GC_24IO_L0N_GC_24IO_L0P_GC_24

    P2V5

    P2V5

    GNDP2V5

    Bank 14

    VCCO_14[5..1]

    IO_L19N_14IO_L19P_14IO_L18N_14IO_L18P_14IO_L17N_14IO_L17P_14IO_L16N_14IO_L16P_14IO_L15N_14IO_L15P_14IO_L14N_VREF_14IO_L14P_14IO_L13N_14IO_L13P_14IO_L12N_VRP_14IO_L12P_VRN_14IO_L11N_SRCC_14IO_L11P_SRCC_14IO_L10N_MRCC_14IO_L10P_MRCC_14IO_L9N_MRCC_14IO_L9P_MRCC_14IO_L8N_SRCC_14IO_L8P_SRCC_14IO_L7N_14IO_L7P_14IO_L6N_14IO_L6P_14IO_L5N_14IO_L5P_14IO_L4N_VREF_14IO_L4P_14IO_L3N_14IO_L3P_14IO_L2N_14IO_L2P_14IO_L1N_14IO_L1P_14IO_L0N_14IO_L0P_14

    GNDBank 15

    VCCO_15[5..1]

    IO_L0P_15IO_L0N_15IO_L1P_15IO_L1N_15IO_L2P_SM8P_15IO_L2N_SM8N_15IO_L3P_SM9P_15IO_L3N_SM9N_15IO_L4P_15IO_L4N_VREF_15IO_L5P_SM10P_15IO_L5N_SM10N_15IO_L6P_SM11P_15IO_L6N_SM11N_15IO_L7P_SM12P_15IO_L7N_SM12N_15IO_L8P_SRCC_15IO_L8N_SRCC_15IO_L9P_MRCC_15IO_L9N_MRCC_15IO_L10P_MRCC_15IO_L10N_MRCC_15IO_L11P_SRCC_15IO_L11N_SRCC_15IO_L12P_SM13P_15IO_L12N_SM13N_15IO_L13P_SM14P_15IO_L13N_SM14N_15IO_L14P_15IO_L14N_VREF_15IO_L15P_SM15P_15IO_L15N_SM15N_15IO_L16P_VRN_15IO_L16N_VRP_15IO_L17P_15IO_L17N_15IO_L18P_15IO_L18N_15IO_L19P_15IO_L19N_15

    Bank 16

    VCCO_16[5..1]

    IO_L0P_16IO_L0N_16IO_L1P_16IO_L1N_16IO_L2P_16IO_L2N_16IO_L3P_16IO_L3N_16IO_L4P_16IO_L4N_VREF_16IO_L5P_16IO_L5N_16IO_L6P_16IO_L6N_16IO_L7P_16IO_L7N_16IO_L8P_SRCC_16IO_L8N_SRCC_16IO_L9P_MRCC_16IO_L9N_MRCC_16IO_L10P_MRCC_16IO_L10N_MRCC_16IO_L11P_SRCC_16IO_L11N_SRCC_16IO_L12P_VRN_16IO_L12N_VRP_16IO_L13P_16IO_L13N_16IO_L14P_16IO_L14N_VREF_16IO_L15P_16IO_L15N_16IO_L16P_16IO_L16N_16IO_L17P_16IO_L17N_16IO_L18P_16IO_L18N_16IO_L19P_16IO_L19N_16

    Bank 23

    VCCO_23[5..1]

    IO_L0P_23IO_L0N_23IO_L1P_23IO_L1N_23IO_L2P_23IO_L2N_23IO_L3P_23IO_L3N_23IO_L4P_23IO_L4N_VREF_23IO_L5P_23IO_L5N_23IO_L6P_23IO_L6N_23IO_L7P_23IO_L7N_23IO_L8P_SRCC_23IO_L8N_SRCC_23IO_L9P_MRCC_23IO_L9N_MRCC_23IO_L10P_MRCC_23IO_L10N_MRCC_23IO_L11P_SRCC_23IO_L11N_SRCC_23IO_L12P_VRN_23IO_L12N_VRP_23IO_L13P_23IO_L13N_23IO_L14P_23IO_L14N_VREF_23IO_L15P_23IO_L15N_23IO_L16P_23IO_L16N_23IO_L17P_23IO_L17N_23IO_L18P_23IO_L18N_23IO_L19P_23IO_L19N_23

  • (3V3)

    1V0 - 3.7A

    2V5 - 4.5A

    (2V5)2V5 - 2.3A

    1V2 - 0.4A

    VME J2/P2

    (1V2)

    3V3 - 1.0A

    Project file:cmx_vme_vat.cpm

    DATE: 11/04/2012Design by: Y. Ermoline

    EDA-02515-V1-0

    MODULE:cmx_vme_vat 15/15

    PCB by:

    PROJECT:CMX VME TestboardSYSTEM: SPB 16.3

    15/15LAST_MODIFIED=Wed May 23 16:20:51 2012

    D32

    Z11Z9Z7Z5Z3Z1D30D29D28D27

    A10

    D26D25D24D23D22D21D20D19D18D17

    A9

    D16D15D14D13D12D11D10D9D8D7

    A8

    D6D5D4D3D2D1C32C31C30C29

    A7

    C28C27C26C25C24C23C22C21C20C19

    A6C18C17C16C15C14C13C12

    C11C10C9

    A5

    C8C7C6C5C4C3C2C1

    A32A31

    A4

    A30A29A28A27A26A25A24A23A22A21

    A3

    A20A19A18A17A16A15A14A13A12

    Z31Z29Z27Z25Z23Z21Z19Z17Z15Z13

    A11

    A2A1

    B3

    B30B29B28B27B26B25B24B23B21B20B19B18B17B16B15B14B11B10B9B8B7B6B5B4

    P2

    R97

    R96

    R99

    R100

    FH4

    C18

    C17

    6 53

    24

    1

    IC51TP29

    FH3

    FH1

    FH2

    ST68

    C13

    C14

    C11

    C12

    C15

    C16

    C19

    6 53

    24

    1

    IC49TP27

    6 53

    24

    1IC48

    R101

    TP26

    TP28

    TP30

    FH5

    C20

    R98

    6 53

    24

    1

    IC50

    R95

    6 53

    24

    1

    IC52

    S3_VCCINT

    S3_VCCO

    S3_VCCAUX

    PTH05050W

    100UF

    100UF

    VCC=P5V02 01 160 2101

    PTH05050W

    100UF

    100UF

    100UF

    100UF

    100UF

    15K

    PTH05050W

    PTH05050W

    100UF

    100UF

    698

    GND

    P3V3P5V

    2.2K

    2.2K

    100UF PTH05050W

    2.4K

    36K

    510

    4 3

    A

    B

    D

    C

    E

    4 3 2 1

    B

    D

    C

    A

    E

    12

    TS/DEM

    SWITZERLAND1211 GENEVA 23for Nuclear ResearchEuropean Organization Project:

    Sheet:Module:

    GND

    P2CONVME64X

    UDUDUDUD

    UDUDUDUDUD

    UDUDUDUDUD

    UD

    UDUDUDUD

    UD

    UDUDUDUD

    UD

    A24RETRY

    UDUDUDUD

    UD

    UDUD

    A25A26A27A28

    D19D18D17D16A31A30A29

    D20D21D22

    D29D28D27D26D25D24D23

    D30D31

    UDUDUD

    UD

    UDUDUDUD

    UD

    UDUD

    UDUDUDUDUDUDUDUDUDUDUDUDUDUD

    UDUDUDUD

    UD

    UDUDUDUD

    UD

    UDUDUDUDUDUDUDUDUDUDUDUDUDUDUDUDUDUDUDUDUDUDUDUDUDUD

    UDUDUDUD

    UDUDUDUD

    UD

    UDUDUDUD

    UD

    UDUD

    VPC

    UD

    F-HOLDER

    VIN VOUT VO_ ADJUST

    GND

    INHIBIT*TRACK

    P1V0

    F-HOLDER

    F-HOLDER

    F-HOLDER

    VIN VOUT VO_ ADJUST

    GND

    INHIBIT*TRACK

    VIN VOUT VO_ ADJUST

    GND

    INHIBIT*TRACK

    F-HOLDER

    P2V5

    VIN VOUT VO_ ADJUST

    GND

    INHIBIT*TRACK

    VIN VOUT VO_ ADJUST

    GND

    INHIBIT*TRACK

    cmx_vme_vat(1-15)page1 (1)page2 (2)page3 (3)page4 (4)page5 (5)page6 (6)page7 (7)page8 (8)page9 (9)page10 (10)page11 (11)page12 (12)page13 (13)page14 (14)page15 (15)