Project Report

8-bit Microprocessor Design

8-BIT PIPELINED MICROPROCESSOR

DESIGN

PROJECT REPORT UNDER THE GUIDANCE OF

DR.M.B.SRINIVASBy

A M VENKATESHWARA RAO (200741002)M KRANTHI KUMAR (200741013)

M.Tech. (VLSI & Embedded Systems)

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Acknowledgements

We wish to express our thanks to Mr.Ravindra and

MR.Srihari for providing us the tools, and the environment required

to complete our project.

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Index

1. Acknowledgements 3

2. Abstract 4

3. Outline of Microprocessor. 5

4. Basic block diagram explanation 6-8

Instruction fetch

Instruction Decoder

Execution Block

Write Back logic

5. Pipelining Process and Instruction Format 9

6. Instruction Types 10

7. Instruction Set Division and Opcodes 11-13

8. List of programs coded in VERILOG 14

9. Sample program for generating Fibonacci series. 15

10. Functional Simulation Waveforms for the above program 16-18

11. Post Layout Simulation Waveforms for the same

program 19-23

12. Synthesis reports 24-25

ALU

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Instruction Decoder Total Processor

11. Maximum Clock Frequency calculation 26

12.Synthesis Diagrams 27-29

ABSTRACT

A description of an 8 bit microprocessor is presented in this

report. The objective is to design a general purpose 8 bit RISC

processor which is pipelined and implement on FPGA. The design has 4

stage pipelined architecture and 38 user instructions to program the

processor. The ROM and RAM are used here for only testing purposes.

The components like ALU, control Unit, Write Back logic, Register File

are al coded in verilog. The target device of the processor is Altera’s

Cyclone II family FPGA (EP20C484C7). The design is progressed with all

the coding of building blocks and finally integration of the whole

design. The code is written and compiled in Active HDL 6.3. Synthesis

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is performed in Altera Quartus II. The synthesized netlist is simulated

for timing in Modelsim 6.1.

Outline of MicroProcessorOutline of MicroProcessor

• 8-bit Data Operations ( 8-bit ALU )

• Load Store Architecture.

• Harvard Architecture.

• Pipelined – 4 stage.

• 10-bit Address bus.

• 24-bit Uniform instruction Length.

• 8 General Purpose Registers.

• 3-bit PSW (Carry, Zero, Parity).

• 1 Special Register- PC.

• 38 Instructions are provided for the User.

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CodeMem

PC

InstructionDecoder

Reg File

ALU

WriteBack

RAM

InstructionFetch

InstructionDecode, Operand

Fetch

Execute

WriteBack

PSW

Basic Block DiagramBasic Block Diagram

Instruction Fetch Block:

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10 bit address in the instruction

10 bit address from PC

Select line from Instruction Decoder

PC

MUX 2X1

clock

Adder+1

10 bit address to ROM


For a branch instruction the address in the instruction is passed to the mux and the select line is set such that the branch address goes to the ROM.i.e., address_to_ROM=branching addressand then the new input to the PC becomes branching address+1;

If there is no branching then select line is set such that the regular address goes to the ROM.i.e., address_to_ROM=address_to_ROM+1;

The PC Block just passes the input to the output on every positive clock edge.

Instruction Decoder:

It generates the necessary control signals for the ALU, Write back logic, RAM, ROM and the multiplexers for proper data flow.It also checks the dependency ( because this is pipelining)

Dependencies:

EXAMPLE1: add r0,r1 Sub r0,r2

While the first instruction is being executed the second instruction is decoded. The r0 value will be written back in the next clock cycle. The Instruction Decoder gives the register addresses in the instruction for the register file so that the data in the corresponding registers are out and are ready for execution in the next clock cycle. But the r0 value is not yet written back. It takes the older value of r0. This is source dependency.

Elimination:

In these sources are same in both the instructions. The control unit sets the adpen signal to the mux 8 bit 2x1 to select REGA for the ALU. One input to the mux is from register file. Other input is the output of ALU. So the new value of r0 is fed to the ALU along with r2. So the results are correct.

EXAMPLE2: add r0,r1 Sub r2,r0

This is same as above except that source and destination are same. The Instruction

Decoder sets bdpen signal to the another mux 8 bit 2x1 to select REGB for the ALU.

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Instruction Execution Block:

Write Back Logic:

Instruction decoder will send the write address and write_reg signals to the write back logic.Write address (3 bit wide) will decide in to which register of the register file the alu output should be written only if the write_reg (enable signal) is set. If not the data will be written to the RAM based on the RAM control signals(write_rdb).

NOP Instruction:\We used NOP instruction before jump instructions.We did not update PSW, did not change the values of the register file and did not change the RAM data.

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ALU

Mux 2x1 8bit

adpen

Mux 2x1 8bit

ALU_outFrom reg file

From previous mux

bdpen


InstructionFetch

Decode andFetch Operands Execute Write Back

InstructionFetch


InstructionFetch


InstructionFetch


InstructionFetch


T1 T2 T3 T4 T5 T6 T7 T8

Pipelining ProcessPipelining Process

4 stage Instruction Pipeline

Instruction FormatInstruction Format

24bit instruction length

8 bit opcodeRegA

AddressRegB

Address10bit

Address

8bit 3bit 3bit 10bit

Registers and corresponding addresses:

R0 000R1 001R2 010R3 011

R4 100R5 101R6 110R7 111

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7

JMP, JC, JZ, JP, JNP, JNC, JNZBranching Instructions

AND, OR, XOR, NOT, SWN, ANDI, ORI, XORI, SHL, SHR, ROL, ROR, ROLC, RORC 14

Logical Instructions

ADD, SUB, MUL, ADDEQ, SUBEQ, ADDC, ADDCS, ADDS, SUBB, SUBS,SUBBS, ADDI, SUBI 13

Arithmetic Instructions

4

MOV, MVI, LOAD, STORE

Data Movement

Instructions

Instruction set divisionInstruction set division

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Instruction Set and opcodesInstruction Set and opcodes

The instruction set consists of 38 instructions.

This set is divided into four categories of instructions as shown below. Data Movement instructions. Arithmetic Operation instructions. Logical Operation Instructions. Branching instructions.

Rd=Rd-Rs (PSW changes)Subs Rd,Rs07SUBS

Rd=Rd-Rs-carry (PSW changes)Subbs Rd,Rs08SUBBS

Rd=Rd-Rs-Carry_flagSubb Rd,Rs06SUBB

Rd=Rd-RsSub Rd,Rs05SUB

Rd=Rd+Rs+carry (PSW changes)Addcs Rd,Rs04ADDCS

Rd=Rd+Rs (PSW changes)Adds Rd,Rs03ADDS

Rd=Rd+Rs+Carry_flagAddc Rd,Rs02ADDC

Rd=Rd+RsAdd Rd,Rs01ADD

DescriptionFormatOpcodeMnemonic

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Instruction Set and Opcodes

Rd=RsMov Rd,Rs10MOVRd=imd valueMvi Rd,<imd value>11MVI

Shift left Rd by imd_value timesShl Rd,<imdvalue>12SHLShift right Rd by imd_value timesShr Rd,<imdvalue>13SHRrotate left Rd by imd_value timesRol Rd,<imdvalue>14ROL

rotate right Rd by imd_value timesRor Rd,<imdvalue>15RORrotate left Rd,C by imd_value timesRolc Rd,<imdvalue>16ROLC

rotate right Rd,C by imd_value timesRorc Rd,<imdvalue>17RORCRd=Rd+<imd_value>Addi Rd,<imd value>18ADDI

Mem[addr]= RsStore Rs,<addr>0FSTORE

Rd=Rd-<imd_value>Subi Rd,<imd_value>19SUBI

Rd=Mem[addr]Load Rd,<addr>0ELOAD

Rd= ~RdNot Rd0DNOT

Rd=Rd XOR RsXor Rd,Rs0CXOR

Rd=Rd | RsOr Rd,Rs0BOR

Rd=Rd & RsAnd Rd,Rs0AAND

Rd=Rd[3:0]*Rs[3:0]Mul Rd,Rs09MUL

DescriptionFormatOpcodeMnemonic

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Instruction Set and Opcodes

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• PC.v• ControlUnit.v• ALU.v• PSW.v• Regfile.v• Code_mem.v (for testing)• Data_mem.v (for testing)• D FlipFlops:

•24 bit wide.•47 bit wide.•12 bit wide.•1 bit wide.

• Multiplexers:•8 bit 2X1 Mux.•1 bit 2X1 Mux.

List of Verilog files codedList of Verilog files coded

Tools UsedTools Used

Active HDL for writing the code and performing functionalsimulation

Altera Quartus II for synthesizing the verilog files, generatingoutput netlist file, SDF file, bitstream file.

Modelsim to perform postlayout simulation.

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Sample ProgramSample Program

org 000mvi r4,00 ;118000mvi r0,01 ;110001mov r1,r0 ;102000Rept:mov r2,r1 ;104400add r2,r0 ;014000mov r0,r1 ;100400mov r1,r2 ;102800addi r3,01 ;186001mov r6,r3 ;10cc00subi r6,05 ;19c005jz Lend ;1e000djmp Rept ;210003Lend:store r2,30 ;0f0830mvi r3,0f ;1160ffLoad r3,30 ;0e6030end

Program to generate first 5 fibonacci numbers (Result is updated in R2 Reg)

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Sample Functional simulation WaveformsSample Functional simulation Waveforms

PSW

REG

FILE

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PSW

REG

FILE


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Waveforms for the Fibonacci program:

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Post Layout Simulation WaveformsPost Layout Simulation WaveformsControl Unit Propagation Delay

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Post Layout Simulation WaveformsPost Layout Simulation WaveformsALU Propagation Delay

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Post Layout Simulation WaveformsPost Layout Simulation WaveformsTopLevel Microprocessor waveforms

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Synthesis ReportsSynthesis Reports

ALU synthesis Report


Control Unit synthesis Report

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Total Microprocessor synthesis Report

Delay reportsDelay reports

ALU Delay report

Control Unit Delay report

Total Microprocessor Delay report

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Max Clock frequency calculationsMax Clock frequency calculations

Control Unit Propagation Delay: 11ns(worst case)

ALU Propagation Delay : 20ns(worst case)

Max Propagation Delay for the whole MicroProcessor:20ns (worst case)

Max Clock Frequency :50 MHz.

Technology Map Schematics

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