PROJECT

PROJECT 1CARRY LOOK AHEAD ADDER

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity cla3 is

Port ( a : in STD_LOGIC_VECTOR (15 downto 0);

b : in STD_LOGIC_VECTOR (15 downto 0);

ci : in STD_LOGIC;

s : out STD_LOGIC_VECTOR (15 downto 0);

cout : out STD_LOGIC);

end cla3;

architecture Behavioral of cla3 is

component fa

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

ci : in STD_LOGIC;

s : out STD_LOGIC;

c : out STD_LOGIC);

end component;

signal g:std_logic_vector(15 downto 0);

signal p:std_logic_vector(15 downto 0);

signal z:std_logic_vector(16 downto 0);

begin

z(0)