w.elsevier.com/locate/tsf

Thin Solid Films 511–51

Progress in thin film free-standing monocrystalline silicon solar cells

H.J. Kim *, V. Depauw, G. Agostinelli, G. Beaucarne, J. Poortmans

IMEC vzw, Kapeldreef 75, B-3001 Leuven, Belgium

Available online 18 January 2006

Abstract

We present an improved process for free-standing monocrystalline silicon (FMS) thin film solar cells developed at IMEC. We demonstrate that

a thick annealed porous layer, or the quasi-monocrystalline silicon (QMS) layer, incorporated into a two-side contacted thin film solar cell

structure does not produce any considerable series resistance. The best cell so far exhibits a conversion efficiency of 12.6% with a fill factor of

75.7% for an active layer thickness of 20 Am. This cell process includes emitter formation by phosphorous diffusion, silicon nitride deposition for

antireflection coating and front surface passivation, and 50-Am-thick annealed porous layer remained on the rear. Despite the expected small

reduction in solar cell’s efficiency, maintaining the porous layer in the device structure renders the processing and handling of the thin FMS film

much easier, thus leading to a better yield and up-scalability. PC1D simulations show that a thick QMS layer can lessen the short circuit current

density in some degree, depending on the active layer quality, thickness, optical confinement, etc., while the other cell parameters remain

substantially unvaried; a 10% to 15% higher process yield is expected to be sufficient to reach a break-even between the two processes.

D 2005 Elsevier B.V. All rights reserved.

Keywords: Thin film silicon solar cells; Porous silicon; Free-standing; QMS

1. Introduction

Thin-film monocrystalline silicon solar cells fabricated by

layer transfer processes (LTP) have received an intensive

attention due to their high attainable energy conversion

efficiency as well as reduced consumption of Si material,

which leads to considerable reduction of the product cost [1–

6]. LTPs include the formation of an intermediate layer that

later enables separation but nevertheless allows epitaxial

growth. An example of such a layer is a double porous silicon

(PS) layer with high porosity at the bottom and low porosity at

the top. In most LTPs, a foreign substrate is employed to

mechanically support the epilayer or device and subsequently

to separate the device from the parent substrate. For any LTP to

be successful, it is crucial that the parent substrate is re-used

many times for further layer separation. The best cell obtained

so far by LTP method presents the conversion efficiency of

15.4% with active layer thickness of 23 Am [5]. This cell

process involved random pyramid formation, emitter formation

by phosphorous diffusion and antireflection coating as well as

surface passivation by a SiNx coating. In contrast to other

LTPs, in our lift-off approach the separation of thin porous

0040-6090/$ - see front matter D 2005 Elsevier B.V. All rights reserved.

doi:10.1016/j.tsf.2005.11.104

* Corresponding author. Tel.: +32 16 288992; fax: +32 16 281501.

E-mail address: hyonju.kim@imec.be (H.J. Kim).

silicon layer is carried out before the epitaxial growth and

device processing [7]. Since the separation step is a crucial

factor in yield, separating the layer before the epitaxial growth

or any other cell processing is advantageous compared to other

approaches where the separation is performed after the epilayer

growth or device fabrication. Another distinctive feature of our

approach is that no foreign substrate is incorporated in the

completed cell structure, and thus termed as a free-standing

monocrystalline Si (FMS) solar cell. The main process steps of

FMS approach can be summarized as: i) porous Si formation

and lift-off; ii) epi-layer deposition; iii) device process; iv)

recycle of the parent Si wafer. Using this innovative lift-off

approach, we previously obtained a 20-Am-thick FMS solar

cell with a power conversion efficiency of 12.0% [8]. Although

this cell exhibited considerably high short-circuit current

density of 33.1 mA/cm2 and open-circuit voltage of 603 mV,

it suffered from a high series resistance resulting in a low fill

factor. A drawback of the FMS LTP is that the handling of

ultra-thin and large-area films is rather challenging, which also

limits the application of some high-efficiency solar cell

processes such as texturing and photolithography.

In this paper, we report on an improved process to obtain

higher fill factor of FMS cells. We also investigate the possibility

to keep the porous silicon film in the solar cell structure instead

of etching it away. Keeping the porous silicon film considerably

2 (2006) 411 – 414

ww

BSF layer (p+)

Base (p)

Emitter (n+)

Double ARC

Front contact

Al rear contact

(a) Front contact

20 µm

50 µm

5 µmBSF layer (p+)

Base (p)

Emitter (n+)

SiNx

Annealed PS (QMS)

(b)

Fig. 1. Schematic cross section of the FMS cell structures. (a) Type A cell with

a double (ZnS–MgF2) ARC layer and no porous layer on the rear side. (b

Type B cell with SiNx film on front surface and 50-Am-thick annealed porous

silicon left on the rear. The thickness of each layer is also denoted in the figure

(not in scale).

H.J. Kim et al. / Thin Solid Films 511–512 (2006) 411–414412

eases handling and processing and might lead to a process that

is better up-scalable. We, however, need to assess what is the

impact of the porous silicon presence on device performance.

2. Formation of free-standing monocrystalline silicon

(FMS) film

2.1. Porous silicon formation and lift-off

As a first step, porous layer is formed in a highly doped p+

Si wafer (boron concentration of >3�1018 cm�3) by

electrochemical anodization in ethanoic HF solution. The

porosity and pore morphology are dependent on the formation

parameters such as HF concentration, current density as well as

the wafer doping concentration. The porosity can generally be

increased by raising the current density or by lowering the HF

concentration in the electrolyte. The porosity of the first layer,

which is used as a seed layer for epitaxial growth later, can lie

from 20% up to 37%. To separate the porous layer, we have

developed different anodization processes [8]. One of them is

the one-step separation (OSS) method, where the separation is

automatically obtained at a constant current density after a

certain thickness, which depends on the other anodization

parameters. However, to achieve more flexibility in the

thickness of the lift-off film, another process has been used

in the present experiments. When the film reaches a desired

thickness (>40 Am), the current density is raised continuously

to increase the porosity over 50% and subsequently to separate

the porous layer from the parent substrate. Details of this two-

step separation method and evaluation of the substrate

reusability are described elsewhere [9].

2.2. QMS formation and epitaxial growth

Epitaxial Si layers are grown by Chemical Vapor Deposition

(CVD) in a commercial reactor (ASM Epsilon 2000). Before

the growth, the PS films are annealed for 30 min at 1130 -Cunder H2 flow. The thermal treatment of porous silicon is

known to lead to a reorganization of the pores driven by the

reduction of the excess free energy due to broken atomic bonds

at the inner surfaces of the porous structures. This annealing

process transforms the porous structures into spherical voids

with a diameter between 50 nm and 1 Am, depending on the

porosity and morphology of the starting PS film. These voids

are embedded in restructured monocrystalline silicon, and thus

named as quasi-monocrystalline silicon (QMS) [10]. This QMS

layer provides an ideal surface for the Si epitaxy. After the pre-

annealing step, 5-Am-thick Si p+ layer with 1�1019 cm�3

boron doping is grown as a back surface field (BSF) layer,

followed by the growth of active layer with thickness of 20 Amand doping density of 1�1017 cm�3. All layers are grown at

1130 -C using trichlorosilane (TCS) as a precursor.

3. Cell processing

Two different types of solar cell structures were made. In the

first design (cell A), the porous silicon is etched away, whereas

it remains in design B. The typical procedures used for the cell

A is as follows. First, front side of the FMS film was

processed by forming an n+ thermal diffusion emitter, followed

by front metallization (Ti+Pd+Ag) using a shadow mask.

Before the evaporation of metallic rear electrode (Al), the

annealed PS layer on the rear surface was removed by etching

in KOH (20 wt.%) solution. To protect the front surface during

this etching process, the FMS film was bonded on to a glass

substrate using wax with the front surface facing the glass. The

etching was stopped when the shiny surface, which is the p+

epilayer, appeared on the rear surface, and then the etching

process was finished with a secco etch (HNO3+H2O+Buffer–

HF). The rear side metal deposition was made without any

mask, thus the whole rear surface was covered by 2-Am-thick

Al layer. As described so far, this cell process includes no

texture and no photolithography, and the antireflection coating

was done at the last step by a double layer coating of ZnS and

MgF2 with thickness of 63 and 110 nm, respectively. The final

cell structure is depicted in Fig. 1a.

In the cell B structure (Fig. 1b), following the n+ diffusion

emitter formation, a SiNx film was deposited at 400 -C by

PECVD in an Oxford Plasma Technology direct plasma system

operating at 13.56 MHz. This SiNx film serves as a surface

passivation as well as an antireflection coating. The emitter

contact was formed using a photolithography-based lift-off

process with evaporated Ti/Pd/Ag contacts. At the rear, the

thick (¨50 Am) annealed PS layer was not removed, but

remained in the cell structure. By evaporating Al contact, the

rear side process was completed, and thus there was no

chemical etching process involved.

4. Results and discussion

4.1. Influence of the porous layer on series resistance

An important concern for cell B is the possible increase in

series resistance due to the presence of the thick annealed

porous Si layer. To determine the resistance of the porous layer,

a series of samples was prepared by forming porous layer with

28% porosity with different thicknesses in p+ Si wafers. For

some of the samples, 20 Am thick epilayers with doping density

)

-0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

0

5

10

15

20

25

30

Cell B structure:ARC: SiN, 75nm, n=2Emitter doping ~1.5x1020 cm-3

Base doping ~1x1017 cm-3

Base LD~ 20 µm

BSF doping ~1x1019 cm-3

QMS LD~ 1µm

Without QMS With a 50µm QMS

J (m

A/c

m2 )

Voltage (V)

Fig. 2. Simulated I –V curves for an FMS thin film solar cell with and without a

50-Am-thick QMS layer on the rear. For details of the device structure, refer to

Fig. 1b. For simulation, the optical absorption coefficient of the QMS layer was

taken from the experimental data given in Rinke et al. [10]. The other modeling

parameters are shown in the figure. Internal reflectance was enabled for the

simulation.

H.J. Kim et al. / Thin Solid Films 511–512 (2006) 411–414 413

of 1�1017 cm�3 were grown onto the porous layers, which

were still attached to the parent substrates. For resistance

measurement, 2 Am thick Al layer was evaporated on both

sides of each sample, the area of which was 4�4 cm2. As a

result, a 40-Am-thick porous layer showed an increase of the

series resistance by 2.24 mV cm2 compared to a reference

sample that is a p+ Si wafer with no epi and no porous layers.

Moreover, a 50-Am-thick reorganized porous layer (QMS) with

20-Am epilayer on top raised the resistance by 0.77 mV cm2

compared to a reference sample that is a p+ Si wafer with 20-

Am epilayer but without porous layer. Therefore, this experi-

mental result demonstrates that a thick porous layer, as-formed

or annealed, does not add any considerable series resistance to

the cell characteristics. It should be noted, however, that the

resistance here was measured along the direction of the pore

growth, and that the perpendicular resistance (against the pore

growth direction) may show enhanced resistance. Moreover,

larger porosities than those in the range investigated in this

work might also lead to a substantial resistance contribution.

4.2. Cell characteristics

The cell parameters of both types of FMS cell structures are

summarized in Table 1. The cell area used in this measurement

was 1.21 and 0.13 cm2, respectively, for type A and B cells.

The cell A without QMS on rear side exhibits an efficiency of

11.0% with short current density and open circuit voltage of

26.0 mA/cm2 and 567.9 mV, respectively. Compared to the

previous result [8], the series and shunt resistances have been

improved significantly. This can be ascribed to the careful

surface cleaning procedures (e.g., HF-dip) employed in each

processing step, and the parasitic junction removal afterwards.

For the type B cell with a thick QMS layer on the rear, higher

open circuit voltage and current density have been obtained as

598.4 mV and 27.8 mA/cm2, respectively. As a result, this cell

produces a higher conversion efficiency of 12.6%. As

expected, this cell still keeps a low series resistance along

with an improved shunt, resulting in a relatively good fill factor

of 75.7%. The improved open circuit voltage for type B cell

compared to A can be attributed to a reduced surface

recombination owing to the surface passivation by SiNx film.

On the other hand, compared to the substantial increase of the

open circuit voltage, the current density shows relatively small

increase. As will be discussed below, this is attributed to the

existence of a thick QMS layer on the rear.

According to the study by Rinke et al. the electrical

properties of QMS layer are comparable to those of the

original bulk silicon [10,11]. For 8-Am-thick QMS layer with

Table 1

Summary of the cell performance under AM1.5 illumination for two different

types of FMS cells

Sample ID Jsc (mA/cm2) Voc (mV) FF (%) g (%) Rs (V cm2) Rsh (V cm2)

Cell A 26.0 567.9 74.3 11.0 0.24 3245.0

Cell B 27.8 598.4 75.7 12.6 0.53 7812.3

The device structure and parameters for each cell A and B are illustrated in

Fig. 1.

resistivity of 0.05 V cm, the hole mobility and minority

carrier lifetime were determined to be 67 cm2/V s and 0.4 As,respectively. This electron lifetime yields a diffusion length

larger than 8 Am, if we assume the electron mobility is larger

than the measured hole mobility (le�3lh). However, the

optical absorption coefficient of 4-Am-thick QMS layer is

found to exceed that of bulk crystalline Si by a factor of 10 in

the energy regime of 1 to 2.5 eV. This is ascribed to the

internal light scattering by voids embedded in the QMS layer.

This indicates, thus, that the QMS layer incorporated in the

rear side of the cell may impair the current density compared

to the case without QMS, at which Al back contact (reflector)

is directly located after the absorber layer. Indeed, as given in

Fig. 2, our device simulation using PC1D indicates that the

presence of a 50-Am-thick QMS layer gives rise to a current

loss at maximum by 2.5 mA/cm2 for an FMS cell with the

active layer thickness of 20 Am [12]. This would place the

breakeven point for maintaining the QMS layer to roughly a

10% higher process yield. It should be also noted that the

influence of a thick QMS layer to the current density can be

minimized by increasing the active layer thickness, or by

enhancing the optical absorption via textured front surface.

For the modeling, the same device structure (type B) as

displayed in Fig. 1b has been used. Detailed input parameters

are given in Fig. 2 as an inset. For QMS layer, we used a low

diffusion length of 1 Am and one order of magnitude higher

optical absorption coefficient than that of Si bulk according to

the experimental data given in Rinke et al. [10].

5. Summary and conclusion

We have solved the series resistance problem that previously

plagued FMS devices. As a result, we have obtained high fill

factors, which are prerequisite for high efficiency solar cells.

The best cell so far has an efficiency of 12.6% with the active

layer thickness of 20 Am. We have demonstrated that a thick

annealed porous layer, or QMS layer, incorporated into a both-

H.J. Kim et al. / Thin Solid Films 511–512 (2006) 411–414414

side contacted thin film solar cell structure does not add any

considerable series resistance. Therefore, keeping the porous

silicon film on the structure during processing is a feasible

technological option for the free-standing approach, easing

handling, avoiding the porous silicon etching issue and leading

to better yield. However, as demonstrated by PC1D simulation,

this QMS layer will diminish, in some degree, the short circuit

current density in the cell output. We conclude that, if practical

solutions are found for handling of very thin films and for

convenient porous silicon etching, a process with porous

silicon removal is the best solution for the FMS technology. If

not, there is a realistic option to keep the porous silicon and still

reach high efficiency.

Acknowledgement

This work was partly funded by the European Commis-

sion under FP6, project CRYSTAL CLEAR, contract SES6-

CT-2003-502583.

References

[1] R. Brendel, Thin-Film Crystalline Silicon Solar Cells: Physics and

Technology, WILEY-VCH, Weinheim, 2003.

[2] R. Brendel, Proceeding of 10th Workshop on Crystalline Silicon Solar

Cell Materials and Processes, NREL, Golden, 2000, p. 117.

[3] R.B. Bergmann, T.J. Rinke, R.M. Hausner, M. Grauvogl, M. Vetter, J.H.

Werner, Int. J. Photoenergy 1 (1999) 1.

[4] H. Tayanaka, K. Yamauchi, T. Matsushita, Proceedings of 2nd World

Conference and Exhibition on Photovoltaic Solar Energy Conversion,

Vienna, Austria, 1998, p. 1272.

[5] C. Berge, R.B. Bergmann, T.J. Rinke, J.H. Werner, Proceedings of the

17th European Photovoltaic Solar Energy Conference, Munich, 2001,

p. 1277.

[6] K. Feldrapp, R. Horbelt, R. Auer, R. Brendel, Prog. Photovolt.: Res. Appl.

11 (2003) 105.

[7] C.S. Solanki, R.R. Bilyalov, J. Poortmans, W. Laureys, J. Nijs,

Proceedings of PV in Europe—from PV Technology to Energy Solutions,

Rome, 2002, p. 387.

[8] C.S. Solanki, R.R. Bilyalov, G. Beaucarne, J. Poortmans, Proceedings of

IEA-PVPS, Osaka, 2003, p. 47.

[9] C.S. Solanki, R.R. Bilyalov, J. Poortmans, J.-P. Celis, J. Nijs, R. Mertens,

J. Electrochem. Soc. 151 (2004) C307.

[10] T.J. Rinke, R.B. Bergmann, R. Bruggemann, J.H. Werner, Solid State

Phenom. 67–68 (1999) 229.

[11] T.J. Rinke, R.B. Bergmann, J.H. Werner, Appl. Phys., A 68 (1999) 705.

[12] D.A. Clugston, P.A. Basore, Proceedings of 26th IEEE Photovoltaic

Specialists Conf., Anaheim, 1997, p. 207.