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Programmable Resistance Switching in Nanoscale Two-Terminal DevicesSung Hyun Jo, Kuk-Hwan Kim, and Wei Lu

Nano Lett., 2009, 9 (1), 496-500 • Publication Date (Web): 29 December 2008

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Programmable Resistance Switching inNanoscale Two-Terminal DevicesSung Hyun Jo, Kuk-Hwan Kim, and Wei Lu*

Department of Electrical Engineering and Computer Science, the UniVersity ofMichigan, Ann Arbor, Michigan 48109

Received December 4, 2008

ABSTRACT

We show that in nanoscale two-terminal resistive switches the resistance switching can be dominated by the formation of a single conductivefilament. The probabilistic filament formation process strongly affects the device operation principle, and can be programmed to facilitate newfunctionalities such as multibit switching with partially formed filaments. In addition, the nanoscale switches exhibit excellent performancemetrics making them well suited for memory or logic operations using conventional or emerging hybrid nano/CMOS architectures.

It is widely expected that new device concepts and archi-tectures may be needed to sustain the relentless trend ofdevice scaling the semiconductor industry has witnessed inthe last forty years.1 One such intriguing concept is tocomplement transistors with two-terminal hysteretic resistiveswitches2–8 (memristive systems or memristors9–11). An arrayof such devices forming a so-called “crossbar” structure hasbeen shown to be a promising candidate for ultrahigh densitymemory storage12–16 or logic applications17–19 due to its smallcell size, large connectivity, and defect tolerance capabilities.In the last few years, a number of resistive switching deviceshave been studied2,3 and the resistance switching effects canbe attributed to the formation of conductive filaments insidethe insulator layer due to Joule heating4,6 and electrochemicalprocesses7,8 in binary oxides (e.g., NiO, CuO2, and TiO2) orredox processes in ionic conductors such as oxides, chalco-genides, and polymers.3,5 Recently, resistance switching hasalso been explained by field-assisted drift/diffusion of ionsin TiO2 based memristors10,11 and amorphous-silicon (a-Si)based resistive switches,20,21 and possibly conformationalchanges in molecules.22–24 Understanding the switchingmechanism in the nanoscale switches and developing newoperation approaches for these novel devices have nowbecome an urgent task. In this work, we show that in ananoscale a-Si based two-terminal resistive switch a singlefilament can dominate the switching characteristics, and thestochastic nature of the filament formation process signifi-cantly affects the operation principles for these nanoscaledevices. We further demonstrate that the filament formationcan be controlled by adjusting both the amplitude and thetime of the applied programming pulse, leading to new

opportunities such as in situ controlled digital or analogswitching modes of the same device.

The active resistive switching element in our study consistsof a nanoscale a-Si pillar embedded in an insulatingdielectric, for example, cured spin-on-glass (SOG).24,25 Figure1a,b shows the schematic and top-view of a single-celldevice. A typical device is composed of a top Ag electrode,a B-doped poly silicon (p-Si) bottom electrode and thenanoscale a-Si pillar forming a plug between the twoelectrodes. Cured SOG is used as the spacer layer that isolatesthe top and bottom electrodes and provides mechanicalsupport for the a-Si pillar (Supporting Information). A singledevice essentially acts as a stand-alone reconfigurableinterconnect or memory bit with its independently controlledtop and bottom electrode pairs. In comparison with ourprevious studies in which a continuous a-Si film was used,24

the pillar structure ensures that the active a-Si and filamentregion is physically restricted to nanoscale sizes. Replacingcrystalline Si20,21 with chemical-vapor deposition (CVD)grown poly silicon as the bottom contact also enables devicefabrication on a variety of substrates including existingCMOS structures and the potential for multilayered three-dimensional (3D) structure integration. Similar to devicesbased on a-Si films,20 the pillar-based nanoscale two-terminalswitches show a number of desirable performance metricsin terms of yield (e.g., >95% for devices with 60 nmdiameter a-Si pillars), speed (<50 ns programming time),ON/OFF ratio (104-107) and endurance (>105 cycles)(Figure 1c-e) that make them well-suited for high-performance memory and logic applications13–19 based onconventional or hybrid nano/CMOS architectures. In addition,the high yield and high uniformity make it possible toperform detailed studies on the switching mechanism thatwill be discussed below.

* To whom correspondence should be addressed. E-mail: wluee@eecs.umich.edu.

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10.1021/nl803669s CCC: $40.75 2009 American Chemical SocietyPublished on Web 12/29/2008

In the following, we focus our discussions on the newprogrammable switching effects observed in these devices.Specifically, we show that resistance switching in thenanoscale pillar devices are dominated by the formation ofindividual filaments, and how the probabilistic (stochastic)nature of the filament formation process brings new chal-lenges and opportunities to the device operation. Theswitching mechanism in a-Si devices has been explained bythe formation and retrieval of nanoscale Ag filaments uponthe application of the programming voltage, schematicallyillustrated in Figure 2d. Prior experimental and theoreticalstudies have suggested the filament to be in the form of aseries of positively charged metal (Ag) particles trapped indefect sites in the a-Si layer.21,26–28 The conduction mecha-nism in the ON state is electron tunneling through the metalparticle chain and the device resistance is determined by thetunneling resistance between the last metal particle and thebottom electrode. In the case of nanoscale resistance switch-ing devices studied here, switching may be dominated by a

single chain of metal islands instead of a large number offilaments. This hypothesis is supported by the stepwiseincrease in current in log scale during the OFF-ON transition(Figure 1c, inset), which is consistent with the fact that anAg chain grows in a step-by-step fashion when an additionalAg particle hops into a new trapping site (Figure 2d).

A direct consequence of this filament formation model isthat the switching rate will be strongly bias-dependent.Unlike electron tunneling, the hopping of the Ag particlesis a thermally activated process (Figure 2d), and the rate Γis determined by the bias-dependent activation energy Ea′

Γ) 1 ⁄ τ) υe-Ea′(V) ⁄ kBT (1)

where kB is Boltzmann’s constant, T is the absolute temper-ature, τ is the characteristic dwell time, and V is the attemptfrequency. Lowering of the apparent activation energy Ea′by the application of the bias voltage V (Figure 2d) will thuslead to bias-dependent switching rates and wait times.

Figure 1. Basic characterization of the nanoscale a-Si based switch. (a) Schematic of the nanoscale Ag/a-Si/p-Si pillar structure. (b) Topview of an a-Si pillar embedded in SOG prior to Ag top electrode deposition. (c) Resistance switching of a typical Ag/a-Si/p-Si pillarswitch. Inset: I-V in log scale showing the stepwise transition during the turn-on process. The ON/OFF ratio is 107 at a typical read voltage∼1 V. (d), A representative write/read/erase/read pulse sequence with 6 V, 50 ns write, 0.8 V read and -3.2 V, 350 ns erase pulses andthe output response from a typical device showing the device can be programmed by 50 ns write/erase pulses with high fidelity. (e) Endurancetest of a device by applying repeated write/read/erase/read signals. A typical device with ON-resistance >50 kΩ can survive >105 programmingcycles without degradation. Beyond that the ON/OFF ratio starts to decrease due to increased OFF state conductance.

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The ability to observe single-filament formation in the a-Sinanopillar structure allows us to perform detailed studies toverify these hypothesizes. Specifically, we directly character-ized the wait time for the first transition (i.e., the first currentstep in the inset of Figure 1c) as a function of bias voltage.The wait time was measured by applying a square pulse witha given voltage magnitude to the device in OFF state andmeasuring the lapse in time t until the first sharp increase incurrent. The device was then erased by a negative voltagepulse and the measurement was repeated. Figure 2a-c showsthe histograms of the wait time for the first transition at biasvoltages of 2.6, 3.2, and 3.6 V on the same device. Becauseof the stochastic nature of the switching process, the waittime is expected to follow Poisson distribution29 and theprobability that a switching (the first step jump) occurs within∆t at time t is given by

P(t)) ∆tτ

e-t ⁄τ (2)

The histograms in Figure 2a-c have been fitted to eq 2using τ as the only fitting parameter and yielded τ values of15.3, 1.2, and 0.029 ms, respectively. It is clear that τ is astrong function of V and decreases by almost 103 when V isincreased by only 1 V. Figure 2e plots the distribution of

the measured τ values at five different bias voltages alongwith a fit assuming exponential decay, treating τ0 and V0 asfitting parameters

τ(V)) τ0e-V⁄V0 (3)

The good agreement with eq 3 further demonstrates thatthe wait time is strongly bias dependent, and more impor-tantly, can be reduced exponentially by increasing the appliedbias if high-speed operation is desired. More discussions onthe filament formation processes can be found in theSupporting Information.

The bias-dependent switching characteristics will haveimportant implications on the device operation. First, theswitching is probabilistic and essentially does not have a“hard” threshold voltage even though the switching can bevery sharp (e.g., Figure 1c), since there is always a finiteprobability for switching to occur even at relatively low biasvoltages (Figure 2). On the other hand, threshold voltagescan be defined for a given programming pulse length. Forexample, if the threshold is defined as the voltage abovewhich 95% success rate is achieved, then the thresholdvoltage is 3.3 V for a 1 ms pulse, and 5.1 V for a 10 nspulse. This observation is consistent with data in Figure 1d

Figure 2. Bias-dependent switching characteristics. (a-c) Histograms of the wait time for the first switching event at bias voltages of 2.6,3.2, and 3.6 V, respectively. The voltages were intentionally chosen to be much lower than the 6 V programming voltage used in Figure1d so that the wait times can be safely recorded. The solid lines are fits according to eq 2 using τ as the only fitting parameter. (d) Top tobottom: schematics of the device in OFF, during the first transition at a finite bias, and in ON state, respectively. (e) Characteristic wait timeτ vs bias voltage V along with an exponential fit according to eq 3.

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where a 6 V programming voltage and 50 ns pulse resultsin ∼100% success rate. Second, multilevel bit storage oranalog switching may be achieved in these devices bycreating partially formed filaments. For example, when aseries-resistor is attached to the switch, the voltage acrossthe device will be reduced after the initial switching eventand resulting in significantly longer wait times for subsequentswitching events. As a result, partially formed filament canbe created by removing the programming pulse before thesubsequent switching events can occur, resulting in inter-mediate resistance values between the ON and OFF states.Figure 3a shows the final device resistance obtained on asingle device using identical programming pulses but withdifferent series resistor values. The 8 ) 23 different resistancelevels obtained on the device suggest that each device as amemory component can store up to three bits of information.In addition, the device resistance R correlates well with theresistance RS of the series resistor, as shown in Figure 3b,since the voltage divider effect that causes the elongation ofthe wait time is most pronounced when R becomes compa-rable with RS. We note that unlike multibit switching basedon the formation of parallel conduction paths,5 that is, throughmodulation of the width of the filament, the differentresistance levels here appear in logarithm scale and cor-respond to modulation of the length of the filament. Forfuture applications in high-density memories or integratedcircuits, the array of control resistors can be replaced by asingle diode in series with the switch, such that multibitprogramming of the switch can be achieved by controlling

the amplitude of the programming signal (which in turnadjusts the resistance of the diode in series).

Since many of the resistance switching devices studiedso far involve some sort of filament formation and activationenergy process, for example, redox processes or the diffusionof ions,2,3 we expect similar arguments may be applicableto other resistive switches when they are scaled down to thelevel that a single-filament dominates the device character-istics. The probabilistic nature of the resistance switchingand the fact that switching is bias- and time-dependent thuspresent new challenges and opportunities in future circuitand algorithm developments based on resistive switches. Asan example, we show that the operation of the device aseither a digital switch (e.g., a single-bit memory) or an analogswitch (e.g., a reconfigurable interconnect in logic opera-tions14–18) depends critically on the proper tuning of theamplitude as well as the duration time of the programmingbias. For the Poissonian processes discussed above, Figure3c plots the probability of exactly one switching event havingoccurred during time t while Figure 3d plots the probabilityof at least one switching event having occurred during timet. They correspond to the case with no external seriesresistance and a single switching rate 1/τ applies to thestepwise filament formation process. It is clear then that thedevice acts as an excellent digital switch for long-enoughprogramming pulses (e.g., 95% success rate is achieved fortpulse > 3τ in Figure 3d). However, for multibit storage oranalog operations of the switch, the pulse width has to beoptimized. For example, tpulse needs to be centered at τ inFigure 3c to achieve the highest probability that only thefirst switching has occurred. Even so the maximum successrate is only ∼38%. On the other hand, the success rate foranalog operations can be significantly improved by theaddition of an external series resistance RS, which dramati-cally reduces the switching rates for subsequent events.Figure 3e plots the probability that only the first switchingevent will occur during time t in a simplified two-stepfilament formation process in which two different rates areused: P(t) ) [(τ2)/(τ1 - τ2)](e-t/τ1 - e-t/τ2) where τ1 ) 3.36µs and τ2 ) 1.30 s correspond to the switching rates beforethe first switching event (R . RS so V ) Vin ) 4 V) andafter the first switching event (R ≈ RS so V ≈ Vin/2 ) 2 V),respectively. Here R and V are the resistance of and voltagedrop across the switch, and Vin ) 4 V is the amplitude ofthe input programming pulse. A much higher success rateof >99% can now be achieved for 5τ1 < tpulse < 0.01τ2

(corresponding to a 13 ms operation margin) that can limitthe switching to the first event only, thus creating a partiallyformed filament in a controlled fashion for the proposed logicoperations using the two-terminal nanoswitches as recon-figurable interconnects.14–18

The activation energy of the barriers Ea can be extractedfrom temperature dependence of the wait time from eq 1.Figure 4a shows the time dependent resistance changemeasured near zero-bias at elevated temperatures from 100to 150 °C for a device originally programmed in the ONstate. The sudden transition to the OFF state corresponds tothe retrieval of the Ag filament through thermally activated

Figure 3. Multibit and time-dependent switching characteristics.(a) Eight levels of resistance can be obtained in a single switchwhen programmed with the same write pulse but different seriesresistance values. (b) Correlation between the device resistance andthe resistance of the series resistor in the multibit storage test. (c)The probability of having exactly one switching event. (d) Theprobability of having at least one switching event during time twithout a series resistor. The device works well as a digital switch.(e) The probability of having exactly one switching event duringtime t with a series resistor RS ) R. A success rate of 99% can beobtained for 5τ1 < tpulse < 0.01τ2.

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hopping of the Ag particles toward the top electrode (Figure2d), as verified by the good fitting in the Arrhenius type plotof the wait time t versus 1/T (Figure 4b). The activationenergy for the ON/OFF transition can be extracted to be 0.87eV for this device from the slope of the Arrhenius plot andthe retention time at room temperature is estimated to be6.8 years from extrapolation.

Besides being fully CMOS compatible, the large knowl-edge base accumulated for a-Si thin-film deposition can beused to adjust and improve the device characteristics. Forexample, intrinsic rectifying (diode-like) and nonrectifying(resistor-like) characteristics have been observed in the ONstate of the a-Si devices by adjusting the a-Si growthconditions.20 The rectifying behavior will be desirable inhigh-density arrays as it reduces crosstalk between adjacentcells.15,30 In addition, a 1D1R (one-diode-one-resistor) struc-ture can be incorporated by the addition of an n-type siliconlayer below the p-type silicon electrode so that a PN junctioncan be formed in series with the a-Si switch. The cell sizein this case will remain at 4F2 where F is the smallest featuresize (i.e., electrode line width) hence maintaining a cleardensity advantage compared with other approaches thatrequires a select transistor (e.g., 1T1R structures).1,15,30 We

expect the integration of the a-Si switches to be smoothconsidering the fabrication processes and materials used arefully compatible with commercial technologies, and the highperformance and yield also make this system well suited totest the feasibility of a number of novel device andarchitecture concepts such as the hybrid nano/CMOS archi-tectures15–18 to perform memory and possibly general logicoperations.

Acknowledgment. We thank Z. Zhong and T. Chang forhelpful discussions. This work was supported in part by theNational Science Foundation (CCF-0621823). This workused the Lurie Nanofabrication Facility at the University ofMichigan, a member of the National NanotechnologyInfrastructure Network (NNIN) funded by the NSF.

Supporting Information Available: Fabrication andelectrical characterization of the nanoscale pillar devices.Additional discussion on the bias-dependent filament forma-tion process including dependence on a-Si layer thickness.This material is available free of charge via the Internet athttp://pubs.acs.org.

References(1) International Technology Roadmap for Semiconductors, 2007 ed.;

http://public.itrs.net/ (accessed 2007).(2) Goronkin, H.; Yang, Y. MRS Bull. 2004, 29, 805–808.(3) Waser, R.; Aono, M. Nat. Mater. 2007, 6, 833–840.(4) Choi, B. J.; Jeong, D. S.; Kim, S. K.; Rohde, C. J. Appl. Phys. 2005,

98, 033715.(5) Terabe, K.; Hasegawa, T.; Nakayama, T.; Aono, M. Nature 2005, 433,

47–50.(6) Kim, D. C.; et al. Appl. Phys. Lett. 2006, 88, 202102.(7) Fang, T.-N.; et al. IEDM Tech. Dig. 2006, 789–792.(8) Lee, D.; Seong, D.-J.; Jo, I.; Xiang, F.; Dong, R.; Oh, S.; Hwang, H.

Appl. Phys. Lett. 2007, 90, 122104.(9) Chua, L. O. IEEE Trans. Circuit Theor. 1971, 18, 507–519.

(10) Strukov, D. B.; Snider, G. S.; Stewart, D. R.; Williams, R. S. Nature2008, 453, 80–83.

(11) Yang, J. J.; Pickett, M. D.; Li, X.; Ohlberg, D. A. A.; Stewart, D. R.;Williams, R. S. Nat. Nanotechnol. 2008, 3, 429–433.

(12) Heath, J. R.; Kuekes, P. J.; Snider, G. S.; Williams, R. S. Science1998, 280, 1716–1721.

(13) Stan, M. R.; Franzon, P. D.; Goldstein, S. C.; Lach, J. C.; Ziegler,M. M. Proc. IEEE 2003, 91, 1940–1957.

(14) Snider, G. S.; Williams, R. S. Nanotechnology 2007, 18, 035204.(15) Lu, W.; Lieber, C. M. Nat. Mater. 2007, 6, 841–850.(16) Strukov, D. B.; Likharev, K. K. Nanotechnology. 2005, 16, 137–148.(17) Strukov, D. B.; Likharev, K. K. Nanotechnology. 2005, 16, 888–900.(18) Snider, G. S.; Williams, R. S. Nanotechnology. 2007, 18, 035204.(19) DeHon, A. IEEE Trans. Nanotechnol. 2003, 2, 23–32.(20) Jo, S. H.; Lu, W. Nano Lett. 2008, 8, 392–397.(21) Dong, Y.; Yu, G.; McAlpine, M.; Lu, W.; Lieber, C. M. Nano Lett.

2008, 8, 386–391.(22) Donhauser, Z. J.; et al. Science 2001, 292, 2303–2307.(23) Reed, M. A.; Chen, J.; Rawlett, A. M.; Price, D. W.; Tour, J. M.

Appl. Phys. Lett. 2001, 78, 3735–3737.(24) Green, J. E.; et al. Nature 2007, 445, 414–417.(25) Liou, H.-C.; Pretzer, J. Thin Solid Films 1998, 335, 186–191.(26) Jafar, M.; Haneman, D. Phys. ReV. B 1994, 49, 13611–13615.(27) Owen, A. E.; Lecomber, P. G.; Hajto, J.; Rose, M. J.; Snell, A. J. Int.

J. Electron. 1992, 73, 897–906.(28) Hu, J.; Branz, H. M.; Crandall, R. S.; Ward, S.; Wang, Q. Thin Solid

Films 2003, 430, 249–252.(29) Grimmett, G.; Stirzaker, D. Probability and Random Processes; 2nd

ed.; Oxford University Press: Oxford, 1992.(30) Scott, J. C. Science 2004, 304, 62–63.

NL803669S

Figure 4. Activation energy and retention time measurement. (a)Resistance vs time measured near zero-bias at temperatures from100 to 150 °C plotted for a device originally programmed in theON state. Elevated temperatures were used in this study to obtainthe wait time within a reasonable time frame. (b) Arrhenius typeplot of the wait time measured from (a) versus 1/T. Ea was estimatedto be 0.87 eV using eq 1 and the retention time at room temperaturewas estimated to be 6.8 years.

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