Processor Structure and Function Chapter 12
description
Transcript of Processor Structure and Function Chapter 12
![Page 1: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/1.jpg)
Computer Organization and ArchitectureDesigning For PerformanceWilliam StallingsSeventh Edition
![Page 2: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/2.jpg)
Team #5Team #5 - 12.1 Processor Organization - 12.2 Register Organization - 12.3 Instruction Cycle - 12.4 Instruction Pipelining/ Dealing with
Branches
![Page 3: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/3.jpg)
12.1 Processor OrganizationFetch InstructionInterpret instructionFetch DataProcess DataWrite Data
![Page 4: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/4.jpg)
Remember….The processor needs to store some
data temporally. It must remember the location of the
last instruction so that it can know where to get the next instruction.
It needs to store instructions and data temporally while an instruction is being executed.
![Page 5: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/5.jpg)
CPU with System Bus
![Page 6: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/6.jpg)
CPU Internal Structure
![Page 7: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/7.jpg)
Register Organization
User-visible registers
Control and status registers
![Page 8: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/8.jpg)
User Visible Registers
General PurposeDataAddressCondition Codes
![Page 9: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/9.jpg)
General Purpose RegistersData
Accumulator
AddressingSegment pointersIndex registersStack Pointer
![Page 10: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/10.jpg)
Control & Status Registers
Program CounterInstruction Decoding RegisterMemory Address RegisterMemory Buffer Register
![Page 11: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/11.jpg)
Program Status WordSign ZeroCarryEqualOverflowInterrupt enable/disableSupervisor
![Page 12: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/12.jpg)
Example Register Org.
![Page 13: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/13.jpg)
Instruction CycleIt is the time in which a single instruction is fetched from memory,
decoded, and executed
An Instruction Cycle requires the following subcycle:
![Page 14: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/14.jpg)
Instruction CycleFetch
Read next instruction from memory into the processor
Indirect Cycle (Decode Cycle)May require memory access to fetch operands, therefore more memory accesses.
Interrupt
Save current instruction and service the interruptExecute
Interpret the opcode and perform the indicated operation
![Page 15: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/15.jpg)
Instruction CycleFetch
Execute
Fetch
Execute
Indirect
Fetch
Execute
Interrupt
Fetch
Execute
IndirectInterrupt
![Page 16: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/16.jpg)
![Page 17: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/17.jpg)
Data Flow (Fetch Diagram)
PC
ControlUnit
PC MARMAR
MemoryMemory
ControlUnit
MBR
Memory
IR MBR
![Page 18: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/18.jpg)
Data Flow (Indirect Diagram)
MBR
MARMAR
Memory
ControlUnit
Memory
MBR
Memory
![Page 19: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/19.jpg)
Data Flow (Execute)May take many formsDepends on instruction being executed
May includeMemory read/writeInput/OutputRegister transfersALU operations
![Page 20: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/20.jpg)
Data Flow (Interrupt Diagram)
ControlUnit
PC
MBR
PC
ControlUnit
MARMAR
Memory
MBR
MemoryMemory
ControlUnit
ControlUnit
PC
![Page 21: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/21.jpg)
12.4 Instruction PipeliningInstruction processing is subdivided:
- Fetch/ Execute instructionPipeline has two independent stages:
1st Stage – Fetch an instruction and buffers it.2nd Stage – Temporarily free until first stage passes it the buffered instruction.While the second stage is executing the instruction, the first stage fetches and buffers the next instruction.
Instruction prefetch or fetch overlap.- Purpose? To speed up instruction execution.
![Page 22: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/22.jpg)
Two-Stage Instruction Pipeline
![Page 23: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/23.jpg)
Instruction ProcessingFetch instruction (FI)Decode instruction (DI)Calculate operands (CO)Fetch operands (FO)Execute instruction (EI)Write operand (WO)
Successive instructions in a program sequence will overlap in execution.
![Page 24: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/24.jpg)
Timing Diagram for Instruction Pipeline Operation
![Page 25: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/25.jpg)
Six-Stage CPU Instruction PipelineThe logic needed for pipelining to account for branches, interrupts, and arising problems.
![Page 26: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/26.jpg)
Alternative Pipeline Depiction
![Page 27: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/27.jpg)
RISC Pipeline1.Instruction fetch2.Instruction decode and register
fetch3.Execute4.Memory Access5.Register write back
![Page 28: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/28.jpg)
Branches
Branch- group of instructions
Branch Instructions – (Jump Instruction) One of it’s operands is the address of the next instruction to be executed.
![Page 29: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/29.jpg)
BranchesTwo Types of Branch Instructions
Unconditional – Branch always happensConditional – Branch only happens if
certain condition is met.The PC is updated to the address specified in the operand of the conditional branch instruction.
A conditional branch instruction is similar to an if statement.
![Page 30: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/30.jpg)
Conditional Branch InstructionsCondition Codes
BRP XBranch to location X if result is
positiveBRZ X
Branch to location X if result is zeroBRE R1,R2,X
Branch to location X if contents of R1 = R2
![Page 31: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/31.jpg)
Conditional Branch Instructions
![Page 32: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/32.jpg)
Dealing with BranchesA major problem in designing an
instruction pipeline is assuring a steady flow of instructions to the initial stages of the pipeline.
Since conditional branches alter the steady flow of instructions, we must come up with ways to execute them efficiently.
![Page 33: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/33.jpg)
Dealing with Branches5 Approaches to Dealing with
Conditional BranchesMultiple StreamsDelayed BranchPrefetch Branch targetLoop BufferBranch Prediction
![Page 34: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/34.jpg)
Dealing with Branches• Multiple Streams (IBM 370/168 and IBM 3033)
Pipeline fetches both instructions. Leads to contention delays, and branches
can lead to too many streams.• Delayed Branch
Branch Instruction occurs later than desired.• Prefetch Branch Target (360/91 IBM)
The target of the branch is prefetched, along with the instruction following the branch, so if the branch is taken this will speed up performance.
![Page 35: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/35.jpg)
Dealing with BranchesLoop buffer ( Motorola 68010)
Memory containing the n most recently fetched instructions.
Useful with if-then and if-then-else statements, as well as loops
Branch PredictionDifferent techniques are used to predict
whether the branch will be taken or notIf the prediction is correct this will
speed up performance
![Page 36: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/36.jpg)
Dealing with Branches
![Page 37: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/37.jpg)
Intel Pentium BranchThe prediction of whether a jump will occur or not, is based on the branch’s previous behavior. There are four possible states that depict a branch’s disposition to jump:
Stage 0: Very unlikely a jump will occurStage 1: Unlikely a jump will occurStage 2: Likely a jump will occurStage 3: Very likely a jump will occur
![Page 38: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/38.jpg)
Intel Pentium BranchIt is actually believed that Pentium’s original algorithm for branch prediction was incorrect. (Left)
![Page 39: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/39.jpg)
Researchhttp://www.it.jcu.edu.au/Subjects/cp1300/resourc
es/lectnotes/system/fde.htmlhttp://dr-pisit.com/csc331/Lec10-
CPU&Pipeline.pdf http://
en.wikipedia.org/wiki/Instruction_pipelininghttp://www.itreviews.co.uk/hardware/h738.ht
m
![Page 40: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/40.jpg)
Review Questions1. What are the major components of a processor?2. What is the function of the ALU?3. What is the function of the control unit?4. What are the two roles that registers in the
processor perform?5. What are bits set by the processor hardware as
a result of operations?6. What is an instruction cycle?7. What are the four subcycle of an instruction
cycle?
![Page 41: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/41.jpg)
8. Is the fetch or execute cycle the same for all CPU?
9. What is the sequence of an interrupt cycle?10. What is the main purpose for instruction
pipelining?11. How can you make the pipelining more
efficient?12. What is a condition code?13. What is another name for a branch
instruction?
![Page 42: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/42.jpg)
Answers1. Arithmetic and Logic Unit (ALU) and the Control Unit
(CU).2. The ALU does the actual computation or processing of
data.3. The control unit controls the movement of data and
instructions into and out of the processor and controls the operations of the ALU.
4. User-visible registers, and control and status registers. 5. Condition codes. 6. It is the time in which a single instruction is fetched
from memory, decoded, and executed. 7. Fetch, Indirect (if any) , execute, and interrupt (if any).
![Page 43: Processor Structure and Function Chapter 12](https://reader035.fdocuments.in/reader035/viewer/2022062222/5681544e550346895dc268ad/html5/thumbnails/43.jpg)
8. No, it depends on the CPU’s design. 9. PC MBR
Address of Stack MAR MAR Memory
PC Memory Control Unit request memory write via Control Bus PC is loaded with address of Interrupt handler
10. To speed up the instruction execution rate. 11. To gain further speedup, the pipeline must have more stages
for decomposition.
12.A statement that if true will allow the branch to be executed.
13.A jump instruction.