Processor & Register

7/30/2019 Processor & Register

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Processor Organization

&

Register Organization


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Interconnection structures

Computer consists of set of components (or modules) of 3 basic

types.

CPU

Memory

I/O

These components communicate with each other.

The collection of paths connecting various modules is called as

Interconnection structure.

There may be different designs of interconnection structure

depending upon exchanges that must be made b/w the modules.


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Computer Components:


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Central Processing Unit :

The organization of a simple computer with one CPU and two I/O devices

Processor Organization


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Processor Organization Cont


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Instruction Execution Steps:

1. Fetch an instruction from memory into instr. Register

2. Change program counter to point to next instruction

3. Determine type of instruction just fetched (Decode)

4. If instructions uses word in memory, determine where Fetchword, if needed, into CPU register(Fetch data)

5. Execute the instruction(Process the data A & L Manip.)

6. Write Data: Result of execution to be stored in Memory or I/O

7. Go to step 1 to begin executing following instruction (Next Instr)


Things that the CPU must do:


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To do all these things CPU needs :

To store data and instruction temporarilywhile an Instruction is executing..

To remember the location of next Instruction

CPU needs small Internal Memory i.e. Register



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Similarity between Internal structure of the Computer as whole and IS of CPU

(collection of major elements)

Computer : CPU, I/P, O/P and Memory

CPU: Control Unit, ALU and Register


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Register Organization

CPU must have some working space (fast access

and close to CPU)

This space is efficiently used to store intermediate

values

The most convenient way to communicate

registers is trough common bus system


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Registers in CPU performs two roles:

User Visible register : To minimize main memory

references by optimizing register uses (enables m/c

and assembly level Programmer)

Control and Status register: Used by control unit to

control the CPU operation

Register Organization Cont.


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User visible Registers:

General Purpose: Can contain the operand forany opcode. (as there are some dedicated registers like SR forstack operations)

Data: Used to hold only data.

Address: Used to hold addresses (ex, Segmentpointer, Index register, Stack Pointer registers)

Condition codes: Are the bits set by CPU h/w asthe result of operation(ex ,Flag Register)



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Control and Status Register:

To control the CPU Operations

Four Registers generally used are

Program Counter: Contains the address of the nextinstruction to be fetched

Instruction Register: Contains the Instruction mostrecently fetched

Memory Address Register: Contains the address of alocation in memory

Memory Buffer Register: Contains the data to be written inthe memory or the data most recently read.



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Bus organization

for 7 CPU registers

2 MUX

BUS A and BUS B

ALU

3 X 8 Decoder

R1R2R4R3

R6R7R5

38decoder

MUX MUX

Arithmetic logic unit(ALU)

Clock Input

Load(7 lines)SELA SELB

A bus B bus

OPR

Output

SELD

(a) Block diagram

(b) Control wordSELA SELDELB OPR

3 5


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Bus organization for 7 CPU registers:

2 MUX: select one of 7 register or external data input bySELA and SELB

BUS A and BUS B : form the inputs to a common ALU

ALU : OPR determine the arithmetic or logic micro-operation

The result of the micro-operation is available forexternal data output and also goes into the inputs ofall registers

3 X 8 Decoder: select the register (by SELD) thatreceives the information from ALU



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An operation is selected by the ALU operation

selector (OPR).

The result of a microoperation is directed to a

destination register selected by a decoder (SELD).

Control word: The 14 binary selection inputs (3

bits for SELA, 3 for SELB, 3 for SELD, and 5 for OPR)



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Binary selector input

1 ) MUX A selector

(SELA) : to place thecontent of R2 into BUSA

2 ) M U X B s e l e c t o r(SELB) : to place thecontent of R3 into BUS

B3 ) ALU operation

selector (OPR) : toprovide the arithmeticaddition R2 + R3

4) Decoder selector

(SELD) : to transferthe content of theoutput bus into R1

321 RRR Register Organization Cont.


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Encoding of Register Selection Fields:

SELA or SELB = 000 (External Input) : MUX selects the external data

SELD = 000 (None) : no destination register is selected but the contents of

the output bus are available in the external output


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ExampleMicro-operation : R1R2 - R3

Control word

Field: SELA SELB SELD OPR

Symbol: R2 R3 R1 SUB

Control word: 010 011 001 00101



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Stack Organization

Stack: A storage device that stores information insuch a manner that the item stored last is the firstitem retrieved.

Also called last-in first-out (LIFO) list. Useful for

compound arithmetic operations and nested

subroutine calls.


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Stack pointer (SP): Aregister that holds theaddress of the top item inthe stack.

SP always points at the topitem in the stack

Push: Operation to insert anitem into the stack.

Pop: Operation to retrieve anitem from the stack.

A stack can be organized asa collection of a finite

number of registers.

Stack Organization Cont

Register Stack :


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In a 64-word stack, thestack pointer contains6 bits.

The one-bit register

FULL is set to 1 whenthe stack is full;EMPTY register is 1when the stack isempty.

The data register DRholds the data to bewritten into or readfrom the stack.

Stack Organization Cont

Register Stack :


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PUSH: Sequence of micro-

Operation

Increment Stack Pointer

Write item on top of the

stack

Check if the stack is full

Mark the stack not empty

POP: Sequence of micro-

Operation

Read item from the top of

stack

Decrement stack pointer

Check if stack is empty

Mark the stack not full

Push & Pop Operation

SP SP + 1

M[SP] DR

If ( SP = 0) then (FULL 1)

FULL 0

DR M[SP]

SP SP - 1

If ( SP = 0) then (EMPTY 1)

EMPTY 0

STACK OPERATIONS


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STACK OPERATIONS

REVERSE POLISH NOTATION (postfix)

Reverse polish notation :is a postfix notation

(places operators after operands)

(Example)

Infix notation = A + BReverse Polish notation = AB+

A stack organization is very effective for evaluating

arithmetic expressions

A * B + C * D (AB *)+(CD *)AB * CD * +

( 3 * 4 ) + ( 5 * 6 ) 34 * 56 * +


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Evaluation procedure:

1. Scan the expression from left to right.

2. When an operator is reached, perform the operationwith the two operands found on the left side of theoperator.

3. Replace the two operands and the operator by the

result obtained from the operation.

(Example) Infix 3 * 4 + 5 * 6 = 42

postfix 3 4 * 5 6 * +

12 5 6 * +

12 30 +

42

STACK OPERATIONS


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Reverse Polish notation evaluation with a stack.

(Example) using stacks to do this.

3 * 4 + 5 * 6 = 42 => 3 4 * 5 6 * +

stack evaluation:

Get value

If value is data: push data

Else if value is operation: pop, pop evaluate and push.

STACK OPERATIONS

I t ti F t


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Instruction Formats

I Op. Code Address

15 14 12 11 0

Layout of bits in an instruction

Includes op-code

Includes (implicit or explicit) operand(s)Usually more than one instruction format in an instruction set

Instruction code format with parts : Mode + Op. Code + Address

Mode : Used to specify the type of Instruction

Op. Code : Specify 8 possible operations(3bits)

Address : Specify the address of an operand(12 bits). If an

operation in an instruction code does not need an operand frommemory, the rest of the bits in the instruction(address field) canbe used for other purpose


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Memory reference Instruction

( Opcode = 000 through 110)

Register reference Instruction

( Opcode = 111 , I = 0)

I/O Instruction

( Opcode = 111 , I = 0)

Instruction Formats Cont

0 1 1 1 Register Operation

1 1 1 1 I/O Operation

0 / 1 Opcode Address

I t ti F t C t


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Instruction Length

Affected by and affects: Memory size Memory organization

Bus structure

CPU complexity

CPU speed

Allocation of Bits

Number of addressing modes

Number of operands Register versus memory

Number of register sets

Address range

Instruction Formats Cont


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PDP-11 Instruction Format


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Pentium Instruction Format


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Types of Operations

Operation Type Example

Arithmetic/Logical(Data Manipulation) ADD, SUB, MULT, DIV, AND, OR,INR/DCR, Shift, Rotate

Data Transfer LOAD, STORE, MOV

Control BRANCH, JUMP, CALL, RET

System OS Call, VM routines

FP FADD, FSUB, FMULT, FDIV, FCOMP

Decimal Dec ADD, MULT, Dec-Char convert

String MOV, COMPARE, SEARCH

Graphics Pixel Ops, Compress/Decompress

Arithmetic/Logic, data transfer & Control : 96% usage

Simple instructions dominate.


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Instruction Types

1. Memory Reference 2. Register Reference

3. Input/output Reference

I t ti F t


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Instruction Formats

Number of operands

Instruction sets may be categorized by the maximum number ofoperands explicitly specified in instructions.

Number of operands in an instruction format depends on the internalCPU Organization:

Single Accumulator Organization

General register Organization

Stack Organization

Thus a system has

Zero address instruction:

One address instructions:

Two address instructions:

Threeaddress instructions:


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Zero address instructions :

Stack is used.

Arithmetic operation pops two operands from the stack and pushes

the result.

Stack-organized computer does not use an address field

for the instructionsADD, and MUL

EvaluateX = ( A + B ) * ( C + D )

PUSH A

PUSH B

ADD

PUSH C

PUSH D

ADD

MUL

POP X TOSX

BADCTOS

DCTOS

DTOS

CTOS

BATOS

BTOS

ATOS

)()(

)(

)(

Advantages: No memory addresses needed during the operation.

Disadvantages: results in longer program codes.


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One address instructions (1-operand m/c)

So called accumulator machines, include early computers

Instructions specify a single right operand (constant, aregister, or a memory location), with the implicit accumulator

as the left operand load a, add b, store c.

All operations are done between the AC register and

memory operand

Instruction: ADD X Micro-operation: AC -> AC + M[X]

LOAD A

ADD B

STORE T ACTM

BMACAC

AMAC

][

][

][

Advantages: fewer bits are needed to specify the address.

Disadvantages: results in writing long programs.


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MOV R1, A

MOV R2, B

ADD R1, R2

MOV X, R1 1][

211

][2

][1

RxM

RRR

BMR

AMR

Advantages: results in writing medium size programs

Disadvantages: more bits are needed to specify two addresses.

Two address instructions (2-operand)

Two address registers or two memory locations are specified,

one for the final result.

Each address fields specify either a processor register or a

memory operand

Many CISC and RISC machines fall under this category.


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Three address instructions (3-operand )

Three address registers or memory locations are specified,one for the final result

It is also called general address organization.

Instruction: ADD R1, R2, R3 Microoperation: R1

R2 + R3

ADD R1, R2, R3 321 RRR

Advantages: results in writing short programs

Disadvantages: more bits are needed to specify three addresses.


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Three-address instructions

ADD R1, A, B

R1M[A] + M[B] ADD R2, C, D

R2M[C] + M[D] MUL X, R1, R2

M[X] R1 * R2

Two-address instructions

MOV R1, A

R1M[A] ADD R1, B

R1 R1 + M[B] MOV R2, C

R2M[C] ADD R2, D

R2 R2 + M[D] MOV X, R2

M[X] R2 MUL X, R1

M[X] R1 * M[X]

(A + B) * ( C+D)


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One-address instructions

LOAD A ACM[A] ADD B AC AC + M[B]

STORE T M[T ] AC LOAD C ACM[C] ADD D

AC

AC + M[D] MUL T AC AC * M[T ] STORE X M[X] AC Store

Zero-address instructions

PUSH A TOS A PUSH B TOS B ADD TOS (A+B) PUSH C TOS C PUSH D TOS D ADD TOS (C+D) MUL TOS (C+D)*(A+B) POP X M[X] TOS

(A + B) * ( C+D)


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Accumulator (before 1960):1 address

add A : acc acc + mem[A]Stack(1960s to 1970s): 0 address

add : tos tos + next

Memory-Memory (1970s to 1980s):2/3 address

add A, B: mem[A] mem[A] + mem[B]

add A, B, C: mem[A] mem[B] + mem[C]Register-Memory (1970s to present):2 address

add R1, A : R1 R1 + mem[A]

load R1, A: R1 mem[A]

Register-Register, also called Load/Store (1960s to present):2/3

address add R1, R2,R3: R1 R2 + R3

load R1, R2 : R1 mem[R2]

store R1, R2 : mem[R1] R2

Operand Locations


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Example: C = A + B

Stack Accumulator Reg-Mem Load-Store

Push A

S[++tos] = M[A]

Load A

accum = M[A]

Load R1, A

R1 = M[A]

Load R1, A

R1 = M[A]

Push B

S[++tos] = M[B]

Add B

accum += M[B]

Add R3, R1, B

R3 = R1 + M[B]

Load R2, B

R2 = M[B]

Add

t1= S[tos--];

t2= S[tos--];S[++tos]= t1 + t2

Store C

M[C] = accum

Store R3, C

M[C] = R3

Add R3, R1, R2

R3 = R1 + R2

Pop C

M[C] = S[tos--]

Store R3, C

M[C] = R[3]

S f ISA


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Summary of ISA

No of

memory

address

Max no of

operands

Arch Examples Advantages Disadvantages

1 1 Acc Less Hardware, high code

density

Memory bottleneck

0 0 Stack X86 (for FP

operations)

Less Hardware, high code

density

Memory, pipeline

bottlenecks

0 3 Load-Store

ARM, MIPS,Sparc, PowerPC

Fixed length instruction,simple code gen, CPI

similar for all instr., easy

decoding

IC high. Largeprograms

1 2 Register-

memory

80x86, Motorola

68k, IBM

360/370

Data without load

instruction. Easy Instr

encoding.

Src operand (mem)

destroyed. Num

registers less. CPI

varies.

2

Or

3

2

Or

3

Memory-

Memory

[not

used]

VAX No registers needed for

temporaries. Most compact

Variable length

instructions. Mem

access bottleneck.


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Operand Location: Registers vs. Memory

Pros and cons of registers+ Faster, direct access

+ Simple cost model (fixed latency, no misses)

+ Short identifier

Must save/restore on procedure calls, context switches

Fixed size (larger-sized structures must live in memory)

Pros and cons of more registers+ Possible to keep more operands for longer in faster memory

Shorter operand access time, lower memory traffic

Longer specifiers

Larger cost for saving CPU state Trend towards more registers

8 (x86) -> 32 (MIPS/Alpha/PPC) -> 128 (IA-64)

Driven by increasing compiler involvement in scheduling


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Memory addressing

Endianness: How is byte ordered in aword: where is the LSB?

Big-endian: LSB in big end,

Ex: Sparc, IBM

Small-endian: LSB in small end

Ex: Intel 8086

Bi-endian: PowerPC, MIPS (supports

both)

Address00 01 10 11

Big-

endian 12 34 56 78Small-

endian 78 56 34 12

Small End Big End

E l P i 32 bi dd i


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Example: Pentium 32-bit addressing

Addressing modes

Register Immediate Memory

Direct[displacement]

Indirect

Register[Base]

Based[Base + disp ]

Indexed[index + scale * disp ]

Based-indexed[ scaled]

No scale factor

[Base + Index + disp]

Scalefactor

[Base + (index *scale)

+ disp ]


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Instruction Cycle

Processor & Register

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