GENERIC VISUAL PERCEPTION PROCESSOR 1 Generic Visual Perception Processor.
Processor
description
Transcript of Processor
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Processor Memory
I/O device 1 I/O device n
Bus
Figure 4.1. A single-bus structure.
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I/O
Bus
Address lines
Data lines
Control lines
Figure 4.2. I/O interface for an input device.
interfacedecoderAddress Data and
status registersControlcircuits
Input device
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KEN
SOUT
CONTROL
DATAIN
Figure 4.3. Registers in keyboard and display interfaces.
DEN
DATAOUT
7
KIRQ SINSTATUS
6 5 4 3 2 1 0
DIRQ
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Move #LINE,R0 Initializememorypointer.WAITK TestBit #0,STATUS Test SIN.
Branch=0 WAITK Wait forcharactertobeentered.Move DATAIN,R1 Readcharacter.
WAITD TestBit #1,STATUS Test SOUT.Branch=0 WAITD Wait fordisplay to becomeready.Move R1,DATAOUT Sendcharactertodisplay.Move R1,(R0)+ Storecharacterandadvance pointer.
Compare #$0D,R1 Check ifCarriageReturn.Branch0 WAITK Ifnot,getanothercharacter.Move #$0A,DATAOUT Otherwise,sendLine Feed.Call PROCESS Call asubroutineto process
theinputline.
Figure 4.4 A program that reads one line from the keyboard stores it in memory buffer, and echoes it back to the display.
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Figure 4.5. Transfer of control through the use of interrupts.
here
Interruptoccurs
M
i
2
1
PRINT routine
Program 2Program 1
COMPUTE routine
i 1+
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Processor
INTR
R
Figure 4.6. An equivalent circuit for an open-drain bus usedto implement a common interrupt-request line.
INTR1 INTR2 INTRn
Vdd
INTR
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Priority arbitration
Device 1 Device 2 Device p
circuit
Pro
cess
or
Figure 4.7. Implementation of interrupt priority using individual
INTA1
INTR1 INTRp
INTA p
interrupt-request and acknowledge lines.
Figure 4.7. Implementation of interrupt priority using individual interrupt-request and acknowledge lines.
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Please see “portrait orientation” PowerPoint file for Chapter 4
Figure 4.8. Interrupt priority schemes.
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MainProgram
Move #LINE,PNTR Initializebufferpointer.Clear EOL Clearend-of-lineindicator.BitSet #2,CONTROL Enablekeyboard interrupts.BitSet #9,PS Set interrupt-enablebit in the PS....
Interrupt-serviceroutine
READ MoveMultiple R0-R1, (SP) SaveregistersR0andR1onstack.Move PNTR,R0 Loadaddresspointer.MoveByte DATAIN,R1 GetinputcharacterandMoveByte R1,(R0)+ storeit inmemory.Move R0,PNTR Updatepointer.
CompareByte #$0D,R1 Check ifCarriageReturn.Branch0 RTRNMove #1,EOL Indicateend ofline.BitClear #2,CONTROL Disablekeyboard interrupts.
RTRN MoveMultiple (SP)+,R0-R1 RestoreregistersR0and R1.Return-from-interrupt
Figure 4.9. Using interrupts to read a line of characters from a keyboard via the registers in Figure 4.3.
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Figure 4.10. A few operating system routines.
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Figure 4.11. Low-order byte of the ARM processor status register.
7 6 5 4 3 2 1 0
M4 M0M1M2M3I F
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Please see “portrait orientation” PowerPoint file for Chapter 4
Figure 4.12. Accessible registers in different modes of accessible processors.
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Figure 4.13. An ARM interrupt-service routine to read an input line from a keyboard based on Figure 4.9.
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ConditionCodesInterrupt
PrioritySupervisor
Trace
T S X N Z V C
012348101315
Figure 4.14. Processor status register in the 68000 processor.
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Mainprogram
MOVE.L #LINE,PNTR Initializebufferpointer.CLR EOL Clearend-of-lineindicator.ORI.B #4,CONTROL Setbit KEN.MOVE #$100,SR Setprocessorpriority to1....
Interrupt-serviceroutine
READ MOVEM.L A0/D0, (A7) SaveregistersA0,D0onstack.MOVEA.L PNTR,A0 Loadaddresspointer.MOVE.B DATAIN,D0 Getinput character.MOVE.B D0,(A0)+ Store it inmemorybuffer.MOVE.L A0,PNTR Updatepointer.CMPI.B #$0D,D0 Check ifCarriageReturn.BNE RTRNMOVE #1,EOL Indicateendofline.ANDI.B #$FB,CONTROL Clearbit KEN.
RTRN MOVEM.L (A7)+,A0/D0 RestoreregistersD0, A0.RTE
Figure 4.15. A 68000 interrupt-service routine to read an input line from a keyboard based on Figure 4.9.
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Figure 4.16. Part of the Pentium's processor status register.
15 14 13 12 11 10 9 8
TFIFIOPL
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Mainprogram
MOV EOL,0MOV BL,4OR CONTROL,BL Set KEN toenablekeyboard interrupts.STI Set interruptflag inprocessorregister....
Interrupt-serviceroutine
READ PUSH EAX SaveregisterEAX onstack.PUSH EBX SaveregisterEBX onstack.MOV EAX,PNTR Loadaddresspointer.MOV BL,DATAIN Get inputcharacter.MOV [EAX],BL Storecharacter.INC DWORDPTR[EAX] Increment PNTR.CMP BL,0DH Check if characteris CR.JNE RTRNMOV BL,4XOR CONTROL,BL Clearbit KEN.MOV EOL,1 Set EOLflag.
RTRN POP EBX RestoreregisterEBX.POP EAX RestoreregisterEAX.IRET
Figure 4.17. An interrupt-servicing routine to read one line from a keyboard using interrupts on IA-32 processors.
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Done
IE
IRQ
Status and control
Starting address
Word count
WR/
31 30 1 0
Figure 4.18. Registers in a DMA interface.
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Figure 4.19. Use of DMA controllers in a computer system.
memoryProcessor
Keyboard
System bus
Main
InterfaceNetwork
Disk/DMAcontroller Printer
DMAcontroller
DiskDisk
Figure 4.19. Use of DMA controllers in a computer system.
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Processor
DMAcontroller
1
DMAcontroller
2BG1 BG2
BR
BBSY
Figure 4.20. A simple arrangement for bus arbitration using a daisy chain.
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BBSY
BG1
BG2
Busmaster
BR
Processor DMA controller 2 Processor
Figure 4.21. Sequence of signals during transfer of b us mastership
for the devices in Figure 4.20.
Time
Figure 4.21. Sequence of signals during transfer of bus mastership for the devices in Figure 4.20.
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Figure 4.22. A distributed arbitration scheme.
Interface circuitfor device A
0 1 0 1 0 1 1 1
O.C.
Vcc
Start-Arbitration
ARB0
ARB1
ARB2
ARB3
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Figure 4.23. Timing of an input transfer on a synchronous bus.
Bus cycle
Data
Bus clock
commandAddress and
t0 t1 t2
Time
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Figure 4.24. A detailed timing diagram for the input transfer of Figure 4.23.
Data
Bus clock
commandAddress and
t0 t1t2
commandAddress and
Data
Seen by master
Seen by slave
tAM
tAS
tDS
tDM
Time
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Figure 4.25. An input transfer using multiple clock cycles.
1 2 3 4
Clock
Address
Command
Data
Slave-ready
Time
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Figure 4.26. Handshake control of data transfer during an input operation.
Slave-ready
Data
Master-ready
and commandAddress
Bus cycle
t1 t2 t3 t4 t5t0
Time
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Figure 4.27. Handshake control of data transfer during an output operation.
Bus cycle
Data
Master-ready
Slave-ready
and commandAddress
t1 t2 t3 t4 t5t0
Time
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Valid
Data
Keyboardswitches
Encoderand
debouncingcircuit
SIN
Inputinterface
Data
Address
R /
Master-ready
Slave-ready
W
DATAIN
Processor
Figure 4.28. Keyboard to processor connection.
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Figure 4.29. Input interface circuit.
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CPU SOUT
Outputinterface
Data
Address
R /
Master-eady
Slave-ready
ValidW
DataDATAOUT
Figure 4.31. Printer to processor connection.
PrinterProcessor
Idle
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Figure 4.32. Output interface circuit.
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Figure 4.33. Combined input/output interface circuit.
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Figure 4.34. A general 8-bit parallel interface.
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Figure 4.35. A parallel point interface for the bus of Figure 4.25,with a state-diagram for the timing logic.
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Figure 4.36. Timing for the output interf ace in Figure 4.35.
1 2 3
Clock
Address
R/W
Data
Sla v e-ready
Go
Time
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Figure 4.37. A serial interface.
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Figure 4.38. An example of a computer system using different interface standards.
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Figure 4.39. Use of a PCI bus in a computer system.
memory
Host
PCI bridge
EthernetPrinterDisk
interface
PCI bus
Main
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1 2 3 4 5 6 7
CLK
Frame#
AD
C/BE#
IRDY#
TRDY#
DEVSEL#
Adress #1 #4
Cmnd Byte enable
Figure 4.40. A read operation on the PCI bus.
#2 #3
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1 2 3 4 5 6 7 8 9
CLK
Frame#
AD
C/BE#
IRDY#
TRDY#
DEVSEL#
Adress #1 #2 #3 #4
Cmnd Byte enable
Figure 4.41. A read operation showing the role of IRDY#/TRDY#.
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Free Arbitration Selection
Targets examine ID
DB2
DB5
DB6
BSY
SEL
Figure 4.42. Arbitration and selection on the SCSI bus.Device 6 wins arbitration and selects device 2.
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Figure 4.43. Universal Serial Bus tree structure.
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Figure 4.44. Split bus operation
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Figure 4.45. USB packet format.
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Figure 4.46. An output transfer.
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Figure 4.47. USB frames.
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BG1 BG2 BGn
BRnBR2BR1
Figure P4.1. A decentralized bus assignment scheme.
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Table 4.1. Interrupt vector addresses for ARM processor
Address Exception Modeentered(hex)
0 Reset Supervisor
4 Undefinedinstruction Undefined
8 Softwareinterrupt Supervisor
C Abortduringprefetch Abort
10 Abort duringdata Abort
14 Reserved
18 IRQ IRQ
1C FIQ FIQ
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Table 4.2. Address correction during return from exception.
Exception Savedaddress* Desired Returninstructionreturnaddress
Undefinedinstruction PC+4 PC+4 MOVS PC,R14und
Softwareinterrupt PC+4 PC+4 MOVS PC,R14svc
Prefetch Abort PC+4 PC SUBS PC,R14abt,#4
DataAbort PC+8 PC SUBS PC,R14abt,#8
IRQ PC+4 PC SUBS PC,R14irq,#4
FIQ PC+4 PC SUBS PC,R14fiq,#4
* PC istheaddressoftheinstructionthatcausedtheexception.For IRQandFIQ,it is theaddressofthefirstinstructionnotexecutedbecauseofthe interrupt.
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Table 4.3. Data transfer signals on the PCI bus.
Name Function
CLK A 33-MHzor 66-MHzclock.
FRAME# Sent by theinitiatortoindicatethedurationofatransaction.
AD 32 address/datalines,which may beoptionallyincreasedto 64.
C/BE# 4command/byte-enablelines(8 for a64-bitbus).
IRDY#, TRD Y# Initiator-readyand Target-readysignals.
DEVSEL# Aresponsefromthedeviceindicatingthat it hasrecognizeditsaddressand is ready for a datatransfertransaction.
IDSEL# InitializationDeviceSelect.
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Table 4.4 The SCSI bus signals.