Process Integrationweng/courses/IC_2007/PROJECT_… · ULSI Fabrication Technology Chap. 1...

ULSI Fabrication Technology Chap. 1

Instructor: Pei-Wen LiDept. of E. E. NCU

1

Process Integration

Text Books: “Silicon Processing for the VLSI Era”, vol. 2

By S. Wolf, Lattice Press, 1990

Reference: “Microchip Fabrication”, 4rd ed. Van Zant, McGraw-Hill,

2000“ULSI Technology” C. Y. Chang and S. M. Sze, McGraw-

Hill, 1996“Design and Analysis of Experiments,” 4th edition, Douglas

C. Montgometry, John Wiley & Sons, New York, 1997Journal and Digest of Conference in Related Field.

Midterm: 40%Final Report and Presentation: 60%



2

Outline

Chap 1. Process Integration for ULSI Chap 2. Basic Process Modulations: Isolation,

Contact, Interconnection.Chap 3. Interaction Between Process ModulesChap 4. Process Integration Consideration: Design

Rules, Compactness, Step Height, Process Window, and Yield

Chap 5. Process SimulationChap 6. Failure AnalysisChap 7. CMOS TechnologyChap 8. MOS Memory TechnologyChap 9. Future Trend



3

Chap 1.

Overview of IC Industry Process Integration and related IssuesStrategiesDesign of Experiments (DOE, Taguchi Methods田口實驗設計法)



4

IC Market



5

Trend Of MOS IC Technology



6

Architecture of IC Fabrication



7

Process Integration

Specify a Process Sequence for a specific technology—Run Card or Run Sheet.Process Integration Tasks:– Development of a process sequence to modify an existing

structure that is only one part of an integrated circuit.• For example: development of a modified LOCOS structure

to reduce BB.– Development of a process sequence to produce a new

device structure.• For example: development of a trench isolation structure to

replace LOCOS.– Enhancement of a complete process sequence by shrinking

the minimum feature size used in the technology.• Direct shrink by higher-resolution lithography process with

minor process modification.– Implementation of a new technology through modification

or enhancement of an older technology.• For example: development of a BiCMOS process through an

existing CMOS process.– Development of a new technology from scratch.

• Most difficult, extremely expensive and time consuming.



8

Process Development and Issues

To develop a new process, it is very important that the circuit designer, product engineers, device designers, and process engineers interact closely.

All the steps in the process sequence are significantly interrelated, (e.g., thermal cycle, defects induced by a specific process, …)The process integration task is to integrate all the processes together, predict the effect of a process change on the circuit or device electrical parameters and solve it.

Set Specifications (Performance requirements

And package sizes)

Design candidate device structures and potential

Process flow

Exploit new materialsAnd innovative processes

To implement the advancedDevice structures

DesignersProduct Engineers

Device designers

Process Engineers



9

Process Integration Strategies

Perform more experiments: – A drastic increase in the costs and cycle time.– Poor physical insight and inadequate quantitative analysis

of the factors governing device operation Computer-aided simulation of the fabrication process to model the device structures that obtained from a specific process sequence.

Actually, Simulation and Experiment are approaches to IC process development.



10

Technology Development Flowchart

Circuit/System Specifications

Initial Process Flow Design

Keystone Product

1st Pass Design Rules

DEVICE DESIGN

Final Integration

Keystone Productβ Samples

Final Specifications

Production Transfer New Products

-Targets-CAD Models-Tolerances-Yield/Cost

-Layout Rules

Test Chip Design

Test Pgms

Initial Integration

Ckt Eval Phys Eval Elec Eval

Initial Device Profile Synthesis

Process/Device/Ckt Simulation

Initial CAD parameters

1st Pass Device FabPhys Eval

Elec Eval

Model Calibration

RSM analysis

Keystone ProductAlpha Samples

Final Design Rules

Process ModuleCharacterization

Process Simulation

Initial ProcessParameters

Elec Eval

Process ModuleOptimization

PROCESS DESIGN

Phys Eval



11

Design of Experiment (DOE)after NDL communications, vol.8, no. 3

一般而言，影響實驗結果的因子(factors)或製程參數(process parameters)有很多；故實驗者的目的極在於決定這些因子對系統輸出的影響，而實驗的策略即是規劃與執行實驗的途徑。

常用的實驗設計法有：

– Best-guess approach(最佳猜測途徑) or shot-gun approach (散彈槍)

• 大部分實驗者所採用的實驗策略• Disadvantages: 無系統化，無學習性 (可能進行很長一段時間卻無任何結果，而所得的結果未必是最佳化)

– Single factor experiment, one-factor-at-a-time(單因子實驗法)

• 實驗之進行，一次只改變一個因子 A (其餘因子固定不變)，由實驗結果決定因子A的最佳水準(如A2)

System (subsystem)

Input signal, M

Control factors

Output response, y

Noise factors



12

Design of Experiment (DOE)

• 將因子A固定於A2，再變換因子B (其餘因子固定不變)，由實驗結果決定因子B的最佳水準(如B4)。於此類推，亦即各因子分開個別處理。

• Disadvantages: 未考慮因子間的可能交互作用(interaction)，容易造成誤判。

實驗節潤的再線性差。

– Full factor experiment (全因子實驗)• 考慮所有因子間的交互作用(包含所有可能的組合)• Disadvantages: 需進行的實驗過多，耗時耗資，且可能導致增大誤差因子的空間。

– Fractional factorial experiment (部分因子實驗)• 基本因子設計的一個變化型態，再其中只有進行一個子集合的實驗。

⇒ Design of Experiments (實驗計劃法)

B2

Output, y

B1

Factor A

A1 A2

Interaction between factor A and factor B



13

Design of Experiment (DOE)

首創於1920 英人Fisher：– 利用變異數分析法(analysis of variance)來做為實驗設計中主要的統計分析工具，其整個檢定程序可摘要為“變異數分析表”。

– 著重於分析各因子間的交互作用– 以廣為工業界(含IC產業)QC採用

1950-1960日本田口玄一博士(Taguchi)提出的田口式實驗法((Taguchi Method)則較接近於工程的方法，又稱為穩健性設計(Robust design)

– 除了各因子的主效應外，旨在尋求各因子監交互作用對輸出回應的最佳化，或避免其對輸出的負面影響。亦即不探討或分析各因子間的交互作用。

– 為工程最佳化的策略，應用在產品/製程開發的初期最為有效。

田口式實驗法

– 定義穩健性(Robustness)為在最低的單位製造成本，使技術或製程性能之狀態對造成變異性知音子的敏感性最小化。

– 田口博士認為信號/誤差比(S/N ratio)式穩健性唯一的評估指標

output harmfuloutput useful

== NSη



14

Taguchi Method (田口式實驗法)

一般而言，發展產品與製程歷經三個階段(phase)1. 系統設計 (System design) 2. 參數設計 (Parameter design)3. 允差設計 (Tolerance design)田口法著重於參數的設計，其基本程序有八個步驟：

– Define objective: 定義目標，認定系統或次系統– Be sure ideal function/response:

確認欲得之結果，定義輸入信號(input signal, M)和輸出回應(output response, y)，建立理想機能：y = βM，決定量測可能性。

– Define signal and noise factor:發展信號漢誤差因子策略，

定義信號水準和範圍(levels and ranges)，選擇關鍵的誤差因子並設定水準，

決定誤差策略

– Setup control factors and levels:確認所有的控制因子，

選擇關鍵的控制因子並設立水準，

選擇直交表，

指定控制因子到直交表，

田口法



15


– 執行實驗與收集數據– Data analysis: 計算S/N ratio和β

完成/解釋回應表執行二階段最佳化

預測結果

– Confirm run: 確認實驗– Documentation: 將實驗所得結果做成報告

量測系統特性之回應是田口式實驗法中最重要的策略。回應的型態可分為：

動態回應 (y = βM)，目標為降低系統機能的變異性(最常被使用)；

非動態回應：若系統無明顯的輸入信號與能量輸出，則將不定義y = βM，而採用非動態回應，其型式有五種：1. Operating window: 找出操作區間2. Smaller-the-Better Response (望小特性):目標為降低變異性和將其平均值最小化

Target value

Bad

dB 1log101

2

−== ∑

=

n

iiy

nNS η

Target value

Good



16


3. Larger-the-Better Response (望大特性):目標為降低變異性和將其平均值最大化

4. Nominal-the Best Response(望目特性)降低變異性且使其在目標植附近，但因沒有公式可同時處理減少變異與調整平均值之工作，故必須執行二階段最佳化(two-step optimization)：Step 1: 從S/N回應表選擇最佳組合(非最佳條件)以減

少變異。

Step 2: 調整平均值，當調整平均值不明顯時可尋找對變異影響最小彈對平均值影響甚大的控制因子，以有效地調整平均值；當所量測的特性全為正值或全為負值時，此時的目標值符號應與特性值同號。

計算望目特性S/N的一般公式為

dB 11log101

2

−== ∑

=

n

i iynNS η Target value

Bad

Target value

Good

1 ; wheredB,

)(1

log10

2

1

2

1−

−

=

=−

=

∑∑==

n

Sy

Vn

y

SV

VSn

m

n

ii

e

n

ii

mem

ηe



17


5. Classified Attribute Response(分級屬性目特性):回應無連續值，只有屬性值(attribute value)，如：好/不良/壞。



18

Chap 2 Basic Process Modules

Isolation technologyContact technologyMultilevel Interconnect technology



19

Isolation technology

Isolate devices built into the silicon from one another.Various isolation technologies exhibit differing attributes, with respect to – minimum isolation spacing,– Surface planarity,– Process complexity,– Density of defect generated during isolation process.

For bipolar ICs: – Junction isolation to isolate the collector regions.– LOCOS– Trench Isolation

For MOS ICs:– LOCOS (LOCal Oxidation of Si)– Modified LOCOS: for small-geometry devices– Trench Isolation– Selective-epitaxial isolation– SOI (silicon-on-insulator) isolation



20

MOS Isolation Technology

Field Oxide Isolation– Simple process but parasitic MOS transistors are formed

between (2) and (3)– The VT of parasitic transistors must keep higher enough to

prevent to form channels. (>VDD + 4V)– VT could be increased by

• Thicker field oxide ⇒ High step; sharp corners ⇒ poor step coverage for the following metal interconnect.—not preferred

• Higher doping beneath the field oxide ⇒ channel stopimplant, however, implant should be done before field oxide growth and thus the AA must subsequently be aligned to the channel-stop regions ⇒limit packing density.



21

LOCOS

Semirecessed LOCOS:Advantage:1. the step has gentle slope

that is better for subsequentlayer deposition.

2. Self-aligned process ⇒packing density↑

Fully Recessed LOCOS:– Silicon is etched (half the

desired FOX thickness)when Si3N4 pattering.

Advantage:planar surface

Disadvantage:complex process;etching induced defects.

SiO2



22

Details of LOCOS

Pad oxide: (100-150 Å)

– is to cushion the transition of stresses between Si3N4 and Si substrate. Thicker oxide, Less edge force. However, a thick pad oxide will render Si3N4 ineffective as an oxidation mask and induce more severe Bird’s Beak (BB) effect. ⇒minimum pad oxide thickness.

• Achieved by the use of CVD SiO2, which is more effective than thermal SiO2 for avoiding edge defects. (1/12 the thickness of the nitride layer)

• Use a pad layer consisting of a thin SiO2 and a buffer poly Si.(Poly-buffered LOCOS)

CVD of Si3N4(1000-1500 Å)

– Functions as an oxidation mask because O2 and H2O vapor diffuse very slow through it (preventing oxidation occurs at the Si surface under nitride). In addition, the nitride itself oxidized very slow compared to Si oxidation.

Active Area (AA) definition – Mask and Dry Etch Pad-Oxide/Nitride layers– AA Profile and overetch induced defects in isolation.



23

Issue of Channel Stop implant

Channel Implant– P-type Boron implant (1012-1013 cm-2) for NMOS and n-

type Arsenic implant for pMOS.Boron segregation and oxidation-enhanced diffusion during subsequently high temperature field oxidation. So Implant peak of Boron should be deep enough to prevent being absorbed by the growing field oxide interface.

However, – if the B implant is too deep and heavy (VT),

⇒ high S/D to substrate junction capacitance (n+-p+)⇒reduce S/D to substrate junction breakdown voltages

– Lateral diffusion of Boron will encroach into the NMOS AA⇒boron surface concentration ↑ near the AA edge ⇒VT ↑ near the AA edge⇒narrowing the AA width, acts as a narrower device.

– Dislocation induced by channel stop ⇒ leakageSolution: Low Thermal Budget Field Oxidation

• Low temperature oxidation (HIPOX, high pressure)• Ge/B coimplant: Boron diffuses much slower in the presence

of Ge ⇒B segregation effects are reduced• Cl implant to enhance the field oxidation rate to reduce

thermal budget



24

Field Oxidation

Bird’s Beak is formed by a lateral extension of the field oxide into the AA. The length of BB increases– Pad oxide thickness↑– Nitride thickness ↓– Field oxide thickness ↑, thermal budget ↑

Issue of BB:– Reduce the effective AA, ⇒AA has to be larger⇒impact packing density.

– Later contact-window-opening steps will overetch away part of the BB oxide and this may expose the substrate region under the source or drain region



25

Issue of BB

– Later contact-window-opening steps will overetch away part of the BB oxide and this may expose the substrate region under the source or drain region. Then, the source might become shorted to the well region when the metal film is deposited.

Solution: FOX etching back, Modified LOCOS

– Oxide field-thinning effect: the field-oxide thickness in narrow spacing is significantly less than the thickness of those grown in wider spacings. That is the oxidation rate depends on the opening geometry.

This has a great impact on field-threshold voltages and on the interconnect capacitances to substrate.

Source is shorted to the well when metal is deposited.



26

Issue of BB

Kooi Effect (Regrow Sacrifical Pad Oxide and Strip)Kooi discovered that NH3 is generated from the reaction between H2O and the masking Si3N4 during the field-oxidation step. NH3 then diffuses through the pad oxide and reacts with Si surface to form a very thin Si3N4 spots. (White Ribbon). When gate oxide is grown, the growth rate becomes impeded at these spots and the gate oxide thickness is thinner, causing low-voltage breakdown.

Solution: growing a “sacrificial” gate oxide before growing the final gate oxide.



27

White Ribbon



28

Limitations of LOCOS for ULSI

The BB encroachment into the device AABoron from the channel-stop implant of NMOS induced unacceptable narrow-width effects. The planarity of the surface topology is inadequate for submicron lithography needs.The field-oxide-thinning effect in submicron regions can produce problems with respect to – Field threshold voltages, – Interconnect-to-substrate capacitance, – Field-edge leakage.

Solution: Modified LOCOS or Non LOCOC technology (Trench Isolation)



29

Modified LOCOS Process

Etch-Back LOCOS:– The simplest way to reduce the BB and to obtain more planar

surface– But the Boron encroachment is not solved

Polybuffered LOCOS– Recall thinner pad oxide;

shorter bird’s beak.– Use polybuffered layer

(poly Si 500Å/oxide 50Å)and a thicker nitride (4000Å) ⇒ Bird’s beak is reduced.(< 0.15 µm)

– Polysilicon is used as cushionagainst damaging stress and without leakage and gate oxidedegradation problems.

– Thinner Field oxide is used and the channel-stop implant isperformed through the FOXand it also serves as thepunchthrough implant in AA

for short channel devices.



30

Sealed-Interface Local Oxidation

SILO: – a thin (100-200Å) nitride

layer is directly on the Si surface to seal the interface,

– a thin pad oxide (200-300Å)and nitride are deposited

– Channel stop implant⇒ BB is reduced; but steeper

BB profile; local interface traps due to stress.

⇒nitride directly contacted to Si leads defects

Laterally SILO– To reduce the defects induced by SILO. However, the problem of

planarity, boron encroachment, and FOX thinning do not addressed.



31

Advanced Fully Recessed LOCOS

SWAMI (Sidewall-Masked Isolation Technique)– Limited lateral encroachment ⇒packing density↑– No severe restrictions on FOX thickness;– Improved surface planarity;– Complete elimination of Kooi effect.– Complex process



32

SWAMI Process Flow

Pad oxide I and CVD Nitride I layerAA photo and Grooves are etched in Si to a depth of ~1/2 FOX thickness. The etch is done by taper etching (for example: a double-silicon plasma etch)Channel-stop implantA thin thermal oxide II (stress relief) is grown selectively on the field region and then a CVD Nitride II and a CVD oxide are depositedEtching back to form Oxide spacerThe CVD oxide spacer is used to protect Nitride II and define Nitride foot on the field regionThe length of Nitride foot is selected to minimize the BB.FOXRemove Nitride and Pad Oxide



33

SPOT

Self-Aligned Planar-Oxidation Technology– Conventional semirecess LOCOS– Buffered HF to remove FOX1– Regrow thin pad oxide and deposit conformal Nitride– Etching back Nitride and oxide– FOX2

Flat surface



34

Non-LOCOS Isolation

Trench IsolationAttraction: 1. Prevent latchup and isolate nMOS and pMOS in CMOS

circuits2. Serve as storage-capacitor structures in DRAMs3. Significantly small isolation width

⇒high packing densityChallenge in etching technology1. Control of the sidewall profile so that the trench can be

refilled by CVD without the formation of voids.2. Undamaged sidewalls to avoid leakage along trench3. The bottom of the trench should be smooth with round

corners for the oxide integrity and for keeping stress-induced defects from being generated during oxide growth

4. Trench depth should be uniform, especially in capacitor structures.



35

Trench Isolation

Grass resulting from a residue oxide on Si surface before trench etching



36

Details of Trench Process

Mask layer:– Inact during the trench etching– Thermal SiO2/Nitride/CVD oxide most popular

After mask layer patterning, the exposed Si surface must be “native oxide” free, otherwise, “grass” or “black” Si would be formed at the bottom of trench.Causes of “black” silicon:– Sputtered material from mask layer can redeposit on Si

surface and act as local spots.– presence of oxygen in Si can produce micromasks.

Taper etching for trench formation– Controlled by the deposition of a carbonaceous polymer

layer during etch process. (protect sidewall)– The polymer at the bottom of trench is sputtered by

energetic ions so that vertical etching process can keep going.

– Polymer deposition is temperature dependent, ⇒the temperature during the etch process must be constant to have a uniform slope sidewall.

– Polymer should be removed effectively (a wet HF and a dry O2 burning) before refill. ⇒poor interface, leakage…



37

Details of Trench Process

Trench profiles: – Cl-based etch gases. (BCl3/Cl2, H2/Cl2/SiCl4, CHCl3/O2/N2,

Cl2/O2/SiCl4, CBrF3N2)

Refilling1. A sacrificial-oxide is thermally grown on the sidewallsand then etched (by vapor HF).– to remove silicon damage layer caused by ion bombardment

during trench etching.– To round any sharp corners of the trench2. A thermal oxide (1000-1500 Å) is refilled (fewest defects

compared to other dielectrics) . Note:– oxidation rate is significantly reduced at the sharp corners of the

trench bottoms. The oxidation rate of the concave corners/surface is lower than that of convex corners/surface.



38

Refill

3. For trench-refill, various materials have been used, depending on the applications. In trench isolation structures, CVD polycilicon, CVD SiO2…In deep, narrow trenches, the deposition occurs in(1) Initial conformal stage: Voids(2) Seam-formation stage(3) Seam-closure stage(4) Cusp-planarization stage: overfill

If the trenches of widely varying widths are filled, the narrow ones must be well overfilled for the wider ones to be filled completely. ⇒topography formed.

4. Etch back or CMP to expose the mask film.



39

SOI Isolation

Silicon-on-Insulator (SOI): devices are completely surrounded with an insulator.Advantages:– A simpler fabrication sequence in some cases– Reduced capacitive coupling, latchup eliminated.– Reduced chip size,⇒packing density ↑– Increase circuit speed due to reductions in parasitic

capacitance and chip size.Disadvantage:– Active-device regions are poorer in crystalline quality



40

SOI Technology

Heteroepitaxial Techniques:Epitaxially growing a silicon film on a single-crystal insulator (eg., Al2O3 sapphire). – Thermal mismatch is the most important factor

determining the physical and electrical properties of heteroepitaxial silicon films.(defects/stress, contamination and wafer breakage)

Recrystallization– Polysilicon deposited on an oxidized silicon surface and

then recrystallized by laser, E-beam, IR source annealing.SIMOX: Separation by IMplanted OxygenFormation of a buried layer of SiO2 by implantation of heavy

dose of oxygen ions beneath the surface of a silicon wafer and then recrystallization by anneal.



41

SOI

As implanted 2 hr anneal at 1150 oC

6 hr anneal at 1185 oC

6 hr anneal at 1300 oC



42

SOI

Wafer Bonding– Two oxidized-silicon wafers are pressed together and

subjected to an oxidizing ambient at 700 oC.– When a moderate voltage is applied between two silicon

wafers, bonding is induced at 1100-1200 oC.– When two flat, hydrophilic surfaces such as oxidized

silicon wafers are placed against one another, bonding naturally occurs.

For CMOS and radiation-harden applications, SIMOX is a major technology. For power, high voltage, and bipolar applications, wafer bonding is the best technique.



43

Isolation for Bipolar ICs

Non-Oxide-Isolated Bipolar technology (large size)– Standard buried-collector (SBC):

– Collector-diffused isolation (CDI):

– Triple-diffused isolation (3D):



44


Oxide-Isolated Technology (shrink the size and propagation-delay times for VLSI ICs)– LOCOS based– Fully recessed



45


SBC (standard buried collector) Junction Isolation– Widely used in bipolar analog-circuit and power-circuit

applications where the power-supply voltages are in the 15-30 V range.

1. Starting material: p-type, lightly doped Si (1015 cm-3) -to minimize the parasitic collector-substratedepletion layer capacitance.

2. An (0.5-1.0 mm) oxide is grownand the oxide windows are openedfor n+ diffusion.

3. N-type epitaxial layer and oxide layer are grown.

4. Oxide windows are opened for p-type isolation diffusion.

5. Oxide layer is regrown over p-type isolation regions



46

Evaluation of Bipolar Isolation

Standard buried-collector (SBC): used in bipolar analog-circuit and power-circuit applications where the supply voltages are in the 15-30 V range.

Advantages: simpleDisadvantages:

1. Large inactive areas ⇒limit packaging density2. Large parasitic C/B and C/sub capacitances ⇒limit speed

Collector-diffused isolation (CDI): used in high-speed and low power-supply voltages digital applicationsAdvantages: flat surface topography suitable for device scalingDisadvantages:

large C/B and C/sub capacitances ⇒ relatively low C/B junction voltages ⇒limit to small power-supply voltages

Triple-diffused isolation (3D): The collector, base, and emitter are formed by ion implantation or diffusion directly into the substrate.

Advantages:1. Simple process (high yields and low costs)2. Smaller-area transistors are possible (no p-type isolation diffusions are

need to surrounded collector)3. Higher BVCEO compared to either CDI or SBC

Disadvantages:High value of RC results from the absence a buried-layer subcollector.



47

Contact Technology

Parasitic resistances exist in the path between the metal-to-Si substrate interface and the region in the device where the actual transistor action begins.

MOSFETs

The parasitic series resistance Rs,RS = Rco + Rsh + Rsp + Rac

Rco: contact resistance between M/S and M/DRsh: sheet resistance of the bulk region of the S and DRsp: resistance of the current lines crowding near the channel end

of the sourceRac: accumulation-layer resistance



48

Parasitic Resistance of BJTs

BJTs



49

M/S Contact

Non-ohmic contact is due to the work function difference between the metal and semiconductor; in general, ϕm > ϕs, and the potential barrier: qϕb = q(ϕm –xS)



50

M/S Contact

To create an ohmic-contact structure, – ϕb ↓, (choosing proper metal material)– n+ or p+, ⇒depletion width in semiconductor ↓ ⇒tunneling

Specific contact resistivity, ρc– a measurement-independent quantity that describes the

incremental resistance of an infinitely small area of a M/S interface. (Ω-cm2)

– ρc derived from experimental data can be modeled by

– native oxide or etching-induced polymer between M/S interface

Contact Resistance, Rco

A macroscopic quantity that depends on – ρc, contact size, contact geometry, and the semiconductor

sheet resistance

≈

D

beSic Nh

m ϕεπρ

4exp



51

Extracting ρc from Measurements

The current flow in actual contact structure is not uniform over the entire contact area, ⇒ ρc=V/IA is not valid for extracting ρc.Contact Structures– Cross-bridge Kevin contact (RK)– Contact end resistor (Re)– Transmission-line tap resistor (Rf)



52

Measurement ρc

Measurement: A specific current I is sourced from the diffusion level

(semiconductor) into the metal level through the contact window. Then measure the voltage drop V between the two levels using two other terminals.

⇒Rc(ρc)= V/I ⇒ρc

A simple way to monitor contact resistance is to use of Contact-Chain Structure

Homework: how to extracting ρc from Rc?Ref: W. M. Loh et al., “Modeling and Measurement of Contact Resistances,” IEEE Trans. Elect. Dev., p.512, 1987



53

Process of Ohmic-Contact

1. Heavily doped regions created for contact formation.– Shallow junction is required. (Implantation/RTP annealing,

barrier layer or diffusing dopant from polysilicon )2. Contact hole etched

– Wetting in small contact (megasonic, IPA dry)– Polymer contamination, etching induced-damage– Microloading effect (decrease of etching rate with decrease in

contact size) – Etching profile control: to provide a contact shape for better

metal step coverage: • lateral and vertical etching rate control (etching/deposition

mechanisms compete)• Multi-layer etching to provide taper profile• PR-erosion approach

3. Surface cleaned to remove the thin native-oxide, dry etching induced polymer or damage layer.

– A 2-5 Å native oxide will be consumed by contact metal during sinter step. However, the native oxide is more than that in general.

– HF dip/vapor to remove oxide: wetting and profile issues.– Sputter etching the contact and then depositing metal:

contamination issue (may cause more oxide deposited than etched)– In situ chemically dry-etch step to remove oxide and damage

layer: extra and complex equipment.



54

Process of Ohmic-Contact

4. Metal film deposition– Good step coverage deposition. (in general, CVD is better

than PVD)– Increase the deposition temperature to improve the step

coverage.

Simulated metal coverage of a contact hole with vertical sidewall.Noting: thinning at the bottom corners.

5. Contact sintering– To allow any interface layer existing between M/S to be

consumed by a chemical reaction and allow the metal and Si to form intimate contact through interdiffusion.



55

Sequence during Al-Si sintering

Al spiking enhanced dissolution of the Si during contact sintering. If the Al is stripped after sintering, Si pits appear.



56

Junction Spiking reduced by Al-Si alloys

~1 wt% Si can be added into Al so that the conc. exceeds the Si solubility in Al at the max. temperature, diffusion of Si into Al won’t occur.Issues:During the cooling cycle of a thermal anneal, the solid solubility of Si in Al ↓ with the temp ↓

⇒Al becomes “spuersaturated” with Si⇒nucleation and growth of Si precipitates out of the Al:Si

solution. These precipitates consist of a p-type Si doped with Al (a conc. of ~ 5x1017 cm-3)

– For a p+ Si-Al contact, these precipitates do not degrade the contact. For a n+ Si-Al contact, contact resistance ↑ for contact size < 3 x 3 µm2.

– Si precipitates formed within Al lines increase the susceptibility of the lines to electromigration failure. (The size of the Si precipitates is ≥ 0.4 µm, large flux-divergence in the current is produced at the locations of the precipitates formed, ⇒electromigration-induced open ckt.

Al-Si contacts are limited in advanced VLSI applications.



57

Diffusion barriers

The role of the barrier metal is – Prevent or retard the diffusion of the two original

materials into each other– Resist the tendency of a chemical reaction to form a new

phase between the adjoining materials.– Adhere well to the adjoining materials and should have a

low contact resistivity to original materials.– Have compatible thermal expansion coefficients to the

original materials– Good electrical conductivity (< 200 µΩ-cm)– In practice, the available barrier materials are not perfect,

the efficiency of such a barrier is determined by “how long”it can extend the lifetime of the contact structure under various thermal treatments.



58

Diffusion Barriers

Sacrificial Barriers:– It reacts with A or B and results in a separation between A

and B. Once the barrier has been totally consumed by the reactions with A or B, it loses functions.

– Polysilicon (Al-PolySi-Si)• Protect Si substrate from undergoing contact-

electromigration failure. Under high current stresses, Si from polysilicon, instead of from substrate, is transported into Al.

– Ti (Al-Ti-Si)• a oxygen-gettering material and oxide-reducing agent, which

causes it to dissolve the native oxide on Si surface during annealing.

• In Si/Ti/Al system, Ti reacts with Al to form TiAl3 as T>400 oC. Thick enough Ti is need to ensure an adequate lifetime.

• TiSi2 will be formed by the reaction of Ti with Si substrate during anneal step. TiSi2 will absorb the dopants from Si, especially if TiSi2 is used to connect n- and p-polysilicon)⇒large Rc, (TiN is needed)



59

Tungsten Plug with Etchback

Passive Barriers: – Chemically inert w.r.t A / B (low solubility for A/B)– TiN (Al-TiN-Ti-Si)

• Most attractive; Impermeable barrier to silicon• Activation energy for diffusion of metals is high• Chemically and thermodynamically stable (to 550 oC)• Sometimes Ti will be deposited before TiN to ensure good

contact resistance. (ρc ofTiN is higher than that of Ti)• Good contact resistance (10-6 Ω-cm2)

W plug (Al/TiN/W/TiN/Ti/Si)– Used as “contact plug” to connect multiple metals and as a

first level metal to connect MOS device terminals due to • high melting point, • comparable thermal expansion coefficient to Si • good step coverage (low stress).

– TiN is used as a diffusion barrier for W/Si and W/Al • to reduce junction leakage (Wormhole induced by lateral

encroachment of W under Si-SiO2 interface) and provides adhesion of W and SiO2.

• As etch stop layer for W etching back. – Resistivity 3~4 times that of Al, unsuitable for

interconnect metal.



60

Issues of Tungsten Plug

Selective W plug:- loss selectivity- Uneven fill- Junction leakage- wormhole

Blank W dep &Etching backUniformity of W deposition, or, W plug will be recessed after etchback, ⇒poor Al step coverage



61

Issues of Tungsten Plug

- TiN weaken at sharp corner by WF6 attack- TiN peeling by Ti and WF6 reaction- W volcano



62

Impact of Rs on MOSFETs

As devices shrinking, Rch ↓ and Rs ↑ due to shrinking contact sizes and shallower S/D junctions.The series resistance, Rs, of the source and drain should be small compared to the channel resistance Rch.

Rs ~0.1 Rch

Recall: RS = Rco + Rsh + Rsp + Rac

– Minumum Rco,• the contact length will be only 1-4 times the channel length

⇒ self-aligned silicides S/D.• ρC minimized by implant dose, annealing, contact premetal

cleaning.– Rsh effect is negligible for silicided S/D.– Rac+Rsp is likely to dominate the value of Rs for channel

length < 0.5 µm. It could be minimized by fabricating S/D junctions with as steep a doping profile as possible.



63

Self-Aligned Silicide Contacts

Have the ENTIRE S/D area as the contact windows instead of part of the areas. ⇒Rco ↓Effects on layout area: For conventional S/D,

For one contact in S/D, ⇒current crowding

Different contact arrangement:⇒ Take away routing area⇒ Increase layout area for

routing

If the S/D is silicided, no current crowding occurs and only one contact is needed.



64


Conventional Structure



65


Folded extended Window structure (FEWMOS)



66

Processing Issue of TiSi2

– Forming of a bridge between gate and S/D.⇒”Short”

Si “pumping”during TiSi2 formation

– Narrow-line-width effect: the grain size is limited by the linewidth, and only a fraction of the line is covered by the C-54 TiSi2

– Difficulty in forming silicide on thin strips of polysilicon and the diffusion region. The transformation of the high-resistance C-49 phase TiSi2 to low-resistance C-54 phase occurs at high T (>750 oC). However, TiSi2 agglomerates at >750 oC. CoSi2 was proposed for very fine lines.

– Dopant depletion at the TiSi2/Si interface during anneal– Thermal stability of thin silicides



67

CoSi2

CoSi2 is attractive due to:– Low resistivity (16-18 µΩ-cm) and high temperature

stability up to 900 oC.– No lateral formation of the CoSi2 or encroachment under

oxide (no bridge problem)– CoSi2/Si interface is smooth and low-resistance contacts to

Si (15 Ω-µm2 for n+ and p+)– The dopant profile remains unchanged when CoSi2

contacts to shallow As and B junctions.– Less silicide loss during overetch that may be needed

when dry-etching the contact openings.But– Co is not an oxygen gettering species, it will not dissolve

the native oxide on Si surface, special interface treatments needed before Co deposition.

– The reliability of CoSi2 is very sensitive to the O2 ambient during the subsequent RTA.

– Solution: A Ti cap layer is used on top of CoSi2.– Complex and high-cost process



68

Shallow Junctions

Conventional Shallow-Junction Formation– Ion Implantation + Annealing– Easy to form shallow n+ junctions by using As.

• Heavy As atoms tend to create amorphous Si surface which prevent As from undergoing significant channeling during implant.

• The amorphous layer could be recrystallized at relatively low temperature anneal.

• The diffusivity of As is low at high temperature– More difficult to form shallow p+ junctions

• Light B atom⇒amorphous layer is not easy to form ⇒channeling.

• Crystal-defect damage caused by B implantation must be annealed at T>900 oC ⇒deep junction.

Solution:• B implant through screen oxide

– Recoiled oxygen atoms and difficult to accurately control the dose penetrating through to Si.

• BF2+ implantation

– Fluorine ions damage • Preamorphized by Si+, Sn+ or Ge+ implantation.• RTA anneal



69

Alternative Ways for Shallow Junction Formation

Implantation into already formed silicide layer and outdiffusion of the dopant into the substrate.– All the implanted ions stop in the silicide, no damage

created in Si, ⇒ leakage currents caused by damage within the junction depletion region are eliminated.

– Annealing temperature is lowered since no implant damage is needed to anneal out.

– Steep dopant profiles since no damage to Si (no transient effect diffusion)

– Uniform dopant profiles since dopants diffuses rapidly in silicide and no shadowing effects occurs

But:– Only works in CoSi2 (~0.12 µm shallow junction); TiSi2 is

not suitable for this way since very high affinity of As and B for TiSi2.

– Further scaling is extremely difficult with silicide(< ~0.1µm), since it is vulnerable to other processing environments and mechanical stress.



70

Alternative Ways for Shallow Junction Formation

Raised Source/Drain Juntions– Selective epi-growth (200-400 nm) of Si over the

source/drain regions followed by implantation into this epi-layers and then driving into the substrate. Finally, a salicide is formed on the epitaxial Si.

– The silicide does not erode the shallow junction since the consumption of Si during salicide formation is from the epitaxial Si,

– The thicker Si, the lower sheet resistance of S/D.But

– Addition to the sidewall capacitance (Miller capacitance). A thicker sidewall spacer is needed to reduce this parasitic.



71

Raised Source/Drain



72

Impact on Contact Formation

The use of shallow junction implies the need for planar contact interfaces that consumes Si slightly (as occurs when PtSi, TiSi2, CoSi2, and CVD W layers are used to contact Si)

– Raised S/D can solve this problemSpecial considerations are necessary for selecting the suitable metal, layer thickness, etc.



73

Multilevel Interconnect

The aim of scaling active device is twofold: (1) to increase circuit speed, and (2) to increase the functional complexity of the circuit.Eventually, the scaling of active device is less practicalsince the limitations of the circuit speed and maximum functional density came to depend more on the interconnects (RC delay) than on the scaled devices.Active-device density:– Is defined as the number of devices per chip area

Functional Density:– Is defined as the number of interconnected devices per

chip area; (how effectively the active devices can be interconnected)



74

Interconnect Limitations of VLSI

Functional Density:– The area occupied by the interconnection lines on the chip

grew more quickly than the area needed to accommodate the active device.

⇒minimum chip area become interconnect-limited ⇒continued shrinking of active devices produces less circuit-performance benefits.Solution: “Multilevel-interconnection”

Propagation Delay– As active device shrink, the device contribution to the

propagation delay decreases; on the other hand, the scaling of the interconnect line widths does not give a corresponding decrease in the propagation delay time. Since the interconnect-path lengths increase as the chip sizes increase.

– The propagation delay in VLSI circuits is almost limited by the large RC delay of the interconnect lines.



75

RC Delay



76

Problems associated with MultimetalInterconnect Processes

– Added process complexity and Loss of topological planarity

– New materials must be used, ⇒extensive characterization to ensure the compatibility.

– New process-related manufacturing difficulties may be encountered that may adversely impact manufacturing yield.

– New failure modes may be encountered: electromigration, corrosion, hillock formation.



77

Multilevel-Interconnection

Terminology:– IMD: the dielectric layers between metals levels.– Contact holes: opening in the dielectric layer between the

first metal and the active device (such as gate, S/D)– Via: opening in IMD

Two tasks in multilevel metallization:– To deposit a void-free interlevel dielectric (ILD)– To smooth out the surfac morphology and reduce

topography



78

Dielectric Materials



79

IMD Deposition

The processing temperature for IMD should be lower (<400 oC).Plasma-enhanced SiO2: Silance-based oxidesSiH4 + 2N2O → SiO2 + 2H2 + 2N2

SiH4 + O2 → SiO2 + 2H2

– Poor step coverage and containing a large amount of hydrogen.

– Can be improved with high-density plasma sources.PETEOSSi(OC2H5)4 + O2 → SiO2 + by products – With plasma enhancement, good-quality oxide can be

achieved at < 400 oC. – Good step conformity, but it has a tendancy to build up at

the upper corners of metal lines.⇒”Voids”– Sometimes, voids are formed due to the imperfect metal

profile or multilayerd structure.Voids will pose – Reliability concern (chemicals trapped in the void)– Metal lines broken during the planarization



80

IMD

Voids open into trenches during planarization

Metal line broken

Voids formed due to the nonperfect TEOS conformity

Voids formed due to the nonperfect metal profile



81

Voids-free IMD

Solution: (But: Expensive process)– Multistep processes using ion bombardment to round off

corners to enhance ILD filling capability deposition/etch/deposition

– TEOS+O3 APCVD or SACVD without plasma at 150-400 oC.

deposition etching deposition

Liquid-like flow



82

IMD

Charateristics of O3-TEOS:– Deposited by AP/SA CVD < 400 oC without plasmas.– Sensitive to the surface conditions– Higher Temp and O3 conc.⇒higher oxide quality but

lower deposition rates.– Good step coverage and higher aspect ratio filling than

PETEOS.But: – Somewhat porous with a shrinkage of 1 to 3% after 450 oC

anneal, which will cause gate oxide damage and poisonmetal contact.

Solution:O3-TEOS etching back to provide a gap filler.



83

O3-TEOS/PETEOS Etching Back

But this etching back is expensive and a potential source of particles.⇒ Nonetchback SOG process is important.



84

IMD-Spin-On-Glass

(SOGs+curing) are widely used for low-cost IMD for gap filling.– Low cost– Good cap filling capability– Better IMD planarity

But– Water absorption and inferior dielectric and mechanical

properties to those of PECVD.Two basic types of SOG:Inorganic: silicate-based– Does not absorb water significantly; Thermal stable– Volume shrinkage during curing is large; ⇒high

stress, cracking ⇒only apply for thin layers– Add up to 4% P can produce a softer SOG, but increase water

absorption and mechanically and electrically unstable.Organic: siloxane– Retain C even after curing, – Lower stress and can be applied in thicker layers– Sensitive to water absorption and poor thermal stability (< 400

oC)– Unstable under plasma exposure.

Apply for >0.35 µm device process.



85

High Density Plasma SiO2

Provides oxides of exceptional quality even at low temperature. And by applying a bias, it can also provide excellent gap filling capability.HDP SiH4 oxide is preferred over TEOS due to– Silane chemistry leaves no C residue– Silane is a gaseous precursor and is easier to handle than

TEOS precursor– Becoming the dominant IMD process for devices 0.35 µm

and below.But

– The deposition rate is low due to Low pressure deposition. (could be solved by increasing Silane flow rate)

– Device damage by ion species. (needs further study)



86

Chap 3 Interaction Between Process Modules

Thermal BudgetsStress induced material stabilityTopography induced photolithography and etching issues

Chap 4 Process Integration Consideration: Design RulesCompactnessStep HeightProcess WindowYield



87

Planarization

The planarity of IMD serves two purposes:– A smooth surface to ensure good metal step coverage– A flat-enough field, within the lithography depth of focus

that contact vias and metal wires can be patterned.

No planarization

Smoothing:

Corners rounded and sidewall sloped,

Partial Planarization:Smoothing plus a reduction in step height locally

Local Planarization:Complete filling up of smaller gaps

Global Planarization:Local planarization + significant reduction in step height



88

Planarization

Quantitative definition of planarization:– R = the relaxation distance– θ = planarization angle

Planarization for various processes



89

Topography

Buildup of topography by multilevel metallization



90

Topography Induced Process Issues

Poor step coverage of the metal lines as they cross over the high and steep steps.

Metal Stringers remain after anisotropic etching

Residue after etching



91

Price Paid for DielectricPlanarization

The increase of maximum variation in the thickness of the dielectric layer at different locations.– IMD layer might be too thin over some of the underlying

conductors, which might cause “short” between metals.– More serious, it will cause “different depth” for via

etching and fillingExample: the variation of via depth for full planarization.

The lateral dimensions of the shallow vias will continue to increase during the time needed to completely etch the deep vias

Overetching induced “ditch”, ⇒”Short”occurs when M2 is deposit.



92

Etchback Planarization

Topography could be smoothed by etchback



93

Global Planarization by Etchback

Global planarization could be done by etchback +– Dummy metal

– The dummy metal should be electrically inactive. But it might impose capacitance and ground problem.

Dummy metal



94


– Dummy oxide mask

– Provide local smoothing and global planarization, but does not remove topography from previous layers.

Dummy Oxide



95


Reverse tone oxide mask

Reverse toned mask

Dry etching with sharp corner

Wet etch removes sharp corners, and then deposit IMD2 + SOG

Etchback

Topography is not reduced



96

Chemical/Mechanical Polishing

CMP: a true global planarization

CMP is used once

CMP twice



97

Design Rules related to IMD and Planarization

Design rules depend on– Type of IMD material and thickness– Method of deposition– Method of planarization

Consider a two-level-metal system: the design rules dealing with the following conditions must be specified:

1. Minimum poly to metal spacing, assuming no metal overlap of poly

– void or crevice (cannot be covered by next metal)

2. Minimum distance between coincident edges

when M1 overlaps polySi– total step height may be

too high for M2 coverage

3. Minimum spacing of M1 to M1

– Crevice or void formed



98

Metal Deposition & Via Filling

Conventional Via processing– Sloped (tapered) sidewall via– Easy for via filling

But: Limit maximum packing densityDesign Rule of multilevel metals for taper vias– The underlying metal pad must be larger than the

via opening; if not⇒crevices will be formed due to overetch and could cause

microcracking or thinning of M2.



99

Design Rule of Taper Vias

– The slope of the vias must be taken into account when deciding the minimum spacing between vias; A minimum space (2d) is needed between the tops of the etched via openings.

– The overlying metal pad must be larger than the top of the via opening to ensure full coverage of the via



100

Vertical Vias

Increases in packing density– Minimum distance between adjacent metal lines are the

via is reduced.

– The pad of metal can be decreased since the plu in the completely filled via provides ample overetch protection to underlying metal w/o mask coverage.



101

Metal Filling



102

Conductor Materials

Al: generally used as the top level of metal in multi-level metal system since wire-bonding technology to Al is a well-characterized process.– Low resistivity, good adhesion to Si

But– Hillocks formed at low temperatures (>300 oC)– Electromigration and corrsion



103

Conductor Materials

W: has been investigated for a number of roles in multilevel- interconnect systems:– Excellent resistance to electromigration hillock formation,

and humidity-induced corrosion.– Better step-coverage by means of CVD– Selective CVD W can fill contact holes and vias with very

high aspect ratios.But– Higher resistivity,– Rough surface after deposition,– Difficulties involved with etching —most severe

• Flourine based etching: W and SiO2 both form volatileflouride by products. ⇒ poor selectivity W/SiO2

• Chlorine based etching: most commonly used with higher selectivity to SiO2, but the selectivity to photoresist is poor. ⇒ inorganic mask or composite PR/SiO2 mask is needed. ⇒ complex process

• Two-step etching:– 1st step: high power RIE mode etching with (SF6, HBr, and

CH4 ) mixture gas– 2nd step: low power rf mode microwave plasma etching with

(SF6, HBr, and CCl4 ) mixture gas, and selectivity of 4:1 to SiO2 is obtained.



104

Conductor

Au:– Low resistivity (2.2 µΩ-cm), good electromigration

resistance and resistance to corrosion.But– “Posion” to devices; causes deep-level traps in the

forbidden gap, degrading the minority carrier lifetime.Cu: – Excellent low resistivity (1.7 µΩ-cm), good

electromigration resistance.– Dry etching issues: but now can be solved with CMP or

selective deposition– Poision to devices: could be controlled by using Si3N4

under the Cu lines.– Corrosion: nickle layer on top of Cu.– Extensive study is undergoing: electroless plating, CVD,

barrier layer, passivation, bonding, …



105

Yield Issues

Yield-limiting factors associated with multilevel-interconnect:– Junction spiking– High contact resistance between M1 and Si– Gate-to-source shorts due to lateral silicidation over oxide

spacer– Contamination of Al interconnects by incorporation of

residual gases present during sputter deposition. For example:Oxygen incorporation⇒film resistance & hardness ↑Nitrogen incorporation ⇒ stress ↑, “crack”



106

Yield Issues

Related Yield Issues– Pinholes and weakspots in the IMD layers ⇒”Short” or

unacceptably “low” breakdown voltages• Particulates,• Hillock growth in the underlying metal• Thinning of the photoresist over the corners of steep steps in

IMD– Misalignment during via patterning processes ⇒”Open”– Topography-related issues:

• Step-coverage problems cause “open” in interconnect• Stringer causes “Short”

– Open circuit or high contact resistance between conductor of different levels, due to

• Incomplete etching of all via holes• Failure to remove the native oxide or etching-induced

polymer prior to the deposition of the next level of metal• “Poisoned vias” occurring when SOG outgas during metal

dep.• High Via resistance

Thermal Budget



107

General Reliability Issues for IC Interconnects

Electromigration – Motion of the ions of a conductor in response to the

passage of current through it. Ions are moved “downstram”by the force of the “electron wind” ⇒accumulation of “vacancies”, forming a void in the metal. ⇒”open ckt”

– Failure rate ↑ as the current density in metal line ↑ or T ↑.Solution:

• Adding Cu (0.5-4%) to Al film.• Adding Ti (0.1-0.5%) to Al.• Using highly electromigration resistance metal (Ti, W, or

Mo) as a central layer between Al films. (Al/Ti/Al)• Planarization to eliminate thinning of the conductor lines as

they cross steps.• Selectively depositing a layer of CVD W over the Al lines.• Replacing Al with W or Mo.

Electromigration at the Contacts Interface– Voids in the Si ⇒”open ckt” or Al spiking

Stress-Induced Metal Cracks and Voids– Cracks or voids observed at elevated temperatures

Corrosion– Moisture and Cl contaminants Cl reacts with metal– P from PSG reacts with moisture to form phosphoric acid

to attack Al.



108

Reliability Issues associated with multilevel interconnects

Hillock Formation– Erupt due to compressive stress in metal films

• Thermal expansion of Al is >> Si ⇒ as T>300 oC, compressive strain becomes very high

• Low melting point of Al and the consequent high rate of vacancy diffusion in Al films.

– ⇒Interlevel shorts or Intralevel shorts



109

Hillock Formation

Interlevel shorts – When hillocks penetrates IMD– Photoresist thinning and might be completely removed

during via-etch processIntralevel shorts– Hillocks protrude from the sides of the metal lines and

cause overlaying dielectric layers to delaminate.



110

Chap 5 Process Simulation

To carry out processing experiments with the aid of a computer, using mathematical models formulated to describe the phenomena being studied; just like a “paper experiments”– Dopant redistribution– Oxide growth– Thin film deposition and etching

Typical Sequence of numerical simulation tools



111

Hierarchy of Simulation for IC development



112

Information obtained from Simulation



113

Benefits and Limitations

Benefits:– Shorter development cycle of a new technology– Allows the analysis of effects that cannot be measured, such as

lateral impurity profiles, the location of depletion regions, impact ionization and punchthrough.

– Process sensitivities and trade-offs in device design can be analyzed.

Limitations:However, many of the physical processes are still not completely

understood. Further, process models must often be simplified to save the computation time.

⇒Error must occurs in the simulation results, therefore, process simulation must still be regards as useful guides, but not yet perfect representations of actual process sequences.

Guidelines to improve the effectiveness of process simulations:– Good understanding of the process or system being used;

including: models being used, range of applicability, and their limitations.

– Understanding the computing environment and to have the capability to modify this environment to accommodate the simulation software.

– Understanding of the numerical technique used in the simulation program and to improve the probability of obtaining accurate results.



114

Process Simulators

TSUPREM4– New models and advanced analysis capabilities

Taurus Process:– 3D process simulation

Photolithography and Etching (SAMPLE)



115

Example: nMOSFET simulated by TSupremIV

$ TMA TSUPREM4 NMOS transistor simulation$ Part a: Through field oxidation

$ Define the gridMESH GRID.FAC=1.5METHOD ERR.FAC=2.0

$ Read the mask definition fileMASK IN.FILE=s4ex4m.tl1 PRINT GRID="Field,Poly"

$ Initialize the structureINITIALIZE <100> BORON=1E15

$ Initial oxidation (350 angstrom)+N WELL IMP+DRIVE INMETHOD PD.TRANS COMPRESSDIFFUSION TIME=50 TEMP=800 T.FINAL=925DIFFUSION TIME=9 TEMP=925 WETO2 DIFFUSION TIME=50 TEMP=925 T.FINAL=800IMPLANT BF2 DOSE=1.2E13 ENERGY=70 TILT=7 ROTATION=30DIFFUSION TIME=72 TEMP=800 T.FINAL=110DIFFUSION TIME=115 TEMP=1100 DRYO2DIFFUSION TIME=72 TEMP=1100 T.FINAL=800 ETCH OXIDE ALL

$ Pad oxide (350 angstrom)+Nitride deposition and field region maskMETHOD PD.TRANS COMPRESSDIFFUSION TIME=50 TEMP=800 T.FINAL=925DIFFUSION TIME=9 TEMP=925 WETO2 DIFFUSION TIME=50 TEMP=925 T.FINAL=800 DEPOSIT NITRIDE THICKNESS=0.15 TEMP=780 SPACES=4DEPOSIT PHOTORESIST POSITIVE THICKNESS=1EXPOSE MASK=FieldDEVELOPETCH NITRIDE TRAP UNDERCUT=0.02

$ BF2 field implantIMPLANT BF2 DOSE=4E13 ENERGY=120 TILT=7 ROTATION=30ETCH PHOTORESIST ALL



116

nMOSFET simulated by TSupremIV

$ Field oxidation (5500 angstrom)METHOD PD.TRANS COMPRESSDIFFUSION TIME=20 TEMP=800 T.FINAL=980DIFFUSION TIME=120 TEMP=980 WETO2 DIFFUSION TIME=20 TEMP=980 T.FINAL=800ETCH OXIDE THICKNESS=0.011ETCH NITRIDE ALLETCH OXIDE THICKNESS=0.04

$ SACIFICED OXIDE (350 angstrom)METHOD PD.TRANS COMPRESSDIFFUSION TIME=50 TEMP=800 T.FINAL=925DIFFUSION TIME=9 TEMP=925 WETO2 DIFFUSION TIME=50 TEMP=925 T.FINAL=800 ETCH OXIDE THICKNESS=0.056

$VT AND APT IMPLANTDEPOSIT OXIDE THICKNESS=0.03IMPLANT BF2 DOSE=5E12 ENERGY=90 TILT=7 ROTATION=30IMPLANT BORON DOSE=4E12 ENERGY=45 TILT=7 ROTATION=30

$REMOVE SACRIFIED OXIDEETCH OXIDE THICKNESS=0.056

$Deposit GATE OXIDE (100 angstrom)ETCH OXIDE THICKNESS=0.008DEPOSIT OXIDE THICKNESS=0.01

$ Save structureSAVEFILE OUT.FILE=NMOSAS

$ Plot the initial NMOS structureSELECT Z=LOG10(BORON) TITLE="LDD Process - NMOS Isolation Region"PLOT.2D SCALE GRID C.GRID=2 Y.MAX=2.0PLOT.2D SCALE Y.MAX=2.0

$ Plot contours of boronFOREACH X (15 TO 20 STEP 0.5)CONTOUR VALUE=X LINE=5 COLOR=2

END

$ Print doping information under field oxideSELECT Z=DOPINGPRINT.1D X.VALUE=4.5 X.MAX=3 OUT.FILE=NMOSDOPINGF



117

Chap 6 Failure Analysis

Process EvaluationResistivity measurement– Four-Point Probe

• Measure the resistivity: ρ (Ω cm) on wafers or the sheet resistance: Rs (Ω/ ) of doped thin layers

Doping Profile– Spreading Resistance Profile (SRP)

IsV /2πρ =

s

IVRs /53.4=



118

Process Evaluation: Doping Profile

Secondary Ions Mass Spectrometry (SIMS)• A combination of ion milling and secondary ion detection

method. Secondary ions are generated from the removed material which contains the wafer material and the dopant atoms. The secondary ions are collected and analyzed to provide a calculation of the amount of dopant at each level.



119

Process Evaluation: thickness

Spectrophotometers/Reflectrometery– Monochromatic light (UV) is reflected off the sample and

analyzed by a photocell. The physical properties of the thin film could be analyzed by the photocell such as the thickness and index of refraction.

Ellipsomters:– Polarized light incident upon the sample surface and detect

the reflected light.Φ0

T1

T2

空氣

第一層

第二層

基板

N0 (=N0)

(=N1-iK1) N1

N3

N2(=N2-iK2)

(=N3-iK3)(=NS-iKS)

parameters measured are ) ,(;tan ϕγ

γϕρ ∆== ∆

s

pie

T1= f2(Δ,φ,λ,Φo,NS,KS,N2,K2,N1,K1,N0,T2)

0 = g2(Δ,φ,λ,Φo,NS,KS,N2,K2,N1,K1,N0,T2)



120

Process Evaluation: thickness

Stylus:– Some films such as metal (Al) can not be measured by

optical techniques ⇒ “stylus”– α-stepper



121

Process Evaluation: Junction Depth

Off-line measurement: “destructive”Stain/SEM

– Etching rate is higher on N-type region or ‘heavily doped region’

SRPSIMSScanning capacitance microscopy (SCM)

– One of the options with atomic force microscopy (AFM) is a probe that measures capacitance. Since the capacitance of a doped layer changes as the junction is approached.



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Process Evaluation: CD

Critical Dimensions (CD) and line width measurements– SEM



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Process Evaluation: Defect

Microscope techniques– Light field microscope– Dark field microscope:

All flat surfaces “black”, and any surface irregularities, such as step or pieces of contamination, appear as bright lines.

⇒ More sensitive than “light-field” to surface irregularity

SEM : Resolution: 20-30 ÅTransmission electron microscope (TEM)– Resolution: 2 Å, best used as off-line tool, but sample

preparation is time consuming and requires precision.Laser detection: (automated in-line detection)– Detect smaller particle size; Wafer mapping



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General Surface Characterization

AFM– A surface profiler that scans a delicately counter-balanced

probe over the surface. (contact or non-contact)– Resolution : 1 Å– Grain size characterization, detect particles, surface

roughness, and CDs in 3DAuger Electron Spectroscopy (AES)X-ray Spectroscopy (XPS); Electron Spectroscope for chemical analysis (ESCA)– Determine the surface chemistry by detecting binding

energy shift.



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Device Evaluation

Electrical Measurement– I-V, C-V– Transconductance, Rs, Ro, VT, current gain,…

Failure Analysis: emission microscopy– When a semiconductor device is operating, it gives off

certain emission of visible light. Spots of visible light are given off at the trouble spot. Microscopes fitted with sensitive detectors and CCD can locate and image these trouble spots.

– Useful when electrical measurements indicate a failure in a sector of a circuit, but cannot pinpoint the exact devices causing the failure.



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Chap 7 CMOS Technology



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CMOS Process Flow, contd,



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BiCMOS Technology



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BiCMOS



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Chap 8 MOS Memory Technology

DRAM: capacitor on bit (COB) structure– Well– Isolation– Device– Bit line– Capacitor– Contact– Interconnect– Passivation



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DRAM



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DRAM Process



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DRAM Process



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DRAM Process



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DRAM Process



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DRAM Process



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DRAM Process



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DRAM Process



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DRAM Process



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DRAM Process



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MEMS

Unlike ICs, which rely on the electrical properties of silicon, MEMS devices utilized silicon’s mechanicalproperties to form flexible membrances capable of moving in response to pressure or other physical parameters change.– Traditional MEMS devices: relay on materials typically

used in Si IC fabrication, such as single-crystal Si, polySi, SiO2, and SiN.

• Sensors: generate an electrical signal from physical stimuli

such as pressure, acceleration, heat, and radiation.– Acceleration sensors: for automobile airbag deployment

control– Pressure sensors: for monitoring blood pressure– Chemical sensors: for detecting gaseous compounds

quantitatively.• Actuators:

convert electrical energy to some form of controlled motion.

– Micromirrors: in video display systems– Ink-dispensing nozzles in inkjet printers– Valve /pumps in miniature fluidic systems.



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MEMS

• Due to the mechanical nature of MEMS devices, intrinsic material properties are important in MEMS design, such as

– Young’s modulus, – Temperature coefficient of expansion– Yield strength– Thin film stress and stress gradients

IC device processing issues:– Gate oxide integrity, device isolation, submicron gate

formation, are not of much concern for MEMS.MEMS processing concerns:– Controlled etching for membrance formation,– Mechanical friction of microscopic parts– Surface tension effects



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Fundamental of Mechanics

A basic knowledge of the mechanics of materials is necessary to design and operate MEMS devices. The concepts includes:– Strain ε :

A tensile force will cause a rod (length L) to lengthen by an amount ∆L. The strain is defined by ∆L/L.

– Stress σ: is defined in terms of the force F and the area over which F is applied.

– Hook’s law:describes the linear relationship between the stress and strain at low stress values. σ = εE, where E is the slope of the linear region of the stress-strain curve, and is commonly called Young’s modulus. MEMS devices are generally designed to operate at stress in the linear region, so E is an important material parameter in MEMS design.

– Poisson’s ratio: the change in lateral dimensions due to an axial force is defined as the lateral strain εa. Poisson’s ratio is defined v by v = - εl / εa



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Film Stress

Intrinsic stress:– Resulting from the nonequilibrium nature of thin film

deposition processes. During deposition, after reaching the surface, atoms often do not have the necessary kinetic energy or sufficient time to migrate to the desired lowest energy state before more atoms arrive, resulting in lattice stress.

– Postdeposition annealing at elevated temperatures is commonly used to relieve intrinsic stress.

Extrinsic stress:– The most common source of extrinsic stress is a difference

in the thermal coefficient of expansion (TCE) between the depsoited thin film and the substrate.



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Mechanical to Electrical Transduction

The measurement of physical quantities such as pressure, acceleration, and mass change is based on sensing mechanisms that convert (or transduce) changes in these quantities to electrically measurable parameters such as resistance, capacitance, and changes in characteristic frequencies. MEMS sensors generally have a structural element that moves in response to the physical quantity being measured, such as membrane diaphragm moving in response to a change in applied pressure.The piezoelectric effect is the phenomena whereby a force applied to certain crystalline materials causes an electrical charge to be generated on the surface of the crystal, with the amount of the charge directly related to the applied force.



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Piezoresistivity

Piezoresistivity is a property of materials that describes the change in electrical resistance as a function of mechanical stress applied to the material. Piexoresistance in single crystal silicon is primarily dependent on:– Doping type (n- or p- type) and concentration– Temperature– The direction of the current flow relative to the orientation

of the crystal lattice– The direction and type of force (tensile or compressive)

relative to the orientation of the crystal lattice. The most important parameter for MEMS devices made with (100) Si wafers is the doping type.



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Mechanics of Common MEMS Devices

Many MEMS devices utilize either thin film membranes or cantilever beam structures. – Thin film membranes in Si MEMS devices are usually

square or rectangular in shape, with side lengths ranging from hundreds of microns to more than several millimeters. The membrane material is usually silicon (either single crystal or polysilicon) or silicon nitride.

– MEMS cantilever beams are commonly hubdreds of micron long, tens to hundreads of micron wide, and less than five micron in thickness.

The important mechanical properties of membranes and cantilever beams can be derived from a stress/strain analysis using thin plate deflection theory or beam deflection theory. In general, for membranes, the relevant assumptions of thin plate deflection theory are – (1) the maximum membrane displacement is less than

20% of the membrane thickness⇒this will put a limit on the force that can be applied to the membrane.

– (2) membrane thickness does not exceed 10% of the plate length

– (3) there is no initial stress in the membrane.



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Bulk Micromachining

Bulk micromachining refers to MEMS fabrication that involve removal of significant amounts of the silicon substrate in order to form the desired structure. Etching is the corner stone of bulk micromachining. – Wet etching (isotropic and anisotropic) has dominated

MEMS devices,• Anistropic etching: KOH, EDP, N2H4, TMAH

– But isotropic vapor phase etching and high-density plasma-based etching are emerging.



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Anisotropic etchant

Effect of mask opening orientation on the etch profile.



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Etch Stop Techniques

An important aspect of MEMS bulk micromachining is the capability of forming structures with reproducible mechanical properties such as resonant frequency and deflection. From a processing standpoint, this requires tight control on the dimensions of MEMS elements. Methods for controlling etch depth in bulk micromachining are called etch stop techniques:– Timed etches: simplest, but least accurate.

Disadvantages: loading effect, where the etch rate changes as silicon is etched, due to dilution of the etch species.

– Anisotropic etching of v grooves: simple, – P++ doping: all anisotropic etchants show a drastic

decrease in etch rate when the silicon is heavily doped with boron.

Disadvantages:(1) added process steps, (2) the piezoresistance

coefficients decrease significantly, (3) the high boron concentration is not compatible with IC technologies, so integration with on chip electronics is difficult.



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Etch Stop Techniques

– Electrochemical etch stop:is based on the fact that electrically biasing n-type silicon positively with respect to the etchant solution prevents the n-type silicon from etching. The electric field induced in the n region interferes with the chemical reaction involving the hydroxide ions that oxidize the silicon surface.

– High density plasma etching



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Comparison of anistropic etchants



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Bulk micromachined silicon pressure sensors

Consider a piezoresistive pressure sensor: – A membrane is formed using anisotropic wet etching, with

piezoresistive elements to detect the membrane deflection.



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Process flow



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Surface Micromaching Basics

Surface micromachining processes take place on the surface of the wafer, where films used for structural elements are deposited using techniques such as LPCVD.Advantages of surface micromachining compared to bulk micromachining:– Compact size: the surface area required for bulk

micormachined pressure sensors, due to the sloped sidewalls of recesses made using anisotropic etchants, was much larger than the actual membrane area.

– Versatile device available: with surface micromachining, structure can be made with several deposited layers, and parts can be “released” to allow them to move laterally as well as vertically. ⇒ MEMS actuators

– Polysilicon, the most common surface micromachining structural material, was well characterized from IC technology, could be deposited with well-controlled, repeatable film stress levels.

– Surface micromachining can more easily be integrated with CMOS processing, allowing signal processing circuitry and MEMS devices to exist on the same chip.



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Key processses in surface micromachining

Key processes:– 1. The deposition of low stress thin films that can be used

for structural elements. • an essential process step for surface micromachining.• PolySi by LPCVD is the most common structural material. • Stress level of PolySi film could be well controlled by

postdeposition annealing. Annealing leads to a slight contraction of the poly-film as a result of the crystallization of the amorphous regions. This contraction causes the stress to change from compressive to tensile. Normally annealing for PolySi stress reduction are performed at > 1000 oC.



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Structural Layer

• The more disordered nature of the polysilicon leads to a reduction in thermal conductivity, fracture strength, and Young’s modulus. The piezoresistance coefficients for polysilicon, although less than for single-crystal Si, are still larger enough to make useful sensors.



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Structural Layers

• In addition to PolySi, silicon nitride by LPCVD can also be used as a low-stress material. Contrary to sotichiometricSi3N4 deposited by LPCVD (DCS: NH3 = 1:5) with high tensile stress, silicon-rich nitride deposited by (DCS: NH3 = 5:1) has considerably lower tensile stress (< 50 MPa).Postannealing has little effect on the stress reduction.

• However, the reverse flowing ratio of DCS and NH3 is undesirable from an equipment standpoint of both sotichiometric and Si-rich nitride need to be run in the same tube. Since the low stress Si-nitride generates a large amount of particulates during the desposition which can cause premature mechanical pump failure.



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Sacrificial layers

– 2. The use of a sacrifical layer to allow the structural layer to de detached from the substrate, thus allowing motion of the structural layer.

• This sacrificial layers are used to release structures and allow motion.

• The key requirement for a sacrificial layer is the existence of an etchant that will remove the sacrificial layer without etching the structural layer. For example, when polysilicon is used as the structural layer, SiO2 is commonly used for sacrificial layer, especially PSG layers are desirable since PSG etches in HF solutions 8 to 10 times faster than undoped SiO2.



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Sacrificial layers

Stiction problems:– The structure is not actually released from the substrate,

but instead is stuck at one or more points to substrate in the region where the sacrificial layer was removed.



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Surface Micromachining Process flow

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