Process Design Kit (PDK) for 2.5D Through Silicon ... Modeling_PDK... · Silicon Interposer (TSI)...

Property of Institute of Microelectronics (IME)-Singapore © August 17, 2012

Process Design Kit (PDK) for 2.5D Through

Silicon Interposer (TSI) Design Enablement

&

2.5D TSI Cost Modeling2.5D TSI Characterization and Modeling Team

2IME’s TSI Consortium on August 17, 2012© IME-Singapore

Technology to Design Enablement: The Ecosystem

IPD Devices: Resistors, Capacitors and Inductors

2.5D TSI Technology Modeling and Characterization

2.5D TSI Design Enablement & Methodology

Deliverables: PDK and 2.5D TSI Design Enablement

2.5D TSI Cost Modeling

Deliverables: 2.5D TSI Cost Modeling

Outline


Technology to Design Enablement: The Ecosystem


Design Development

Modeling, Characterization, PDK and EDA flow

Development

Evolving Technology

Development

Constant interaction between

Technology, Characterization and Design groups

to develop trustworthy IME PDK & EDA flow

RC models using

simulations/analytical models

RC measurements &

characterization using

technology vehicle

Verified RC models confirming

characterization results inside IME PDK

Leveraging the design flow for

design optimization

Physical design EDA flow for

2.5D TSI design enablement

Technology to Design Enablement:

Ecosystem for evolving Technologies such as 2.5D TSI


2.5D Through Silicon Interposer (TSI) Technology

PDK Elements:

Technology/Viewer Files

(.tf/.drf)

Library Components/

Integrated Passive Devices

(IPDs)

Resistor

Capacitor (MIMCAP)

Spiral Inductor

TSI Component RC

Models:

Micro-bumps

M1-M4 BEOL

TSV

RDL Layer

C4 bump

DRC/LVS/PEX Rule

decks

Scope of Work: Integrate the PDK components

streamlining 2.5D TSI design process

Cu/Ni/SnAg

Cu/Ni/Au

TSV

Cu

Cu

M1 Cu

M2 Cu

2 µm

2 µm

2 µm

2 µm

2 µm

2 µm

2 µm

0.8-1 µm

Passivation Layer, i.e.,

intervia

Si

SiO2

100 µm

10 µm

1 µm

Al

V1

V2

V3

0.3-0.5 µm

SiN

~0.05 µm

1 µm

SiO2 1um

M2

2 µm

2 µm

2 µm2 µm

2 µm

SiN

~0.3 µm

RDL Cu

UBM Ti/Cu ~0.2/0.4um

5-6 µm

80 µm

110 µm

80 µm 0.2-0.4 µm

7-8 µm

IME’s 2.5D TSI Layer Map

ResistorMIMCAP


IPD Devices: Resistors, Capacitors and Inductors


Applications:

DC Biasing

Termination

Integrated Resistors

IME’s thin film resistor process

Deposition Temperature: 180oC

Resistivity

[10-8 Ohm.m]

CTE @

25 C

[10-6K−1]

Process Thickness

[Å]

Min

size

[µm]

Sheet

resistance

[/]

Ti 43 8.6 300mm 250 2 17.2

Layout of integrated resistor element

Scope of Work: Design and Parameterized Cell implementation

Characterization across layout variations

Cu/Ni/SnAg

Cu/Ni/Au

TSV

Cu

Cu

M1 Cu

M2 Cu

2 µm

2 µm

2 µm

2 µm

2 µm

2 µm

2 µm

0.8-1 µm


intervia

Si

SiO2

100 µm

10 µm

1 µm

Al

V1

V2

V3

0.3-0.5 µm

SiN

~0.05 µm

1 µm

SiO2 1um

M2

2 µm

2 µm

2 µm2 µm

2 µm

SiN

~0.3 µm

RDL Cu


5-6 µm

80 µm

110 µm

80 µm 0.2-0.4 µm

7-8 µm


Cu/Ni/SnAg

Cu/Ni/Au

TSV

Cu

Cu

M1 Cu

M2 Cu

2 µm

2 µm

2 µm

2 µm

2 µm

2 µm

2 µm

0.8-1 µm


intervia

Si

SiO2

100 µm

10 µm

1 µm

Al

V1

V2

V3

0.3-0.5 µm

SiN

~0.05 µm

1 µm

SiO2 1um

M2

2 µm

2 µm

2 µm2 µm

2 µm

SiN

~0.3 µm

RDL Cu


5-6 µm

80 µm

110 µm

80 µm 0.2-0.4 µm

7-8 µm

Integrated Capacitors

IME’s Metal-Insulator-Metal Capacitor (MIM)

Dielectric

Material

Relative

Permittivity

Process Dielectric

Thickness [Å]

Capacitance

[fF/um2]

Min and Max

dimension

[µm]

Si3N4 7.5 300mm 300-500 2.21-1.32 2 -12μm

Applications:

DC isolation

AC bypass

Power Distribution

Network

Filtering,

Impedance matching T=300-500Å

W=2-12m

Integrated MIMCAP

Cross section

Scope of work: Design and Parameterized Cell implementation

Characterization across layout variations

MIMCAP


Integrated Spiral Inductors

Meander Loop Spiral

Pattern

Inductance Medium Low High

Favorable due

to wide

inductance

range

Integrated Inductor

Prototype

Tape out in year 2012

Defined by technology:

W_min - W_max = 2-16µm; S_min - S_max = 2-16µm

Stack-up aligned with electrical design:

Metal thickness: 2µm; Dielectric (SiO2) thickness: 2µm

Area: Dimension 0.5 x 0.5mm2; 5.5 turns

W

[μm]

S

[μm]

L

[nH]Qmax

SRF

[GHz]

16 2 7.5 9.8 2.59

16 16 4.8 8.5 3.23

Scope of work: Design and Parameterized Cell implementation

RF Characterization across layout variations


2.5D TSI Technology Modeling and Characterization


Assumptions:

• Minimum Size wires considered Ground substrate for TSV & C4 bump capacitance assumed*Electrical Characterization & Modeling of Through Silicon Via (TSV) for 3D ICs; G. Katti et al.; TED; Jan. 2010

Resistance Capacitance

Micro bump 2.4mΩ 0.7fF

M1/M2/M3/M4 (interline) 4.2Ω/mm 34fF/mm

M1/M2/M3/M4

(line-to-ground)

4.2Ω/mm 34/13.8/7.6 /5.31

fF/mm

TSV (Cox) /TSV (CTSV) 21.4mΩ 120fF/80fF*

RDL (interline) 280mΩ/mm 15.9fF/mm

RDL (line-to-ground) 280mΩ/mm 34fF/mm

C4 Bump (line-to-ground) 2.4mΩ 116.84fF

RC Estimations using Analytical Models

Parasitic RC Elements:

Can it be

reduced?

Analytical RC estimations for 2.5D TSI Design to be implemented in PDK Rev0.0 To be

verified using TSI characterization suite


Impact of isolation thickness on C4 bump capacitance

0

20

40

60

80

100

120

140

1 2 3 4 5 6 7 8 9 10

Series2

C4 bump

Capacitance

Isolation Thickness [um]

Increased Isolation Thickness Reduced C4 bump capacitance

Initial isolation specification 1µm increased to 2µm to

reduce C4 Bump capacitance from ~120fF 60fF


Component RC

characterization

using C-V and I-V

measurements to

verify/update the RC

models

TSVs Bank: TSV C-V

characterization

Meander Forks: M1-M4, RDL resistance

and interline capacitance characterization

Stacked Metals: BEOL

Line Capacitance

TSV Daisy chains: TSV

Resistance characterization

M1-M2; M2-M3;M3-M4 Daisy chains:

V1, V2, V3 resistance characterization

Pass/Fail Test: Top-Bottom-Top chain

to perform short/open test

RF characterization: RF characterization

Of BEOLs, RDL and TSV

Resistance Measurements:

Four point resistance

measurements using I-V meter

Capacitance Measurements:

C-V and C-t measurements

using LCR meter

RF Measurements:

Network Analyzer

Scope of Work: To design a comprehensive test structure characterization

suite for model verification and PDK implementation

2.5D TSI Technology Characterization Vehicle


2.5D TSI Design Enablement & Methodology


2.5D TSI Design Enablement Methodologies

Thermo Mechanical simulations

• WarpageEstimation

• Thermal Fatigue Analysis

Scope of Work: Leveraging established EDA

tools for 2.5D TSI Design

Evaluate 3D IC EDA tools for 2.5D platform

Thermal simulations

• Thermal Map/ Hot spot Estimation

• Heat Sink Design

• Thermal System sign-off

2.5D TSI Physical Design Flow

• Auto PnR

• Timing Verification

• Power Ground Network Analysis

• Sign-off .gds

Package & PCB Design Flow

• Package Design

• SI and PI verification

• System sign-off

Electrical Domain Mechanical/Thermal Domain

Cadence

Virtuoso

SOC Encounter

SiP

Synopsys

ICC

Astro

Potential Tools Mentor Graphics

Calibre


Physical Design (EDA) Flow for 2.5D TSI Design

Synthesized Netlist

Floor planning & Placement

of µBumps and C4 bumps

(in sync with guest die &

package specs) [Co-Design]

Routing on 2.5D TSI

Parasitic

Extraction

Timing/Power

Verification

DRC/LVS

Verification

Sign off Flow(.gds)

Component

RC Models

in PEX

rule decks

DRC/LVS

rule decks

Design

Constraints

Specifications

Features:

Auto placement and routing of TSVs

TSV is considered as a device for PEX

Clock Tree Synthesis (CTS)

Platform for design exploration and optimization

Objective: To Develop EDA Flow enabling external partners to

design novel 2.5D TSI chips leveraging 2.5D TSI technology


IC, Package & PCB Co-design Flow

IC, Package & PCB co-design for 2.5D TSI

Allegro (SiP)

Virtuoso

Open

Access (OA)

Encounter

IBIS

Identifying package/PCB

(BGA/Direct Attach)

Auto Spider Route

Import TSI

Connectivity

SI & PI Verification

(Time & Frequency

Domain Analysis)

Constraints

Specifications

Package/PCB

Design sign-off 2.5D TSI*Package* PCB*

* Not a true representation


Schematic/Netlist Entry

Memory Die

FPGA Die

FPGA & Memory

Auto placement

Auto-routed Design with TSVs

Memory Die

FPGA Die

Eye Diagram Verification on TSIPackage to IC timing verification

FPGA & Memory integration on TSI – A Case Study


Deliverables: PDK & 2.5D TSI Design Enablement

PDK with Rev0.0 RC models, IPDs & DRC/LVS/PEX implementation

Design and tape out 2.5D TSI technology characterization vehicle

Verification of electrical models with test vehicle characterization Models

implementation within PDK Rev 1.0

Corner analysis employing min-typ-max RC values

Develop a design flow to enable external partners to leverage 2.5D TSI technology

IC, Package and PCB co-design

Auto placement and routing of TSVs

Routability/congestion analysis

SI/PI Analysis

Platform to optimize 2.5D TSI Designs



“Cost” is the most important factor to mainstream 2.5D TSI

technology

Wafer Cost ($)

& Die Cost ($)

TSV ArchitectureDie Area

# Metal Layers

Equipments

MaterialsProcess flow

Process Yield

Labor cost Line Infrastructure

RDL, UBM &

C4 Bump technologies

Manufacturing cost needs to be estimated



Via Etch

Via Isolation

Via Fill

TSV Formation

BEOL Processing

TSV RevealBump &

RDL Formation

2.5D TSI Cost = Cost of { TSV Formation & Reveal + BEOL

processing + UBM, RDL & C4 bump formation}

Single Damascene

Or

Dual Damascene Temporary

Bonding

Thinning UBM

RDL

C4 bump

processing

TSV Formation & TSV Reveal TSV cost model

BEOL processing BEOL cost model

RDL processing RDL cost model

UBM, C4 Bump processing Bump cost model

Base Model: Yole

To be calibrated

& enhanced

within consortium

Base Model: Yole

To be calibrated

& enhanced

within consortium Base Model:

To be calibrated

Within consortium

Base Model:

To be calibrated

within consortium


Cost of TSV formation & reveal

varying with Manufacturing Volume and Yield

# Wafers/year

High Volume

Production (HVP)

200.00Low Volume

Production (LVP)

Volume and Yield are critical to reduce cost

Assumptions:

Location: Singapore

Processing line: 300mm

TSV Architecture: 12x100µm

Source: Yole


Cost of TSV formation & reveal

25%

3%

44%

4%

24%Wafer Cost ($)

Wafer Cost varying with TSV Architectures

Source: Yole

Assumptions:

Location: Singapore

Processing Line: 300mm

Volume: 500k wafers/year (HVM)

10k wafers/year (LVM)

Yield: 85%

% Cost distribution of different TSV processes in HVM

Observations:

Huge variation (~5.25x) with volume

between LVM and HVM

TSV filling is the most expensive process

TSV Reveal cost is independent of TSV

Height

12x100µm TSV formation and reveal wafer cost demonstrates huge

variation with volume: $1075 (LVM) $205 (HVM)

200

LVM CostHVM Cost


% Cost distribution of 2.5D TSI

44%

30%

7%

19%

2.5D TSI FPGA & Memory Integration Cost Estimation for HVM

Cost Estimations:

2.5D TSI wafer (4 BEOL layers and 1 RDL)

manufacturing cost = $470 (HVM) & $2470 (LVM)

Estimated 2.5D TSI FPGA & Memory Interposer

(25x30mm) die cost = $6 (HVM) & $35 (LVM)

Estimated cost per wafer (Assumptions):

BEOL processing = $35 per metal layer (HVM)

RDL processing = $35 (HVM)

UBM and C4 bump processing = $90 (HVM)

LVM Cost = 5.25x HVM Cost

Scope of Work: 2.5D TSI Cost Model Calibration

2.5D TSI Die Area [mm2]

Variation of Die cost for HVM

Die Area = 750mm2


Deliverables: 2.5D TSI Cost Modeling

Si-substrateSi-substrate

1st FS

RDL

2nd FS RDL

3rd FS RDL

T=5-7um

T=5-7umT = 3um

BS UBM

FS UBM

TS

V ø10

µm

Liner oxide

Cu B/S

H

100µm

1st polyimide

BS RDL

Polyimide

MIM

capacitor

28-Aug-12Si substrate

10um

(Cu)~100um

T[1]=1-2um

T[2]= 1-2umT[3]=1-2 um

T[4]=1 -2um

T[5]=1-2 um

T[6]= 1-2um

T[7]= 1-2um

T[8]= 1-2um

16um>W>2um

Cu/Ni/AuAl

BS RDLPolyimide

MIM capacitors Resistors

TSV

ø10um

BS UBM

TSI with front side and backside RDL TSI with BEOL & back side RDL

TSV formation and TSV reveal cost to be calibrated/enhanced

Invariant cost variation with wafer thickness to be confirmed (to be

enhanced if required)

Support PECVD

Work with consortium members to incorporate BEOL and RDL, UBM and C4

Bump cost

Is RDL significantly cheaper than BEOL?

Cost comparison of two 2.5D TSI systems


Thank you

Q & A

Process Design Kit (PDK) for 2.5D Through Silicon ... Modeling_PDK... · Silicon Interposer (TSI)...

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