Proc. of the 2003 Design Automation Conference , DAC '03, June 2003, pp.318-323.

A transformation based algorithm for reversible logic synthesis

D.M. Miller Dept. of Computer Science, Univ. of Victoria, CanadaD. Maslov and G.W. DueckFaculty of Computer Science, Univ. of New Brunswick Canada

Motivation To present a transformation based

algorithm for the synthesis of reversible circuits

Power not to be dissipated in arbitrary circuits Built from reversible gates

Outline

Introduction Background The algorithm Template matching Experimental results Conclusion

Introduction

k*k Reversible gate

i1

i2

i3

in

o1

o2

o3

on

.

.

.

.

.

.

.

.

Reversible logic gate

Introduction 1 x 1 reversible gate is an inverter Classical XOR gate is irreversible Reversible XOR gate (FG)

2 x 2 Feynman gate: (also called “controlled NOT” )

P = A Q = A ♁ B

if B = 0 then P= Q = A (copying gate)

A B P Q

0 00 11 01 1

0 00 11 11 0

Introduction

3 x 3 Fredkin gate (FG) P = A Q = C ♁AB ♁AC R = B ♁AB ♁ AC

A B C P Q R

0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

0 0 00 1 00 0 10 1 11 0 01 0 11 1 01 1 1

Introduction

3 x 3 Toffoli gate (TG) P = A Q = B R =AB ♁ C

A B C P Q R

0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

0 0 00 0 10 1 00 1 11 0 01 0 11 1 11 1 0

Introduction 3 x 3 New gate P = A Q = AB ♁ C R =A’C’ ♁ B’

Exist 40320 ( 8! ) 3x3 reversible logic

gates

A B C P Q R

0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

0 0 00 1 10 0 10 1 01 0 11 1 11 1 01 0 0

A fulladder using reversible gates TG

A

B

0

FG

AA

B

TG

A♁B

Cin

AB

FG

A♁BA♁B

Cin

(A♁B)Cin♁AB = CoutA♁B♁Cin = Sum

A fulladder using reversible gates NG

A

B

0

FG

AB

A

AB

NG

(A♁B)Cin

Cin

A♁B

Cin

A♁B♁Cin = Sum

0

(A♁B)Cin♁AB = Cout

A fulladder using reversible gates NG

A

B

0

FG

A♁B

A

AB

TG

Cin

A♁B

Cin

A♁B♁Cin = Sum

AB (A♁B)Cin♁AB = Cout

Reversible logic gates

X1 X’1

(a)

X2 X’2

X1 X1

(b) X3 X’3

X2 X2

(c)

X1 X1

a. TOF1(x1), b. TOF2(x1,x2), c. TOF3(x1,x2, x3) Toffoli Gates.

Example of applying the basic

algorithm (i) (ii) (iii) (iv) (v)

cba C0b0a0 C1b1a1 C2b2a2 C3b3a3 C4b4a4

000 001 000 000 000 000

001 000 001 001 001 001

010 011 010 010 010 010

011 010 011 011 011 011

100 101 100 100 100 100

101 111 110 111 101 101

110 100 101 101 111 110

111 110 111 110 110 111

Circuit for the previous example

a

b

c c0

a0

b0

Example of applying the bidirectional

algorithm (i) (ii) (iii) (iv)

cba C0b0a0 C1b1a1 C2b2a2 C3b3a3

000 111 000 000 000

001 000 111 001 001

010 001 010 010 010

011 010 001 111 011

100 011 100 100 100

101 100 011 101 101

110 101 110 110 110

111 110 101 011 111

Example of applying the bidirectional

algorithm

Input (i) Specification

cba c0b0a0

000 111

001 000

010 001

011 010

100 011

101 100

110 101

111 110

Input Inverting a

cba cxbxax

000 001

001 000

010 011

011 010

100 101

101 100

110 111

111 110

Inverting a (ii)

cxbxax c1b1a1

000 000

001 111

010 010

011 001

100 100

101 011

110 110

111 101

Circuit for the function of previous example

c0

a0

b0

a

b

c

A

,

B

a

b

c

a0

b0

c0

Templates 2 inputs involving SWAP

1.1

1.2

Templates 2 input gate reduction no SWAP

2.1

2.2

TOF2(b, a), TOF1(b), TOF1(a)

replaced by

TOF1(b);

TOF2(b,a)

Templates Using transformation rule 3 [5]

3.1

3.2

3.3

reduce the no. of gates

Symmetric templates

4.1

4.2

4.3

reduce the no. of gates

Symmetric templates (Cont.)

4.4

4.5

4.6

reduce the no. of gates

5.1

Templates Controlled SWAP ( Fredkin gate )

A B C P Q R

0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

0 0 00 0 10 1 00 1 11 0 01 1 01 0 11 1 1

Interchange property

Two gates in a circuit TOFk( x1, x2, … , xk – 1, xk ) and TOFl( y1, y2, … , yl – 1, yl ) adjacent can be interchanged iff xk ≠{ y1, y2, … , y l – 1 } and yl ≠ { x1, x2, … , x k – 1 }.

Garbage outputs required

Minimum no. of garbage outputs required is ┌ log2 q ┐ q is maximum output pattern multiplicity of

the irreversible function. Maximum output pattern multiplicity of

a multiple-output Boolean function is the maximum no. of input assignments yielding the same output pattern.

Full adder

a

b

c

d

(constant 0)A

Bgarbagepropagate

sum

carryC

d c b a d’ c’ b’ a’

0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

0 0 0 00 1 1 10 1 1 01 0 0 10 1 1 01 0 1 11 0 1 01 1 0 11 0 0 01 1 1 11 1 1 00 0 0 11 1 0 00 0 1 10 0 1 00 1 0 1

1 garbage output

maximum output pattern multiplicity 2

Template 3.2

Circuit for rd53

a

b

c

d

e

f(=0)

g(=0)

a’

b’

c’

d’

h0

h1

h2

maximum output pattern multiplicity 10, 4 garbage

to get no. of 1's in the input pattern

00000yields 000

00100yields 001

11111yields

101

5 inputs, 3 outputs

Experimental results Size (a) (b) (b) (d) (e) (f)

13 1113 72 87

12 2468 477 550 3

11 4311 1759 1901 86 5

10 6083 4179 4267 493 110

9 7044 6912 6828 2312 792

8 6754 8389 8221 6944 4726 12

7 5379 7766 7670 11206 11199 6817

6 3549 5615 5610 10169 12076 17531

5 1922 3183 3204 5945 7518 11194

4 839 1391 1402 2375 2981 3752

3 286 453 455 650 767 844

2 72 104 104 121 130 134

1 12 15 15 15 15 15

0 1 1 1 1 1 1

Avg. gates 8.67 7.65 7.67 6.53 6.18 5.63

Time (sec.) 0.94 2.19 3.87 3.92 20.2

Conclusion

A simple algorithm for the synthesis of a reversible circuit composed of generalized Toffoli gates has been presented.

studying the extension of templates to n>3