Probleme PAC2 in VHDL

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    Problema 1

    entity circ is

    port (a,b,CLK,EN: in std_logic;sel: in std_logic_vector (1 downto 0);Q: out std_logic);

    end circ;architecture comp of circ is

    beginprocess (CLK,EN)

    beginif EN=0 thenQ

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    end process;process

    begin EN

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    TESTBENCH

    entity DFFtest is;dffnsrarchitecture testbench of DFFtest is

    componentport (D,CLK,R,S: in std_logic;

    Q: out std_logic);end component;

    signal: D,CLK,R,S,Q: std_logic;beginUUT: DFF port map (D,CLK,R,S,Q);process

    begin CLK

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    end process;Q

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    port (CK: in std_logic;

    SR: in std_logic_vector(10);

    Q: out std_logic);end component;

    signal CK,Q: std_logic;

    signal SR: std_logic_vector(1

    0);beginUUT: SR port map (CK,SR,Q);

    processbegin

    CK

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    else stareviitif INIT=0 thenstareviit

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    Problema 5

    Sincron cu CK asincron prioritar fata de ceas.

    entity circuit isgeneric (n: natural=4)

    port (RS: in std_logic_vector (10);CK: std_logic;

    D: in std_logic_vector ((n-1)0);Q: out std_logic_vector ((n-1)0);

    end circuit;

    architecture beh of circuit isbegin

    process (RS,CK)begin if RS=00

    QQ

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    processbegin

    D

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    end test;Problema 7

    library IEEE;use IEEE.std_logic_1164.all;entity circuit is

    port (CLK,EN1,EN2,R: in std_logic;Q: out std_logic);end circuit;architecture fcircuit of circuit is

    begin

    process (R,CLK)variable temp1,temp2: std_logic;

    beginif R=0 thenQ

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    R