Presented by:Presented by:

Reshef SchreiberReshef SchreiberItay LeibovitzItay Leibovitz

Instructed by:Instructed by:

Eran SegevEran Segev

Board ObjectivesBoard Objectives The second part of the Serial Communication Board The second part of the Serial Communication Board

(SCB) project adds USB Host capability to the SCB (SCB) project adds USB Host capability to the SCB mezzanine board designed in part I and by that mezzanine board designed in part I and by that expanding its I/O capabilities expanding its I/O capabilities

The SCB interfaces mechanically and electrically to The SCB interfaces mechanically and electrically to the External Memory Interface (EMIF) connectors of the External Memory Interface (EMIF) connectors of the evaluation boardthe evaluation board

To evaluate the use of the Philips ISP1362 USB To evaluate the use of the Philips ISP1362 USB controllercontroller

DSP Evaluation BoardDSP Evaluation Board

SCB InterfaceSCB Interface

SCB USBExternal Memory Interface (EMIF)

Power

3.3 V

Interrupts

Power

5 V

EMIFEMIF The memory signals required for the daughter-card The memory signals required for the daughter-card

interface connectors are:interface connectors are: Address pinsAddress pins

7 address signals of the DSP are provided to give the address 7 address signals of the DSP are provided to give the address space to the daughter-card.space to the daughter-card.

Data pinsData pins 16 data signals are provided to facilitate access to memory 16 data signals are provided to facilitate access to memory

and parallel peripherals.and parallel peripherals. Chip SelectChip Select

CE3 is provided to access individual memory and I/O space.CE3 is provided to access individual memory and I/O space. Byte EnableByte Enable

BE0, BE1 are used in order to access the 16 bit words out of BE0, BE1 are used in order to access the 16 bit words out of the 32bit wide words of the DSP.the 32bit wide words of the DSP.

SCB Block DiagramSCB Block Diagram

FPGA

ISP1362

D(0:15)

INT1

CS

WR

RD

BE0,BE1

ADR(6:0) CS

ADR(1:0)

SCB Main BlocksSCB Main Blocks Address Decoder: used to bridge between the DSP Address Decoder: used to bridge between the DSP

EMIF and the USB host controller. The FPGA EMIF and the USB host controller. The FPGA decodes the control signals of the EMIF bus to a decodes the control signals of the EMIF bus to a simple control line (CS) needed by the USB controller.simple control line (CS) needed by the USB controller.

USB Host Controller: The USB host functions are USB Host Controller: The USB host functions are

controlled using various control registers and status controlled using various control registers and status ports. These I/O ports (read and write) are accessed by ports. These I/O ports (read and write) are accessed by the DSP using a special “two phase” access. the DSP using a special “two phase” access.

FPGA Main FunctionFPGA Main Function

ADDRESS DECODER

CS

BE0,BE1

ADR(6:0)CS

FPGA Signal DescriptionFPGA Signal Description

Signal NameSignal NameDirectionDirectionDescriptionDescription

ADDRESS(8:2)ADDRESS(8:2)IIAddress bus. Defines the unit to be accessedAddress bus. Defines the unit to be accessed

CE3#CE3#IIMemory space enables. When low indicatesMemory space enables. When low indicatesaccess to the EMIF space of the SCB.access to the EMIF space of the SCB.

BE(1:0)#BE(1:0)#IIByte enables. When low indicates that the data isByte enables. When low indicates that the data ispresent on the low byte.present on the low byte.

AOE#AOE#IIAsynchronous output enables.Asynchronous output enables.

CSCSOOchip select output (active LOW); enables the HCchip select output (active LOW); enables the HCdriver to access the buffer memory and registers driver to access the buffer memory and registers of the HC.of the HC.

CLKCLKIIAltera clock input.Altera clock input.

Address Decoding (1)Address Decoding (1) The ISP1362 is made of a Host Controller (HC) and a Device Controller The ISP1362 is made of a Host Controller (HC) and a Device Controller

(DC)(DC) The ISP1362 Chip Select (CS) is shared between the HC and the DCThe ISP1362 Chip Select (CS) is shared between the HC and the DC Each Controller has two I/O ports :Each Controller has two I/O ports :

Command portCommand port Data portData port

Access to each of these ports is made by a combination of the following Access to each of these ports is made by a combination of the following control signals:control signals: A0,A1,CSA0,A1,CS

CSCSA1A1A0A0ACCESSACCESSWidth(bits)Width(bits)descriptiondescription

000000R/WR/W1616HC data portHC data port

000011WW1616HC command portHC command port

001100R/WR/W1616DC data portDC data port

001111WW1616DC command portDC command port

Address Decoding (2)Address Decoding (2) The right combination of control signals that will force the CS to Low is:The right combination of control signals that will force the CS to Low is:

AddressAddressBE1BE1BE0BE0CE3CE3

00000XX00000XX000000

The absolute addresses of the relevant ports (in the DSP memory space) are defined The absolute addresses of the relevant ports (in the DSP memory space) are defined using the CE programming in the DSP initialization using the CE programming in the DSP initialization

AddressAddressR/WR/WDevice SelectedDevice Selected

0xA00000000xA0000000R/WR/WHC data portHC data port

0xA00000020xA0000002WWHC command portHC command port

0xA00000040xA0000004R/WR/WDC data portDC data port

0xA00000060xA0000006WWDC command portDC command port

ISP1362ISP1362

ISP1362 DescriptionISP1362 Description The ISP1362 is a single-chip Universal Serial Bus (USB) On-The-Go The ISP1362 is a single-chip Universal Serial Bus (USB) On-The-Go

(OTG) controller integrated with the advanced Philips Slave Host (OTG) controller integrated with the advanced Philips Slave Host Controller (PSHC) and the Philips ISP1181B Device Controller (DC).Controller (PSHC) and the Philips ISP1181B Device Controller (DC).

Only the Host Controller is implemented in the SCB.Only the Host Controller is implemented in the SCB.

The ISP1362 has two USB ports: port 1 and port 2. Port 1 can be The ISP1362 has two USB ports: port 1 and port 2. Port 1 can be hardware configured to function as a downstream port, an upstream hardware configured to function as a downstream port, an upstream port or an OTG port, Whereas port 2 can only be used as a downstream port or an OTG port, Whereas port 2 can only be used as a downstream port. The SCB uses only the HC port which is port 2.port. The SCB uses only the HC port which is port 2.

attributesattributes:: Supports integrated physical 4096 bytes of multi-configuration memorySupports integrated physical 4096 bytes of multi-configuration memory Supports all four types of USB transfers: control, bulk, interrupt and Supports all four types of USB transfers: control, bulk, interrupt and

isochronousisochronous Directly addressable memory architecture; memory can be updated on-the-Directly addressable memory architecture; memory can be updated on-the-

flyfly

ISP1362 Signal DescriptionISP1362 Signal DescriptionSignal NameSignal NameDirectionDirectionDescriptionDescription

A0A0IIWhen pulled low, choose data phase. When pulled high When pulled low, choose data phase. When pulled high choose command phase.choose command phase.

A1A1IIWhen pulled low, choose HC port. When pulled highWhen pulled low, choose HC port. When pulled highchoose DC port.choose DC port.

DATA(15:0)DATA(15:0)I/OI/OData bus. Connects to the low word of the evaluationData bus. Connects to the low word of the evaluationboard.board.

CSCSIIchip select input (active LOW); enables the HC driver tochip select input (active LOW); enables the HC driver toaccess the buffer memory and registers of the HC.access the buffer memory and registers of the HC.

INT1INT1OOInterrupt request from the HC; provides a mechanism for Interrupt request from the HC; provides a mechanism for he HC to interrupt the microprocessor.he HC to interrupt the microprocessor.

X1X1IICrystal input. This pin is connected to an external clock Crystal input. This pin is connected to an external clock oscillator, leave the X2 pin open.oscillator, leave the X2 pin open.

X2X2OOCrystal output. Left open, because X1 is connected to an Crystal output. Left open, because X1 is connected to an external clock oscillator.external clock oscillator.

H_DP2H_DP2I/OI/ODownstream D+ signal; host only, port 2. Connects to D+ Downstream D+ signal; host only, port 2. Connects to D+ pin in the USB connector. Has internal pull up resistor.pin in the USB connector. Has internal pull up resistor.

H_DM2H_DM2I/OI/ODownstream D- signal; host only, port 2. Connects to D+Downstream D- signal; host only, port 2. Connects to D+pin in the USB connector. Has internal pull up resistor.pin in the USB connector. Has internal pull up resistor.

PIO interface of the ISP1362 PIO interface of the ISP1362

PIO Register AccessPIO Register Access The ISP1362 has 2 types of registers: The ISP1362 has 2 types of registers:

16 bit registers 16 bit registers 32 bit registers.32 bit registers.

The 16 bit registers access is made in 2 stages: The 16 bit registers access is made in 2 stages: Command stage. Command stage. Data stage.Data stage.

The first stage (command stage) chooses the register address. It is done by The first stage (command stage) chooses the register address. It is done by simply writing the register’s address to the command port of the HC. simply writing the register’s address to the command port of the HC.

Before continuing to the next stage, CS must be kept inactive (high) for at Before continuing to the next stage, CS must be kept inactive (high) for at least 300 ns.least 300 ns.

The second (data) stage enables reading/writing to the port defined in the The second (data) stage enables reading/writing to the port defined in the in the command stage.in the command stage.

The 32 bit registers access is made in 3 stagesThe 32 bit registers access is made in 3 stages: : one command stage and one command stage and two data stages.two data stages.

Reading 16/32 bits registerReading 16/32 bits register

Writing 16/32 bits registerWriting 16/32 bits register

The software developed includes the driver for the The software developed includes the driver for the SCB which provides the card with the basic ability SCB which provides the card with the basic ability to function as a general USB host. Specific to function as a general USB host. Specific implementations will make use of these functions to implementations will make use of these functions to

build a dedicated driver.build a dedicated driver.

The driver runs on the DSP and serves as the HCD The driver runs on the DSP and serves as the HCD (Host Controller Driver) of the ISP1362.(Host Controller Driver) of the ISP1362.

Software ObjectivesSoftware Objectives

Software ImplementationSoftware Implementation

The software consists of 3 main layers:The software consists of 3 main layers:

Main program takes care of initialization of the Main program takes care of initialization of the SCB and the ISP1362.SCB and the ISP1362.

Functions for reading and writing to the ISP1362’s Functions for reading and writing to the ISP1362’s registers and buffer. These are later used for registers and buffer. These are later used for configuring the ISP1362.configuring the ISP1362.

Functions for arranging USB transfers from the Functions for arranging USB transfers from the attached device.attached device.

The Main ProgramThe Main Program Writing a specific value into a scratch register and reading it.

A Software Reset is issued by the HCD.

The buffer memory of the HC is shared by the isochronous, interrupt and control functions.

Several characterizations of the HC are set by evaluating the ISP1362’s registers.

The HC is generating SOF packets and is ready to operate.

Checking Existence of Host Controller

Initiate buffer sizes

OperationalMode

Software Reset

Hardware Configuration

Enumeration

Device Connected?

InterruptsInterrupts

The ISP1362 HC generates interrupts on The ISP1362 HC generates interrupts on several events:several events:

Unrecoverable Error Unrecoverable Error Frame Number Overflow Frame Number Overflow Device Connection Device Connection

Philips Transfer Descriptor (PTD)Philips Transfer Descriptor (PTD)

A PTD is a struct that consists of a PTD header and a payload A PTD is a struct that consists of a PTD header and a payload data. data.

The PTD provides a communication channel between the The PTD provides a communication channel between the HCD and the ISP1362 USB HC.HCD and the ISP1362 USB HC.

A PTD header contains information required for data transfer, A PTD header contains information required for data transfer, such as data packet size, transfer status and transfer token such as data packet size, transfer status and transfer token types. types.

Certain fields in the PTD header are used by the HC to inform Certain fields in the PTD header are used by the HC to inform the HCD about the status of the transfer.the HCD about the status of the transfer.

PTD HeaderPTD HeaderSettings:Settings:

SpeedSpeed Low Speed/High SpeedLow Speed/High Speed

Maximum Packet SizeMaximum Packet Size Endpoint NumberEndpoint Number Total BytesTotal Bytes Token TypeToken Type

IN/OUT/SETUPIN/OUT/SETUP AddressAddress

PTD HeaderPTD Header

Status:Status:

Actual Bytes transferredActual Bytes transferred Active – transfer Active – transfer

completedcompleted Completion CodeCompletion Code

Success/FailureSuccess/Failure

EnumerationEnumeration

When a USB device is attached to or removed When a USB device is attached to or removed from the ISP1362, the host uses a process from the ISP1362, the host uses a process known as bus enumeration to identify and known as bus enumeration to identify and manage the device state changes necessary.manage the device state changes necessary.

Several functions were written in order to take Several functions were written in order to take care of the enumeration process of the device.care of the enumeration process of the device.

AAuxiliaryuxiliary Functions Functions make_control_ptdmake_control_ptd

Constructs the PTD given the relevant parameters passed to it Constructs the PTD given the relevant parameters passed to it and a pointer.and a pointer.

Send_ControlSend_Control this function sends out the packet to the device.this function sends out the packet to the device. polls Active Bit to determine when the transaction is completed. polls Active Bit to determine when the transaction is completed. stores the reply in a dedicated buffer.stores the reply in a dedicated buffer.

Set_AddressSet_Address assigns a unique address by sending a Set Address request in a assigns a unique address by sending a Set Address request in a

containing the new address.containing the new address.

ControlControl The function Get_control is used for getting the Descriptors from the The function Get_control is used for getting the Descriptors from the

device upon connection.device upon connection. Device DescriptorDevice Descriptor

A device descriptor describes general information about a USB A device descriptor describes general information about a USB device.device.

Configuration DescriptorConfiguration Descriptor A configuration descriptor describes information about a specific A configuration descriptor describes information about a specific

device configuration. all related interface and endpoint descriptors device configuration. all related interface and endpoint descriptors are returned.are returned.

Set ConfigurationSet Configuration The device is set to its default configuration.The device is set to its default configuration.

The device is now enumerated and ready for The device is now enumerated and ready for data transactions.data transactions.

For testing, The HCD contains functions for For testing, The HCD contains functions for generating a Bulk compatible PTD, and for generating a Bulk compatible PTD, and for sending and receiving bulk data transactions.sending and receiving bulk data transactions.