Cache Coherence Protocols MSI,MESI,MEOSI

Presented By:-Prerna Puri M.Tech(C.S.E.)Cache Coherence ProtocolsMSI & MESIContentsCache and cache coherenceShared cache design advantagesMSI WB ProtocolState Transition in the MSI ProtocolCache coherence problemMSI exampleMESI WB ProtocolFour states-MESIMESI state transition diagram

Cache and Cache coherenceCache play an important role toReduce average latencyMain memory access costs from 100 to 1000 cyclesCaches can reduce latency to few cyclesReduce average bandwidth and demand to access main memoryReduce access to shared bus or interconnectBut private caches create a problemCopies of a variable can be present in multiple caches A write by one processor may NOT become visible to others.Other processors keep accessing old value in their caches

Shared Cache Design: AdvantagesCache placement identical to single cacheOnly one copy of any cached blockNo coherence problem

Communication latency is reduced when sharing cacheAttractive to Chip Multiprocessors (CMP), latency is few cyclesBetter utilization of total storageOnly one copy of code/data used

4MSI Write-Back Invalidate ProtocolThree States:Modified: only this cache has a modified valid copy of the blockShared: block is clean and may be cached in more than one cache, memory is up-to-dateInvalid: block is invalidFour bus transactions: Bus Read: BusRd on a read missBus Read Exclusive: BusRdXObtain exclusive copy of cache block

Bus Write-Back: BusWB on replacementFlush on BusRd or BusRdXCache puts data block on the bus in lieu of memory Cache-to-cache transfer and memory is updated

Cont..State Transitions in the MSI ProtocolProcessor ReadCache miss causes a Bus ReadCache hit (S or M) no bus activityProcessor WriteGenerates a BusRdX when not ModifiedBusRdX causes other caches to invalidate No bus activity when Modified blockObserving a Bus ReadIf Modified, flush block on busPicked by memory and requesting cacheBlock is now shared Observing a Bus Read ExclusiveInvalidate blockFlush data on bus if block is modified

MISPrRd/PrWr/PrRd/BusRdPrWr/BusRdXPrWr/BusRdXPrRd/BusRd/BusRd/FlushBusRdX/FlushReplace/BusWBBusRdX/Replace/The Cache Coherence Problem

Processors see different values for u after event 3With write back caches value written back to memory depends on which cache flushes or writes back value when processes accessing main memory may see very old valueUnacceptable to programs MSI ExampleP1CacheP2P3BusCacheCacheMEMORYBusRdProcessor ActionState in P1State in P2State in P3Bus TransactionData SupplierS------BusRdMemoryP1 reads XX=10X=10S9 P1CacheP2P3BusCacheCacheMEMORYX=10SProcessor ActionState in P1State in P2State in P3Bus TransactionData SupplierS------BusRdMemoryP1 reads XP3 reads XBusRdX=10SS---SBusRdMemoryX=1010 P1CacheP2P3BusCacheCacheMEMORYX=10SProcessor ActionState in P1State in P2State in P3Bus TransactionData SupplierS------BusRdMemoryP1 reads XP3 reads XX=10SS---SBusRdMemoryP3 writes XBusRdX---IMI---MBusRdXX=10X=-2511 P1CacheP2P3BusCacheCacheMEMORYProcessor ActionState in P1State in P2State in P3Bus TransactionData SupplierS------BusRdMemoryP1 reads XP3 reads XX=-25MS---SBusRdMemoryP3 writes X---II---MBusRdXP1 reads XBusRdX=-25SSS---SBusRdP3 CacheX=10X=-2512MESI Write-Back Invalidation ProtocolTo reduce two types of unnecessary bus transactionsBusRdX that snoops and converts the block from S to M when only you are the sole owner of the blockBusRd that gets the line in S state when there is no sharers (that lead to the overhead above)

Introduce the Exclusive stateOne can write to the copy without generating BusRdX

Illinois Protocol: Proposed by Pamarcos and Patel in 1984Employed in Intel, PowerPC, MIPS

Four States: MESI M: ModifiedOnly this cache has copy and is modifiedMain memory copy is staleE: Exclusive or exclusive-cleanOnly this cache has copy which is not modifiedMain memory is up-to-dateS: SharedMore than one cache may have copies, which are not modifiedMain memory is up-to-dateI: Invalid

MESI State Transition DiagramProcessor ReadCauses a BusRd on a read missBusRd(S) => shared line assertedValid copy in another cacheGoto state SBusRd(~S) => shared line not assertedNo cache has this blockGoto state ENo bus transaction on a read hit

PrWr/PrRd/EMISPrRdPrRd/BusRd(S)BusRdX/FlushBusRd/PrWr/BusUpgrPrWr/BusRdXBusRd/FlushBusRdX orBusUpgr/BusRdX/PrRd/ BusRd/PrRd/BusRd(~S)PrWr/Replace/BusWBReplace/Replace/Processor WritePromotes block to state MCauses BusRdX / BusUpgr for states I / STo invalidate other copiesNo bus transaction for states E and MCont.. Thank you!!