Presented By David Q. KellyPrincipal Investigator: Sanjay K. Banerjee

Microelectronics Research CenterUniversity of Texas at Austin

Austin, Texas, U.S.A.

Germanium-Carbon Layers on Sifor Enhanced-Channel-Mobility MOSFETs

Advantages of Germanium

• Bulk Ge has higher electron (2.5×) and hole (4×) mobility than Si– Buried channel PMOS has shown very high mobility

enhancements

• Compatible with high-κ gate dielectrics

• Lower temperature processing

Ge Sin (cm2/V·s) 3900 1500

p (cm2/V·s) 1900 450

Eg (eV) 0.66 1.12

Background:Disadvantages of Germanium

Native GeO2 cannot be used as gate dielectric– Thermally desorbs above 420°C– Soluble in water

• Requires surface passivation for good interface with high-κ dielectrics

• Smaller energy bandgap– Increased subthreshold leakage current

• Poor NMOSFET Performance– Would require a separate approach

Graded Si1-xGex Buffer Layers (MIT)

• Thick, relaxed, graded SiGe virtual substrates with compressively-strained Ge top layer

• Calls for a CMP step to remove surface roughness on the virtual substrate prior to strained Ge layer growth

Currie, et al. APL 1998

Other Approaches to Ge on Si• Cyclical Thermal Annealing

– L. Kimerling (MIT)– Two-step growth following by cyclical

annealing at 900°C and 780°C

• Surfactant-mediated epitaxy– K. R. Hofmann (Germany)– Surfactant doping (Sb atoms)– Has only been demonstrated using

MBE

• Thermal annealing in hydrogen– Saraswat (Stanford)– Pure Ge layer grown on Si is annealed

in hydrogen to fully relax layer– Low-defect density Ge layer is re-

grown over relaxed layer

• Condensation of epitaxial SiGe– S. Takagi (Japan) / IBM– Could be promising for Ge-on-insulator– Requires SGOI substrate

Cyclical Annealing

Hydrogen Annealing

Ge Condensation

CVD Ge1-xCx Grown Directly on Si

• Group at Arizona State University was the first to demonstrate Ge1-xCx films grown directly on Si (100) by UHVCVD– Appl. Phys. Lett. 68 (17) pp. 2407-2409, 1996.– Chem. Mat. 8 (10) pp. 2491-2498, 1996.

• Key to achieving efficient C incorporation is to use precursors with “pre-formed” Ge–C bonds– Methylgermane CH3GeH3

– Digermylmethane CH2(GeH3)2

– Trigermylmethane CH(GeH3)3

• MOS devices never reported until now

Ge1-xCx Layer Growth by UHVCVD

• 4” n-type wafers cleaned using HF-last process

• Base pressure prior to deposition was 7.0×10-10 Torr

• Growth Temperature 450°C

• Mixture of GeH4 and CH3GeH3 precursors introduced at deposition pressure of 5 mTorr

• Final layer thickness ~ 30 nm

XTEM Results (30 nm Ge1-xCx on Si)

Si Substrate

Ge 1-

xC x

Si c

ap

glue (sample preparation)

Si Substrate

Ge 1-

xC x

Si c

ap

glue (sample preparation)

• Larger area scan shows that Ge1-xCx layer is epitaxial and has no visible threading dislocations– Strain relaxation is thought to occur through misfit

dislocations confined at interface

Ge1-yCy Surface Roughness Dependence on Growth Temperature and C Incorporation

• Film quality depends on both the growth temperature and the amount of methylgermane flow– AFM RMS surface roughness improves with decreasing

growth temperature– Higher carbon incorporation also leads to smoother film

11.9415.5831.03

0.641.01

0.10

1.00

10.00

100.00

0 0.02 0.04 0.06 0.08

CH3GeH3:GeH4 Ratio

AF

M R

MS

Ro

ug

hn

es

s (

nm

)

Temp. = 550C

Temp = 480C

3.862

1.724

0.911

0

1

2

3

4

5

400 450 500Growth Temperature (°C)

AF

M R

MS

Ro

ug

hn

es

s (

nm

)

CH3GeH3:GeH4Ratio = 0.04

Very Low RMS Surface Roughness Measured by AFM

• Low growth temperature is important for achieving smooth Ge1-xCx film

• Nearly atomically flat

• RMS Roughness = 0.32 nm

• Large 3D islands• RMS Roughness = 31 nm

600°C Growth Temperature 450°C Growth Temperature

Ge1-xCx

20 nmSi (001)

Substrate

glue (sample preparation)

20 nm

Pure Ge

Si (001) Substrate

glue (sample preparation)

XTEM Comparison of Ge1-xCx on Si with pure Ge on Si

• Pure Ge grown at low temperature directly on Si shows large number of threading dislocations

• Not present in Ge1-xCx layer

Ge1-xCx Pure Ge

• Threading dislocation densities cannot be calculated using conventional etch-pit techniques because Ge1-xCx is too thin– Use a diluted etch pit solution in conjunction

with atomic force microscopy (AFM)– 30µm×30µm measurement window

– Estimated density for Ge1-xCx ~3×105 cm-2

Bulk Ge Ge1-xCx on Si Pure Ge on Si

No etch pits

3 etch pits Numerous etch pits

EPD technique was developed by UT-Austin Master’s student Isaac Wiedmann

2.1×108 cm-2

Si (001) Substrate

Ge1-xCx

in-plane mismatch

perpendicular mismatch

Lattice Parameter and Strain Relaxation (XRD)

aGe

5.658 Å

a||

5.598 Å a ⊥

5.679 Å ar

5.643 Å

Ge1-xCx

Reciprocal space map of (224) reflection78% relaxed

Carbon Segregation Effects

1E+17

1E+18

1E+19

1E+20

1E+21

1E+22

1E+23

1E+24

0 10 20 30 40 50 60 70 80

Depth (nm)

Co

nc

en

tra

tio

n (

ato

ms

/cm

-3)

12C

28Si

Interface withSi Substrate

SIMS EFTEM

• Brighter regions correspond to higher C concentration

• Suggests chemical reaction of C with Si at the GeC/Si interface

• SIMS measured using standard prepared by ion implantation

• Higher C level at interface

EELS Data

• Energy of the C plasmon peak energy increases as we get closer to the Ge1‑xCx/Si substrate interface

• This is evidence for the higher sp3 character of the C atoms located near this interface

• This higher sp3 character could indicate the presence C-containing interstitial complexes or substitutional C in Ge near the interface. Both of these are mechanisms for strain relaxation, which helps to explain the low density of threading dislocations in the films

0.2

0.25

0.3

0.35

0.4

0.45

0.5

No Anneal 600C 700C 800C

Anneal Temperature (1 min. RTA)

RM

S S

urf

ac

e R

ou

gh

ne

ss

(n

m)

Thermal Stability:AFM and XRD Rocking Curves

-8000 -6000 -4000 -2000 0 2000

Δθ (arcseconds)

Inte

ns

ity

(a

rb. u

nit

s)

Ge1-xCx

Si

as grown

600 °C

700 °C

800 °C

• Layers were 30nm Ge1-xCx with 5nm Si cap

• Ge1-xCx peak in XRD rocking curve is shifting toward the Si peak

– Lattice constant decreasing due to relaxation and Si diffusion

• RMS roughness measured by AFM increases slightly but remains smooth

Effect of Annealing on Lattice Parameter(Si Diffusion, Relaxation)

1.0303

1.04571.0468

1.0398

1.0261.0281.0301.0321.0341.0361.0381.0401.0421.0441.0461.0481.050

no anneal(as grown)

600C1 min. RTA

700C1 min. RTA

800C1 min. RTA

Anneal Condition

d4

00 r

atio

GeC

fully relaxed bulk Ge• d400 ratio defined as ratio of Si

and Ge1-xCx d-spacings measured using rocking curves with (004) reflection

• Shows that lattice parameter decreases below the value for fully-relaxed Ge

– Most likely due to diffusion of Si atoms during annealing

– Also due to strain relaxation

• Need to use reciprocal space maps for more precise lattice parameter measurement

Step Process Notes

1Si Substrate

Cleaning2:1 H2SO4:H2O2 piranha followed by 40:1 DI:HF

2 Ge1-xCx Growth5 mTorr, GeH4 and CH3GeH3, 450C

3Surface

pretreatment

Si control - 40:1 DI:HFBC Ge1-xCx - 40:1 DI:HFSC Ge1-xCx - None

4 PVD HfO2/TaN ~7nm HfO2, 200nm TaN

5 Gate PatternLithography (Ring-type gates), RIE w/ CF4

6 Ion Implant BF2, 5×1015 cm-2, 25 keV

7 Contact LTO 530C, 2 hrs., 200nm

8 Contact/Metal Lithography, sputtered Al

9 Forming gas 6 slm, 450C, 30 min.

R2

R1

R1 = 75 µm

R2 = 85 µm

Leq ~ 10 µm

Weq ~ 500 µm

PMOSFET Fabrication Process

PMOSFET Device Structures(Buried- and Surface-Channel Devices)

Ge1-xCx BC Gate Stack

n-type Si (001) Substrate

Ge1-xCx (30 nm)

HfO2

TaN

Si cap layer (6 nm)

Ge1-xCx SC Gate Stack

n-type Si (001) Substrate

Ge1-xCx (30 nm)

HfO2

TaN

Ge1-xCx HfO2/TaN MOS CapacitorC-V Characteristics

• No Si cap layer• EOT

2.3 nm• Leakage J @ 1V

3.3×10-5 A/cm2

• Dit

4.8×1011 eV-1cm-2

• High VFB could be due to fixed negative charged introduced by diffusion of C atoms

0.0

0.5

1.0

1.5

0.0 1.0 2.0 3.0 4.0

1 MHzCalc. Low-Freq.

Cap

acit

ance

(µ

F/c

m2)

Voltage (V)

Ge1-xCx HfO2/TaN MOS CapacitorC-V Hysteresis

• Measured using forward and reverse voltage sweeps

• 78 mV at 1 MHz• 85 mV at 500 kHz• About 250 mV

dispersion between two measurement frequencies

0.0

0.5

1.0

1.5

0.0 1.0 2.0 3.0 4.0

1 MHz500 kHz

Ca

pac

itan

ce

(µ

F/c

m2 )

Voltage (V)

78 mV

85 mV

Ge1-xCx BC and SC pMOSFETsGate Leakage Current

• Higher gate leakage for surface-channel device

• Could be due to inadequate surface passivation prior to HfO2 deposition and/or HfO2/Ge1-xCx interdiffusion10-9

10-810-710-610-510-410-310-210-1100101

-3.0 -2.0 -1.0 0.0 1.0 2.0 3.0

Si ControlBC GeCSC GeC

Lea

kag

e C

urr

ent

(A/c

m2)

Voltage (V)

Output Characteristics forBuried-Channel Ge1-xCx pMOSFET

• Good saturation behavior

• IDsat = 10.8 µA/µm

@ VGS-VT = 1.0 V

• 2× enhancement over Si control

• EOT = 1.9 nm• W ~ 500 µm• L ~ 10 µm

0

2

4

6

8

10

12

-1.5 -1.0 -0.5 0.0

BC GeCSi Control

I D (

µA

/µm

)

VDS

(V)

~2X

VGS

-VT (V) = -0.2, -0.4, -0.6, -0.8, -1.0

Gate C-V Characteristic for BC pMOSFET

• Gate C-V shows buried-channel behavior

• “Kink” is due to valence band offset between Ge1-xCx and Si cap layer

• Gate leakage (inset) is 2.6×10-6 A/cm2 @ -1V

0.0

0.5

1.0

1.5

2.0

-3.0 -2.0 -1.0 0.0 1.0 2.0 3.0

Gat

e C

ap

acit

anc

e (µ

F/c

m2 )

Gate Voltage (V)

EOT = 1.9 nm

Linear ID and Gm Characteristics forBuried-Channel Ge1-xCx pMOSFET

Si ControlBC GeC

• 1.8× enhancement in both IDlin and Gm over Si control

• Ion/Ioff = 5×104

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-1.0 -0.5 0.0 0.5

Gm

(µ

S/µ

m)

VGS

- VT (V)

1.8X

0.0

0.2

0.4

0.6

0.8

1.0

-1.0 -0.5 0.0 0.5

I D (

µA

/µm

)

VGS

- VT (V)

1.8X

VDS

= 50 mV

Output Characteristics forSurface-Channel Ge1-xCx pMOSFET

• IDsat = 15.2 µA/µm

@ VGS-VT = 1.0 V

• 3× enhancement over Si control

• EOT = 1.9 nm• W ~ 500 µm• L ~ 10 µm

02468

10121416

-1.5 -1.0 -0.5 0.0

SC GeCSi Control

I D (

µA

/µm

)

VDS

(V)

~3X

VGS

-VT (V) = -0.2, -0.4, -0.6, -0.8, -1.0

Linear ID and Gm Characteristics forSurface-Channel Ge1-xCx pMOSFET

Si ControlSC GeC

• 2× enhancement in both IDlin and Gm over Si control

• Ion/Ioff < 102

0.0

0.2

0.4

0.6

0.8

1.0

-1.0 -0.5 0.0 0.5

I D (

µA

/µm

)

VGS

- VT (V)

~2X

VDS

= 50 mV

0.00.20.40.60.81.01.21.41.6

-1.0 -0.5 0.0 0.5

Gm

(µ

S/µ

m)

VGS

- VT (V)

~2X

Subthreshold Characteristics forBC and SC Ge1-xCx pMOSFETs

10-710-610-510-410-310-210-1100101

-1.0 -0.5 0.0 0.5 1.0

I D (

µA

/µm

)

VGS

- VT (V)

VDS

= 50 mV

Si ControlGeC

• High subthreshold leakage makes SS calculation difficult

• Ion/Ioff BC = >5×104, SC = >102

10-710-610-510-410-310-210-1100101

-1.0 -0.5 0.0 0.5 1.0

I D (

µA

/µm

)

VGS

- VT (V)

VDS

= 50 mV

BC

SC

Effective Hole Mobility Comparisons

• BC and SC pMOSFETs exhibit 1.5× and 2.5× enhancement over universal Si, respectively

0.0

100.0

200.0

300.0

400.0

0.0 0.1 0.2 0.3 0.4 0.5 0.6

Universal SiSi ControlBC GeCSC GeCStrained Ge onrelaxed SiGe(Ritenour, et al.)

µef

f (c

m2 V

-1s-1

)

Eeff

(MV/cm)

2 12

lnDsat

effox TGS

R RIC V V

1

3i

eff dGe

QE Q

( )i ox GS TQ C V V 4d Ge a bQ qN