Slide 1

The 8051 MicroControllerIn this class, we will be discussing the MCS-51 family of microcontrollers, in particular the 8051 architecture, which is the generic IC representative of this family.

1Important 8051 Features4K bytes ROM128 bytes RAMFour 8-bit I/O portsTwo 16-bit timersSerial interface64K external code memory space64K external data memory space

8051 Block Diagram

4Pin LayoutThe 8051 is a 40 pin device, but out of these 40 pins, 32 are used for I/O. 24 of these are dual purpose, i.e. they can operate as I/O or a control line or as part of address or date bus.

12345678910111213141516171819204039383736353433323130292827262524232221P1.0P1.1P1.2P1.3P1.4P1.5P1.6P1.7RST(RXD)P3.0(TXD)P3.1(T0)P3.4(T1)P3.5XTAL2XTAL1GND(INT0)P3.2(INT1)P3.3(RD)P3.7(WR)P3.6VccP0.0(AD0)P0.1(AD1)P0.2(AD2)P0.3(AD3)P0.4(AD4)P0.5(AD5)P0.6(AD6)P0.7(AD7)EA/VPPALE/PROGPSENP2.7(A15)P2.6(A14)P2.5(A13)P2.4(A12)P2.3(A11)P2.2(A10)P2.1(A9)P2.0(A8) 8051(8031)7Pins of 80511/4Vccpin 40Vcc provides supply voltage to the chip. The voltage source is +5V.GNDpin 20groundXTAL1 and XTAL2pins 19,18These 2 pins provide external clock.Way 1using a quartz crystal oscillatorWay 2using a TTL oscillatorExample 4-1 shows the relationship between XTAL and the machine cycle. 8Pins of 80512/4RSTpin 9resetIt is an input pin and is active highnormally low.The high pulse must be high at least 2 machine cycles.It is a power-on reset.Upon applying a high pulse to RST, the microcontroller will reset and all values in registers will be lost.Reset values of some 8051 registersWay 1Power-on reset circuitWay 2Power-on reset with debounce9Pins of 80513/4EApin 31external accessThere is no on-chip ROM in 8031 and 8032 .The EA pin is connected to GND to indicate the code is stored externally.PSEN ALE are used for external ROM.For 8051, /EA pin is connected to Vcc.PSENpin 29program store enableThis is an output pin and is connected to the OE pin of the ROM.10Pins of 80514/4ALEpin 30address latch enableIt is an output pin and is active high.8051 port 0 provides both address and data.The ALE pin is used for de-multiplexing the address and data by connecting to the G pin of the 74LS373 latch.I/O port pinsThe four ports P0, P1, P2, and P3.Each port uses 8 pins.All I/O pins are bi-directional.Reset OperationTo reset the 8051, the RST pin must be held high for at least 2 machine cycles.This can be achieved upon powerup using an RC network.The 2 circuits for achieving this, one is a manual reset, the other is a power-on reset.How does the 2 circuit works? Try to remember capacitor is open during steady-state.

Two circuits for system reset. (a) Manual reset (b) Power-on reset.

1213RESET Value of Some 8051 Registers:0000DPTR0007SP0000PSW0000B0000ACC0000PCReset ValueRegisterRAM are all zero.Oscillator ( clock) InputThe 8051 is typically driven by a crystal oscillator connected to pin 18 and 19 as shown in figThe words XTAL is short for crystal.

15XTAL Connection to 8051

C230pFC130pFXTAL2XTAL1GNDUsing a quartz crystal oscillatorWe can observe the frequency on the XTAL2 pin.16XTAL Connection to an External Clock SourceNCEXTERNALOSCILLATORSIGNALXTAL2XTAL1GNDUsing a TTL oscillatorXTAL2 is unconnected.Machine Cycle and Clock Cycle 12 clock cycles make one machine cycle as shown in fig 2-5.E.g. if we use a 12 MHz oscillator, each clock cycle will have a time period of 1/12MHz. Twelve of these make one machine cycle so 12 x (1/12 MHz) = 1 microsecond. Thats the time of 1 machine cycle.Relationship between oscillator clock cycles, states, and the machine cycle

1819Example :Find the machine cycle for(a) XTAL = 11.0592 MHz (b) XTAL = 16 MHz.

Solution:

(a) 11.0592 MHz / 12 = 921.6 kHz; machine cycle = 1 / 921.6 kHz = 1.085 s(b) 16 MHz / 12 = 1.333 MHz; machine cycle = 1 / 1.333 MHz = 0.75 sPort 0 and Port 1Port 0 is a dual purpose port, it is located from pin 32 to pin 39 (8 pins) and is labeled as AD0 to AD7. Port 1 is a dedicated I/O port from pin 1 to pin 8. It is generally used for interfacing to external device thus if you need to connect to switches or LEDs, you could make use of these 8 pins. Port 2 and Port 3Like port 0, port 2 is a dual-purpose port. It can be used for general I/O or as the high byte of the address bus for designs with external code memory.

Port 3 is also dual purpose but designers generally avoid using this port unnecessarily for I/O because the pins have alternate functions which are related to special features of the 8051. Indiscriminate use of these pins may interfere with the normal operation of the 8051.Alternate Pin-functions

16 April 201523A Pin of Port 0 8051 ICD Q

Clk QRead latchRead pinWrite to latchInternal CPU busM1P0.X pinP1.X TB1TB216 April 201524Hardware Structure of I/O Pin Each pin of I/O portsInternal CPU buscommunicate with CPUA D latch store the value of this pinD latch is controlled by Write to latchWrite to latch1write data into the D latch2 Tri-state bufferTB1: controlled by Read pinRead pin1really read the data present at the pinTB2: controlled by Read latchRead latch1read value from internal latchA transistor M1 gateGate=0: openGate=1: close16 April 201525Tri-state BufferOutputInputTri-state control (active high)LHLowHighimpedance (open-circuit)HHLH16 April 201526Port 0pins 32-39P0 is an open drain.Open drain is a term used for MOS chips in the same way that open collector is used for TTL chips.When P0 is used for simple data I/O we must connect it to external pull-up resistors.Each pin of P0 must be connected externally to a 10K ohm pull-up resistor.With external pull-up resistors connected upon reset, port 0 is configured as an output port.26Open drain is a term used for MOS chips in the same way that open collector is used for TTL chips.

16 April 201527Port 0 with Pull-Up ResistorsP0.0P0.1P0.2P0.3P0.4P0.5P0.6P0.7DS500087518951Vcc10 KPort 016 April 201528Dual Role of Port 0When connecting an 8051/8031 to an external memory, the 8051 uses ports to send addresses and read instructions.8031 is capable of accessing 64K bytes of external memory.16-bit addressP0 provides both address A0-A7, P2 provides address A8-A15.Also, P0 provides data lines D0-D7. When P0 is used for address/data multiplexing, it is connected to the 74LS373 to latch the address.There is no need for external pull-up resistors as shown in Chapter 14.16 April 20152974LS373D74LS373ALEP0.0 P0.7PSENA0 A7D0 D7P2.0 P2.7A8 A15OEOCEAG8051ROM16 April 201530Reading ROM (1/2)D74LS373ALEP0.0 P0.7PSENA0 A7D0 D7P2.0 P2.7A8 A12OEOCEAG8051ROM1. Send address to ROM2. 74373 latches the address and send to ROMAddress16 April 201531Reading ROM (2/2)D74LS373ALEP0.0 P0.7PSENA0 A7D0 D7P2.0 P2.7A8 A12OEOCEAG8051ROM2. 74373 latches the address and send to ROMAddress3. ROM send the instruction back16 April 201532ALE PinThe ALE pin is used for de-multiplexing the address and data by connecting to the G pin of the 74LS373 latch.When ALE=0, P0 provides data D0-D7.When ALE=1, P0 provides address A0-A7.The reason is to allow P0 to multiplex address and data.16 April 201533Port 2pins 21-28Port 2 does not need any pull-up resistors since it already has pull-up resistors internally.In an 8031-based system, P2 are used to provide address A8-A15.16 April 201534Port 3pins 10-17Port 3 does not need any pull-up resistors since it already has pull-up resistors internally.Although port 3 is configured as an output port upon reset, this is not the way it is most commonly used.Port 3 has the additional function of providing signals.Serial communications signalRxD, TxDExternal interrupt/INT0, /INT1Timer/counterT0, T1External memory accesses in 8031-based system/WR, /RD3416 April 201535Port 3 Alternate Functions17RDP3.716WRP3.615T1P3.514T0P3.413INT1P3.312INT0P3.211TxDP3.110RxDP3.0PinFunctionP3 Bit16 April 201536A Pin of Port 1 8051 ICD Q

Clk QVcc Load(L1)Read latchRead pinWrite to latchInternal CPU busM1P1.X pinP1.X TB1TB216 April 201537Writing 1 to Output Pin P1.XD Q

Clk QVcc Load(L1)Read latchRead pinWrite to latchInternal CPU busM1P1.X pinP1.X 8051 IC2. output pin is Vcc1. write a 1 to the pin10output 1TB1TB216 April 201538Writing 0 to Output Pin P1.XD Q

Clk QVcc Load(L1)Read latchRead pinWrite to latchInternal CPU busM1P1.X pinP1.X 8051 IC2. output pin is ground1. write a 0 to the pin01output 0TB1TB216 April 201539Reading High at Input PinD Q

Clk QVcc Load(L1)Read latchRead pinWrite to latchInternal CPU busM1P1.X pinP1.X 8051 IC2. MOV A,P1 external pin=Highwrite a 1 to the pin MOV P1,#0FFH103. Read pin=1 Read latch=0 Write to latch=11TB1TB216 April 201540Reading Low at Input PinD Q

Clk QVcc Load(L1)Read latchRead pinWrite to latchInternal CPU busM1P1.X pinP1.X 8051 IC2. MOV A,P1external pin=Lowwrite a 1 to the pinMOV P1,#0FFH103. Read pin=1 Read latch=0 Write to latch=10TB1TB2Memory StructureWhile most microprocessors implement a shared memory space for data and code (programs), microcontrollers has limited memory and the program is usually stored in ROM.In the 8051, both code and data may be internal but they are stored in separate memories, namely the internal ROM and RAM. Expandable to a max of 64K using external memory.The next page shows the 8031 which has no internal ROM.Summary of the 8031 memory spaces

42Summary of the 8051 on chip data memory

43Register Banks4 Register Banks Bank0, Bank1, Bank2 and Bank3Each Bank consists of R0, R1, R2, R3, R4, R5, R6, R7Bank 0 is the default upon power up of the microcontrollerOther banks can be selected by programming PSW register.

45RAM memory space allocation in the 80517FH30H2FH20H1FH17H10H0FH07H08H18H00HRegister Bank 0(Stack) Register Bank 1 Register Bank 2Register Bank 3Bit-Addressable RAMScratch pad RAMGeneral Purpose RAMThe general purpose RAM area is from address 30H to 7FH. The locations from address 20H to 2FH can also be used as general purpose RAM although these addresses have very specific role.Bit-Addressable RAMThe 8051 contains 210 bit-addressable locations of which 128 are at byte address 20H through 2FH.

This is the powerful feature of most microcontroller because individual bits can be set, cleared, ANDed, ORed etc. with a single instruction instead of having to read a byte and modify.488051 Flag bits and the PSW register PSW Register

CYACF0RS1OVRS0P--CYPSW.7Carry flagACPSW.6Auxiliary carry flag--PSW.5Available to the user for general purposeRS1PSW.4Register Bank selector bit 1RS0PSW.3Register Bank selector bit 0OVPSW.2Overflow flag--PSW.1User define bitPPSW.0Parity flag Set/Reset odd/even parityRS1RS0Register BankAddress0 0 0 00H-07H0 1 1 08H-0FH1 0 2 10H-17H1 1 3 18H-1FH49Stack in the 8051The register used to access the stack is called SP (stack pointer) register.

The stack pointer in the 8051 is only 8 bits wide, which means that it can take value 00 to FFH. When 8051 powered up, the SP register contains value 07.7FH30H2FH20H1FH17H10H0FH07H08H18H00HRegister Bank 0(Stack) Register Bank 1 Register Bank 2Register Bank 3Bit-Addressable RAMScratch pad RAMSpecial Function RegistersAbove 7FH, there is another block of memory 80H to 0FFH in all the version of MCS51 uP

this 128 bytes of memory are reserved for Special Function Register (SFR). There are 21 SFRs. SFRsSFR are usually addressed by nameMemory location 0F0H is given a name called Register B, similarly 80H is called P0.Not all memory location has a namememory location 35H has no nameSome locations between the SFRs have no names as well e.g. 91H. Such locations should not be used to store any data. If you do it then your data may be lost.Some important or commonly used SFRs will be discussed while others will be explained when you need to use them in your projects.

Special Function RegistersName FunctionInternal RAM address (hex)PCONPower control87PSWProgram status word0D0SCONSerial port control98SBUFSerial port data buffer99SPStack pointer81TMODtimer./counter mode89TCONTimer control88TL0Timer 0 low byte8ATH0Timer 0 high byte8CTL1Timer 1 low byte8BTH1Timer 1 high byte8DSpecial Function Registers

Commonly used SFRsAccumulator, it has two names, A and ACC. Many instruction make use of the accumulator, eg: mov A,R0, push accSP, always pointing to the top of the stack, increasing by 1 before write to stack, decreasing by 1 after read from stack

Program Status Word (PSW)This is a very important register because it contains status bits which indicates the current state of the cpu.PSW.7CarrY(CY)PSW.6Aux Carry (AC)PSW.5Flag 0 (F0)PSW.4Register Bank Select 1PSW.3Register Bank Select 0PSW.2Overflow(OV)PSW.1reservedPSW.0Even Parity Flag (P)

Accessing External Code MemoryIf the design involves external code memory, both P0 and P2 should not be used as general purpose I/O since P2 is now the Higher address bus while P0 is the multiplexed Lower address bus and the data bus. As stated earlier, the PSEN pin must be used. 16 April 20155774LS373D74LS373ALEP0.0 P0.7PSENA0 A7D0 D7P2.0 P2.7A8 A15OEOCEAG8051ROM16 April 201558Reading ROM (1/2)D74LS373ALEP0.0 P0.7PSENA0 A7D0 D7P2.0 P2.7A8 A12OEOCEAG8051ROM1. Send address to ROM2. 74373 latches the address and send to ROMAddress16 April 201559Reading ROM (2/2)D74LS373ALEP0.0 P0.7PSENA0 A7D0 D7P2.0 P2.7A8 A12OEOCEAG8051ROM2. 74373 latches the address and send to ROMAddress3. ROM send the instruction backMultiplexing the address bus (low-byte) and data bus

60Accessing external code memory

61FIGURE 211 Timing for MOVX instruction

62Internal TimersOriginal 8051 has 2 timers16 bitsTH0 : TL0Timer 016 bitsTH1 : TL1Timer 1Timers increment on each system clockTimer registers (TH0, TL0, TH1, TL1) can be read or written toTimer overflow can cause interrupts or set SFR bits high16 April 201564

Timer/Counter Logic16 April 201565PROGRAMMING 8051 TIMERSTimer 0 registersTL0 ( timer 0 low byte )TH0 ( timer 0 high byte )

16 April 201566Timer 1 registersTL1 ( timer 1 low byte )TH1 ( timer 1 high byte )

16 April 201567TMOD (timer mode) register

16 April 201568

16 April 201569Operation of Timer on Mode-0

16 April 201570Operation of Timer in Mode 1

16 April 201571Operation of Timer in Mode 2

16 April 201572Operation of Timer in Mode 3