PRELIMINARYFORM - Carnegie Mellon University

PRELIMINARY MCF AN/UYK-19 Archilecture November 22, ] 977

PRELIMINARY FORM

This document is still in a PRELIMINARY form. Any comments, sugsestions, addilions orquestions should be addressed to:

William B. DietzCarnel_ie -Mellon University

Computer Science DepartmentPittsburgh, Pa. 15213

(412) 578 - 2616

ARPAnet address:[email protected]

MILITARY COMPUTER FAMILY

AN/UYK- 19 INSTRUCTION SETARCHITECTURE SPECIFICATION

(Preliminary)

Spec.No. EL-CG-2809-MCF

November 22, 1977

This document is still in the process of development and shall be treated as aworking document.

Prepared and maintained by:

Carnegie -Mellon University, Computer Science DepartmentPit|sburgh, Pennsylvania

In support of the MCF program of:

USA CORADCOM (Prov)U.S. ARMY ELECTRONICS COMMAND

Fort Monmouth, New Jersey

PRELIMINARY MCF AN/UYK-19 Archilecture November 22, ]977

TABLE OF CONTENTS

Section PayLe_

1. SCOPE 11. ! Scope !1.2 Description 1

2. APPLICABLE DOCUMENTS 22.1 Government documents 22.2 Non-Government documents 22.3 Order of precedence 2

3. REQUIREMENTS 3

3.1 General requirements 33.2 Functional organization 33.2.1. The central processing unit 33.2.2. The primary memory 43.2.3. The memory management unit 43.2.4. The input/output and DMA interface 43.3 Processor state 43.3.1. Modes 43.3.2. Status 43.3.2.1 The CPUstatus word 4

3.3.2.1.1 Carry and overflow 53.3.2.].2 Expand memory(EM) 53.3.2.].3 Interrupt on(ION) and interrupt branch and nest(|BN) 53.3.2.1.Zl Executive mode(XMD) " 5

3.3.2.2 Floating point status 53.3.2.2.1 Floating point fault flags 53.3.2.2.2 Other floating point flags 53.3.2.3 The map status register and map violation register 53.3.3. Registers 63.3.3.1 Accumulators 73.3.3.2 Slack rep=is|ers 73.3.3.3 Base address resisters 73.3.3.4 Program counter 73.3.3.5 Floatin 8 point accumulators 73.3.4. Reserved memory locations 73.3.5. Initial state 83.4 Data types 83.4.]. Fixed point integer S

PRELIMINARY MCF AN/UYK-19 Archilecture November 22, | 977

3.4.2. Floating point numbers 8" 3.4.3. Character strings 9

3.5 |nlerruptions 93.5.]. Interrupt sequences 93.5.1.1 Interruptable instructions 93.5.2. Processor traps 103.6 Addressing 113.6.]. Direct addressing ' 113.6.2. Relative addressing J 1

3.6.3. Index register addressing Jl3.6.4. Indirect addressing !13.6.5. Auto-indexing 1 ]3.6.6. Base register addressing 123.7 Instructions 123.7.1. Classes 123.7.1.1 Memory reference 123.7.1.2 Byle manipulation ].33.7.1.3 Bit manipulation 133.7.1.4 File processing 133.7.1.5 Fixed point arithmetic 14

3.7.1.5.1 Arithmetic and logical multiple operation instructions 143.7.1.6 Floating point arithmetic ].53.7.1.7 Logical and shift operations 173.7.1.8 Stack manipulation 183.7.1.9 Program flow alteration 193.7.1.10 Resource management 193.7.1.11 Input /output 193.7.2. Instruction repertoire 203.8 Input/output 213.8.1. Special MCF I/O 2]3.9 Special features 2]3.9.1. Extended memory • 21

; 4. QUALITY ASSURANCE PROVISIONS 23

4.1 Responsibility for inspection 234.2 Classification of inspections 234.3 Archileclure Verification Programs 23

5. PREPARATION FOR DELIVERY 24

6. NOTES 256.1 Unresolved Issues 25

Appendix A: ARCHITECTURE REFERENCES 26

PRELIMINARY MCF AN/UYK-19 Architecture November 22, 1977

Appendix B: AN/UYK-19 INSTRUCTION SET 27

Appendix C: INSTRUCTION COMPARISON 35

Appendix D: AN/UYK-19 ISPL SOURCE DESCRIPTION 43

40. VERSION DESCRIPTIONS 4640.t Version 1.1 4640.2 Version J.2 4640.3 Version 1.3 4640.4 Version ].4 4640.5 Version 1.5 4740.6 Version 1.6 4740.7 Version 2.0 47

41. DECLARATIONS 4841.1 Ma{ros 4841.2 Processor State 4841.2.l. Status 48

41.2.2. Registers 4941.2.3. Main Memory 5041.3 ISPL Variables 50

42. UTILITY ROUTINES OR FUNCTIONS 5242.1. Memory Routines 5242.2 Stack Manipulation Routines 5642.3 Interrupt and Trap Routines 5742.4 Arithmetic and Logical routines 5942.5 Other Instruction utility routines 60

43. INSTRUCTION EXECUTION ROUTINES 6243.1 Memory reference 6243.2 Byte manipulation • 6643.3 Bit manipulalion 67

' 43.4 File processing 6843.5 Fixed point arithmetic 6943.6 Enhanced Floating Point Instructions 7843.6.1. Memory Reference 7843.6.2. Data Manipulation 7943.6.3. Arithmetic 8043.6.4. Test 8343.6.5. Control 8543.6.6. Diagnostic 8543.7 General Register Floating Point Instructions 8543.8 Logical Instructions 87

PRELIMINARY MCF AN/UYK-] 9 Architecture November 22, 1977

43.9 Shift instructions 90

43.10 Stack Manipulation Instructions 9243.11 Program Flow Alteration Instructions 9543.12 Resource Management Instructions 95z13.13 Input/Output Instructions 9943.14 MCF i/O Instructions 10043.15 Status Control instructions 101

44. INSTRUCTION DECODE PROCEDURES I05

45. MAIN PROCESSING LOOPS ] 17

PREL]M]NARY MCF AN/UYK-19 Architecture November 22, ]977

1. SCOPE

1.1 Scope. This specification establishes the requirements for a military computerinslruction-sel architecture, hereinafter refered to as the AN/UYK-19 architecture.

1.2 Description. The AN/UYK-19 architecture is specified so that all computers whichconform to this specification shall execute identical time independent, binary machinelanguage programs in the identical way, yielding identical results after the execution ofeach ins, truction, and varying only in the speed of execution. The definition ofcomputer architecture used in this specification is:

Computer Architecture : the structure of a

computer a programmer needs to know in orderto write any time-independenl, machine languageprogram which will run correctly on thecomputer.

The purpose of this document is to specify the architecture of the AN/UYK-]9computer, independent of any specific implementation or vendor, with sufficientprecision to permit independent implementations of AN/UYK-19 computers, whichexecute identical programs in the identical manner.

This specification is a subordinate specification la the Central Processin_ Unit(CPU3) Equipment Specification for Military Computer Family (MCF), specification EL--CP-2815-MCF. This specification in turn refers extensively to a subordinate document,the ROLM 1602 Users Manual, and to a description of the AN/UYK-19 architecturewritten in ]SPL, a formal language for the description of computer architectures, whictlis found in Appendix D of this specification.

PREL]M]NARY MCF AN/UYK-19 Architecture November 22, J97; 7

2. APPLICABLE DOCUMENTS

2.1 Government documents. The following documents of the exact issue shown form apart of this specification to the extent specified herein.

No government documents were found necessary for this specification at thistime.

2.2 Non-Government documents. The following documents form a part 'of thisspecification 1o the extend specified herein. Unless otherwise indicated the latestissue in effect shall apply.

1. Pr,ogrammer's Reference Manual for the ROLM Model 1666 Processor_Roim Corporation, Sunnyvale, Ca., ]977.

2. ROLM model 1602 User's Manual, Rolm Corporation, Sunnyvale, Ca.,1976.

3. |SPL Compiler and Simulator Manual, technical report, ComputerScience Department, Carnegie -Mellon University, Pittsburgh, Pa.,1977.

4. AN/UYK-19 _ Source Descrip!ion, Computer Science Departmenl,Carnegie -Mellon University, Pittsburgh, Pa., 1977.

Tile reference number will be used when referring to these documents below(e.g. /ref. 2/sec. 2.2.3 para. 2-3 p. 2.5 refers to section 2.2.3 paragraph 2 through 3 ofthe Rolm model 1602 User's Manual which starts on page 2.5. If no paragraphs aregiven, the whole section applies.)

2.3 Order of precedence, in the event of conflict, the requirements specified in thecontract; the Central Procesing Unit Equipment specification, this specification, theROLM Model 1602 Users Manual, Appendix D of this specification, and other documentsreferenced herein shall govern in that order of precedence.

PRELIMINARY MCF AN/UYK-]9 Architecture November 22, 1977

3. REQUIREMENTS

3.1 General requirements. A computer or processor implementing tile AN/UYK-19architecture shall perform operations at the macro-instruction level as defined in thisspecification and in the documents referenced in this section.

3.2 Functional .orKanization. An AN/UYK-19 can be divided into four main functionalsections:

a. The Central Processing Unit (CPU)b. The Primary Memoryc. The Memory Management Systemd. The input/Output and DMA interface

MEMORY <l----I> M

l I 1PROCESSORJ

I DEVICE DEVICE I ICE I

DEVINTERFACE INTERFACE INTERFACE

I CONTROL ii PANELI I

DEVICE DEVICE DEVICE

Figure 3.1. AN/UYK-19 Functional Diagram

3.2.1 Th__.£ecentral processinp_, unit. The CPU shall be responsable for all control,arithmetic and logic operations in the systern. It shall perform 16 bit si_ned 2'scomplement arithmetic, and 64 bit floating point arithmetic. There shall be four _eneralpurpose accumulators(ACO-AC3) used by the CPU in various ways, and eipoht floatinoopoint accumulalors(FACO-FAC7) used for ftoatin 8 point arithmetic:. /'re.f. J/ sec. 1.2.3par_. 3-5 p. 1.4


3.2.2 The primary memory. The processor and DMA shall have the capability toaddress up to 1024k 16 bit words of primary memory. Both the CPU and the DMAinterface shall have access to the primary memory throuBh the memory mappinB.

3.2.3 The memory manap.ement unit. The memory managemenl system shall havememory management and Rrotection functions. It shall translate J6 bit virtualaddresses into 20 bit physical addresses for up to six users, the DMA interface andthe executive. It shall offer various kinds of protection described below. (The memorymanagement system is refered to as the resource management unil(RMU) in thereferences.) /re[. J/ sec. 1.2.4 p. 1.5, [re[. I] sec. 3.4.J0 p. 3.52

3.2.4 The input/output and DMA interface. The I/O section shall consisl of the I/O busand all devices which are connected to it. There is no I/O processor or channel so all[/O, except interrupts and DMA, shall be performed under direct processor(pro_oram)control. The DMA interface shall have a map, associated with the memory managementsystem, which shall allow DMA to be mapped to physical addresses independent of tilecurrent user. /re[. I/sec. 1.2.8 parcL. 3-7 p. 1.10, /'ref. 2] sec. 2.4.2 p. 2.11

3.3 Processor state.

3.3.1 Modes. The processor shall operate in two states or modes. The execu|ivemode shall allow execution of all instructions, including full access to memory maps andprotection registers. When in the user mode, the processor shall trap at any attemptto execute a privileged instruction.

3.3.2 Status.

3.3.2.1 The CPU status word. The CPU status word shall contain six flass, which arevisable to the programmer. The instruction Push Status(PST) shall place all six flags onthe stack and provide an easy means of savin 8 or readin 8 the flags. The layout of theCPU slatus word is shown in fiBure 3.2. /'re[. l/sec. 2.2.6 parch. 2-3 p.].8

0 J5

' I i' l'l i....I° I° ]°l0 - ]ON l_lE_u_ o_ 3 - CARRYc^_,_q_,o.1.- IBN -INIE..u_,_.^_c..'_sl 4 - EM _×,'^,_Dro,_,,o_,,

Figure 3.2. CPU Status word format

PRELIMINARY MCF AN/UYK-19 Archilecture November 22, 1977

3.3.2.1.] Carry_ an__.ddoverflow. The CARRY and overflow(OVF) flags shall beautomatically controlled based on the results of certain arithmetic operalions. Theycan be tested and the carry can be preset under program control.

3.3.2.[.2 Expand memory(EM). The EM flag shall determine whether memoryaddresses are treated as ]5 bits with mulliple indirect capability or ]6 bits with onlyone level of indirection possible. When EM is clear, the logical address space shall be32k words. When EM is set, the logical address space shall be 64k words.

3.3.2.1.3 Interrupt on(ION) and interrupt branch and nesl{lBN). The ION flao shalldetermine whether interrupts are serviced by the processor. The ]BN flag shalldetermine the hardware interrupt sequence that is performed.

3.3.2.1.4 Executive mode(XMD). The XMD flag, when set, shall indicate that theprocessor is in the executive mode. This means that all instructions may be executed,and all the priviledges of the executive mode are enabled. The processor shall be inuser mode when XMD is clear.

3.3.2.2 FloalinK point status. The 32 bit Floating Point Status Rc'gister(FPSR) shallcontain ]l flags and the Floating Point Program Counter(FPPC). The FPPC shall containthe address of the last floating point instruction executed (the instruction for whichthe status flags apply). /ref. lJ sec. 3.4.6 #ara. II IO.3.27

3.3.2.2.1 Floating point fault flap_,s. There shall be six bits in the FPSR which indicatefloating point faults. ANY shall be set when one or more of the other floating poinlfaull bits (1-5) is set. OVF shall indicate an exponent overflow during a floating pointoperation. UNF shall indicate exponent overflow. DVZ shall be set when a zero divisoris detected. MOF shall be get if a high order significant bit is shifted out of themantissa during an operation. SQN shall indicate a square root operation attempt on anegative operand.

3.3.2.2.2 Other floatinR point flap,s. There shall be five other floating point flass whichindicate conditions of floating point operands and the status of the floating poi'nlsystem. The Z flag shall be set when the last operation resulted in true zero. The Nflag shall be set if the result of the last operation was less than zero. The TE bit shallbe set if floating point traps are enabled. The TWD bit shall be set when exlendedprecision mode is used.

3.3.2.3 The map status re_ister and map violation re&ister. The bits or fla£s of themap status register shall indicate map and protection status. Bits 6-9 shall indicatewhich kinds of protection are in effect. The map violation re_oister shall report varioustypes of protection violations. [re[. 1] sec. 3.4.]0 pa,rcL.31-34 #. 3.59

5

PRELIMINARY MCF AN/UYK-19 Archileclure November 22, 1977

0 15

ANYIOVF UNFDVZMOFSQN Z N TE - DM - TWD - - --I ! I I I 1 I I I I I 1 I 1FPPC

0 - ANY ,,,_.,or .l,s ,._st, 6 - Z 7F,o,l.1 - OVF _×pom._ov_..ow 7 - N ',,_,",v, ,,'2 - UNF t×.o,_r,_u.,_.,to.,, 8 - TE ..,..,,,-,,,3 - DVZ z,,o Dl,lso, 10 - DM o,,,{;,,o_,,c,,,,,,4 - MOF _,,.,,ss,, o,,_:.r[o,,, 12 - TWD _×,L.D,_,,_,ICi._,o.o.,._, ,_,_5 - SQN N,r.A_lv_SQ,,_,._Roo,o,'t.._,o 16-31 - FPPC _Lor,ll.{,,'olN,,'.or..,,,_co....

Figure 3.3. The floating point status register format

0 15

0 - XMD u._. _or), 6 - P ,,_.. o,,_.,..o,,_.,o,,l - XEM E×_CU_V_F×PA..tDMt.ORY 7 - D -r)irl_(INI)l._ct)rRoIECIION

2- UEM U_E.E×.ANr_M_M0.Y 8- l/O -,.o..o,_¢,Io,,3 - XDM ,.,cu,,v, DA,A_,^. 9- DP _..,,°o,,_,,o,4 - UDM u._,,_AiAMA, 10-12 - RESERVED

5 - DMA ._,,,_-,,, 13-15- USER_,,_,_,o.,_.,_c,,_,o_,°_

Figure 3.4. The map status register format

0 15

o - DM o,_,,°.o,,_,,o_,..o. 5 - i/o ,o_.o,_c,,o_,.oo.1 - E ,×,_,,._.°o,F_,,o._.°o. 6 - PR o°,_._c..,,._,.,,_,,o..°o.,,:,,o._.°o_2 - R -.,,,...o,,_,,o.,..o. 7 - SC ,,,o,,,,,o,,,>u.,,,c,,_,,,_,,,c_c,,o.,.,,,,o.3 - W .w._...olcc, JoNt,Ro, 8-12 - RESERVED4 - D ,..,...o,,_.,o.,.°o. ;3-;5 - USERcu..,._o.,._,̂_,,_o..,o

Figure 3.5. The map violation register format

3.3.3 Re_isters. There shall be 18 registers of various lengths visable toprogrammers; four general purpose accumulators, three sla{k registers, two baseaddress registers, the program courtier and eight floating point accumulators, lre.L 1]sec. 1.2.6 para. ! p.!.7

PRELIMINARY MCF AN/UYK- 19 Architecture November 22, 1977

3.3.3.1 Accumulators. The four 16 bit arithmetic and logic Accumulators(AC0-AC3)shall be used for arithmetic and logic operations. In addition, AC3 and AC4 can beused as index registers by memory reference instructions, and with the base registersfor byte and bit addresses.

3.3.3.2 Stack re£_isters. The Stack Pointer(SP) shall be a 16 bit register which holdsthe address of the "lop" entry in the stack, a last in first out queue. The stack pointershall be automatically incremented or decremented by operations which remove(pop)entries from the stack or add(push) entries onto the stack. The stack shall bedownward growing which means that if entry X on the stack is at address Y, thenentry X+I shall be at address Y-].

The Stack Limit(SL) register shall be a t6 bit register which holds the lastaddress available to the stack. When the value held in the stack pointer exceeds thatin the stack limit register, a stack overflow trap shall be initiated.

The Frame Pointer(FP) shall be a ]6 bit reBister which holds the address of thebeginning of a frame, which is a stack area reserved for special use.

3.3.3.3 Base address rep_isters. The two 16 bit Base registers(B2-B3)shall be usedwith AC2 and AC3 to produce byte addresses 17 bits long and bit addresses 20 bitslong for the byte and bit manipulation instructions.

3.3.3.4 Program counter. The Program Counter(PC) shall be a J6 bit register whichcontains the address of the instruction currently being executed by the CPU. It shallbe "incremented at the end of the execution of the instruction. It can also be

incremented by the skip portion of an arithmetic or logic instructon. Jump instructionsshall cause a new value to be placed in the PC. The PC shall be "wrap around" whichmeans that if the value in the PC is 77777 octal and the EM flag is clear, whenincremented the PC becomes 0 and no indication is _iven. (If EM is set all ]6 bits ofthe PC are used and 177777=>0 when incremented.) This wrap around shall apply toall PC relative operations includin 8 situations where a displacemenl is added to the PC.

3.3.3.5 FloatinK point accumulators. The eiBht 64 bit Floating PointAccumulators(FACO-FAC7) shall be used for floating point operations. FAC0 shall be

used as one operand for most floatin8 point operations_ with the other operandfetched from memory or another floalin8 point accumulator.

3.3.4 Reserved memory locations. There shall be special memory locations which havespecial functions in relation to operations of the processor. [re[. 1]sec. 2.7 Io. 2.J2

Table |. Reserved memory locations

Location Use

PRELIMINARY MCF AN/UYK-]9 Architecture November 22, ]977

0 Interrupt relurn address1 Interrupt service table address or

Master interrupt routine address2 Trap service table address3 System data table address4 AC3 system data table address5 Current interrupt mask20-27 Auto-increment locations30-37 Auto decrement locations

42 Address of instruction causingUnimplemented instruction trap

43 Address of unimplerr, ented instructioninstruction trap handler

44 Address of NEXT instruction

following stack overflow45 Address of stack overflow trap handlerNOTE: All addresses are in octal

3.3.5 i__n_nitia..___.[Istal__e. The initial contents, or state, of the processor registers after arestart shall be as follows:

Any register not mentioned in the above list shall be considered random immediatelyafter a restart.

3.4 Data types. The AN/UYK-19 shall support the following data types; fixed pointintegers; floating point numbers and chacter strings. /re]'. 2/sec. 3.2.1 p. 3.1 [re]'. 1/sec. 2.4 IO.2.2

3.4.1 Fixed point integeG integers on the AN/UYK-]9 shall be represented in severalways; single and double precision, signed and unsigned. Single precision integers shalloccupy one 16 bit word. Double precision integers shall occupy two :16 bit words withword 1 containing the most significant bits. Signed integers shall be in two'scomplement form with lhe higlq order bit representing the sign.

3.4.2 Floatinp. point numbers. Floating point numbers shall use two, three or four"contiguous 16-bit words for their represenl at ion. Word ] shall contain the sign of themantissa in bit O. Bits 1-7 shall hold the exponent in hexidecimal excess 64 code. Bits8-15 of word 1 are the most significant bits of the manlissa's magnitude. Word 2 shallcontain the next significant part of the mantissa providing 24 bits of mantissa forsingle precision (2 word) floating point. Extended precision (3 word) shall add anolher16 bits of low precision for a total of 40 bits of mantissa. Double precision (4 word)

PRELIMINARY MCF AN/UYK-J 9 Architecture November 22, ] 977

floating point shall add a fourth word for a total of 56 bits of mantissa. The generalvalue for floating point numbers is:

(+e - 100 8)N=:tMx 16

where M is the mantissa and e is tile exponent.

Zero shall have one representation in the floating point formats; all bits equal to zero.Calculations resulting in a zero mantissa shall force the result to all zero bits (truezero).

01 78 15

T T '_ EXPONENT MANTISSA 0-7 WORD 1EXTENDED "_ MANTISSA 8-23 WORD 2

DOUBLE _ MANTISSA 24-39 WORD 3

MANTISSA 40-55 WORD 4

Figure 3.6. Floating point number formats

3.4.3 Character strings. Characters in the AN/UYK-19 shall occupy one 8 bit byte andshall usually be stored two to a word with character 0 in bits 8-15 and character 1 inbits 0-7. Characters are usually encoded using the ascii standard encoding.

3.5 Interruptions. [re[. J] see. 2.8 p. 2.13

3.5.1 Interrupt sequences. The AN/UYK-19 shall have three interrupt sequences. Theconventional interrupt shall cause a branch to a master interrupt routine. Tilevectored interrupt shall transfer control automatically to the service routine for tileinterrupting device. Nested vectored interrupts shall store return information on thestack to allow higher priority interrupts during servicing. [ref. 1] sec. 1.2.8 parch. 5p. 1.I0

The power fail interrupt shall be a special interrupt which is unmaskable. Ifinterrupts are enabled, a loss of power sllall generate an interrupt with the highestpriority and device code O.

3.5.1.1 Interruptable instructions. The following instructions shall be interruptable.This means thai during execution, the microprogram sequence shall check forinterrupts and respond if a request is detected. Upon completion of the interrupt

PRELIMINARY MCF AN/UYK- 19 Architecture November 22, ] 977

service, the processor shall continue execution of the instruction, from the point whereit was interrupted. Proper completion of the inlerrupled instruction shall depend uponrestoration of any registers used by the interrupt routine. The interruptableinstructions are:

FS File SearchLKLS Linked List SearchBAM Block Add and Move

ZAP Set MemoryCOMB Compare Byte StringsCOMBT Compare Byte Strings with TerminatorMOVB Move Byte StringMOVBT Move Byte String with Terminator

LDA LoadSTA Store

ISZ Increment and Skip if ZeroDsz Decrement and Skip if ZeroJMP Jump

JSR Jump to Subroutine

3.5.2 Processor lraps. There shall be three ways in which the processor caninterrupt itself; the unimplemented instruction trap, tile stack overflow trap, and thesystem trap. The unimplemented instruction trap shall occur when the processor triesto execute an unimplemented instruction. No switch to the executive mode shall beperformed. The stack overflow trap shall occur at the end of an operation which usesthe stack and causes the stack pointer to be less than the stack limit. No switch |oexecutive mode shall be performed. The system trap shall be initiated in a number ofways, both hardware and software. Tile addresses of the trap service routines shallbe contained in a table with 16 possible entries.

Table ]I. Syslem trap table

Index description

0 Memory access violationor TRAP 0

1 ECALL or TRAP 1

2 Privileged instruction violationor TRAP 2

3 1/0 violation or TRAP 34 TRAP 4

5 Floating point fault or TRAP 56-17 TRAP's 6-17Indexes are in octal

If in user mode, the processor shall switch to executive mode on system trap. /re./. I]sec. 2.8.2 p. 2.18, /re[. 2] sec. 2.2.4 p. 2.6

10

PRELIMINARY MCF AN/UYK-19 Architecture Noven',ber 22, ]977

3.6 Addressinp,. There shall be six types of addressing which allow the inslructions tomanipulate the 64k word logical memory. Addressin 6 procedure shall be selected formany instructions throu_;h the interpretation of two index bits, an indirect bit and adisplacement field. These shall be interpreted and acted upon to form the Effectiveaddress which is the address of the final operand. There shall also be a group of lwoword instructions which have their addressin 6 determined directly by the instruction./re[. 1 ] sec. 2.5 p. 2.4, trey. I] sec. 1.2.6 p(zra. 4 p.l.8

3.6.1 Dire addressin&. Direct addressing shall be done two ways. If the index bilsare O0 and the indirect bit is clear(no indirection) then the displacement of theinstruction shall be taken as tile direct address and shall be used as the effectiveaddress. There are also some two word inslructions which use the second word of theinstruction as a direct address.

3.6.2 Relative addressin;q. When the index bits are Ol and the indirect bit is clear, thevalue of the program counter shall be added to tile displacement to form tile effectiveaddress. The operand is located relative to the address of the instruction(the PCvalue). There are some two word instructions which use the second word of the

instruction as the operand. Since the operand is located at address PC+l, il could beconsidered relative addressing.

3.6.3 Index reRister addressinR. When the index bils are 10 or 11 and the indirect bitis clear, the value of AC2 or AC3, respectively, shall be added to the displacement toform the effective address. The accumulators are used as index rep_isters. Some ofI'

the two word instructions use AC2 as an index register which is added to thedisplacement conlained in the second word of the instruction.

3.6.4 Indirect a.cJdressin _. Indirect addressin 8 shall be determined by the indirect bit.When sel, lhe indirect bit causes at least one level of indirection to take place. TheEM flag shall also play a role in indirect addressinoo. If the EM flao is set, only onelevel of indirection shall be possible and the effective address, formed as describedabove, shall be taken as an intermediate address which points to the Ioc.ationcontaining the final effective address. If EM is clear, multi-level indirecl addressin 6shall be possible. ]f bit zero of the location pointed to by the intermediate addresscontains a I, the rest of the contents shall form a new intermediate address. Thisprocess of looking for a 1 in bit zero shall continue, with the chan_in_., of theintermediate address, until a 0 is found in bit zero of the word poinled to by theintermediate address. When the 0 is found, the rest of the contents of the word shallbe taken as the effective address. This process can be limited to ]7 levels byprotection of lhe RMU.

3.6.5 Auto-indexing. Auto-indexing shall only apply, to single word instructions witheip_,ht bit displacement fields. If an indirect address references one of the auto-indexing Iocalions (20-37 octal), the contents shall be fetched, incremented (20-27

11

PRELIMINARY MCF AN/UYK- 19 Architecture November 22, 1977

octal) or decremenled (30-37 octal), written back into the indexing location, and theupdated value shall be used in the addressing chain. The state of bit zero before theindexing shall be used Io determine furlher indirection.

3.6.6 Base reAister addressinp_. Special bit and byte manipulation instructions shalluse the base registers (B2-B3) and AC2-AC3 to form bit and byle addresses. Byteaddresses shall be 17 bits wide and shall be formed by shiflin 8 the base re_ister leftone place and adding lhe result to the correspondin_ accumulator. Bit J6 of the byteaddress shall be the byte pointer. A 0 selects the left(bits 0-7) byte, and a ] select,.,the ri6hl(bils 8-]5) byle of the word addressed by bits 0-]5 of the byte address. Bitaddresses shall be 20 bits wide and shall be formed by shiftin_ the base register leftfour places and addin8 the result to the correspondins_ accumulator. Bits ]6-]9 of thebit address shall form the bit pointer. The bit pointer shall select a specific bit fromthe word addressed by bils 0-]5 of the bit address.

3.7 Instructions.

3.7.1 Classes. The AN/UYK-I9's insiructions are divided inlo It classes or types,.Privileged instructions are listed with a , after the title. (Conditionally privile_oedinstructions are followed by a *C.)Attempting to execute a privilesed, while in usermode, causes a system trap. [re[. J/ sec. 1.2.5 p. 1.5

3.7.1.1 Memory reference. Memory reference instructions shall transfer data betweenregisters and memory. Also included here are instructions which shall increment ordecrement memory contents. [ref. I] sec, 3.4.1 p. 3.6

l'lemor,t.j Reference ]nstr,uctions

LDA Load Accunlu Iator

LDAE Load Accumu I a tar-, ExtendedDLD Double LoadDLDX Daub le Load IndexedLEF Load Effective AddressLDFNA Load From Next ActdressLDFNX Load From Next Address, IndexedLDFNH Load from Next WordSTA Store AccumulatorSTAE Store Accumulator` ExtendedDST Double StoreDSTX Double Store IndexedSTTNA Store to Next AddressSTTNX Store to Next Address Indexed

DI'IE Decrement Memory ExtenctedIME I ncr'ement memory ExtenctedXCHH Exchange vJith Memor'yDSZ Decrement and Skip if Zer,o

• 12


ISZ Increment and Skip if Zero

]nslructions DSZ and ]SZ shall be read/modify/write instructions. This will allowsynchronization in multiple processor syslems. Only the final operand fetch of theseinstructions shall be read/modify/write as shown in the ISPL.

3.7.1.2 _B_.ytemanipulation. Byte manipulation instructions shall move bytes, comparebyte strings, move byte strings and search byte strings. [re[. J/sec. 3.4.2 IO.3.8

Bgte Manipulation Instructions

LDB Load ByteSTB Store Bgte]BA ]ncrement Byte AddressRBR Read Base Register14BR Mrite Base RegisterCOHB Compare Bgte StringCOtlBT Conlpare Byte String r4ith TernlinatorrlOVB Hove Bgte StringHOVBT Hove Byte String with TerminatorSRCB Search Bcjte StringSRCBT Search Bgte String with Terminator

3.7.1.3 Bit manipulation. Bit manipulation instructions shall operate on bits and bitfields. [ref. 1] sec. 3.4.3 p. 3.13

Bit Hanipulation Instructions

LDF Load Bit FieldSTF Store Bit FieldBTO Set Bit to OneBTZ Set Bit to Zero

SZB Skip if Bit ZeroSZBO Skip if Bit Zero, Set OneCOB Count One B i t s

3.7.1.4 Fil__eprocessing. File processing instructions shall operate on blocks of data.[ref. 1] sec. 3.4.4 p. 3.14

File Processing Instructions

FS F i l e SearchLKLS Linked List SearchBAH Block Acid and Hove

ZAP Set tlenlorgABD Add to Bottom of DequeATD Add to Top of Deque

13

PRELIMINARY MCF AN/UYK-] 9 Arcl_ilecture November 22, J 977

RBD Renlove fron_ Bottom of DequeRTD Remove fronl Top of Deque

3.7.1.5 Fixed point arithmetic. These instructions shall perform fixed point binary

arithmetic on 16 and 32 bit operands. /re[, I] ;c¢, 3,4,5 p, 3,20

Fixed Point Arithmetic Instructions

ADD Acld

ADC Add Complemen tADN] Add Negative ImmediateADP] Add Positive ]nlmecliateDAD Double AcidDADX Do_ble Adcl ]ndexedADFNA Add fronl Next AddressADFNX Add from Next Adclress, ] ndexedADFNLI Add fronl Next NordADTNA Add to Next Address

ADTNX Add to Next Address, IndexedSUB SubtractSBFNA Subtract from Next Address

SBFNX Subtract from Next Address, ] ndexedSBFNN Subtract from Next klordDEC Decrenlen t J

] NC ] ncrenlen t

DME Decrement Memory ExtendedIME ] ncrenlent nlemorg ExtendedDSZ Decrement and Skip if Zero]SZ Increment and Skip if ZeroNEG NegateDNA Double Negate and AddDNAX Double Negate and Actd, IndexedSDVD S i gned D i v i deUDVD Uns i gnecl D i v i cJeUDVI Unsigned Integer DivideSMPY S i gned I'lu I t i p l 9UP1PY Unsi gned I'lu I t i p l gUMPA Llnsigned FlultiplLj Wittm AddTCO Test and Clear Overflow

SSGE Signed Skip on 13tr or EqlSSGT S i gned Sk i p on IStr

3.7.1.5.1 Arithmetic and Io__ical multiple o_peration instructions. These eightinstructions shall be taken from the orisinal Nova computer. They shall allow multipleoperations in a single word instruclion. Figure 7 illustrates the operation of lhe£einstructions. /ref. I] se¢. 2.6 p. 2.8

14

PRELIMINARY MCF AN/UYK-19 Archilecture November 22, ]977

0 15

so,,.c_ _,,,.-,o_ FUNCTION SHIFT CARRY ,o^r_"ACCU_U_^,O_^CCUMUl^10. PRESET _,Lo_, SKiP

J I I i i I ] ] I I

LtNSHIF lED l_fSUt I /

FUNCTION GENERATOR _,ND_.,,.(,7_1,s>t SHIFTER

(BI]S 5.:/) {nits _,9)

i 1 SHIF IID If!,gLJl1

ttN,rlC#k_Clv(i7 i]i"g)

.......

SKIP ]

SENSOR ].. PROGRAM(f_ITS,3,_) COUNTER

(17 llIIg)

[I fill)

, ,,

(

LOAD16 fillS)

:16 BllS) I SWI1CH

CARRY CARRY ACS ACD , sPRESET FLAG

(BII,_ iO It) (B]IS I-7) (BI_S 3 a)

t (i Bll)

Figure 7. Arithmetic/Logical Instruction Function

#

3.7.1.6 Floating point arilhmetic. Two sets of floating point instructions shall besupported; an enhanced set which uses the floating poin| accumulators and a generalregister set which uses ACO-ACI. Some of the instruction encodings have beenchanged and are not the same as those cited in the reference. One mnemonic has beenchanged; FAD of the enhanced set is now FADD. However, the function of theinstructions remains the same as that stated in the reference. (See the inslruction

appendix for the encodini_s of all the instruclions,) [rcJ'. 1/ sec. 3.4.6 p. 3.25, Ire[. 2]see. 3.6.1 p. 3.47

Enhanced Floating point instruction set

Floating Point Hemorg Reference

FLDS Load FAC SingleFLDD Load FAC Double

FSTS Store FAC SingleFSTD Store FAC DoubleFPSH Push FAC's and FPSR

FPOP Pop FAC's and FPSR

15

PREL]M]NARY MCF AN/UYK-]9 Archileclure November 22, 1977

Floating Point Data Manipulation

FCLR Clear FACFNORM Normal i ze FAC

FLOS Float SingleFLOD Float Double

FIXS Fix SingleFIXD Fix Double

FINTS Fix Single + FractionFINTD Fix Double + Fraction

FXCH Exchange FAC _i th FACBFMOV Mov FAC to FAC8FMOV Hov FAC8 to FAC

FREXP Read Exp of FACB to ACI]FRST Read FPSR into ACB,AC1FSCAL Scale FAC8 into ACB

FLIEXP klrite Exp to FACB from ACI]FLIST 14rite FPSR From ACB,AC1

Floating Point Arithmetic

FABS Absolute Value of FACB

FAS Add SingleFADD Add Double

FAHS Adci from Memor 9 S ingleFArlD Add from Memory DoubleFSS Subtract SingleFSD Subtract Double

FSI1S Subtract Memor-9 SingleFSMD Sub tract Menlortj Doub I eFHS Hultiplg SingleFHD Multiply DoubleFMHS Hultiply Henlory SingleFHHD Mul t i plLJ Memory DoubleFDS Divide SingleFDD Divide Double

FDHS D i v i de by Henlorcj S i ng I eFDHD D i v i de by llemor 9 Doubl eFHLV Halve FAC8F]NC ] ncrement FAC

F ] NVS ] nver se o f FAg S i ng I eF ] NVD ] nver se o f FAC Doub I e

FNEO Negate FACFSQRS Square Root of FACB SingleFSQRD Square Root of FAC8 Double

Floating Point Test

FCMP Compare FAC8 w i th FACFSNER Skip if NO FP Error

16

PRELIMINARY MCF AN/UYK-19 Architecture November 22, ]977

FSER Skip i f FP ErrorFSEQ Skip on Ectual to ZeroFSGE Skip on Or or Eq ZeroFSGT Skip on Greater Than ZeroFSLE Skip on Ls or Eq ZeroFSLT Skip on Less Than ZeroFSNE Skip on Not Equal to ZeroFTST Test FAC

Floating Point Control

FCLE Clear FPSR Error Bits

FDTRP Disable Floating Point TrapFETRP Enable Floating Point TrapFSET3 Set Extended Preci signFSET4 Set Double Precision

Floating Point Diagnostic

RNADR Read Next Address

General Register Floating Point Instruction Set

FLO Floa tFIX Fix

FNM Nornla I i zeFAD AddFSB Subtract

FHP Mul t iplyFDV D i v i deFLD LoadFLDX Load ]ndexedFST StoreFSTX Store ]ndexed

FNG Algebraic Negate

3.7.1.7 Lo_o_gicaland shift operations. These inslruclions shall perform logical arilhmeticand mulliple shifl operalions. /re[. I] sac. 3.4.7 p. 3.39

Logical Instructions

AND AndANFNA And from Next Address

ANFNX And from Next Address, IndexedANFNN And from Next WordANTNA And to Next AddressANTNX Ancl to Next Address, indexedCOP1 Complement

17


IOR Inclusive OrXOR Exclusive Or

XCH Exchange AccumulatorsMOV Move

MGTNA Merge to Next Acldress

MGTNX Merge to Next a Address, Inclexed

Shift Instructions

LASH Left Arithmetic Shift

RASH Right Arithmetic ShiftLASHD Left Arithnletic Shift, DoubleRASHD Right Arithmetic Shift, DoubleLDSHD Left Dual-Mode Shift, DoubleLLSH Left Logical ShiftRLSH Right Logical ShiftLLSHD Left Logical Shift, DoubleRLSHD Right Logical Shift, DoubleLROT Left Rotate

3.7.1.8 Stack manipulation. Tile stackinstructions shalt allow manipulation of the stackvariables. _efi 1]sec. 3.4.8 p. 3.42, _e_ l/sec. 1.2.6 par_.5 p. 1.8

Stack Manipulation Instructions

STISZ ]ncr Top EIt,, Skip if ZeroPOP Pop Accumulator fronl StackPOPS Pop Block Fronl Stack

PRT Pop ancl ReturnPSH Push AC onto Stack

PJS Push and Jump to SubroutinePJSE Push and Jump to Subr, ExtendedPST Push Status

RTRN Pop Block and ReturnSAVE SaveRSP React Stack PointerWSP Write Stack PointerRFP Read Frame PointerNFP Write Frame Pointer

RSL Read Stack Limit

WSL Write Stack LimitFPSH Push FAC's and FPSR

FPOP Pop FAC's and FPSRRTFN| Return fronl Nested Interrupt#

18

PRELIMINARY MCF AN/UYK-] 9 Architecture November 22, 1977

3.7.].9 ProGram flow alteration. These instructionr, shall allow rnanipulalion of thepro6ram counter and shall cause the savin 6 and restorin8 of various re£_isters. /re[. l/sec. 3.4.,0 p. 3,51

Program Flou Alteration Instructions

JHP JumpJHPE Jump ExtendedJSR Jump to SubroutinePJS Push and Jump to SubroutinePJSE Push and Jump to Subr, Extended

PRT Pop and ReturnRTRN Pop B Iock and Return

3.7.l.]0 Resource manaF_ement. These instructions shall enable the manipulation ofthe memory mapping files and protection re_islers. /rej'. I] s¢c. 3.4.10 p. 3.52 exceptfor the section titled Read Remote Memory Chassis Status. The function of the ReadRemote Memory Chassis Status (RMST)instruction shall be implernentation dependent.

Resource I'lanagement Instructions

NRI1AP _r i te Map F i l e,RDMAP Read Map F i l e_',-NRNRD Mr i te S i ng I e klorcJ¢cRDLIRD Read S ingle Nord#

NMSR Nrite Map Status Register¢_RHSR Read Hal) Status Register_'¢RrlVR Read Hap Violation Register_'cCI'IVR Clear Map Violation Register,,_CDtlA C I ear DF1A V i o I a t i on,RLAF Read Last Adclress F i l e_',,

EXtlAP Enable Execut i ve Data I'lal)-'cDXMAP Disable Executive Data I'lap-,cMAPS] I'lap Single Instruction,MAPSD Map S i ng I e Da t a-,_RI'IST Read StatusUJFIP Executive to User Jump#EUB Executive to User Branch,ECALL Executive Ca l I

TRAP Sgstem Trap

3.7.1.li _ /_outpu!. The input/oulputinstructionsshallenable output to, input

from and testing of the device registers. Special device addresses allow l/Oinstructions to manipulate status conditions. /re[. l/sec. 3.4.1! p. 3.66

Input/Output Instruct ions

N]O No ]/0 (Control Signals)DIA Data Input From A Register

]9

PREL]M]NARY MCF AN/UYK-19 Architecture November 22, ]977

[lIB Data Input From B ReqisterDIC Data Input From C RegisterDEIA Data Output to A Register"DOB Data Output to B RegisterDOC Data Output to C RegisterSKPBN Skip on Busy nonzeroSKPBZ Skip on Busy ZeroSKPDN Skip on Done NonzeroSKPDZ Skip on Done Zero

Status Control ]nstructions

INTEN |nterrupt Enable,C]NTDS ]nterrupt Disable_'_C

INTA Interrupt Acknowledge_'_CMSKO Mask Out ]nterrupts,CREADS Read St4i tches-:_C]ORST Reset ]/O_'_CHALT HaJ t Processor_',-CSt<P CPU Test ION anti Poller Fail

DSPD Display AC1 in Data Display,CLRD B Iank Da t a D i sp I ayfcCSTEM Set Extended I'lemoryCLEM Clear Extended I'lenlorgST]BN Enable Interrupt Br. and Nest_'_CLIBN Clear Interrupt Br. and Nest,NA]T 14ai t for InterruptRTFN] Return from Nested ]nterrupt_'_

Special HCF ]/0 Instructions

DOA MCF Load aclctress and start transfer

DOB MCF Load output dataDOC HCF Load MCF channel informationDIA HCF Load device tables_'-

DIB MCF Get input dataDIC MCF Get MCF interrupt information

3.7.2 Instruction repertoire. There is no reference which contains the completeinstruction set of the AN/UYK-]9. Most of the instructions are described in reference

1 listed above. However, some of the encodinss of certain floating point instructionsare not the same as those listed in |he reference. Ttne operations of all theinstructions listed in reference ] are the sarne as that described in the reference.

Reference 2 contains the description of a second 8roup of floating poinl instructionswhich shall be included as described. (Note: there is an error in a bit in fisure 3.30reference 2.) /'re/. 2] sec. 3.6.1 p. 3.47,/ref. 1/sec. 3 Io. 3.I

20

PREL]MINARY MCF AN/UYK-]9 Architecture November 22, ]977

3.8 ]_o_np_.uJ_Z__Ld.There is no ]npul Output Proces.,,or supporled in the AN/UYK-]9architecture. All input and output, except interrupts and DMA, t,hatl be done underprocessor conlrol using the ]/0 instructions listed above.

3.8.1 Special MCF. ]/0. Device code 76 octal shall have a special use for MCF AN/UYK-i9's. The use of inpul / output inslructions with the MCF device code (76 octal), shallallow direct communication with the MCF bus. There shall be 5 pseudo device l/Oregisters which shall be accessed by MCF l/O instructions. The MCF ]/O instructionstake the following form:

DOA ac,MCF AddressDOB ac,MCF Data outDOC ac,MCF MCF channel information

D|A ac,MCF Load device/channel tableD]B ac,MCF Data inD]C ac,MCF MCF interrupt information

When pseudo oulpul register A is loaded, an MCF bus communication shall I)egeneraled using the inforrnation in pseudo oulput registers A, B and C. Theinformation in these registers shall be not changed by the bus communication.

MCF interrupts shall be masked on bit TBD. MCF interrupts sha_l placeinformation in pseudo input regisler C. They shall respond to ]NTA with the MCFdevice code, and it will be up to the interrupt handler to use lhe information inregister C 1o respond to the interrupt. MCF channel information and interruptinformation can be found in TBD.

The D|A MCF instruction shall be privileged and shall use the contents of lheaccumulator as the address of a block of dala which shall be loaded into the

device/channel scratchpad table. The other MCF in.'.,truc:tions shall use the standardI/0 protection mechanism for the MCF device code.

3.9 Special features.

3.9.1 Extended memory. Extended memory shall allow the virtual memory to beexpanded from 32k words with multi-level indirect addressing to 64k words with only

one level of indirection poss!ble. Effective addresses shall be J6 bils with expandedmemory operating, and 15 bits (with bit 0 acting as an indirect bit) with e×tendedmemory disabled. Careful attention needs to be paid to the effect of lhe extendedmemory mode on the slack, lhe program counter and the auto-indexing locations.

21

PRELIMINARY MCF AN/UYK-]9 Archilecture Noveml)er 22, ] 977

22

PRELIMINARY MCF AN/UYK-19 Architeclure November 22, 1977

4. QUALITY ASSURANCEPROVISIONS

4.1 Responsibilily for inspeclion.

TBD

4.2 Classification of inspections.

TBD

4.3 Architecture Verification Prop_rams.

TBD

23

PRELIMINARY MCF AN/UYK-J9 Architecture November ;_)2, 1977

5. PREPARATION FOR DELIVERY

TBD

24

PRELIMINARY MCF AN/UYK-19 Architecture November 22, ] 977

6. NOTES

6.1 Unresolved Issues. Current outstanding questions about the AN/UYK-19:

1666 memory mapping data and instruction differentation?

25


Appendix A:ARCHITECTURE REFERENCES

t. programmer's Reference Manual fo.._Lrth.._&ROLM Model 1666 Processor,Rolm Corporation, Sunnyvale, Ca., 1977.

2. _LM model 1602 User's Manual, Rolm Corporation, Sunnyvale, Ca.,]976.

Information about the AN/UYK-19 architecture can be found in the followingsections of reference 1:

SECTION PARAGRAPH(S) PAGE

1.2.3 3-5 1.41.2.4 all 1.5].2.5 all 1.5

1.2.6 all except 10-13,151.7Paragraph 10 starts with "Microprocessor". Paragraptl 13 contains onedetail about the architecture- device code 0 is returned on ]NTA.

1.2.8 all 1.10

Section 2.2 explains conventions, but contains no information about thearchitecture.

2.4 all 2.22.5 all 2.42.6 all 2.82.7 all 2.122.8 all 2.13

Section 3.3 explains conventions, but contains no information about thearchitecture.

3.4 all except parts of 3.4.6 and 3.4.10Paragraph titled "Interrupt latency" and the one that follows on p. 3.29and part titled "Read Remote Memory Chassis Stalus" on p. 3.64

Because reference 1 supercedes reference 2, much of the material in reference2 is either updated or repeated in reference 1. Much of the information in reference 2is still useful, however only those sections containing needed additional information arelisted:

SECTION PARAGRAPH(S) PAGE

2.2.4 all 2.63.6.1 all 3.47

Careful: figure 3.30 contains printing errors.

26

PRELIMINARY MCF AN/UYK-J9 Archileclure November 22, J 977

Appendix B:AN/UYK-I 9 INSTRUCTION SET

IIN/UYK-19INSIRUCIION5El

Memory Reference Instructions

Instruction Mnemonic TitleOOlRCIXXDDDDDDDD LDR Load gccumulator

IOIQCIXXOOOBIQBO D LDQE Load Accumulator,Extended01"II1018801111110Q DLD Double Load

0111101081111111 B@ DLDX Double Load Indexed

180QCIXXBBO81888 D LEF Load E(fective Address

811QC081800888810Q LDFNQ Load From Next Address

811Q001108080081BQ LDFNX Load From Next Address, Indexed011QC181088080810P LDFN# Load from Next Word

BIOQCIXXDDDDDDDD STR Store AccumulatorllBQCIXXOOOOIOBB D STQE Store Accumulator Extended

8118881808111111 OR DST Double Store

8118001001111111BQ DSTX Double Store Indexed

811RC00100000808 OQ STTNQ Store to Next Address

011QC01100008000 BQ STTNX Store to Next Address Inde×ed

IO01IIXXOOOII800 D DME Decrement Memory Extended

100101XX00011800 D IME Increment memory Extended

11I.RCIXXOOO01000 D XCIIM Exchange with Memorw

00011IXXDDDDDDDD DSZ Decrement and Skip if Zero

OOOIOIXXDDDDDDDD ISZ Increment and Skip if Zero

Byte Manipulation Instructions

Instruction Mnemonic Title

1RBQC00001081000 LDB Load Byte

JRBRCOOO01011000 STB Store Byte

100QBOOOOJOBJOOO IBQ Increment Byte Rddr'ess

IBNQC00001111000 RBR Read Base RegisterIBNQCO0001JOI800 WBR Write Base Register

0111001801000000 COMB Compare Byte String

0111101001000008 COMBT Compare Byte String with Terminator

0111001000000000 MOVB Move Byte String

0111101000000000 MOVBT Move Byte String _lith Terminator0111001010000000 SRCB Search Byte String

0111101010000008 SRCBT Search Byte String with Terminator

Bit Manipulation Inslruclions

Inslrucllon Mnemonic Title

811AB11000008008 LDF Load Bit Field011AB11001000000 STF Store Bit FieldIR00100101001000 BIO Set Bit to One

IRB8000101001000 BTZ Set Bit to Zero

1Q01000101001000 SZB Skip if Bit Zero

IRB1188181001008 SZBO Skip i( Bit Zero, Set One0110811011088000 COB Count One Bits

File Processing Instructions

27


Instruction Mnemonic TitleOlJOllOOJlOBOOOJ M FS File Search

OJJllIlO]OOBO008 M 0 LKLS Linked List Search

OlIlOJlOJ8000000 BQM Block Add and Move

8JJ. JOJlOJIO00008 Z@P Set Memory

0]10111800000080 RBD Add to Bottom o! OequeOJ]Oll]OJO0000OO ATD Add to Top of Deque

0110111001000008 RBD Remove from Bottom o! DequeOlJ811JO]lO0080O RTD Remove from Top o! Deque


Ins truct ion Mnemonic Tit leIQSAB118SHCCNSKP ADD Add

1ASAD IOOSHCCNSKP ADC Add Complement

811OI8001]NNNNNN QDNI Add Negat ivo Immediate

OIIOIOO000NNNNNN ADPI Add Posttiv0 ImmediateOJJOlOJOOOllllll OR DAD Double Add

0110101801111111BA DADX Double Add Indexed

OllACO01OIOOOOOI OR ADFNA Add from Next Address

OIIACOII8100OOOl BA ADFNX Add from Next Address, IndexedOllgClOlOlOOOO010P ADFNH Add from Next _lord

OIIACO01OlOO0000 OA QDTNA Add to Next Address

OIIACOIIOIOO0000 B9 ADTNX Add to Next Address, IndexedIASADIOISHCCNSYP SUB Subtract

OllACO01180OOO010g SBFNA Subtract from Next Address

811ACOIIIOOODOOI BA SBFNX Subtract from Next Address, Indexed811AC101180088810P SBFNW Subtract from Next Word

OIIACIOOlOOOOOOl DEC Decrement

IASADO 11SIICCNSKP INC I ncremen t

18811IXXOOOlIO80 D DME Decrement Memorg Extended

IOBI81XXOO011000 D IME Increlnent memory Extended80811IXXDDDDDDDD DSZ Decrement and Skip if ZeroOOOlOlXXDDDDDDDD ISZ Increment and Skip if Zero

IASADOOISHCCNSKP NEG Negate

01110010001111110A DNA Double Negate and Add

OlllO01OOlllllll BA DNAX Double Negate and Add, Indexed

OIIACOIOIIIlIlII SDVD Signed Divide

OllnClJO01000081 UDVD Unsigned Divide

OlIRCIIOIOOOOO81 UDVI Unsigned Integer DivideOlIACOIOIOIIIItl SMPY Signed Ilultiplg

OLIACIIOOOOOOO81 UMPY Unsigned MultiplgOllACIIOlIBOOOOl UMPA Unsigned Multiplg With AddOllO01110OOOOO01 TCO Test and Clear Overflow

IASADOBIOlIIIOO0 SSGE Signed Skip on Gtr or Eql

IASADOOlOlI01OO8 SSGT Signed Skip on Gtr

ENHANCED FLOATING POINT INSTRUCTION SET

Floating Point Memory Reference


OIIIOO000IIXXFAC O FLDS Load FAC Single811188OOIlIXXFRC D FLDD Load FQC Double

OIIIO000001XXFAC D FSTS Store FAC SingleOIIJOOOO]BIXXFAC D FSTD Store FAC Double

OllOOOlOO000000O N FPSH Push FAg's and FPSR

OlJOOOJOO]O00OOO FPOP Pop FAC's and FPSR

28

PRELIM]NARY MCF AN/UYK-J9 Architecture November 22, 1977

Floating Point Data Nanipulation


8111100011801FNC FCLR Clear FRC8111188011811818 FNORM Normalize FRC

8111108811811188 FLOS Float Single8111100011111100 FLDD Float Double

011JI00011011101 FIXS FIx 5ingle0111100011111101 FIXD Fix Oouble

8111108011811118 FINTS Fix Single + Fraction9111100011111118 FINTD Fix Double + Fraction

0111108081811FRC FXCH Exchange FAC with FRCO0111108888818FAC FMOV Mov FAC to FRCO

0111108881818FAC FMOV Mov FRC8 to FflC

0111100811811001 FREXP Read Exp of FflCO to RCO

8118081818000088 FRST Read FPSR into ACO,ACI0111100011111018 FSCRL Scale F£00 into RCO

0111188011111001 FHEXP Wr te Exp to FRCO from RCO

0110801011000088 FWST Wr te FPSR From QCO,ACI

Floating Point Arithmetic

Instruction Mnemonic T tie

8111108811811808 FRBS Absolute Value of FACO

0111180888118FRC FRS Add Single0111100001118FRC FRS Add Single0111100000110FAC FRDD Add Double

0111100001110FAC FRDD Add Double

81111000101XX010 O FRMS Add from Memory Single

01111000101XXI18 D FRMD Add from Memory Double

OIIIIOOOOBIIIFRC FSS Subtract Single

0111100801111FAC FSS Subtract Single8JIIIOOOOOIIIFRC FSD Subtract Double

QIIIIQB881111FAC FSD Subtract Double

01111000101XX0110 FSMS Subtract Memory SingleOJlIIOOOIOIXXIll O FSHD Subtract Memory Double

0111100000000FRC FMS Hu tiplg SingleOIIIIO0001OOOFRC FMS Mu tiply Single

8111100000100FRC FHD Mu tiply Double

0111100001100FRC FMD Mu tiplg Double

01111000101XX000 O FMMS Mu tiply Memory Single

01111000101XX100 O Ffl/'ID flu tiplg Memory Double

0111100000001FAC FDS Divide Single

OIIJlOO00JOOJFRC FDS Divide SingleOlIIIO0000IOJFRC FDD Divide Double

8111108001101FAC FDD Divide Double

OllllOOOlOIXXOOl O FDMS Divide by Memory Single

01111000JOIXXI010 FDMD Divide l)yMemory Double0111100011111000 FflLV Halve FRCO

OIIllOO01IIOOFAC FINC Increment FQC

OlIIIO00110JOFAC FINVS Inverso of FQC Single01JIJOOOIlIIOFRC FINVD Inverso of FQC Double

OIIIIO0011000FRC FNEG Negate FRC

9111100011011011 FSQRS Square Root of FRCO Single0111100011111011 FSQRD Square Root ol FRCO Double

Floating Point Test

29

PREL]MINARY MCF AN/UYK-19 Archileclure November 22, 1977


8111100000011FRC FCMP Compare FnCO with FQC

0118018111.800000 FSNER Skip i( NO FP E,-ro,-811811011J888088 FSER Skip if FP Error

0118181888080088 FSEO Skip on Equal to Zero

01J8181001080800 FSGE Skip on Gr or Eq Zero

0110181810008000 FSGT Skip on Greater Than Zero

0110101811008008 FSLE Skipon Ls or Eq Zero

0111001011808008 FSLT Skip on Less Than Zero

0111181811800088 FSNE Skip on Not Equal to Zero0111100011101FRC FTST Test FQC



0110008080888088 FCLE Clear FPSR Error Bits

0110080801080000 FDTRP Disable Floating Point Trap

0110000010008080 FETRP Enable Floating Point Trap011.1010111000008 FSET3 Set Extended Precision

8110000011008008 FSET4 Set Double Precision

Ftoatin 9 Point Diagnostic

Instruction Mnemonic Title8111118111000008 RNRDR Read Next Rddress

GENERQL REGISTER FLORTING POINT INSTRUCTION SET

Instruct ion Mnemonic Title

011SN10J00080000 FLO Float011SN18101000008 FIX Fix

81JSNIOJ 18008800 FNM Normal ize811SN10000800000 OR FRD Rdd

011SN10001000080 OR FSB Subtract

011SN10010080000 OR FMP Ilultiply0113NIOOIJOOOOO0 OR FDV Divide0111101008111111 OR FLD Load

0111181001111111 BR FLDX Load Indexed

0118001800111111 OR FST Store

0110001001111111 BR FSTX Store Indexed

1880011810180888 FNG Rlgebra ic Negate


Instruct ion Mnemonic TitleIQSFIDIIISHCCNSKP RND grid

8110C08111000801 OR RNFNIq Qnd from Next Rddress

011FIC81111000001 BR RNFNX Find frotnNext Rddress, Indexed011QC18111000881 OP QNFNH And from Next Word

811RC00111080000 OR RNTNR Find to Next Iqddress

011nC01111000000 BR RNTNX Find to Next Address, indexed

1FISIqDO80SHCCNSKP COM Comp Iomen t

011gC18001080081 fOR Inclusive Or

011QC10000008001 XOR Exc lus lye Or

IRSRDOOJOJOIIOSO XCH Exchange FlccumuIatorstlqSlqDOlOSHCCNSKP MOV Move

3O

PRELIMINARY MCF AN/UYK-19 Archileclure November 22, ] 97; 7

0111qC00110000008 OR MGINR Merge to Next Addres_

011AC01110000000 BI:::I MG'rNX Merge to Next a Address_ Indexed

Shift Instruct ions


BlIOIOBOIB180NNN LI:ISH Left Arithmetic Shitt

81JSlO0010101NNN RASH Right Rrithmetic Shift

OIJ.OJO8001JOONNN LRSHD Left Rrithmet ic Shift, DoubleOJJOIOOO01JOINNN RRSHD Right Arithmetic Shift, Double

OJJOIO000]OONNNN LDSHD Left Dual-Mode Shift, Double

OI]OIOGO]OOJNNNN LLSH Lett Logical Shift

OJJOJO0010JINNNN RLSH Right Logical Shift

011010000101NNNN LLSHD Left Logical Shift, DoubleOJJgJOOOOJlINNNN RLSHD Right Logical Shift, Double011010801800NNNN LROT Left Rotate

Stack Manipulation Instruct ions


8110011110000001 STISZ Incr Top Elt., Skip if Zero

811RCOIOIOO00001 POP Pop Rccumulator from Stack0118011091000000 POPB Pop Block From Stack

0110000010080001 PRT Pop and Re.turn011RC01001000001 PSH Push FIE onto Stack

e110011101000081 n PJS Push and Jump to Subroutine

10001IXXeOOlZ000 D PJSE Push and Jump to Subr, Extended0110011111800081 PST Push Status

0110011010000000 RTRN Pop Block and Return0110011000000000 N SRVE Save

811RC01000000001 RSP Read Stack Pointer-0110C01011880001 WSP _]rite Stack Pointer

1801qC00001111800 RFP Read Frame Pointer-

180QC00091101000 gFP Nrite Frame Pointer

IOlRCOOOOIIIIOOO RSL Read Stack Limit

101RC00001181009 LISL l.Irito Stack Limit0110001008000008 N FPSR Push FRC's and FPSR

8110001001000000 FPOP Pop FRC's and FPSR

0118800811808001 RTFNI Return from Nested Interrupt

Program Flow Alteration Instruct ions


800001XXDDDDDDDD JI'IP Julnp

IO0001XXO00110OO D JMPE Jump Extended

088011XXDDDDDDDD JSR Jump to Subroutine

9110011101008081 R PJS Push and Jump to Subroutine

108011XX00811080 D PJSE Push and Jump to Subr, Extended0118000818008801 PRT Pop and Return

0110011010008000 RTRN Pop Block and Return

Resource Management Instruct ions

Instruct ion Mnemonic Tit le

JO0000JOOJOJJOOe HRMRP _Jrite Map File

1000101081011000 RDriAP Read Map File

1081001001011808 IJRWRD IJrite Single _Jord

31

PRELIMINARY MCF AN/UYK-19 Architecture November 22, ] 977

101)1101001011088 RDI.IRD Read Single I,Iord .... . -'"

10]QC01001001000 WMSR IJrito Map Status Register

J00QC0100.100]880 RMSR Road Map Statu_ Register

JIORCOJO0100JOO0 RMVR Road Map Violation Register

JOJ080JOO[OllO00 CMVR Clear Map Violation Register1010101001011008 COMA Clear DI1A Violation

0110011101000808 RLRF Read Last Address F i le

1100001001011000 EXMAP Enable Executive Data Map

1100101001011000 DxMIqP Disable Executive Data Map

1011881001011000 MFIPSI Map Single Instruction1811101001811088 MRPSD Map Single Data1101001001811008 RMST Read Chass is Status

111QC01001081000 UJMP Executive to User Jump8118811110000080 EUB Executive to User Branch01J001111]000000 ECQLL Executive Call

181AC00081001000 TRAP System Trap



BIIO8000FFDEVICE NIO No I/O (Control Signals)8IIQCO@JFFDEVICE DIQ Data Input From A Register

811AC811FFDEVICE DID, Data Input From B Register

OIIRCIBIFFDEVICE DIC Data Input From C Register

OIIQCOIOFFDEVICE DOn Data Output to I:t Register

OIJRCIOOFFDEVICE DOB Data Output to B Register

OIIQCIlOFFDEVICE DOC Data Output to C Register

OI10811108DEVICE SKPBN SKip on Busy nonzero

OI180111OIDEVICE SKPBZ Skip on Busy Zero

OIIBBIIIIODEVICE SKPDN Skip on Done Nonzero

0118011111DEVICE SKPDZ Skip on Done Zero

Status Control Instruct ions


0110800881111111 INTEN Interrupt Enable

8110880818111111 INTDS Interrupt Disable

811QCOIIFFIlIlII INTQ Interrupt Acknowledge

811NCISOFFJ11111 MSKO Mask Out InterruptsOIJQCOOIFFIIIIII READS Read Switches

01180181FF111111 IORST Reset I/O

81]QCIOIFFIlIlll IORST Reset I/OOllOOlJOFF111111 HALT Halt Processor

01 IAC 1IOFF 111111 HALT Ha It Processor

01100111FF]11111 SKP CPU Test ION and Po14er Fail

0118010011080001 DSPD Display ACt in Data Display

0]J0000011]J]]1J CLRD [_,lank Data Display

NIJOF_OOOOIONOOOI STEM Sot Extended Memory

01]0000000000001 CLEM Clear Extended Melnory01110]0011000001 STIBN Enable Interrupt Dr. and Nest

0111110011000001 CLIBN Clear Interrupt Br. and Nest01111110J1000000 WAIT IJai t for Interrupt

01J0000011008001 RTFNI Return from Nested Interrupt

MCF I/O Instructions

81.1QCOIOFFIlllIO DOQ MCF Address out and transfer init late

32


81]ACIOOFF111118 DOB MCF Dala Output811RCIlOFFIII118 DOE t]CF MCF Channel informal ion Out

01]RCOBIFFIIIllO OIA MCF Reserved for laler use

OlJRCBIJFFlIII18 DIB MCF Dala Input

811RCIOIFFI1111B DIC MCF MCF Interrupt information In

No-ops

8118008888111111 NOP No operation(NlO 77)

8111188811811111 NOP No operalion(reserved)

8111188811111111 NOP No operation(reserved)

Unimplemented Instructions

IXXXXXXX881XIBB8 U8

181XXXXXOBB11880 UI

110XXXXXOBOIIOO8 ' U2

111XXXXXOOOIIOB8 U3

IOxxxooB81811888 U4leooxoe8o1801880 US

IOXXXOOl818OlOOO U6

01101111XXXXXXXX U7

OIIIOJIIXXXXXXXX U8OIIIIIIIXXXXXXXX U9

1XXXXBOOIBXX]OO8 UlO

1XXXXOOB1,IXXIOOO UII

IXXXXOOI]OXX]O80 U12

IXXXXOOIIIXXIOO0 U13

IXXXXOJOIOXXJ808 UI4

]XXXXO1011XXIOOO U]5

IXXXXOI]BIXXJOO8 U16

JXXXXOIIIOXX]OO8 U17

llOllOlO0101]OOO U]8

]I].XXO]OOIOIIO00 UI9

1XXXX01001181808 U28IXXXXOlO8111100O U21

OllO81118OOOO008 U22

IOJOXOIBOIOIIBBB UX8

IXXXXIXXOIXXJOOB UXI

IXXXXXXXIXXXJOOO UX2 (covBr$ some of above)

8118OOOOXX111118 MCF8

011XX00101111110 MCF!

OlIXXOOIIO111118 MCF2811XX80111111110 MCF3811XXO100111111B MCF4

011XX01010111118 MCF5811XX01811111110 MCF6

011XXB110111111B MCF7811XXOlllOl1111B MCF8

011XX01111111110 MCF9

811XX18001111118 MCF18

OlIXX10818111118 MCFII

811XX1081111111e MCF12811XXlOIOI11111B MCF13

811XXIBIIO11111B MCF14011XX10111111110 MCFIS

33

PREL]M]NARY MCF AN/UYK-19 Architec.ture November 22, 1977

OI1XXIIOOIIIIIIO MCFI6OlIXXIIOIBIIIIlB MCFI7811XXllOlllllll8 MCF18OllOOlllXXlllllO MCFI9

34


" " Appendix C:

INSTRUCTION COMPARISON

KEY.

Tilts is a comparison of the instruction sets of two machines; the ROLM 1602 andthe ROLM 1666. Each line contains the instruction bit pattern, additional wordsneeded, the instruc|ion mnemonics, two columns showing the instruction's relationshipwith the two machines and the instruction lille. A "Y" in a column indicates that ttleinstruction is included in tile machine's instruction set. A "C" in a column indicates thatthere is a conflict with an instruction in the machine and the mnemonic in conflictfollows the "C" (if an instruction has more than one conflict with the same machine, theline is repealed to indicate all conflicts). A "*" in a column indicates that there is noconflict because the instruction uses a noload, no skip type of no-op encoding. A "." ina column indicates that no conflicts were found in an automated comparison of the bitpatterns. (Note: Mnemonics Uxx and U]xx are unimplemented instructions for the 1666and the 1602 respectively.)

1682 - 1666 INSTRUCTION SETS

Memory Reference Instructions

Instruction Mnemonic 1682 1666 Title

801RCIXXDDDDDDDD LDQ Y Y Load nccumulator

IOIRCIXXOOO81888 D LDQE _ Y Load Accumulator,Extended

8111101008111111 OR DLD Y FLD Y Double Load

011110188JI11111BR DLDX Y FLDX Y Double Load Indexed

IOORCIXX80001880 D LEF _ Y Load Effective Address

811RC08100000881 DR LDFNR Y Y Load From Next address

811RC0110088B001BR L_FNX Y Y Load From Next nddress, Indexed

811RC181808888810P LDFNW Y Y Load }rom Next Hord

810nCIXXDDDDDDDD STQ Y Y Store Rccumulator

llOQCIXXOO081080 D STQE ¢ Y Store Qccumulato," Extended8118881888111111 OR DST Y FST Y Double Store

8118001801111111BR DSTX YFSTX Y Double Store Indexed

811QC08108000000 OR STTNR Y Y Store to Next Rdd,-ess

011QC01108880800 Bfl STTNX Y Y Store to Next Rddress It,dexed

IOOJIIXXO0011OOO D DME _ Y Decrement tlemory Extended

IOOIOlXXO0011000 D IME _ Y Increment memorg Extended

JIIRCIXXO00OlOOO D XCHM _ Y Exchange with Mcmorq

O00IIIXXDDDDDDDD DSZ Y Y Decrement and Skip if Zero

OOOIOIXXDDDDDDDD ISZ Y Y Increment and Skip il Zero

Byte Manipulation Instructions


1QBQC00001081808 LDB, _ Y Load Byte

JQBQCO00OJOIIOOO STB • Y Store Bgte

100Q000001001088 IBQ _ Y Increment Byte Rddress

JBNRCOO00111]O00 RBR _ Y Read Base Register

]_NQCOOOOlIOIOOO WBR _ Y llrite Base Regisler

0111001001000000 COMB Y Compare Byte String

0111101001000000 COMBT . Y Compare Byte String with Terminator

35

PRELIMINARY MCF AN/UYK-]9 Archilecture November 22, 1977

0111001000000080 MOVB . Y Move Byte String

0111101000080000 MOVBT . Y Move Byte String 14ith Terminator0111081018080800 SRCB . Y Search Byte String

8111101810000000 SRCBT . Y Search Bgte String with Terminator

Bit Manipulation Instructions


811AB11000000088 LDF . Y Load Bit Field011AB11001008880 STF . Y Store Bit Field

1RB0100101001808 BTO _ Y Set Bit to One

IAB0000101001000 BTZ ,_ Y Set Bit to Zero

]ABJOOBI011)01000 SZB (" Y Skip if Bit Zero

IRB1108101001008 SZBO 8 Y Skip if Bit Zero, Set One8118811011888808 COB . Y Count One Bits

File Processing Instruct ions

Instruct ion Mnemonic 1602 1666 T i t le0110110011000081 M FS Y Y File Search

0111111810088000 M 0 LKLS . Y Linked List Search

0111011010000000 BAM . Y Block Iqdd and Move

OJ11011011000008 ZAP . Y Set ltemory0110111000000000 l:l_D . Y Add to Bottom ol Oeque

0110111810000888 ATD Y Add to Top of Deque

0118111001008080 RBD Y Remove trom Bottom of Deque0110111011008008 RTO . Y Remove from Top of Oeque


Instruct ion Mnemonic 1602 1666 Title1RSlqDIIOSHCCNSKP ADO Y Y Add

1FISIqDlO05t4CCNSKP IqDC Y Y Reid Complement

0110100011NNNNNN FIDNI Y Y Add Negative Immodimte01JBI00000NNNNNN I:IDPI Y Y Add Positive Ilnvnodtate

0110101000111111 OR DAD Y Y Double Add

0110101001111111 BA DFIOX Y Y Double Fldd Indexed

011FIC00101808001 OR IqDFNA Y Y Add from Next Address

0111qC01101000001 Blq ADFNX Y Y Add Irom Next Address, Indexed011RC10101000881 OP IqDFNW Y Y FIdd from Next Herd011AC00101800000 OR ADTNA Y Y Add to Next Ftddv-ess

011PLC01101800000 BA FIDTNX Y Y Fldd to Next Flddress, IndexedIFISIqDIO1SHCCNSKP SUB Y Y Subtract

0111qC00110080001 OA SBFNA Y Y Subtract from Next Address

011RC01110000001 BA SBFNX Y Y Subtract from Next Address, Indexed011nC10110080001 OP SBFNI4 Y Y Subtract from Next [,lord8111qC10010000001 DEC Y Y Decreinent

1RSiqD011 SHCCNSKP INC Y Y Incr omen t

100111XX00011000 D DME • Y Decrc_ment Melnory Extended

100101XX80011008 D IME :;- Y Increment memor.q Extended

80811IXXDDDDDDDD DSZ Y Y Decrement and Skip i! Zero

08810IXXDDDDDDDD ISZ Y Y Increlnent and Sk ip i f Zero

1FISFID00] SHCCNSKP NEG Y Y Negate

0111001000111111 OR DNA Y Y Double Negate and Add

0111001001111111 BFI DNAX Y Y Double Negate and Ftdd, Indexed

011RC01011111111 SDVD Y Y Signed Divide

011PLC11001000801 UDVD Y Y Unsigned Divide

36


OIJRCllOlO000001 UOVl Y Y Unsigned Integer Divide

OIJQCOJOIOJ]IIII SMPY Y Y Signed Multiply

OJJQCJlOOOOOOOOJ UMPY Y Y Unsigned MultiplyOIJQCJIOJIOOOOOI UMPA Y Y Unsigned Multiply With AddOJJOOlllO000OOOl TCO Y Y Test and Clear Overflow

1ASAD80]OIIIlOO0 SSGE _ Y Signed Skip on Gtr or Eql

IASRDO010llOJOOO SSGT _ Y Signed Skip on Gtr


Instruction Mnemonic JG02 J666 Title

]QSRDIIlSIICCNSKP AND Y y And

OlIQCOOIIJOO8001 OR QNFNQ Y y And from Next Address

OIJACOlIllOOOO01BQ QNFNX Y y And from Next Address, Indexed811RCJ8111800801DP RNFNW Y y And from Next Word

OJlQCOOll]O000OO OR RNTNQ Y y And to Next Address

OlIACOIlllOOO800 BR RNTNX Y y And to Next Address, indexedIASADOOOSHCCNSKP COM Y Y ComplementOlJQCIOOOI800001 fOR Y Y Inclusive Or

OlIACIOOOOOOOOOl XOR Y y Exclusive Or

IRSADSBJBIOllOOO XCH _ Y Exchange Accumulators

IRSRDBIOSHCCNSKP MOV, Y y Move

OlJQCOOIIOOBOOOO DR MGTNQ Y y Merge to Next Address

OIJQCOIJJOOO800O BQ MGTNX Y Y Merge to Next a Address, Indexed

Shift Instructions

Instruction Mnemonic 1602 J666 Title

81IBIOOBIBIBBNNN LASH Y Y Left Arithmetic Shift

8110188010181NNN RASH Y Y Right Arithmetic Shill

OllOlBOO81180NNN LQSHD Y Y Left Arithmetic Shill, Double

BIIBIBOBB1181NNN RASHD Y Y Right Arithmetic Shift, DoubleOIIBJOSBOIBBNNNN LDSHD Y Y Left Dual-Mode Shill, Double

811810081801NNNN LLSH Y Y Left Logical Shill

8118lOOOI811NNNN RLSH Y Y Right Logical Shift

OlIOIOOOOIOlNNNN LLSHD Y Y Left Logical Shift, DoubleOlJOIOOO011INNNN RLSHD Y Y Right Logical Shift, DoubleOIIOlOOOI800NNNN LROT Y Y Left Rotate

Stack Manipulation Instructions

Instruction Mnemonic 1602 J666 Title

OlJOOllllOOOOOOl STISZ Y Y lncr Top E I t., Sk ip i t Zero01IACOIOIOOOOOOJ POP Y Y Pop Accumulator from Stack

OJJOOJJOOJO00000 POPB . Y Pop Block From Stack

OJJOOOOOJOO00001 PR1 Y Y Pop and ReturnOiJACSlOOJOOOOgJ PSH Y y Push AC onto Stack

OJJOOllJOJOOOOO] A PJS Y Y Push and Jump to Subroutine

lOOOllXXOOOllOOO O PJSE _ Y Push and Jump to Subr, Extended0110011111000001 PST Y Y Push Status

OllOOIlOIOOOOOOO RTRN Y Pop Block and ReturnO]lOOJJOOOOOO000 N SAVE Y SaveOJJACOJOOOOOOOO] RSP Y y Read Stack Pointer

8lJACOJOIJOOOOOJ WSP Y Y tit,re Stack PointerJOOACOOOOIIIJOO0 RFP ¢ y Read Frame Pointer

lOOACOOOOllOJOOO #FP _ y Hrite Frame Pointer]O]ACO000IlIlOOO RSL _ Y Read Stack Limit

37

PRELIMINARY MCF AN/UYK-19 Architecture November 22, /977

1810C00001181000 IJSL _ Y Wr ite Stack L imi t

0110018088088000 N FPSH C FFID Y Push FQC's and FPSR

8118810801080808 FPOP C FSB Y Pop FQC's and FPSR

811080B011000001 RI'FNI Y Y Return item Nested Interrupt

Program Flow I:llteration Instruct ions


98808 IXXDDDDDDDD JMP Y Y Jump

100001XX00011000 D JMPE , Y Jump Extended

000011XXDDDDDDDD JSR Y Y Jump to Subroutine

0110011101000001 ¢I PJS Y Y Push and Jump to Subrout ine

100011XX00011000 D PJSE _;', Y Push and Jump to Subr, E×tended

8110000010000001 PRT Y Y Pop and Return

OlIOOJIOJO00OO00 RTRN . Y Pop Block and Return

Resource Management Instruct ions

Instruct ion Mnemonic 1602 1666 Ti t le

1000001001011000 WRMQP , Y Write Map File1000101001011000 RDMQP ¢ Y Read Map F i le

1001801001011880 gRURD , Y Write Single Word

1001101001011000 RDI4RD _ Y Read Single Word

181RC01081801000 IJMSR , Y 14rite Map Status Register

1009C01881081008 RMSR , Y Read Map Status Register

110QC81001081800 RMVR 8 Y Read I'1;,f) Violation Register101800100J011000 CIIVR _ Y Clear Map Violation Register1018101801011000 CDM£ ¢ Y Clear DMQ Violation0110011101800000 RLFIF . Y Read Last Qddress File

1100881801011000 EXIIFIP ¢ Y Enable Executive Data Map

1108181881811808 DXMFIP _ Y Disable Executive Data Map

1011001001011088 MRPSI * Y Map Single Instruct ion1011181801811808 MRPSO * Y Map Single Data1101001801011000 RMST _: Y Read Chassis St,_tus

111QC01001001000 UJMP * Y Executive to User Jumi)

0110811118008088 EUB . Y Executive to User Branch

0118811111000080 ECFtLL . Y Executive Ca l I

181QC00001081800 TRRP , Y System Trap



01-IOOOOOFFDEVICE NIO Y Y No ]/0 (Control Signals):OIIQCOOJFFDEVICE DIe Y Y Data Input From Ft Register

811RCOIJFFDEVICE DIB Y Y Data Input From B Register

OIIQCIOIFFDEVICE DIC Y Y Data Input From C Register

OIIRCOIOFFDEVICE DOg Y Y Data Output to g Register

OIIQCIBDFFDEVICE DOe Y Y Data Output to B Register

OIIQCIIOFFDEVICE DOC Y Y Data Output to C Register

OI180J, I100DEVICE SKPDN Y Y Sk ip on D,usy nonze,-o

01100111010EVICE SKPBZ Y Y Skip on BUSy Zero

8110011118DEVICE SKPDN Y Y Skip on Done Nonzero011801111JDEVICE SKPDZ Y Y Skip on Done Zero

Status Control Instructions

Instruct ion Mnemonic 1602 1666 Tit le

38

PRELIMINARY MCF AN/UYK-19 Ar(hilecture November 22, 1977

01100800_1111111 ]NTEN Y Y Interrupt Enable011008881011]111 INTDS Y Y Interrupt Disable

01JRCOI1FFIIIJII INTR Y Y Interrupt Rcknow ledgeOIIRCJOOFFIIIII1 MSKO Y Y Mask Out Interrupts811RCOOIFFilIJII REflDS Y Y Read S_Jitches

81180181FF111111 IORST Y Reset I/0

011ACJO1FF111111 IORST Y Reset l/O

01188110FF111111 HRLT Y Halt Processor

011RCIIBFF111111 HRLT Y Halt Processor01100111FF111111 SKP CPU Y Y Test ION and Po_,er Fail

0110010011800001 DSPD Y Y Display RCI in Data Display0110808011111111 CLRD Y Y Blank Data Display

0118800001000081 STEM Y Y Set Extended Memory0110000080008081 CLEM .Y Y Clear Extended Memory0111810011000001 STIBN Y Y Enable Interrupt Dr. and Nest

0111118811088081 CLIBN Y Y Clear Interrupt Br. and Nest

8111111811888888 WRIT . Y Wait (or Interrupt

8118808811880881 RTFNI Y Y Return from Nested Interrupt

1666 FLOATING POINT PROCESSOR INSTRUCTIONS

Floating Point Memory Reference


OIIIOOOOOIIXXFQC D FLDS . Y Load FRC Single01118008111XXF¢IC D FLDD . Y Load FAC Double

81110080881XXFAC D FSTS . Y Store FIrICSingleOIIIOOO8101XXFRC D FSTD . Y Store FAC Double

0110818008000888 N FPSH C FAD Y Push FlqC's ,_nd FPSR

8118818881888888 FPOP C FSB Y Pop FRC's and FPSR

Floating Point Data Manipulation

Instruction Mnemonic 1602 1666 Title8111100811081FRC FCLR . Y Clear, FFIC _

0111100011011010 FNORM . Y Normalize FRC

8111100011011108 FLOS . Y Float Single0111100011111188 FLOD . Y Float Double

8111180011011181 FIXS . Y Fix Single0111100811111101 FIXD . Y Fix Double

0111108011011110 FINTS Y ' Fix Single + Fraction011110801111]110 FINTD Y Fix Double + Fraction

0111100001011FRC FXCH Y Exclnange FRC with FRCOOIIIIOOOOOOlOFRC FMOV Y Mov FRO to FI:ICO8111100001010FRC FMOV Y Mov FRCO to F#C

8111100011011001 FREXP Y Read ExI)of FRC8 to RC8

0111118100000000 FRST C FLO Y Read FPSR into RCO,RC10111100011111018 FSCClL . Y Scale FRCO into RC8

01.11]00011111001 FUEXP , Y I.Jrite Exp to FRCO froth FICO

0111110]01080008 FWST C FIX Y Write FPSR From PlCO,lqC1

Floating Point Rrithmetic

Instruction Mnemonic 1602 1666 Title0111100011011000 FRB5 Y Rbsolute Value of FFICO

01 I1100000110FRC FRS . Y Rdd Single

39

PRELIMINARY MCF AN/UYK-]9 Archileclure November 22, 1977

0111188081118FNC FRS Y Add Single8111100000118F#C FAD Y Add Double

8111180081118FRC FQD . Y Rdd Double

01111080181XX818 D FRMS . Y Acld from Memory Single

81111888181XXI18 D FAMD . Y Add from Memoru Double

0111180880111FAC FSS . y Subtract Single

8111100081111FQC FSS . Y Subtract Single8111108888111FRC FSD' . Y Subtract Double

0111108081111FAC FSD . Y Subtract Double

8111108010]XX811D FSMS . Y Subtract Memory Single01111088181XX111D FSMD . Y Subtract llemory Double

8111100808089FAC FMS . Y Mu tiply Single

0111100801809F8C FMS . Y Mu tiply Single8111188888188F£C FMD . Y Mu tiply Double

0111188801100FAC FMD . Y flu tiply Double

0111100910IXX808 D FMMS . Y Mu tiply Memory Single0111100018IXX108 D FMMD . Y Mu tiply Memory Double

0111188080881F£C FDS . Y Divide Single

8111100801001FRC FDS . Y Divide SingleDJJIJOO800JOJFRC FDD . Y Divide Double

0111100001101FRC FDD . Y Divide Double

01111800181XX001D FDMS Y Divide by Memory Single81111880101XX101D FDMD Y Divide by Memor 9 Double0111100011111008 FHLV Y Halve FRCO

0111100011100FRC FINC . Y Increment FRC

8111100811010FRC FINVS . Y Inverse of FQC Single8111180011JIOFRC. FINVD . Y Inverse of FRC Double

OlJ.IIOOOIIOOOFRC FNEG Y Negate FRC

0111100811011011 FSORS . Y Square Root el FRCO Single

011110001111J011 FSQRD . Y Square Root el FQCO Double

Floating Point Test


0111100808011FRC FCMP . Y Compare FRC9 _ith FRC8110810111000808 FSNER . Y Skip if NO FP Error

8118118111088808 FSER . Y Skip if FP Error

0110110181009800 FSEQ C FIX Y Skip on Equal to Zero

0110010188009000 FSGE C FLO Y Skip on Gr or Eq Zero

8110010110000008 FSGT C FNM Y Skip on Greater Than Zero

0110110110000000 FSLE C FNM Y Skip on Ls or Eq Zero

0110110100000008 FSLT C FLO Y Skip on Less Than Zero

0110010101000008 FSNE C FIX Y Skip on Not Equal to Zero8111180811101FRC FTST . y Test FAC


Instruction Mnemonic 1602 J666 Title0111110110809808 FCLE C FNM Y Clear FPSR Error Bits

8111818101800008 FDTRP C FIX Y Disable Floating Point Trap

8111810188898898 FETRP C FLO Y Enable Floating Point Trap0111010111080088 FSET3 . Y Set Extended Precision8111018118008888 FSET4 C FNUM Y Set Double Precision

Floating Point Diagnostic


40


8111118111080888 RNRDR . Y Read Next Rddress

1602 Floating Point Option Instructions

Instpuct ion Mnemonic 1602 1666 Title011SN10108080008 FLO Y C FRST Float

011SN18100000080 FLO Y C FSGE Float011SN10180080800 FLO Y C FSLT Float

01ISN18]88008000 FLO Y C FETRP Float

Ot]SNJOIOJO00000 FIX Y C FSEO Fix

011SN10101000000 FIX Y C FSNE Fix811SNIO]OlOOOOO8 FIX Y C FDTRP Fix

011SN10J81088080 FIX Y C FIJST Fix

011SN]8110808808 FNfl Y C FSGT Nor,m,_l_ze

011SN181J8000008 FNI1 Y C FSLE Normal ize01J.SN18110000008 FNII Y C FCLE Normal ize

OlISNIOIJOOOOOOO FNI'I Y C FSET4 Normalize

811SN10080800808 OA FAD Y C FPSH l:Idd

011SN10001000000 DA FSB Y C FPOP Subtract

0115N10010008800 01:1 FI'IP Y . Multiply0113N].8011000000 OA FOV Y . Divide

0111101000111111 OA FLD Y C DLD Load

0111101001111111 BI:I FLDX Y C DLDX Load Indexed

8118001000111111 OR FST Y C DST Store0110001001111111 BA FSTX Y C OSTX Store Indexed

1000011810108800 FNG Y . Algebraic Negate

1682' Unimplemented Instruct ions

811XX101XXOOOOO8 UIB(FP) Y

011XXIOOXXOBO808 UII(FP) Y

81JOOOOOXX800008 UI2 (FP) Y

811XXBlOXXSO8888 UI3 Y

8118011100080000 UI4 Y0118811181080000 UI5 Y

8118811118880880 UI6 Y

8118811111808080 UI7" Y011XXIIBXX888008 UI8 Y

81181111XXXXXXXX UI9 Y





1666 Unilnplemented Instruct ions

1XXXXXXXOOIX1008 UO _ Y181XXXXXO8011008 UI _, Y

I]8XXXXX88811888 U2 _ Y11J XXXXX88811080 U3 5,, Y

10XXX88801811888 U4 _( y

18OOX 00081801880 U5 _ Y -'-

10XXXOOJOI081000 U6 _ Y

01] 001001XO00000 U7 . Y

0118010011000000 U8 . Y

gJ 101100XXOO8000 U9 Y

41

PRELIM]NARY MCF AN/UYK-]9 Architeclure November 22, 1977

011]X18011000000 U]O , Y

OI]OOO]OXXO80000 UJJ , Y

OIJOIOIOXXOOO00O UJ2 . Y

0111X01011800000 UI3 , Y81101111XXXXX×XX UJ4 Y

81110111XXXXXXXX U]5 YOlIIII11XXXXXXXX U16 Y1XXXXOOOIOXXlOO0 U17 _ Y

1XXXXOOOIIXXIOO0 U18 _ Y

. IXXXXOOIIOXXIOO8 U19 ¢ Y

1XXXXOO111XXJSO8 U20 • YIXXXXOIBIOXX1000 U21 _ Y

IXXXXB1011XX1008 U22 _ Y

lXXXXOllOlXXlOOO U23 _ Y

1XXXXOIJlOXX]OB8 U24 ¢ YllOllOlO01OllOOO U25 , Y

111XX81801811880 U26 , YIXXXXOIOOJ181808 U27 • Y

IXXXXBIB81111808 U28 # Y81180880XX088888 U29 . Y

0118811100880808 U38 . Y

42


Appendix D:AN/UYK- 19 ISPL SOURCE DESCRIPTION

The following is a description of the AN/UYK-19 architecture written in ]SPL, amachine readable computer architecture symbolic description language.

43

PRELIMINARY MCF AN/UYK-]9 Architecture November 22, 1977

4Zl

PREL]M]NARY MCF AN/UYK-J9 Architecture November 22, ]977

45

40. VERSION DESCRIPTIONS

40.1 Version I.I.l This is the ISP for the ROLM 1602 (ANIUYK-19) Computer.Three

' types of instructions have been left out of this ISPLdiscription of the ROLM 1602. They are "INPUT-OUTPUT WII'H

i ACCUNULATOR", "INPUT-OUTPUT WITIIOUTACCUNULAIOR", and "CODF.-77i IO WITH ACCUMULATOR" (Figure 3-2, Page 3-13 of the "1602

OPERATION AND _IAINTENANCE MANUAL", Rolm Corporation, 1974).l All the other I/O and interupt instructions have been included

in this discription. The decoding for the "INPUT-OUTPUT" is abit messey in that IR is tested repeatedly to determine the

w instruction. ADOL 3121/77

40.2 Version 1.2.l Single precision floating point instructions have beenI implemented as fixed point. The entire INPUT.OUTPUT sectioni has been changed from DECODEs to IF statements with BAII.OUTs.' WD15 6115177

40.3 Version 1.3.

i ROI.M 1566 Resource Management Unlt has been added. Part ofJ the decoding is in the arithmetic section, and part is in the

I/O section. Instructions have separate routines. KL30 andI WDI5 7113/77

40.4 Version 1.4.i Indirection has to be started by IR<5>. The msb of an address

will be ignored if EM=O, except indirection is possible. AllI address registers are 16 bits wide, module 2t16. The msb isi ignored if necessary. Auto increment and decrement are onlyt possible inside indirect chains. KL30 8/I/77

46

PRELIMINARY MCFAN/UYK-19 Archileclure November 22, ] 977

40.5 Version 1.5.J Device I/0 instructions and the interrupt sequence have beenl added. LS20.

40.6 Version 1.6.t Code 77 IlO with ACC has been added. L820

40.7 Version 2.0.i The ISPL has been completely reorganized to allow for properl maintenance. The instruction space is comp]etely decoded and

all unimplemented instructions are trapped. The decoding forl the Rolm 1666 instructions has been included, makJn9 this the

ISPL for the MCF AN/UYK-19. Not all the instruction routines .

l have been completed, but they are included _is hops. WD15! 111g0177 ,

47

41. DECLARATIONS

UYKI9 :=

(!START MCF AN/UYK-19DECLARE

41.1 Macros.

NACRO BEGIN := ( $MACRO END := ) $MACRO INCR.PC:= PC<O:IS>_(PC<0:15>+1)<15:0> $NACRO INCR2.PC:= PC<O:I5>_(PC<0:15>+2)<15:0> $

41.2 Processor State.

41.Z.i Status.

STATUS<0-]5>; !Status of the computerION<> -=STATUS<0> ; ! Interupts ONIBN<> -=STATUS; !Banching interupt sequences ONOVF<> :=STATUS<2> ; ! OVerFlow bitCARRY<> -=STATUS<3>; !Carry bitEM<> :=STATUS<4>; !Expanded Memory

XMD<> ::STATUS<5>; !Executive Node

FPSR<0:3]>; !Floating Point Status RegisterANY<> "=FPSR<O>; !ANY of bits I-5 setFOVF< > "=FPSR; !Exponent overflowFUNF< > "=FPSR<2>; !Exponent UNl)erflowFDVZ< > :=FPSR<3>; !Zero divisorF_IOF<> -=FPSR<4>; !F1antissaOverflowFSQN<> :=FPSR<5>; !Negative square root operandFZ<> :=FPSR<6>; !Zero bitFN<> :=FPSR<7>; !Negative bitFTE<> "=FPSR<8>; !Trap enableFD_I<> -=FPSR<IO>; !Diagnostic )nodeFTWD<> :=FPSR<13>; !Extended precision operationFPPC<O:lS>-=FPSR<16:31>;!Floating Point Program Counter

t

HSR<0:15>; !Map Status RegisterXMDC<> "= MSR<O>; i executive I_loDe ComplementXEM<> := MSR; ! executive Expanded Memory

48

UEM<> := MSR<2>; n User Expanded Nemory

XD_I<> -= MSR<3>; _ eXec Data NapUDM<> "= MSR<4>; , User Data _lap

• ! D_IA mapDMA<> := MSR<5>,P<> :: HSR<6>; 0 User R/W/ExecLIte page Prot, ectionD<> -= MSR<7>; t Defer(indirect) Protection1.O<> -= MSR<8>; 0 I/O ProtectionDP<> "= MSR<9>; ! DMA Protection

u := MSR<lO:12>; o ReservedUSER<Z'O>::MSR<I3:I5>; n User or last active user(Z-7)

MVR<0:15>; !Map Violation RegisterDMPE<> "= MVR<0>; t DMA Protection ErrorEPE<> "= NVR; u Execute Protection ErrorRPE<> .= NVR<2>; i Read Protection ErrorWPE<> -= NVR<3>; I Write Protection ErrorDPE<> -= _IVR<4>; _ Defer Protection ErrorIOPE<> -= NVR<5>; l 1/O Protection ErrorPRPE<> -= MVR<6>; t PRiveleged inst Protection ErrorSCPE<> := MVR<7>; n Violation occured during Sillgle Clyle op

0 := MVR<8" 12>; _ ReservedVUSER<Z:O>:=NVR<13:15>; [ last active USER

41.2.2 Registers.

AC[ 0 : 3 ]<0 : 15>; !Accumulator SetAC0<0:IS> := AC[0]<0:IS>; !Accumulator 0ACI<0:15> := AC[I]<0:15>; !Accumulator 1AC2<0:15> := AC[2]<0:15>; !Accumulator 2AC3<0:15> :: AC[3]<0:15>; !Accumulator 3

SP<0" 15>; !Stack Pointer8L<0:15>; !Stack LimitFP<0-15>; !Frame Pointer

BR[O-I]<0-15>; !Base Registers

B2<O:IS>:=BR[O]<0:15>; !Base reg 2

B3<O:15>:=BR[1]<O:lS>; !Base reg 3

PC<0:15>; !Program Counter

FAC[0:7]<0:63>; !Floating point accumulatorsFAC0<0:63>:=FAC[0]<0:63>; !Accumulator 0FACl<0:63>:=FAC[l]<0:63>; !Accumulator lFAC2<0:63>:=FAC[2]<0:63>; !Accumulator 2FAC3<0:63>:=FAC[3]<0:63>; !Accumulator 3

49

PRELIMINARY MCF AN/UYK-19 Archileclure November 22, ]977

FAC4<0:63>:=FAC[4]<0:63>; !Accumulator 4FAC5<0:63>:=FAC[5]<0:63>; !Accumulator 5FAC6<0:63> : =FAC[6]<0:63> ; !Accumulator 6FAC7<0:63> :=FAC[ 7]<0:63>; !Accumulator 7

MAPREG[0:511]<0:15>; !Hemory NAP REGisterPROTECTREG[0:23]<0:]5>% !I/O Protection Files

I,AF[0:3]<0:IS>; !Last Address FileLDNR<O:]5>:=LAF[O]<O:]5>; !Address of last DHA accessLDAR<0:]5>:=LAF[1]<0:15>; !Address of Last Non fetch accessNFAR<O:I5>:=LAF[2]<O:IS>; !Address of Next to Last FetchLFAR<0:I5>:=LAF[3]<0:15>; !Address of Last Instruction Fetch

41.2.3 Main Memory.

HEMORY[0:98303]<0:IS>; !Hain HEMORY (96K for now, I024K max.)

41.3 ISPL Variables.

CPDATA<0:15>; !Control Panel DATA lightsSWITCH<0:IS>; !Console Switches .POV;ER.FAIL<>; !Power Fail flagAUTO.RESTART<0:15>; !Auto restart address

IR<0:15>; !Instruction RegisterLOGICAL.ADR<0:15>; !Logical address for memory mappingHI)R<0:15>; !Memory Data Register for memory transfersMHAP<2:0>; !Hap Number to be used

MAP.ENTRY<0:15>; !Holds last map entry from memory mapPIIYADR<0:19>; !Physical Address after translation

MSI<>; !Hap Single Instrution flagH,SD<>; !Nap Single Data f]agDATREF<>; !DATa REFerence f]ag

TRAP.INDEX<3:0>; !Trap Index for System Trap

ISA<0:16>; !Interrupt Service AddressINTNSK<0:15>; !INTerrupt NaSK

INDX.FLD<0:I>; !INDEX FIELD for effective addressUDISPL<0:15>; !Unsigned DISPLacement fieldDISPL<0:15>; !Sign Extended DISPLacement field

5O

PRELIMINARY MCF AN/UYK-19 Archiledure November 22, ]977

INI)R.BIT<>; !INDIRECT BIT for effective addressSIIORT<>; !F]ag Indicates ,SIIORT form

1NI)IR.CNT<4:0>; !Indirect count for defer protection

BYTE.ADR<0:16>; !Temproary byte addressABN<0:I>; !Temporary base register pointer

SIGN<>; !Temporary Sign holder.

DEV.INREG<O:]5>; !Source for inputDEV.OUTREG<0:15>; !Destination for outputDEV.NUMBER<0:5>; !Device Number of interrupting deviceDEV.IBIT<O:]5>; !Interrupt bit for each bit in mask word

THI'.NO.OP<O>; !For No-opsTMP.FCTN.OPT<0:16>; !Temporary buffer at input of ShifterTNI'.SHIFTER<O:16>; !Temporary input of No Load/Load SwitchTMPDOUBLEREG<0:3£>; !Temporary double registerTMI'OSIGN<O>; !Teml)orary sign holderTMPISIGN<O>; !Temporary sign holderTI)0<0:31>; !Temporary double registerTD]<0:3I>; !Temporary double registerTENPO<0:15>; !Temporary register 0TENP1<0:15>; !Temporary register ITISNI_2<O:lfi>; !'remporaryregister Z

TEPIP3<O:15>; !Temporary register 3

51

PRELIMINARY MCF AN/UYK-] 9 Archileclure November 22, ] 977

42. UTILITY ROUTINES OR FUNCTIONS

NOP:= !No operationBEGINTNP.NO.OP _ TMP.NO.OP

END;

42.1 Memory Routines.

NAP.NEM:= !Performs actual physical address calculationBEGIN

(DECODE EFI =>\0 FlAP.ENTRY<O:15> ,,- MAPREG[(NriAP<2:0>*64 +

LOGICAL.ADR< 1:5>)<8:0> ]<0 : 15> ;

\I MAP.ENTRY<0:15> _ MAPREG[ (N_IAI'<2:0>*64+LOGICAL,ADR<0:5>)<8:0>]<0:15>) NEXT

PIIYADR<0:19> 4- (MAP.ENTRY<6:15>@ LOGICAL.ADR<6:15>)<19:0>END;

W.NAP.BIT:= !Writes "Dirty Page" bit in map fileBEGIN

MAP.ENTRY<0> _ i;(DECODE EFI =>\0 MAPREG[(NNAP<2:O>*64 +LOGICAL.ADR<I:5>)<8:0>]<0:15> "-

FIAP.ENTRY<O :15>;

\l MAPREG[(NMAP<2:O>*64 + LOGICAL.ADR<0:5>)<8:0>]<0:15> ,-FLAP.ENTRY<0 :15>)

END;

VIRT.REAL:= !Virtual to real address translationBEGIN

(DECODE XMDC =>\0 BEGIN !Executive mode

(DECODE DATREF =>\0 PHYAI)R<0:19>_'0000@I,OGICAL .AI)R<0;15>;.•\1 (DECODE (XDM OR MS1 OR PISD):>

\0 PHYADR<0 :19>_'[email protected])R<0:15>;\i BEGIN

(IF XDM => NMAP<2:0)_USER<2:0>) NEXT(IF NSl => (NMAP<Z:O>_USER<Z:0>;

M,SI*0))NEXT(IF MSD :>

BEGIN

(DECODE UDM AND (USER<Z:O> LEO 4) =>\0 N_IAP<Z:O>*-USER<2:0>;

52

\ 1 NI_IAP<2 :0 >.-(USER<2:O>+3 )<2:O> ) ;

I'ISD.-O

END) NEXTHAl) .HEH

END) )END;

\1 BEGIN !USER NODE(DECODE UDH AND (USER<2:0> LEQ 4) :>\0 NHAP<2 : 0>.-U,SER<2:0> ;\l NFIAP<Z:O>.-(USER<2:O>+3 )<Z:O> ) NEXTFlAP. FlEFl

END)END;

o

READ.MEHORY:= ) Fill HDR with data in rlEFIORYlocation LOGICAL.ADR.BEGINVIRT.REAL NEXT

(IF XHDC =>BEGIN

(IF NOT(RPE OR WPE) :> LDAR _ LOGICAL.ADR) NEXT(IF (P AND HAP.ENTRY<2>) =>

BEGIN !Read Protection Violation

RPE _ 1;TRAP.INDEX _ 0 NEXT8YSTRAP

END)END) NEXT

HDR<0: 15> _ HEFIORY[PHYADR<0:19>]<0 :15>

END;

WRITE.HEHORY:= ! Store HDR into HEMORYlocation LOGICAL.ADR.BEGINVIRT.REAL NEXT(IF XrlDC =>

BEGIN

(IF NOT(RPE OR WPE) => LDAR _ LOGICAL.ADR) NEXT(IF (P AND FlAP.ENTRY<3>) =>

BEGIN !Write Protection Violation

WPE _ I;TRAP.INDEX * 0 NEXT8YSTRAP

END )END) NEXT

HEHORY[PIIYADR<0:19>]<0:15> _ HDR<0:15>;W.FlAP.BIT

53

END;

R.DATA:: !Read Data From MemoryBEGINDATREF - 1 NEXTREAD.MEMORY NEXTDATREF _ 0

END;

W.I)ATA:= !Write Data into MemoryBEGINDATREF _ I NEXTWR ITE. MEMORY NEXTDATREF _ 0END;

R.BYTE:= !Read a byte from meraoryBEGIN

BYTE.ADR-(BR[ABN]@O + AC[ABN])<I6:O> NEXT(DECODE EM => '\0 LOGICAL.ADR_'[email protected]< 1:15>;\I LOGICAL.ADR_BYTE.ADR<0:I5>) NEXTR.DATA NEXT

(DECODE BYTE.ADR<I6> =>\0 MDR_'00000000@FIDR<0:7>;\l MDR_-'OOOOOOOO@_IDR<8:15>)END;

W.BYTE:= !Write a byte into memoryBEGINTEMPO_MDR NEXT

BYTE.ADR_(BR[ABN]@O + AC[ABN])<16:0> NEXT(DECODE EM =>\0 LOGICAL .ADR,-' [email protected]<1 : 15> ;\1 LOGICAL.ADR_-BYTE.ADR<0:15>) NEXTR.DATA NEXT

(DECODE BYTE.ADR<16> =>\0 MDR_TEMPO<8: 15>@MDR<8:15>;\1 NDR_MDR<O:7>@TE_|PO<8:15>) NEXTW. DATA

END;

INCR.DECR.MEMORY:= !Do the AUTOINCRE_IENT or AUTODECREMENT!of the special _]EMORYlocations.

BEGIN

(DECODE LOGICAL.ADR<IZ> => !Decrement(--O) or Increment( =l )\0 MDR<O:15>_(NDR<O:15> + 1)<15:0>;

54

PRELIMINARY MCF AN/UYK-I9 Archileclure November 22, J977

\I MDR<O:I5>.-(HDR<O:I5> - I)<15:0>) NEXTURI TE. HEMORY

END;

EFF.ADR.CALC:: !Puts Final Address in LOGICAL.ADRBEGIN(DECODE INDX.FLD<O:I> :> !Decode. ]ndex Field\00 LOGICAL.ADR<O: 15>_UDISPL; ! DIRECT ADDRESSING\Ol LOGICAL.ADR<O:15>_(PC<O:15) + DISf'L<O:15>)<15:0>;\10 LOGICAL.ADR<O:15>o(AC2<0:15> + DISPL<0:15>)<15:0>;\II LOGICAL.ADR<O:IS>_-(AC3<O:I5> + DISPL<O:I5>)<I5:0>) NEXTINDIR.CNT - 0 NEXT(IF INDR.BIT =) !Indirection?

INDIR.LOOP := BEGININDIR.CNT _ (INDIR.CNT + I)<4:0> NEXT(IF (INDIR.CNT GEQ 17) AND D =>

BEGIN !Indirect (Defer) Protection ViolationDPE * 1 ;TRAP.INDEX _ 1 NEXTSYSTRAP

END) NEXTREAD. HEtiORY NEXTINDR.BIT_MDR<O> NEXT

(IF (LOGICAL.ADR<I:II> EQL I) AND SIlORTAND NOT(EFI AND LOGICAL.ADR<O>) :> !Auto index?INCR.DECR.MEMORY) NEXT

LOGICAL.ADR<O:I5>_NI)R<0:15> NEXT(IF INDR.BIT AND NOT EH => INDIR.LOOP)END)

END;

SHORT.ADR.$ETUP:: !Sets up Short form effective addressBEGIN

INDX.FLD_IR<6:7>;UDISPL<0:15>_'00000000@IR<8:I5>;(DECODE IR<8> =>\0 DISPL<O : 15>_'00000000@IR<8 : 15>;\I DISPL<O : 15>_' Iii 11111@IR<8 : 15>) ;INDR.BIT * IR<5>;SIIORT*-1 NEXTEFF.ADR.CALC NEXT,SI-IORT,-O

END;

EXT.ADR.,SETUP:: !Sets up Extended Effective AddressBEGININDX. FLD*-IR<6:7>;

55

PRELIMINARY MCF AN/UYK-]9 Archilecture November 22, ] 977 !

LOGlCAI..ADR,-(PC +1)<15:0> NEXTREAD.rlEHORY NEXTUI)] SP L,-HDR;DI SPL,-rlDR ;INDR. BI T,-IR<5> ;BilORT,-0 NEXTEFF,ADR. CALC

END;

INSTR. FETCH := ! Fetch an Instruction from NemoryBEGINLOGICAL.ADR<O:I5>_-PC<0:15> NEXTVIRT.REAL NEXT( IF XHDC = >

BEGIN

(IF NOT(RPE OR WPE) =>NFAR_ LFAR NEXTLFAR _ PC) NEXT

(IF (P AND HAP.ENTRY) =>BEGIN !Execute Protection ViolationEPE _" 1 ;TRAP. INDEX .- 0 NEXTSYSTRAP

END)END) NEXT

IR<0 : 15>...MENORY[PItYADR<O:19>]<0 : 15>END;

42.2 Stack Hanipulation Routines.

CHK.STACK.OVF:= !Check for Stack Overflow and TrapBEGI N(IF 8P<0:15> L88 SL<0:15> => !Stack overflow?

BEGINION_O;MDR<O: 15>_PC<0 : 15>;LOGICAL.ADR<O:I5>_ 44 NEXTURI TE. HEHORY;LOGICAL.ADR<O:IS>_ 45 NEXTREAD.HEMORY NEXTPC<O: 15>_NDR<O: 15> NEXTBAILOUT INST. DECODE.EXECUTEEND)

END;

56

PUSH. STACK:= !Push MDR onto StackBEG IN

SP '- (SP - 1)<15:0> NEXT

(DECODE EM =>

\0 LOGICAL.ADR_0@SP<1:15>;\1 LOGICAL.ADR_SP<0:IS>) NEXTWRITE. FIEMORY

END ;

POP. STACK: = ! Pop stack into MDRBEG IN

(DECODE EM =>

\0 LOGICAL.ADR_0esP;

\l LOGICAL.ADR*-SP<0:15>) NEXTREAD. IqElqORY NEXT

SP ",- (SP+I)<IS:0>END ;

42.3 Interrupt and Trap Routines.

INTERRUPT:= !Perform Interrup_ LinkageBEGIN

TEMPI_MSR NEXT

XMD ,-- 1; XNDC T O;XDIq .- O;Et,l ,-- XElq NEXT

(DECODE IBN =>

\0 BEG IN !Ordinary interruptION _ O;MEMORY[O] _ PC NEXTPC<O:IS>_IENORY[I]<O:IS> !Indirect through loc 1END;

\1 BEGIN !Branch sequence interruptISA ,- MEMORY[(DEV.NUMBER+MENORY[I])<IS:0>] NEXT(DECODE ISA<O> =>\0 BEGIN ! Simple

ION _ O;NENORY[O] _ PC NEXTNENORY[NENORY[3]] _ TEMPI ;NENORY[4] _ AC3;PC _ 18A<1:15>END;

\I BEGIN !Branch and nestFIDR _ PC NEXTPUSH. ;STACK NEXT

57

PRELIMINARY MCF AN/UYK-19 Archileciure November 22, ] 977

HDR _ HEHORY[5] NEXT !Get current mask• PUSII.STACK NEXT

INTHSK _ rlEHORY[(TEHPO-1)<14"O)] NEXTHErIORY[5] ',-- INTHSK NEXTCHK.STACK.OVF NEXTPC .- ISA<1:15>

END)END)

END;

UNIHP:= !Onimplemented instruction trapBEGIN

LOG ICAL.ADR_34 ;IDR.-PC NEXTWRITE .HEHORY NEXTLOGICAL.ADR_35 NEXTREAD.HEMORY NEXTPC_HDR

END;

!The Stack Overflow Trap is included in CHK.STACK.OVF above.

SYSTRAP:- !System Trap SequenceBEGIN

TEHP1 _ HSR ;XDH_O; EH_XEH;TEHP2 .- SP ;TErtP3 _- SL NEXT

(IF NOT XHD =>XMD _ 1 ; XHDC _ 0 NEXTSP _ HEHORY[HEHORY[3]] NEXTSL ,- HEHORY[HEHORY[3] + 1]) NEXT

rlDR ,-- TEHP3 NEXTPUSH. STACK NEXT

HDR ,- TEHP2 NEXTPUSH. STACK NEXTHDR ,-- TEHP1 NEXTPUSH. STACK NEXTHDR .,-- PC NEXTPUSH. STACK NEXT

HDR ,,-- HEHORY[5] NEXTPUSit.STACK NEXT

PC,-- HEHORY[HEHORY[2] + TRAP.INDEX<3:0)]<O:15) NEXTC}IK.STACK.OVF NEXTBAILOUT FETCH. EXECUTE

END;

58

PRELIMINARY MCF AN/UYK-19 Archllec|ure November 22, ]977

42.4 Arithmetic and Loflical routines.

CARRY. SETUP: : ! Initialize the Carry bit.BEGIN(DECODE IR<IO:II> :> !Decode set up options.\00 NOP; !O0=Leave as is.\01 CARRY_O; !01=Clear initially.\lO CARRY_I; !10=Set initially.\11 CARRY_NOT(CARRY)) !ll:Coml)lement present value.END;

SIIIFT:= !Take care of shift determined by shift FIELDBEGIN(DECODE IR<8:9> => !SH field\00 TNP.SHIFTER<O:I6>,-TNP.FCTN.OPT<O:I6>; !NO SIIIFT\01 TNP.SHIFTER<O:16>_-TNP.FCTN.OPT<O:IG> tRL I; !SHIFT LEFT 1\10 TrlP.SHIFTER<O:I6>,-TNP.FCTN.OPT<0:16> tRR I; !S}IIFT RIGIIT l\II BEGIN !SWAP BYTES AND PASS CARRY

TMP.SHIFTER<O>_TNP.FCTN.OPT<O>;TMP.SHIFTER_TNP.FCTN.OPT<9 : 16> ;TMP.SHIFTER<9 : 16>-TNP.FCTN.OPT< 1:8>END)

END;

NOLOAD.LOAD:= !Load the Destination and Carry if true.BEGI N(IF IR<12> EQL 0 => !Do we load?

BEG]N

CARRY',-TMP.Sit I FTER<0 > ;AC[ IR<3:4>]<0: 15>_TNP.SHIFTEREND)

END;

SKIP:: !Handles the Skip operation specified by the SKIP field.BEGIN

(DECODE IR<13:15> => !Skip field\000 NOP; !NO SKIP\001 INCR.PC; !SKIP\010 (IF (TNP.SHIFTER<O> EQL O) => INCR.PC);\Oll (IF (TNP.SHIFTER<O> NEQ O) => INCR.PC);\I00 (IF (TNP.SIIIFTER<I:I6> EQL O) => INCR.PC);\101 (IF (TNP.SHIFTER<I:I6> NEQ O) => INCR.PC);\110 (IF ((THP.SIIIFTER<O> EQL O) OR

(TNP.SHIFTER<I:IG> EQL 0))=> INCR.PC);\111 (IF ((TNP.SIIIFTER<O> NEQ O) AND

(TNP.SHlFTER<I:16> NEQ 0))=> INCR.PC)) NEXTINCR.PC

59

PRELIMINARY MCF AN/UYK-19 Archileclure Novornber 22, 1977

END;

42..5 Other Instruction utility routines.

CTL77:= !Control Functions for CODE 77 InstructionsBEGIN

(DECODE IR<8:9> =>\00 NOP;\01 ION_I ;\ 10 ION-O ;\ i i CPDATA_O)END;

FP.OP.SETUP:= !Sets up operand for gen reg floating point instructionsBEGINLOGICAL.ADR<O:15>-(LOGICAL.ADR<O:I5>+I)<15:0> NEXTREAD. MEMORYNEXTLOGICAL.ADR<O : 15>.-NDR<O: 15> NEXTR.DATA NEXTTDl<O:15>*-f'IDR<0:15> NEXT

LOGICAL.ADR<O:15>',-(LOGICAL.ADR<0:15>+l)<15:0> NEXTR.DATA NEXTTDI< 16:31>*-MDR<O : 15>

END;

FP.SKIP:: !General Register Floating Point Skip FunctionsBEGIN

(DECODE IR<3:4>=>\00 NOP ; !no operation\Ol (IF(INPDOUBLEREG EQL O)=>INCR.PC); !skip on positive\10 (IF(TMPDOUBLEREG EQL I)=>INCR.PC); !skip on negative\11 NOP) !normalize(not implemented)END;

CKI'RV:= !Check for Privi]eged Instruction ViolationBEGINIF XMDC =>

PRPE _ i NEXTTRAP. INDEX _ 2 NEXTSYSTRAP

END;

CKIO.PROTECT:= !Check for I/0 Protection ViolationsBEGINTEMPO_PROTECTREG[(USER-2)*4+IR<lO:II>]<0:15> NEXT

6O

PRELIMINARY MCF AN/UYK-19 Arc:hileclure November 22, ] 977

TErqPO.--(TEI_lt'OtSLO IR<IZ:]5>)<IS:0> NEXT(iF (XI_IDC AND I.O AND TEI_IPO<O>)=>

BEGIN !I/O Protection VlolationIOPE _ i ;TRAP. INDEX _ 3 NEXTSYSTRAPEND)

END;

INDEV:= !Input from device registerBEG IN

AC[ IR<3:4>] _ DEV. INRE6END;

OUTDEV:= !Output to device registerBEGINDEV.OUTREG _ AC[IR<3:4>]END ;

61

43. INSTRUCTION EXECUTION ROUTINES

43.1 Memory reference.

LDA::BEGINSHORT.ADR.SETUP NEXTR.DATA NEXT

AC[ IR<3:4>]<0 :15>,-MDR<0:15>;INCR.PC

END;

LDAE :=BEGINEXT.ADR.SETUP NEXTR.DATA NEXT

AC[ IR<3 :4 > ],.-MDREND;

DLD:= !FLD alsoBEGIN

LOGICAL.ADR<O:IS>,-(PC<O:IS> + I)<15:0> NEXTREAD. I'IE_IORYNEXTLOG]CAL.ADR<0:I5>,-MDR<0:15> NEXTR.DATA NEXTAC0<0 :15>*-MDR<0:15> NEXT

LOGICAL.ADR<0:15>*-(LOGICAL.ADR<0:15>+I)<15:0> NEXTR.DATA NEXTACt<0 :15>*-MDR<0:15> NEXTINCR2.PC

END;

DLDX:= !FLDX alsoBEGIN

LOGICAL.ADR<0:15>,-(PC<0:15> + i)<15:0> NEXTREAD.MEMORY NEXT

LOGICAL.ADR<0:IS>,-(FIDR<0:15>+ AC2<0:15>)<15:0> NEXTR.DATA NEXTAC0<0 :15>_MDR<0 :15> NEXT

I,O(iICAI,.ADR<0:15>_(I,OGICAL.AI)R<0:15>+I)<IS'0>NEXTR,DATA NEXTAC]<0:IS>,-NDR<0:I5> NEXTINCRZ .PCEND;

62

PRELIMINARY MCFAN/UYK-19 Architecture November 22, 1977

LEF:=BEGINEXT.ADR.SETUP NEXT

AC[ I R( 3 : 4 > ]',-LOGI CAL. ADREND;

LDFNA::BEGIN

LOGICAL.ADR<O:I5>.-(PC<O:I5> + I)<15:0> NEXTREAD. MEt'IORYNEXTLOGICAL.ADR<0:I5>.-IIDR<0:I5> NEXTR.DATA NEXTAC[IR<3:4>]<0:I5>.-NDR<0:15> NEXTINCR2.PCEND;

LDFNX::BEGIN

LOGICAL.ADR<0:I5>.-(PC<0:I5> + I)<15:0> NEXTREAD.MErlORY NEXT

LOGICAL.ADR<0:I5>.-(MDR<0:15> + AC2<0:15>)<15:0> NEXTR.DATA NEXT

AC[IR<3:4>]<0:I5>_MDR<0:15> NEXTINCRZ.PC

END;

LDFNW::BEGINLOGICAL.ADR<0:I5>'-(PC<0:I5> + 1)<15:0> NEXTREAD. MEMORYNEXT

AC[IR<3:4>]<0:15>.-riDR<0:15> NEXTINCR2. PC

END;

_;TA::BEGINSHORT.ADR.SETUP NEXTI_IDR<0:I5>.-AC[IR<3:4>]<0:15> NEXTW. DATA;INCR.PCEND;

,STAE::BEGIN

['II)R,-AC[IR<3:4>];EXT.ADR.SETUP NEXTW. DATA

63

END;

DSI': = ! FST alsoBEGINLOGICAL.ADR<O:]5>,-(PC<0:15> + I)<]5:0> NEXTREAD. NENORYNEXTLOGICAL.AI)R<0:15>,-MDR<0:15> NEXTMDR<0: 15>,-AC0<0 : 15> NEXTW.DATA NEXTLOGICAL.ADR<0 : 15>,-(LOGICAL.ADR<0 : 15>+I)<15:0>;NDR<0: 15>,-AC]<0 : 15> NEXTW.DATA NEXTINCR2 .PCEND;

DSTX:= !FSTX alsoBEGINLOGICAL.ADR<O:I5>,-(PC<O:I5> + i)<15:0> NEXTREAD.NEMORY NEXTLOGICAL.ADR<0:I5>,-(NDR<0:15> + AC2<0:15>)<15:0> NEXTNDR<0:I5>--AC0<0:15> NEXTW.DATA NEXTLOGICAL.ADR<0 : 15>,-(LOGICAL.ADR<0 : 15>+I)<15:0> ;NDR<0:I5>_-ACI<0:15> NEXTW.DATA NEXTINCR2.PCEND;

STTNA : =BEGINLOGICAL.ADR<O:I5>_-(PC<0:15> + i)<15:0> NEXTREAD.MEMORYNEXTLOGICAL.ADR<0:I5>,-MDR<0:15> NEXTNDR<0:lS>,-AC[IR<3:4>]<0:15> NEXTW.DATA NEXTINCR2 .PCEND;

STTNX : =BEGINLOGICAL.ADR<O:IS>_-(PC<O:IS> + I)<15:0> NEXTREAD.NENORY NEXTLOGICAL.ADR<0:I5>_-(MDR<0:15> + AC2<0:15>)<15:0> NEXTMDR<0:I5>'-AC[IR<3:4>]<0:15> NEXTW.DATA NEXTINCR2 .PCEND;

64

DME: =BEGINEXT.ADR.3ETUP NEXTR.DATA NEXT

_IDR.-(_IDR-1)<15:0> NEXTW. DATA

END;

IME:=BEGI NEXT.ADR.gETUP NEXTR.DATA NEXT

MDR.--(MDR+I)<15:0> NEXTW. DATA

END;

XCtlM : "BEGINEXT.ADR.SETUP NEXTR.DATA NEXTTEMPO.-MDR NEXT

MDR,-AC[IR<3:4>] NEXTAC[ IR<3:4> ]_-TEMP0;U. DATA

END;

DSZ : =BEGINSltORT.ADR. SETUP NEXTR.DATA NEXT !READMDR<O:IS>_-(MDR<0:15> - I)<15:0> NEXT !NODIFYU. DATA; !URITE(DECODE (MDR<0:15> EQL O) =>!;Skip one if zero\0 INCR.PC;\I INCR2.PC)END;

ISZ:=DEft IN

• SHORT.ADR.SETUP NEXTR.DATA NEXT !READt'|DR<O:lS>.-(MDR<0:15> + 1)<15:0> NEXT !_IODIFYW.DATA; !WRITE(DECODE (MDR<O:IS> EQL O) =>!Skip one if zero\0 INCR.PC;\1 INCR2.PC)END;

65

PRELIMINARY MCF AN/UYK-19 Archileciure rqovember 22, 1977

43.2 B_3'te manipulation.

LDB: =BEGINABN_IR<I:2> NEXTR.BYTE NEXTAC[ IR<3:4>]'-MDR NEXTINCR.PCEND;

STB :=BEGIN

ABN,--IR< I:2> NEXT

MDR,-AC[IR<3:4>] NEXTW.BYTE NEXTINCR.PC

END;

IBA:=BEGIN

BYTE.ADR<O" 16>,-((O@AC[IR<3:4>]<0:15>)+I)<16"0> NEXTAC[ IR<3:4>]<0:15>_BYTE.ADR<1:16>;(IF BYTE.ADR<O> => BR[IR<4>]<O>,-NOTBR[IR<4>]<O>) NEXTINCR.PC

END;

RBR:=BEGIN

AC[ IR<3:4>]'-BR[IR<2>] NEXTINCR .PC

END;

UBR: :BEGINBR[IR<2>]_AC[IR<3:4>] NEXTINCR,PCEND;

CONB:=BEGININCR.PC

END;

COMBT:=BEGININCR.PCEND;

66

PRELIMINARY MCF AN/UYK-19 Archileciure November 22, 1977

I_IOVB : =BEGININCR.PCEND;

MOVBT: =BEGININCR .PC

END;

_;RCB:=BEG ININCR.PC

END ;

_RCBT:=BEGININCR.PCEND;

43.3 Bit manipulation.

LDF:=BEG ININCR.PC

END;

STF :=BEGININCR.PCEND;

BTO:=BEG ININCR.PCEND;

BTZ :=BEG ININCR.PC

END;

8ZB:=BEGININCR.PC

67

PRELIMINARY MCF AN/UYK-]9 Archilecture November 22, ] 977

END;

SZBO: =BEGININCR.PC

END;

COB :=BEGININCR.PC

END;

43.4 File processing.

FS:=BEG IN

LOGICAL.ADR<0:I5>,--(PC<0:I5> + i)<15:0> NEXTREAD.MENORY NEXT

TEHP0<0 :15>,"NDR<0:15>;TEMPI<0 :15>'AC2<0 :15> NEXT

FSI.OOP:= BEGIN

(IF (AC3<0:15> EQL TEMPI<0:15>)=>BEGININCR2.PC NEXTBAILOUT INPUT.OUTPUT

END) NEXT

TEMPI<O:]5>"(TENPI<O:IS> + I)<15:0>.NEXTLOGICAL .ADR<0:15>'-TENPl<0:]5> NEXTR.DATA NEXTNDR<0:I5>,-NDR<0:]5> AND TEMP0<0:15> NEXT

(IF (ACO<O:15> LEQ NDR<0:15>) AND(NDR<0:15> LEQ AC1<0:15>)=>

BEGINPC<O:I5>.-(PC<0:15> + 3)<15:0> NEXTBAILOUT INPUT.OUTPUTEND) NEXT

ACZ<O:I5>_TEHPI<0:15> NEXTFSLOOPEND

END;

LKLS:=BEGI N

INCRg.PC;INCR.PC

END;

68

PRELIM]NARY MCF AN/UYK-19 Archilecture November 22, ] 977

BA_I: =BEOININCR.PC

END;

ZAi' : =BEGININCR. PC

END;

ABD:=BEGIN1NCR.PCEND;

ATD:=BEGININCR.PCEND;

RBD::BEGININCR.PCEND;

RTD::BEGININCR.PCEND;

43.5 Fixed point arithmetic.

ADD : =BEGINCARRY.SETUP NEXT !Take care of the Carry bit.TEMPO<O: 15>_AC[ IR< 1:2>]<0:15>;TEMPI<O:I5>_AC[IR<3:4>]<O:15> NEXTTNP.FCTN.OPT<O:I6>_TENPO<0:15> + TENPI<O:15> NEXT(IF (TENPO<O> EQL TENPI<O>) AND

(TENPO<O> NEQ TNP.FCTN.OPT)=>OVF_I); !Take care of OVerFlow

(1)ECODE TMP.FCTN.OPT<O> =) !Take care of tile Carry bit.\0 TRIP.FCTN.OPT<O>_CARRY;\1 TMP.FCTN.OPT<O>_ NOT (CARRY)) NEXTSHIFT NEXTNOLOAD.LOAD NEXT

69

PRELIMINARY MCF AN/UYK-19 Architeclure November 22, ]977

SKIP

END;

ADC::BEG 1NCARRY.SETUP NEXT !Take care of the Carry bit.TEMP0<0 :15>_AC[ IR<I:2>]<0:15>;TEMP1<0:15>_AC[IR<3:4>]<0:15> NEXTTMP.FCTN.OPT<0:I6>_NOT(TE_IP0<0:15>) + TEMPI<0:15> NEXT

(IF (TEMP0<0> NEQ TEIIPI<0>)AND(TEMP0<0> EQL TMP.FCTN.OPT)=>

OVF-I); !Take care or OVerFlow

(DECODE TMP..FCTN.OPT<0> => !Take care of the Carry bit.\0 TRIP.FCTN.OPT<0>,--CARRY;\I TMP.FCTN.OPT<0>_ NOT(CARRY)) NEXTSHIFT NEXTNOLOAD. LOAD NEXTSKIP

END;

ADNI::BEGIN

AC2<O:I5>*((AC2<0:15> + IR<I0:I5>) MINUS '1000000)<15:0> NEXTINCR.PC

END;

ADI'I::BEGINACZ<0"IS>*(AC2<0:15> + IR<I0:15>)<15:0> NEXTINCR.PC

END;

DAD :=BEGINLOGICAI..ADR<0:I5>_(PC<0:15> + 1)<15:0> NEXTREAD. r,lEriORY NEXTLOGICAL .ADR<0 : 15>,--I_lDR<0: 15> NEXTTMPDOUBLEREG<0:32>,-0 NEXT !MB25 7/9/77R.DATA NEXT

TMPDOUBLEREG<0:16>,--(MDR<0:lS> + AC0<0:15>)<15:0>;LOGICAL.ADR<0:lS>,,-(LOGICAL.ADR<0:15> + 1)<15:0> NEXTR.DATA NEXTT_IPDOUBLEREG<0:3Z>,-(ACI<0 : ] 5> +

_lDR<0:15> + TMPDOUBLEREG<0:32>)<32:0> NEXT• AC0<0:15>.-TIiPDOUBLEREG<1:16>;

ACI<0 : 15>,--TI_IPDOUBLEREG<17:32> NEXTINCRZ.PC

70

END;

DADX: =BEGI NLOBICAL.ADR<0:I5>,-(PC<0:I5> + I)<15:0> NEXTREAD. MEMORYNEXTLOGICAL.ADR<0:15>,-(NDR<0:15> + AC2<0:15>)<15:0> NEXTTMPDOUBLEREG<0:32>,-0 NEXT !HB25 7/9/77R.DATA NEXTTHPDOUBLEREG<0:16>,-(I_IDR<0:15> + AC0<0:15>)<15:0>;LOGICAL.ADR<0:I5>,-(LOGICAL.ADR<0:I5> + I)<15:0> NEXTR.DATA NEXTTFIPDOUBLEREG<0:32>,-(ACI<0: 15> +

MDR<0:15> + THPDOUBLEREG<0:32>)<32:0> NEXTAC0<0: 15>,-THPDOUBLEREG<1:16>;AC]<0:lS>,-TMPDOUBLEREG<17:32> NEXTINCR2 .PCEND;

ADFNA : =BEGINLOGICAL.ADR<O:15>,-(PC<O:15> + i)<15:0> NEXTREAD.MEMORYNEXTLOfilCAL.ADR<0:I5>_-MDR<0:15> NEXTR.DATA NEXTTEMP1<0:I5>,-AC[IR<3:4>]<0:15> NEXT(IF (TEMPI<0> EQL HDR<0>) AND

(MDR<0> NEQ (HDR<0:I5> + TEMPl<0:15>)<15>) =>OVF.-I ) ;

AC[IR<3:4>]<O:15>.-(HDR<O:lS> + TEHPl<0:15>)<15:0> NEXTINCR2.PC

END;

ADFNX:=BEGINLOGICAI..ADR<O:I5>,-(PC<0:15> + I)<15:0> NEXT

• READ.l_IEt'lORYNEXTLOGICAL.ADR<0:I5>,-(NDR<0:15> + AC2<0:15>)<15:0> NEXTR.DATA NEXTTENP]<0:I5>,-AC[IR<3:4>]<0:15> NEXT(IF (TEMPI<0> EQL MDR<0>) AND

(HDR<0> NEQ (NDR<0:15> + TENPI<0"I5>)<15>) :>OVF,-I );

AC[IR<3"4>]<0"I5>_-(t'IDR<0:IS> + TENPI<0'15>)<15"0> NEXTINCR2.PCEND;

71

PRELIMINARY MCFAN/UYK-19 Architecture November 22, 1977

ADFNW: =BEGINLOGICAL.ADR<O:15>,-(PC<O:15> + 1)<15:0> NEXTREAD. [iEr'iORY NEXTTENPI<O:I5>_AC[IR<3:4>]<O:I5> NEXT(IF (TEMPI<O> EQL MDR<O>) AND

(MDR<O> NEQ (MDR<0:15> + TEMPI<0:15>)<15>) =>OVF_I );

AC[IR<3:4>]<O:I5>_(MDR<O:I5> + TEMPI<O:IS>)<15:O> NEXTINCR2. PCEND;

ADTNA :=BEGIN

LOGICAL.ADR<O:IS>_(PC<0:15> + 1)<15:0> NEXTREAD. MEMORY NEXTLOGICAL .ADR<O:15>_MDR<O :15> NEXTR.DATA NEXT

TEMPI<O:I5>_AC[IR<3:4>]<O:I5> NEXT(IF (TEMPI<O> EQL MDR<O>) AND

(MDR<O> NEQ (MDR<O:15> + TEMPI<O:I5>)<15>) =>OVF_I ) ;

MDR<O:I5>_(TEMPI<O:IS>+_IBR<0:15>)<15:0> NEXTW.DATA NEXTINCRZ.PC

END ;

ADTNX :=BEGIN

LOGICAL.ADR<O:I5>_(PC<O:]5> + 1)<15:0> NEXTREAD. MEMORY NEXT

LOGICAL.ADR<O:15>_(_IDR<0:15> + AC2<0:15>)<15:0> NEXTR.DATA NEXT

TEMP1<O:IS>_AC[IR<3:4>]<0:15> NEXT(IF (TEMPI<O> EQL _IDR<O>)AND

(MDR<O> NEQ (MDR<0:15> + TE_IPI<O:15>)<15>) =>OVF_ 1 ) ;

MDR<O:I5>_(TE[IPI<O:I5>+MDR<O:I5>)<15:0> NEXTW.DATA NEXTINCR2 .PC

END;

SUB:=BEGINCARRY.SETUP NEXT !Take care of the Carry bit.TEMPO<O: 15>_AC[ IR<1:2>]<0:15>;TEMPI<O:I5>_AC[IR<3:4>]<0:15> NEXT

72

TMP.FCTN.OPT<O'16>4-(TI'MP]<O'15> +(NOT(TEP1PO<O'15>) + 1))<]6"0> NEXT

(IF (TE_IPO<O> NEQ TE_IPI<O>) AN[)(TEMPO<O> EQL TIqP.FCTN.OPT)=>

OVF*-I); !Take care of OVerFlow(DECODE TMP.FCTN.OPT<O> => !Take care of Carry bit.\0 THP. FCTN.OPT<0 >,-CARRY;\1 TMP.FCTN.OPT<O>_- NOT (CARRY)) NEXTSHIFT NEXT

NOLOAD.LOAD NEXTSKIP

END;

SBFNA:=BEGINLOGICAL.ADR<O'15>*-(PC<O'15> + 1)<15-0> NEXTREAl). NEIqORYNEXTLOGICAL.ADR<O:IS>*FIDR<O:IS> NEXTR.DATA NEXTTEMPl<O-15>,-AC[IR<3"4>]<0"15> NEXT(IF (NDR<O> NEQ TEHPI<O>) AND

(lqDR<O> EQL (TEMPI<O:15> - fqDR<O'15>)<lS:0>) =>OVF*-] ) ;

AC[IR<3:4>]<O:15>*-(TEf'iPI<O'IS> - MDR<O'15>)<15"O> NEXTINCR2.PC

END;

8BFNX:=BEGI NLOGICAL.ADR<0-15>,-(PC<0"15> + 1)<15-0> NEXTREAD. t,IEIqORY NEXTLOGICAL.ADR<0:15>,--(MDR<0:15> + AC2<0-15>)<15"0> NEXTR.DATA NEXTTEMPl<0"15>*-AC[IR<3"4>]<0:15> NEXT

(IF (MDR<O> NEQ TEMPI<O>) AND(t'IDR<0> EQL (TEFIPI<0"IS> - IqDR<0"15>)<15:0>) =>

OVF,-1 );AC[IR<3-4>](O:15>*--(TEt'IPI<O:15> - _lDR<O:15>)<15"O> NEXTINCR2.PCEND;

SBFNW:=BEGINLOGICAL.ADR<0"IS>*-(PC<0:I5> + i)<15:0> NEXTREAD. PIEPIORYNEXTTEMPI<0:IS>¢-AC[IR<3:4>]<0:I5> NEXT

( I V (I_IDR<0 > NEQ TElqP1< 0 >) AND\

73

PRELIMINARY MCF AN/UYK-]9 Archilecture November 22, 1977

(MDR<0> EQL (TEMP1<0:15> - MDR<0:15>)<]5:0>) =>OVF_I );

AC[IR<3:4>]<0:I5>-(TEMPI<0:I5> - MDR<0:15>)<15:0> NEXTINCR2 .PC

END ;

DEC:=BEGIN

AC[IR<3:4>]<O:IS>.-(AC[IR<3:4>]<O:I5> - I)<15:0> NEXTINCR2 .PC

END;

INC:=BEGINCARRY.SETUP NEXT !Take care of the Carry bit.TEMP0<0:i5>_AC[IR<I:2>]<0:15> NEXTTrIP.FCTN.OPT<0:16>_TEMP0<0:15>+I NEXT

(IF (TEMP0<0:]5> EQL 77777)=> !Will allOVerFlow occur?OVF_I );

(DECODE TMP.FCTN.OPT<0) :> !Take care of the Carry b_t.\0 TRIP.FCTN.OPT<0>_CARRY;\1 TriP.FCTN.OPT<0>_ NOT (CARRY)) NEXTSH IFT NEXTNOLOAD. LOAD NEXTSKIP

END;

NEG::BEGINCARRY.SETUP NEXT !Take care of the Carry bit.

TE_IP0<0:15)_AC[ IR<I:2>]<0:]5> NEXTTMP.FCTN.OPT<0:]6>-NOT(TEMP0<0:]5>) + 1 NEXT(IF (TEMP0<0:I5> EQL 'I000000000000000)=> !OVERFLOW?

OVF_I ) ;(DECODE TMP.FCTN.OPT<0> => !Take care of the Carry bit\0 TRIP.FCTN .OPT<0>_CARRY;\I TrlP.FCTN.OPT<0>_ NOT (CARRY)) NEXTSHIFT NEXTNOLOAD. LOAD NEXTSKIP

END;

DNA :=BEGINLOGICAL.ADR<0:15)_(PC<0:15> + i)<15:0> NEXTREAD.NEMORY NEXTLOGICAL.ADR<0 :15>_MDR<0:15> NEXT

74

PRELIMINARY MCF AN/UYK-19 Arct_ileclure November 22, ]977

R.DATA NEXTTMI'DOUBLEREG<0:32>'-NOT(AC0(0:]5>@ACl<0:15>)<3]:0> • 1<31:0> NEXTTNPDOUBLEREG<O:IO>,-(TNPDOUBLEREfi<O:16> + MDR<O:15>)<16:0> NEXTI,OGICAL.ADR(O:lS>.-(LOGlCAL.ADR(0:15> + 1)<15:0> NEXTR.DATA NEXT

TNPDOUBLEREG<O:32>_-(NDR<O:15> + TNPDOUBLERE(i<O:3Z>)<3Z:O> NEXTACO<O : 15 >.-TI'IPDOUBLEREG< 1 : 16> ;

ACl<O:15>.-T_lPDOUBLERE6<17:32> NEXTINCR2.PC

END;

DNAX :=

BErlIN

LOGICAL.ADR<O:IS>.-(PC<O:15> + I)<15:0> NEXTREAD. MEMORY NEXT

LOGICAI..ADR<0:15>,--(MDR<0:15> + ACZ<0:15>)<15:0> NEXTR.DATA NEXT

Tr'IPDOUBLEREG<0:32>_-NOT(AC0<0:15>@ACl<0:15>)<31:0> + 1<31:0> NEXT

TMPDOUBLEREG<0:lf>,-(TI_IPDOUBLEREfi<0:16> + r'IDR<0:15>)<16:0> NEXTLOGICAL.ADR<0:15>,-(LOGICAL.ADR<0:15> + 1)<15:0> NEXTR.DATA NEXT

Tr,lPDOUBLEREG<0:32>,-(I'IDR<0:15> + Tl_IPDOUBLEREG<0:32>)<32:0> NEXTAC0< 0 : 15 >,-TMPDOUBLEREG< 1 : 16> ;ACI<0:15>*-TI_IPDOUBLEREfi<17:3Z> NEXTINCRZ.PC

END;

SDVD :=

BEGIN

TMPDOUBLEREG< I:3Z>,-ACO<O :15>OACI<O :15>;

TEMPI<O:I5>_AC[IR<3:4>]<O:IS> NEXT

TMPOSIfN<O>,-TNPDOUBLEREG XOR TENPI<O>;

TMPISIGN<O>,-TNPDOUBLEREG NEXT

(IF TNPDOUBLEREG EQL I=>TMPDOUBLEREG<I:32>,-(NINU8 TMPDOUBLEREfi<I:3Z>)<31:O>);

(IF TEPIPI<O> EQL I=>TENPI<O:IS>,-(NINUS TENPI<0:15>)<15:0>) NEXT

(DECODE (TENPI<O:I5> EQL O) OR

(TENPI<O:I5> LS8 TI.IPDOUBLERE6<I:16>) =>

\0 BEGINTENPO<O:lS>.-(TNPDOUBLERE6<l:32> / TEMPl<O:15>)<15:0> NEXT

TEMPl<0:15>,-(TNPDOUBLEREG<l:32> NINUS(TENPO<O:IS> _ TENPl<O:15>)<31:O>)<15:0> NEXT

(IF TNPOSIfN<O> EQL 1=>TENPO<O:15>.-(I'IlNUS TEI_IP0<0:15>)<15:0>);

(IF TFIPlSIGN<O> EQL 1=>TEMPl<O:15>,-(NINUS TEMPI<O:15>)<15:0>) NEXT

75

PRELIMINARY MCF AN/UYK-19 Ar(hilecture Noveml)er 22, ]977

Ag0<0:15 >,,-.TEI_IP1< 0 : 15>;

ACI<O :J5>.-TENPO<O :15>;CARRY,-0

END;

\I BEGINOVF,-1 ;CARRY,.-1END ) NEXT

INCR.PC

END;

UDVD : =BEGI N

TNPDOUBLEREG<I:3Z>.-AC0<0: 15>@ACI<0: 15>;TEMPI<0:I5>,-AC[IR<3:4>]<0:15> NEXT(DECODE (TEMPI<O:15> EQL O) OR

(TENPl<0:15> LSS I'NPDOUBLEREG<I:16>) =>

\0 BEGIN

TENPO<O:lS>.-(TNPI-IOUBLEREG<l:32> / I'ENPl<0:15>)<15:0> NEXTTENPl<O:15>'-(TNPDOUBLEREG<li3Z> I_IINU8

(TEMPO<0:15> _ TEMPI<O:15>)<31:O>)<15:0> NEXTACO<O : 15>,-TENP 1<0:15>;

ACI<O : 15>.--TENPO<O : 15>;CARRY,-0

END;\i BEGIN

OVF,--I ;CARRY.-I

END) NEXTINCR.PC

END ;

UDVI :=

BEGIN

TMPDOUBLEREG< 1:16>_ACI<O :15>;

TEMPI<O:I5>_-AC[IR<3:4>]<0:15> NEXT

(DECODE (TENPI<0:15> EQL 0)=> !OVERFLOW?

\0 BEGINTEMPO<O:15>_-(TNPDOUBLEREG<I:16> / TEl'IPl<0:15>)<15:0> NEXTTENPl<O:15>,-(TI_IPDOUBLEREG<l:16> MINUS

CTEMPO<O:15> _ TENPI<O:15>)<31:O>)<15:0> NEXT

AC0<0 : 15>.-TEMP I<0 : 15>;ACI<O : I5>.-TENPO<0 :15>;CARRY,-0

END;

\1 BEGINOVF.- 1 ;

76

PRELIMINARY MCF AN/UYK-]9 Archilec:lure November 22, ] 977

CARRY.-1

END) NEXTINCR.PC

END;

SMI'Y : =BEGIN

TEMP0<0 : 15>'-ACI<0 : 15> ;TEMPl<0:15>'-AC[IR<3:4>]<0:15> NEXTTMPOSIGN<0>*-TEMP0<0> XOR TEMPI<0> NEXT

(IF TEMP0<0> EQL 1=>TENP0<0:15>*-(MINUS TEMt'0<0:15>)<15:0>);

(IF TEMPI<0> EQL l=>TEMPI<0:15>*-(MINUS TEMPI<0:15>)<15:0>) NEXT

TMPDOUBLEREG<1:32>*-TEMP0<0:lS> * TEMPl<0:15> NEXT

(IF TMI'0S1GN<0> EQL 1=>TMPDOUBLEREG<l'32>,-(MINUS TNPDOUBLEREG<l:32>)<31:0>) NEXT

AC0<0 : 15>'-TMPDOUBLEREG<1 : 16>;ACl<0:15>"-TMPDOUBLERE6<17:32> NEXTINCR.PC

END;

UMPY: =BEGIN

TNPDOUBLEREG<I"3Z>"AC[ IR<3:4>]<0:15> * ACI<0:15> NEXTAC0<0 : 15>'-THPDOUBLEREG;ACI<0 : 15>'-TMPDOUBLEREG<17:32> NEXTINCR.PC

END;

UMPA: -BEGIN

TMPDOUBLERE6<1 : 3Z>.--( (AC[ IR<3:4>]<0 : 15> *AC1<0:15>)<31:0> + AC0<0:15>)<31:0> NEXT

AC0< 0 : 15 >,-TMPDOUBLEREG<i: 16>;ACI<O:IS>,-TMPDOUBLEREG<17:32> NEXTINCR.PCEND;

TCO:=BEGIN(DECODE OVF=>\0 PC<O:15>*'(PC<0:15> + 2)<15:0>;\ i BEGIN

OVF..-O;INCR.PCEND)

77

END;

5SG E : =BEG I N

(IF AC[IR<I:2>] GEQ AC[]R<3:4>] => INCR.PC);INCR.PC o

END;

SSGT: =

BEGIN

(IF AC[IR<I:2>] GTR AC[IR<3:4>] => INCR.PC);INCR.PC

END;

43.6 Enhanced Floating Point Instructions.

43.6.1 Memory. Reference.

• FLDS : =BEG I NINCR2. PCEND;

FLDD : =BEGI NINCR2. PC

END;

FSTS:=BEGI NINCR2.PC

END;

FSTD::BEGININCRE.PCEND;

FPSH:=BEGININCR2.PC

END;

FPOP : =

78


BEGININCR. PC

END;

43.6.2 Data Manipulation.

FCI.R:=BEGI NINCR.PCEND;

FNORFI: =BEGI NINCR.PCEND;

FLO_;: =BEflNINCR.PC

END;

FLOD : =BEGININCR.PC

END;

FIX$::BErliN

INCR.PCEND;

FIXD:=BEG ININCR.PC

END;

FINT$ : :BEGININCR.PCEND;

FINTD:=BEGININCR.PCEND;

79


FXCH:=BEGIN]NCR.PC

END;

FNOVO:=BEGININCR.PCEND;

FMOVI:=BEGININCR.PC

END;

FREXP:=BEGININCR.PC

END;

FRST :=BEGININCR.PC

END;

FSCAL:=BEGININCR.PC

END;

FWEXP:=BEGININCR.PC

END;

FWST:=BEGININCR.PC

END;

43.6.3 Arithmetic.

FABS:=BEGININCR.PCEND;

80

PRELIMINARY MCF AN/UYK-19 Architeclure November 22, ] 977

FAI)DO : =BEGININCR.PC

END;

FADD 1 : =BEGININCR.PC

END;

FABS : =BEGININCR2.PC

END;

FAN [I : =

BEGININCR2.PC

END;

FSDO : =BEGIN

INCR.PC

END;

FSDI : =

BEGININCR.PC

END;

FSrI,S : =

BEGININCRg .PC

END;

FSND : =BEGININCR2 .PC

END;

FMSO : :BEG l NINCR.PC

END;

FNS l : =BEGIN

81

PRELIMINARY MCF AN/UYK-19 Arcililecture November 22, t977

INCR.PCEND;

FMi)O: =BEGININCR.PC

END;

FMD1 :=BEGININCR.PC

END;

FM_IS:=BEG ]NINCR2.PC

END;

FMI'ID:=BEG ININCR2 .PCEND;

FDSO:=BEGININCR.PC

END;

FDSI:=BEGININCR.PC

END;

FDDO :=BEGININCR.PCEND;

FDDI:=BEGIN]NCR.PC

END;

FDM8:=BEGININCR2.PCEND;

82

PRELIMINARY MCF AN/UYK-J9 Archilecture Novembe, 22, 1977

FDMD: =BEGIN

" INCR2. PC

END;

FHLV:=BEGININCR.PC

END;

FINC:=BEG I NINCR.PC

END;

FINVS: =BEGININCR.PCEND;

FINVD :=BEGININCR.PC

END;

FNEG :=

BEGININCR.PC

END;

FSQRS :=BEGININCR.PCEND;

FSQRD:=BEGININCR.PC

END;

43.6.4 Test.

FCNP : =BEGININCR.PCEND;

83

PRELIMINARY MCFAN/UYK-19 Archilecture November 22, ]977

FSNER:=BEGININCR.PC

END;

FSER:=BEGI NINCR.PC

END;

FSEQ:--BE61NINCR.PC

END;

FSGE : -BEGININCR.PC

END;

FSGT:=BEGININCR.PCEND;

FSI.E:=BEGININCR.PC

END;

FSLT:=BEGININCR.PC

END ;

FSNE:=BEGININCR.PC

END;

FTST:=BEGININCR.PC

END;

84

PRELIMINARY MCF AN/UYK-19 Arch_leclure November 22, 1977

43.6.5 Control.

FCLE:=BEGININCR.PC

END;

FDTRP : =BEGININCR.PC

END;

FETRP : =BEGININCR.PC

END;

FSET3:=BEGININCR.PC

END;

FSET4 :=BEGININCR .PC

END;

43.6.6 Diagnostic.

RNADR: =BEGININCR.PCEND;

43.7 General Register Floatin9 Point Instructions.

FLO:=BEGINNOP; !not implementedFP.SKIP NEXTINCR.PCEND;

FIX:=

85

PRELIMINARY MCF AN/UYK-19 Architecture rqovember 2'2, ]977

BEGINFP.SKIP NEXTINCR.PC

END;

FNI_I::BEGINFP.SKIP NEXTINCR.PCEND ;

FAD :=BEGINFP.OP.SETUP NEXT

TMPDOUBI,EREG<O:32>,-(TDl<0:31> + ACO<O'IS>@ACI<O'15>)<32:0> NEXTACO< 0 :15>,,-TMPDOUBLEREG<I:16>;AC]<O :]5>,--TMPDOUBLEREG<17:3Z> NEXTFP.SKIP NEXTINCR.PCEND;

FSB:=BEG INFP.OP.SETUP NEXTTI_IPDOUBLEREG<O'32>,--(ACO<O'15>@ACI<0"15>MINUS TD1<0:31>)<32"0> NEXTACO<O :15)*--TMPDOUBLEREG<I:16);ACl<O:I5).--TMPDOUBLEREG<I7:3Z> NEXTFP.SKIP NEXTINCR.PCEND;

FMP:=

BEGINFP.OP.SETUP NEXTTDO<0:3I> ,--ACO<O:I5>@ACI<0:15> NEXTSIGN ,--TDO<O> XOR TDI<O) NEXT

(IF TDO<O> =) TDO<0:31) ,--(I'IINUSTD0<0:31))<31:0));(IF TDI<O) =) TD]<0:31)_ (I'IINUSTDI<0:31))<31:0)) NEXTTI'IPDOUBLEREG<0:32),--((TDO * TDI) tSRO 16)<31:0) NEXT(IF SIGN =) TFIPDOUBLEREG<0:32> ,,-(MINUS TI'IPDOUBLEREG)<31"O>) NEXTACO<O :15),,-TfiPDOUBLEREG<I:16);ACI<O :15>',-TMPDOUBLEREG<17:32) NEXTFP.SKIP NEXTINCR.PC

END;

FDV: =

86

PREL|M]NARY MCF AN/UYK-19 Architecture November 22, 1977

BEGI NFP.OP.SETUP NEXT

(IF TD1(0:31> EQL 0 =>BEGIN !divide by 0OVF,--1 ;INCR.PC NEXTBAILOUT INPUT.OUTPUT

END) NEXTTDO<0:31>,- ACO<O:15>@ACI<O:IS> NEXTSIGN ,- TDO<O> XOR TDI<O> NEXT

(IF TDO<O> => TDO ,- (_IINU.S TDO<0-31>)<31"O>);(IF TDI<O> => TDI ,- (_IINU8 TDl<0.31>)<31:O>) NEXTT_IPDOUBLEREG ,- ((TDO@O<15:0>) / TD1)<31:O> NEXT(IF SIGN => TMPDOUBLEREG*- (MINUS TMPDOUBLEREG<l'32>)<31"O>) NEXTACO<O: 15>,-TMPDOUBLEREG;ACI<O : 15>,-TMPDOUBLEREG<lT:32> NEXTFP.SKIP NEXTINCR.PC

END;

43.8 Lc__q9ical Instructions.

ANDD:=BEGINCARRY.SETUP NEXT !Take care of the Carry bit.

TMP.FCTN.OPT<O" ]6>_CARRY@(AC[ IR<I'2>]<O' ]5> ANDAC[IR<3:4>]<O:IS>) NEXT

5H IFT NEXTNOLOAD. LOAD NEXTSKIP

END;

ANFNA:=BEGINLOGICAL.ADR<O:IS>_(PC<O:]5> + I)<15:0> NEXTREAD. MEMORYNEXTLOGICAL.ADR<O:i5>_HDR<0:15> NEXTR. DATA NF.XT

AC[IR<3"4>]<O:15>_AC[IR<3:4>]<0:15> AND MDR<0:15> NEXI"INCR2.PC

END;

ANI'NX:=BEGIN

LOGICAL.ADR<O:15>_(PC<O:IS> + i)<15:0> NEXT

87

REAI).NENORY NEXT

LOGICAL.ADR<0 : 15>_(NDR<0: 15> + AC2<0 : 15))<15:0> NEXTIt. DATA NEXTAC[IR<3:4>]<0:I5>_AC[IR<3:4>]<0:15> AND NDR<0:15> NEXTINCR2.PCEND;

ANFNU : :BEGINLOGICAL.ADR<O:,I5>,-(PC<0:15> + I)<15:0> NEXTREAD. MEMORYNEXTAC[IR<3:4>]<0:I5>_AC[IR<3:4>]<0:15> AND MDR<0:15) NEXTINCR2.PCEND;

ANTNA : =BEGINLOGICAL.ADR<O:I5>,-(PC<0:15> + I)<15:0> NEXTREAD. MEMORYNEXTLOGICAL.ADR<0 : 15)_MDR<0: I5> NEXTR.DATA NEXTMDR<0:I5>_AC[IR<3:4>]<0:15> AND MDR<0:15> NEXTW.DATA NEXTINCR2.PC

END;

ANTNX : :BEGIN

LOGICAL.ADR<O:I5>_-(PC<0:15> + I)<15:0> NEXTREAD. MEMORYNEXTLOGICAL.ADR<0:I5>-(MDR<0:15> + AC2<0:15>)<15:0> NEXTR.DATA NEXTHDR<0:I5>_AC[IR<3:4>]<0:15> AND NDR<0:15> NEXTW.DATA NEXTINCR2.PCEND;

CON: =BE6IN

CARRY.SETUP NEXT !Take care of the Carry bit.T_IP.FCTN.OPT<0:I6>_CARRY@NOT(AC[IR<I:2>]<0:I5>) NEXTSHI FT NEXTNOLOAD.LOAD NEXTSKIPEND;

IOR:=

88

BEGIN

AC[IR<3"4>]<0"I5>,-AC[IR<3:4>]<0:15> OR AC0<0"15> NEXTINCR.PC

END;

XXOR ::BEGIN

AC[IR<3:4>]<0:I5>,-AC[IR<3:4>]<0:15> XOR AC0<0:I5> NEXTINCR.PC

END;

XCH: :BEGIN

TENP0,-AC[IR] NEXTAC[IR<I:2)],--AC[IR<3:4)]NEXTAC[IR<3:4>],-TEMP0 NEXTINCR.PC

END;

MOV:=BEGINCARRY.gETUP NEXT !Take care of the Carry bit.TNP.FCTN.OPT<0:I6>*-CARRY@AC[IR<I:2>]<0:15> NEXTSHIFT NEXTNOLOAD. LOAD NEXTSKIPEND;

N6 TNA :=BEGIN

LOGICAL.ADR<0"I5>*'(PC<0:15) + I)<15:0> NEXTREAD.NEMORY NEXTLOG ICAL.ADR<0 :15>,--MDR<0:15> NEXTR.DATA NEXTTEMPI<0 :15>"ACj<0 :15> NEXTMDR<0:I5>*-(TENPI<0:15> AND AC[IR<3:4>]<0:I5>) OR

(NDR<0:15> AND NOT(TEIiPI<0:15>)) NEXTW.DATA NEXTINCR2 .PC

END;

figTNX :=BEGIN

LOGICAL.ADR<0:I5>,--(PC<0:15>+ I)<15:0> NEXTREAD. MEMORYNEXT

LOGICAL.ADR<O:15).-(MDR<0:15> . AC2<0:15))<15:0) NEXTR.DATA NEXT

89

PREL]M|NARY MCFAN/U't'K-19 Architeclure r',lovember 22, 1977

TEr'lPl<O:15>.-ACl<O:l.5> NEXT

r'IDR<O:15>.-(TEMPl<O:lS> AND AC[IR<3:4>]<O:IS>) OR(MDR<O:15> AND NOT(TEl_IPl<0:15>)) NEXT

W.DATA NEXTINCRZ.PCEND;

,43.9 Shift Instructions.

LASH :=BEGINTENP0<0 : 15>,-AC0<0 : 15> NEXT

(DECODE ((TENP0<0:15> tSR0(15 - IR<I3:15>))EQL 0)OR(((TEPIP0<0"15> tSR1(15 - IR<13"15>))<15"0> +

1)<15:0> EQL 0) =>.\0 BEGIN

CARRY.-1 ;OVF_IEND;

\1 BEGINTEMPO<O:15>,-TEMPO<O:IS> tSL0 IR<13:15> NEXT

AC0<0 : 15>,-TENP0<0: 15>;CARRY,-0END) NEXT

INCR.PCEND;

RASH :=BEGINTEMPO<O :15>_AC0<0 :15> NEXT

(DECODE TENPO<O>=> !Positive or negative\0 TENPO<O:I5>_TE_IPO<0:15> tSRO IR<13:15>;\I TENPO<O:15>,,-TEI_IPO<O:15> tSR1 IR<13:15>) NEXTACO<O: 15>.--TEI_lPO<O: 15> NEXTINCR.PCEND;

LA,SIID: :BEGINT)IPDOUBLEREG<I:32>_-AC0<0:I5>@ACI<0:15> NEXT

(DECODE ((TNPDOUBLERE6<I:32> _SR0(31 - 1R<13:15>))EQL 0)OR(((TNPDOUBLEREG<I:32> _8RI(31 - IR<13:15>))<31"0> +

1)<31:0> EQL 0)=>\o BEGIN

CARRY_ I;OVF_I

9O

END;

\ 1 BEGINT_IPDOUBLEREG<l:32>-TNPDOUBLEREG<]:32> _SLO 1R<]3:15> NEXTACO<O:15>_-TMPDOUBLEREG< 1 : 16>;ACI<O : 15>,-TNPDOUBLEREG< 17:32> ;CARRY,-O

END) NEXTINCR.PC

END;

RASH D :=

BEGIN

TNPDOUBLEREG<l:B2>,,-ACO<O:15>@ACl<0:15> NEXT

(DECODE TNPDOUBI,EREG=> !Positive or negative\0 TNPDOUBLEREG<l:32>,-TNPDOUBLEREG<l:32> tSRO IR<13:15>;

\l TMPDOUBLEREG(l:32>_TNPDOUBLEREG(l:32> _SRI IR<13'IS>) NEXT

ACO<O: 15>.-TNPDOUBLEREG< 1:16>;ACl<O:15>.--TNPDOUBLEREG<17:32> NEXTINCR.PC

END;

LDSHD:=

BEG IN

TENPl<O:15>,-ACO<O:15> NEXT

ACI<0:I5>,,-TENPI<0:I5> tSL0 IR<lZ:15>;AC0<0:I5>.-TENPI<0:15> tRL IR<12:15> NEXTINCR.PC

END ;

LLSH:=BEGINACO<O:IS>,-ACO<0:15> tSL0 IR<12:15) NEXTINCR .PC

END;

RLSH:=BEGIN

ACO<O:15>*-ACO<O:15> _SRO IR<12:15> NEXTINCR.PC

END;

LLSHD:=

BEGIN

TNI'DOUBLEREG<l:32>,-ACO<O:15>@ACl<0:15> NEXTTMPDOUBLEREG<l:32>_TNPDOUBLEREG<l:32> 1SLO 1R<12:15> NEXT

ACO<O: ]5>_TNPDOUBLEREG< 1: 16>;ACl<O:15>_TNPDOUBLEREG<17:32> NEXT

91

PRELIMINARY MCF, AN/UYK-J9 Architecture November 22, ]977

INCR.PC

END ;

RLSHD:-"BEG IN

TMPDOUBLEREG<l:32>.-ACO<O:lS>@ACl<O:15> NEXTTMPDOUBLEREG<l:3Z>.-TNPDOUBLEREG<l:32> _SRO IR<12:15> NEXT

ACO<O : 15>-TrlPDOUBLEREG< 1 : 16> ;ACI<0 : 15>,-TNPDOUBLERE6<17:32> NEXTINCR.PC

END;

LROT : =BEGIN

AC0<0:I5>_-AC0<0:I5> _RL IR<12:15> NEXT

INCR.PC

END;

43.10 Stack Manipulation Instructions.

STISZ:=BEGINLOGICAL.ADR<O:15>.-$P<0:15> NEXTREAD.MEHORY NEXT

MDR<O:I5>_-(MDR<O:I5> + 1)<15:0> NEXT

WRITE.MEMORY ;

(DECODE (NDR<0:15> EQL 0)=>

\0 INCR.PC;\i INCRZ.PC)END;

POP::BEG I N

POP.STACK NEXT

AC[ IR<3:4>]<0 :15>.-NDR<0 :15> NEXTINCR.PC

END;

POPB ::

BEGIN

SP,-(FP+] )<15:0> NEXTPOP.STACK NEXT

CARRY,-NDR<O> ; OVF_-MDR<1> NEXTPOP.STACK NEXT

ACO _ NDR NEXT

POP.STACK NEXT

92

PRELIMINARY MCFAN/UYK-]9 Architecture November 22, ]977

AC] '- i_ll)R NEXTPOP.STACK NEXTAC2 '- lqDP NEXTPOP. STACK NEXTAC3 ,-- t'll)R NEXTPOP.STACK NEXTSP *- t'IDR NEXTLOGICAL.ADR *-- FP NEXTREAD. PiEriORY NEXT

FP ,-- IqDR;INCR.PC

END;

PRT:-BEGINPOP.STACK NEXTPC<0 : 15>.-HDR<0 : 1,5>

END;

PSi1:=BEGIN

HDR<0:I5>*-AC[IR<3:4>]<0:15> NEXTPUSH. STACK NEXTCIIK.STACK.OVF NEXT]NCR.PC

END;

POS:=BEGIN

IqDR<0:I5>*-(PC<0:]5>+ 2)<15:0> NEXTPUSH. STACK NEXTPC<0:I5>,--(PC+i)<I5:0>NEXTCHK.STACK.OVF NEXTLOGICAL.ADR<0 :15>*-PC<0:15>NEXTREAD. I'IEMORYNEXTPC<0 :15>_HDR<0 :15>

END;

PJSE :=BEGINI_IDR,--(PC+2)<15:0> NEXTPUSH. STACK NEXTEXT.ADR.SETUP NEXTPC,--I.,OGICAL .ADR NEXTCHK. STACK. OVFEND;

o

93

PST:=BEGI NrIDR<O:IS>,-STATUS<O:IS> NEXTPUSH. STACK NEXTINCR. PC NEXTCiIK. STACK. OVF

END;

RTRN : :BEGININCR.PC

END;

SAVE:=BEGININCR2.PC

END;

RSP:=BEGIN

AC[IR<3:4>]<O:15>_SP<0:15> NEXTINCR.PC

END;

WSP:=BEGIN

SP<O:I5>_AC[IR<3:4>]<0:15> NEXTINCR.PC

END;

RFP::BEGIN

AC[IR<3:4>]_FP;INCR.PCEND;

WFP:=BEGIN

FP,-AC[ IR<3:4>];INCR.PC

END;

RSL:=BEGIN

AC[ IR<3:4>],-SL ;INCR.PCEND;

94

PREL]M]NARY MCF AN/UYK-19 Archileclure November 22, ] 9:77

WSL:=BEGIN

SL_AC[ IR<3:4>];INCR.PC

END;

RTFN I:=BEGINCKPRV NEXT

POP.STACK NEXT.LOGICAL.ADR<0:15)_5; INTMSK _ MDR NEXTWRITE .MErIORYNEXTPOP.STACK NEXTPC<O :15)_MDR<O :15)

END;

43.11 I, rogram Flow A]teratJon Instructions.

JMP :=BEGINSIIORT.ADR.SETUP NEXTPC<O :]5>_LOCiICAL.ADR<O:15>

END;

JNi'E:=BEGINEXT.ADR.SETUP NEXTPC_LOG ICAL .ADR

END;

JSR:=BEGINSHORT.ADR.SETUP NEXTAC[3]<O:15>_(PC<O:15> + 1)<15:0> NEXTPC<O : 15>_LOGICAL.ADR<O : 15>

END;

43.12 Resource Management Instructions.

WRNAP:= !Write map fileBEGINCKPRV NEXT

TENI'I .-ACO; TENP2 _ ACI; LOGICAL.ADR _ AC2 NEXT

95

PRELIMINARY MCF AN/UYK- ] 9 Arctlitecture November 22, ] 977

(DECODE TEMPI<6> =>\0 TEMP1 *-- TEI_IPl<13:15>*64 + TENPI<0:5>;

\l BAILOUT WR_IAP) NEXTWRMAPl:=(IF TEMP2 GTR 0 =>

READ. r,1Er,IORY NEXT

MAPREG[TE_IPl<7:IS>] .- NDR NEXTLOGICAL.ADR ,- (LOGICAL.ADR + 1)<15:0> ;

TEMPl ,-- (TEr'IPl + 1)<15:0> ;TEMPE ,- (TEr'IP2 - 1)<15:0> NEXTWRFIAP1 )

END;

RD}iAP := !Read map fileBEGIN

CKPRV NEXT '

TENP1 ,- AC0; TENP2 _- AC1; LOGICAL.ADR ,- ACg NEXT

(DECODE TEMPI<6> =>

\0 TEr'IP1 ,,- TEr_IPl<13:15>*64 + TEMPI<0:5>;\1 BAILOUT RDr'IAP) NEXT

RDI_IAPI:=(IF TEr,IP2 GTR 0 =>r,IDR ,,- NAPREG[TENPl<7:IS>] NEXT_dRITE.I_IEI_IORY NEXT

LOGICAL.ADR ,,- (LOGICAL.ADR + 1)<15:0> ;

TEMPI ,- (TEMPI + 1)<15:0> ;

TEI_IP2 ,- (TENP2 - 1)<15:0> NEXTRDr'lAP ] )

END;

WR}IRD:= !Write single wordBEGINCKPRV NEXTTEr'IP0,-AC0 NEXT

MAPREG[(TEiSlP0<13:15>*64+TEr'IP0<0:5>)<8:0>]<0:15> ',- AC1<0:15>END;

RD_/RD:= !Read _ingle wordBEGINCKPRV NEXTTEr'iP 0,-AC0 NEXT

ACI<0:IS> ,- HAPREG[(TENPO<13:15>*64+TENPO<0:5>)<8:0>]<O:15>END ;

WMSR:: !Write map status registerBEGINCKPRV NEXT

UEM _ AC[IR<3:4>]<2>;MSR<4:15> _ AC[IR<3:4>]<4:15> NEXT

96

MVI_<13:15> _ MSR<I3:I5>END;

RMSR:= !Read map status registerBEGINCKPRV NEXT

AC[IR<3:4>]<0:15> _ MSR<0:15>END;

RMVR:: !Read map violation registerBE61NCKPRV NEXTAC[IR<3:4>]<0:15> ,- NVR<0:I5>END;

CHVR:= !Clear map violation registerBEGINCKPRV NEXTMVR<I:7> _ 0

END;

CDNA:= !Clear DMA violationBEGINCKPRV NEXTMVR<0> _ 0END;

RLAF:: !Read last address fileBEGINCKPRV NEXTNOPEND;

EXMAP:= !Enable executive data mapBEGINCKPRV NEXTXDI_I.- 1

END;

DXFIAP:= !Disable executive data mapBEGINCKPRV NEXTXDr'I .- 0

END;

MAI'SI:= !Flapsingle instructionBEGIN

97

PRELIMINARY MCF AN/UYK-19 Arct_ileclure November 22, ] 977

CKPRV NEXTr,isI ,- 1

END;

MAI'SD:= !Hap single dataBEGINCKPRV NEXTMSD _ 1END;

RMST:= !Read remote memory chassis statusBEGINCKPRV NEXTNOP

END;

UJrlP:= !Executive to user jumpBEGINCKPRV NEXT

XNDC _ O; XND _ 1 ;EM _ UEM ;MVR<I:7> _ 0 ;PC<0:15> * AC[IR<3:4>]<0:IS>END;

EUB:= !Executive to user branchBEGINCKPRV NEXTLOGICAL.ADR<0:15> _ AC0<0:15> NEXTREAD._IENORY NEXTPC<O: ]5> _ MDR<0:15> NEXT

LOGICAL.ADR<0:15> _ (LOGICAL.ADR<0:15> + I)<15:0> NEXTREAD. MEMORY NEXTSP<0:15> _ NDR<0:15> NEXTLOGICAL.ADR<0:15> _ (LOGICAL.ADR<0:15> + I)<15:0> NEXTREAD.MEMORY NEXTMSR<0:15> _ NDR<0:15> NEXT

LOGICAL.ADR<O:I5> ,- (LOGICAL.ADR<0:15> + I)<15:0> NEXTREAD.HEHORY NEXT

SL<0:15> _ NDR<O:I5> NEXT

XFIDC _ 1 ; XDH ,- 0 ; XFID_ 0 NEXTHVR<I:7> ,- 0 NEXTEH ,- UEti

END;

ECALL:= !Executive callBEGIN

98

TRAP.INDEX ,- 1 NEXT,SYSTRAP

END;

TRAP : = !$ystem trapBEG I N

TRAP. INDEX ,- AC[IR<3:4>]<12:15> NEXT,.SYSTRAP

END;

43.13 ]nputlOutput Instruct±ons.

NIO::

BEGIN

CKIO.PROTECT NEXT

NOP ;INCR.PC

END;

DIA:=

BEG IN

CKIO.PROTECT NEXT

INDEV NEXT

•,• INCR.PC

•_. END ;

DIB:=

BEGIN

CKIO.PROTECT NEXT

INDEV NEXT

INCR.PC

END;

DIC'=

BEGIN

CKIO.PROTECT NEXT

INDEV NEXT

INCR.PC

END;

BOA :=

BEGIN

CKIO.PROTECT NEXTOUTDEV NEXT

INCR.PC

END;

- •

PRELIM]NARY MCF AN/UYK-19 Archileclure November 22, ]977

DOB: :BEGINCKIO.PROTECT NEXTOUTDEV NEXTINCR.PC

END;..,.-

DOC:=BEGINCKIO.PROTECT NEXTOUTDEV NEXTINCR.PC

END;

SKI' : =BEGI NCKIO.PROTECT NEXT

NOP;INCR.PC

END;

43.14 rlCF I/O Instructions.

DOAM CF :=BEGINCKIO.PROTECT NEXTINCR.PC

END;

DOBrICF : =BEGINCKIO.PROTECT NEXTINCR. PC

END;

DOCrICF: =BEGINCKIO.PROTECT NEXTINCR.PCEND;

DIAMCF :=BEG INCKPRV NEXTINCR.PC

100 .... : . :...

PRELIMINARY MCF AN/UYK-19 Architeclure Novernl)cr 22, 197: _

ENI);

DI B_,ICF: =BErlINCKIO.PROTECT NEXTINCR.PC

END;

DICMCF:=BEG INCKIO.PROTECT NEXTINCR.PC

END;

43.15 _Status Control Instructions.

INTEN:=BEGINCKIO.PROTECT NEXTION.- l NEXTINCR.PCEND;

INTDS : :BEGINCKIO.PROTECT NEXTION_O NEXTINCR.PCEND;

INTA:=BEGINCKIO.PROTECT NEXTAC[ IR<3:4>]_DEV.NUMBER NEXTCTL77 NEXTINCR.PCEND;

t'hSKO: :BEGINCKIO. PROTECT NEXTINTMSK_AC[IR<3:4>] NEXTCTL77 NEXTINCR.PCEND;

I01

PRELIMINARY MCF AN/UYK-]9 Archileclure November 22, ]977

READS: =BEGINCKIO.PROTECT NEXT

AC[IR(3:4>],-SWITCH NEXTCTL77 NEXTINCR.PC

END;

IORST:=BEGIN

CKIO.PROTECT NEXT]ON,--0NEXTCTL77 NEXTINCR.PCEND;

HALT :=BEG INCKIO.PROTECT NEXTCTL77 NEXTINCR.PC NEXTSTOP

END;

SKPBNCPU :=BEG IN

(IF ION => INCR.PC) NEXTINCR.PC

END;

SKPBZCPU:=BEGIN

(IF NOT ION =5 INCR.PC) NEXTINCR.PCEND;

SKPDNCPU:=BEGIN

(IF POWER.FAIL => INCR.PC) NEXTINCR.PC

END;

SKPDZCPU:=BEGIN

(IF NOT POWER.FAIL => INCR.PC) NEXTINCR.PC

END;

102

PRELIM]NARY MCF AN/UYK-19 Archilecture November 22, ]977

DSPD:=BEGINCKPRV NEXT

CPDATA<O: 15>_ACI<O: 15>;INCR.PCEND;

CLRD::BEGINCKIO.PROTECT NEXTCPDATA<0 : 15>_0 ;INCR.PCEND;

STEM:=BEGINEMil ;INCR.PCEND;

CLEFI:=BEGIN

EM'-O;INCR.PC

END;

ST I BN :=BEGINCKPRV NEXT

IBN.-I;INCR.PC

END;

CLIBN:=BEGINCKPRV NEXT

IBN*-O;INCR.PC

END;

WAI TT ::BEGI NSTOP !wait for interruptEND;

103

PRELIMINARY MCF AN/UYK-19 Archilec|ure November 22, 1977

104

PRELIMINARY MCF AN/UYK-19 Architecture November 22, J977

44. INSTRUCTION DECODE PROCEDURES

J

NOAC.EFFECTIVE.ADDRESS:= !Decode instructions beginning with 000BEGIN(DECODE IR<3:4> => !Decode op-code\00 JMP;\01 JSR;\10 ISZ;\ ] i DSZ)END;

INPUT.OUTPUT:= !Decode instructions beginning with OllBEGIN

(DLCODE IR<5:7> => !blainINPUT.OUTPUT decode\000 BEGIN !NIO Group

(DECODE IR<3:45 =5\00 BEGIN

(IF IR<IO:145 EQL '00000 =>BEGIN

(DECODE IR<IG>@IR<8:9> =>\000 FCLE;\001 FDTRP;\010 FETRP ;\011 FSET4 ;\100 CLEN;\ 101 8TEN;\110 PRT;\111 RTFNI) NEXTBAILOUT INPUT.OUTPUT

END) NEXT(IF IR<I0:14> EQL '11111 =>

BEGIN

, (DECODE 1R<15> =>\0 UNINP; !NCFO\I BEGIN

(DECODE IR<8:9> =>\00 NOP;\OI INTEN;\lO INTD8;\11 CLRD)END) NEXT

BAILOUT INPUT.OUTPUT

END) NEXTNIO !NIO INSTRUCTION

END;\01 BEGIN

(DECODE IR<8:9> =>

I05

\00 ADPI;\01 BEGIN

(DECODE IR<]O:I]> =>

\00 LDStlD;\01 I,I..SHD;\10 BEGIN

(DECODE IR<I2> =>

\0 LASIID;\ l RASHD)END;

\11 RLStiD)END;

\10 BEGIN(DECODE IR<IO:II> =>\00 LROT;\01 LLSH;\10 BEGIN

(DECODE IR<IZ> =>

\0 LASH;\1 RASIi)END;

\ll RLSH)END;

\1 ] ADN I)END;

\10 BEGIN

(DECODE IR<8:9> =>\00 FSTS;\01 FLDS;\10 FSTD;\11 FLDD)END;

\11 BEGIN(DECODE IR<8:9> =>\00 BEGIN

(DECODE IR<IO:I2> =>

\000 FNSO;\001 FDSO;\0 IO FNOVO ;\011 FCNP ;\I00 FtIPO;\lOl FDDO;\110 FADDO; !FAS\l l l FSDO) !FSSEND;

\01 BEGIN(DECODE IR<IO:I2> =>

106

\000 FI_IS1;\OOl FDSI;

• \ 010 FI_IOV] ;\011 FXCtl;\lO0 FNDI;\101 FDDI ;\110 FADDI ; !FAS\111 FSDI) !FSSEND;

\I0 BEGIN' (DECODE IR<13:15> =>

\000 FMMS;

\OOl FDN8;\010 FAM8;lOll FSNS;\100 FI_IID;\ ] 01 FDI_ID;\ l l 0 FAND;\111 FSMD)END;

\11 BEGIN(DECODE IR<I0:12> =>

\000 FNEG;\001 FCLR;\010 FINVS;\011 BEGIN

(DECODE IR<13:15> =>\000 FABS;\O01 FRE×P;\0I0 FNOR_I;\011 FSQRS;\I00 FLOS;\I01 FIXS;\llO FINTS;\111 NoD)END;

\lO0 FINC;\I01 FTST;\110 FINVD;\111 BEGIN

(DECODE IR<13:15> =>\000 FHLV;\O01 FWEXP;\010 FSCAL;lOll FSQRD;\100 FLOD;\I01 FIXD;

107

PRELIMINARY MCFAN/UYK-19 Arciliteclure November 22, 1977

\110 FINTD;\ 111 NO[,)END)

END)END)

END;\001 BEGIN !DIA Group

(IF IR<IO:14> EQL'O0000 =>BEGIN

(DECODE IR<I5>@IR<8:9> =>\000 STTNA;\001 ADTNA;\010 _IGTNA;\011 ANTNA ;\i00 LDFNA;\ l 01 ADFNA;\ ll0 SBFNA;\111 ANFNA) NEXTBAILOUT IN[,UT.OUT[,UTEND) NEXT

(IF IR<lO:14> EQL '11111 =>BEG IN

(DECODE IR<15> =>\0 BEGIN

(DECODE IR<8:9> =>\00 DIAFICF;\01 UNIl_l[,; ! I'ICFI\10 UNIM[,; !NCF2\11 UNI_I[,) !MCF3END;

\i READS) NEXTBAILOUT IN['UT.OUI'[,UTEND) NEXT

DIA !DIA INSTRUCTION

END;\010 BEGIN !DOA Group

(IF IR<10:I4> EQL'O0000 =>BEGIN(DECODE IR<15> =>\0 BEGIN

(DECODE IR<B:9>@IR<3:4> =>

\0000 FPStl;\0001 FSEQ;\OOlO I'IOVB;\0011 _IOVBT;\0100 FPOI';\0101 FSGE;

108

PRELIMINARY MCF AN/UYK-J9 Archilcclure November 22, 1977

\OllO CO_'II3;- \ 01 ] 1 COI_IBT;

X1000 FRST; " _\ 1001 FSGT;\ 1010 :-;RCB;\1011 ,SRCBT;\1100 FWST ;\1101 FSLE;\I]I0 FSLT;\1]11 FSNE )END;

\I BEGIN(DECODE IR<8:9> -->\00 RSP;\01 PSH;\10 POP ;\11 wsp)END) NEXT

BAILOUT INPUT.OUTPUTEND) NEXT

(IF IR<I0:14> EQL '11111 =>• BEGIN

(DECODE IR<15>OIR<8:9> =>• \000 DOAIqCF;

\OOl UNIMP; !MCF4\010 UNINP; !NCF5\Oll UNIMP; !FICF6\I00 BEGIN

(DECODE IP,<3:4>=>\00 DST ; !FST\01 DAD;\10 DNA;\ll DLD) !FLDEND;

\101 BEGIN(DECODE ]R<3:4> =>\00 DSTX ; !FSTX\ 01 DADX;\10 DNAX ;\11 DLDX) !FLDXEND;

\110 8NPY;\111 8DVD) NEXTBAILOUT INPUT.OUTPUTEND) NEXT

DOA !DOA INSTRUCTIONEND;

109

t

PRELIMINAI_Y MCF AN/UYK-19 Archileclure November 22, 1977

\Oil BEGIN !DIB Group(IF IR<IO:14> EQL'O0000 =>

BEGIN(DECODE IR<lG>OIR<8:9> =>\ 000 STTNX;\001 ADTNX;\0I0 HGTNX ;\011 ANTNX ;\]00 LDFNX;\I01 ADFNX ;\110 SBFNX ;\Ill ANFNX) NEXTBAILOUT INPUT.OUTPUTEND) NEXT

(IF IR<lO:14> EQL 'llIll =>BEGIN

(DECODE IR<]5> =>\0 BEGIN

(DECODE 1R<8:9> =>\00 I)IBHCF;\01 UNIHP; !IqCF7\IO UNIHP; !MCF8\iI UNIHP) !_ICF9END;

\l INTA) NEXTBAILOUT INPUT.OUTPUT

END) NEXTDID !DID INSTRUCTIONEND;

\100 BEG IN !DOB Group(IF IR<lO:14> EQL'O0000 =>

BEGIN(DECODE IR<I5>@IR<8:9> =>

\000 FAD;\OOl FSB;\OlO FMP;\0 ]I FDV ;\loo XXOR;\lOl IOR;\110 DEC;\Iii BEGIN

(DECODE ]R<3:4> =>\00 DSPD;\01 FS;\i0 S'FIIIN;\11 CLIBN)

110

PRELIMINARY MCF AN/UYK-19 Architeclure November 22, ]977

END) NEXTBAIl,OUT INPUT.OUTPUTEND) NEXT

(IF IR<lO'145 EQL 'lllll =5BEGIN

(DECODE IR<15) "->\0 BEGIN

{DECODE ]R<8-9> :>\00 DOBNCF;\01 UNINP; !NCFIOX10 UNINP; !NCFII\II LININP) !MCFI2END;

\1 NSKO) NEXTBAILOUT INPUT.OUTPUTEND ) NEXT

DOB !DOB INSTRUCTIONEND;

\lOl BEGIN !DIC Group(IF IR<10.14> EQL'O0000 =>

BEGIN(DECODE IR<]5>@IR<8"9> ->\000 " FLO,X001 FIX;X010 FNI'I;X011 (DECODE IR<3:4> =>

\00 FSNER;\01 FSER;\lO FSETD;\ 11 RNADR) ;

\100 LDFNW;\ l 01 ADFNW;\110 SBFNW;\]II ANFNW) NEXTBAILOUT INPUT.OUTPUTEND) NEXT

{IF IR<lO:14> EQL '11111 :>BEGIN(DECODE IR<IS> =>\0 BEGIN

(DECODE IR<8:9> =>\00 DICNCF ;\01 UNINP; _NCF]3\lO UNINP; ! I_ICF14\11 UNINP) !NCF15END;

111

\] ]ORST) NEXTBAILOUT INPUT.OUTPUTEND) NEXT

DIC !DIC INSTRUCTION

END;

\llO BEGIN !DOC Group(IF IR<lO:14> EQL'O0000 =>

BEGIN(DECODE IR<15> =>\0 BEGIN

(DECODE IR<8:9>@IR<3:4> =>\0000 SAVE;\000 ] ABD;\00]0 LDF;\0011 LDF;\0]00 POPB;\O]Ol RBD;\0110 STF;\0111 STF;\1000 RTRN;\I001 ATD;\]010 BAN;\1011 I_,KLS;\1100 COB;\1101 RTD;\1110 ZAP;\1111 WAITT)END;

\1 BEGIN

(DECODE 1R<8:9> :>100 UfiPY;\01 UDVD;\10 UDVI ;\ll UNPA)END ) NEXT

BAILOUT INPUT.OUTPUTEND) NEXT

(IF IR<IO:14> EQL 'lllll =>BEGIN(DECODE IR<I5> =>\0 BEGIN

(DECODE 1R<8:9> =>\00 DOCNCF ;\01 UNINP; !NCF16\10 UNINP; !NCF17\II UNINP) !f'ICF18

' 112

PRELIMINARY MCF AN/UYK-19 Architecture r'Joveml)_:r 22, 1977

END;\1 ilALT) NEXTBAILOUT INPUT.OUTPUTEND) ,NEXT

DOC !DOC INSTRUCTIONEND;

i

\111 BEGIN !SKP Group(DECODE IR<3:4> =>\00 BEGIN

(IF IR<I0:14> EQL '00000 =>BEGIN

(DECODE IR<15>@IR<8:9> :>\000 kINIFIP; !U22\001 RLAF;\OlO EUB;\0 11 ECALL;\100 TCO;\i01 PJS;\l]0 STISZ;\III PST) NEXTBAli,OUT INPUT.OUTPUTEND) NEXT

(IF IR<I0:14> EQL 'Ii111 :>BEGIN(DECODE IR<I5> =>\0 UNINP; !I'ICFI9\I BEGIN

(DECODE IR<8:9> =>\00 SKPBNCPU;\01 SKPBZCPU;\10 SKI'DNCPU;\ll SKPDZCPU)END) NEXT

BAILOUT INPUT.OUTPUT

END) NEXTSKP !SKP INSTRUCTIONEND;

\01 UNIMP; !U7\IO UNIMP; _U8\II UNINP) !U9END )

END; !END OF INPUT.OUTPUT DECODE

ARITitNETIC.or.LOGIC:= !Decode instructions beginning with a ] bitBEGIN

(IF IR<IZ:15> EQL '1000 => !decode the noload/noskJp instFuctJons

113

PRELIMINARY MCF AN/UYK-19 Archilecture bJovember 22, ]977

BEGIN(DECODE IR<8:9> =>\oo BEGIN

(DECODEIR<IO>=>\o BEGIN

(DECODEIR<ll>elR<3:4> =>\000 LEF;\OOl LDAE;\OIO 8TAE;\0 11 XCHH;

• \100 (DECODE IR<3:4> =>\00 JHPE ;\01 PJSE;\ 10 INE ;\ l ] DNE);

\lO1 UNINP; !U1\1]0 UNI_IP; !U2\] 11 UNI_IP) ! U3END;

\ 1 UNI MP) !UOEND;

\01 BEGIN(DECODE IR<5:7> =>\000 BEGIN

DECODE IR<]O:]I> =>

kO0 (DECODE IR<I:2> =>\00 (DECODE IR<3> =>

\o UNI_IP; !U5\] IBA);

\01 TRAP;\ ] 0 LI}B;\ 1] LDB) ;

\Of (DECODE IR =>

Xo UNIPIP; !U4\l STB);

\10 (DECODE IR =>\0 (DECODE ]R<2> =>

\0 WFP;\] WSL);

\ ] WBR) ;\ll (DECODE IR =>

\0 (DECODE IR<2> =>

\0 RFP;\] RSL);

\l RBR)END;

\001 (DECODE IP,<IO:ll> =>

114

PRELIMINARY MCF AN/UYK-J9 Architecture November 22, 1977

\00 (DECODE IR =>\0 UNINP ; !U6\I (DECODE IR<3-4> =>

\00 BTZ;\01 BTO;\lO 8ZB;\ ] ] ,SZBO) ) ;

\01 XCH;\10 SSGT;\II SSGE) ;

\010 (DECODE IR<]O:I]> =>\00 (DECODE IR<I-Z> =>

\00 RNSR ;\01 UMSR;\ 10 RNVR;\]I UJNP );

\01 (DECODE IR<]:Z> => .\00 (DECODE IR<3"4> =>

\00 WR_IAP;\01 RDNAP ;\l0 WRWRD ;\ii RDWRD );

\01 (DECODE IR<3-4> =>\00 CNVR ;\01 C[¿MA;\10 I_IAPSl;

\11 NAPSD) ;\10 (DECODE IR<3> =>

\0 UNINP; !UXO\1 (DECODE IR<4> =>

\0 RNST ;\] UNIMP)) ; !U]8

\II UNII'IP); {U19\I0 UNII_IP; !U20\II UNII_IP); !U21

\011 . UNII_IP; !U16\I00 UNINP; !UXI\]Ol UNINP; !UXI\ii0 UNII'IP; !UXI\Ill UNIMP) !UX1END;

\i0 (DECODE IR<5-7> =>

\000 UNINP ; !UIO\OOl UNIMP; !UI2\OlO UNINP; !U14\Oll UNIMP; !U17\i00 UNII_IP; !UX2

115

PRELIMINARY MCF AN/UYK-19 Archiiecture November 22, 1977

\101 UNINP; !UX2\llO UNINP; !UX2\111 UNINP) ; !UX2

\11 (DECODE IR<5:7> =>\000 UNIMP; !UI]\00l UNIt'IP; !UI3\010 UNIf'IP; !U15\OI l UNINP; !UX2\lO0 UNINP; !UX2\IOl UNINP; !UX2\110 UNItiP ; !UX2\111 UNINP)) NEXT !UX2

BAILOUT ARITtlNETIC.OR.LOGIC

END) NEXT !end of noloadlnoskip instruction decode

(DECODE IR<5:7> => !Decode Function Generator\000 COH;\00 1 NEG ;\010 HOV ;\011 INC;\ 100 ,ADC ;\101 SUB;\110 ADD;\ l ] 1 ANDD)END ;

INST. DECODE. EXECUTE:: !Nain Instruction Decode ProcedureBEGIN

(DECODE IR<O> :> !Begin instruction decode and execute\0 (DECODE IR<I:2> =>

\00 NOAC.EFFECTIVE.ADDRESS;\Ol LDA;\lO 8TA;\11 INPUT.OUTPUT) ;

\1 ARITIIMETIC.or.LOGIC)END;

116

45. MAIN PROCESSING LOOPS

FETCH. EXECUTE:= !This is the fetch execute loopBEG I N

(IF ION AND ((NOT INTNSK AND DEV.IBIT) NEQ O) =>INTERRUPT) NEXT

INSTR. FETCH NEXT

INST. DECODE. EXECUTEEND

ERALCED !>>>>>>>>>>>>>>>>>END ROUTINES<<<<<<<<<<<<<<<<<<<<<<<<

RESTART:= !Initialize and Run loopBEGIN

STATUS<0 : !5>'-' 000001111111 I000 ;FPSR<0 : 31 >',-0 ;MSR<0 : 15>,-0 ;MVR<0:15>_-0 NEXTPC.-AUTO. RESTART NEXT

RUN. LOOP := BEGINFETCH. EXECUTE NEXT

RUN.LOOPEND

END

)!END MCF AN/UYK-19

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PRELIMINARYFORM - Carnegie Mellon University

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