Preliminary stuff Prof. Paul Hasler. Capacitor Circuits V out (t) GND C2C2 Q I.
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Transcript of Preliminary stuff Prof. Paul Hasler. Capacitor Circuits V out (t) GND C2C2 Q I.
![Page 1: Preliminary stuff Prof. Paul Hasler. Capacitor Circuits V out (t) GND C2C2 Q I.](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649db15503460f94a9fd06/html5/thumbnails/1.jpg)
Preliminary stuff
Prof. Paul Hasler
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Capacitor Circuits
Vout(t)GND
C2
QI
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Capacitor Circuits
Vout(t)GND
C2
QdVout(t)
dtC2 = - Iin
I
dQ(t)
dt = Iin
We get an integration….
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Capacitor Circuits
Vout(t)GND
C2
QdVout(t)
dtC2 = - Iin
Vout(t) = Vstart - t C2
Iin
I
dQ(t)
dt = Iin
We get an integration….
For constant I, we get
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Capacitor Circuits
Vout(t)GND
C2
QdVout(t)
dtC2 = - Iin
Vout(t) = Vstart - t C2
Iin
I
dQ(t)
dt = Iin
We get an integration….
For constant I, we get
t
Vout(t)
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Capacitor Circuits
Vdd
C
Vd
Vref
Vout
Vtun
t
Vout(t)
Injection
Tunneling
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Floating-Gate Systems
Prof. Paul Hasler
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Floating-Gate Devices
• Information Storage
• Floating-Gate Transistor
• Modifying Floating-Gate Charge- UV photo-injection- Electron tunneling- Hot-electron injection
• Digital Memory (EEPROMs)• Analog Memory• Floating-Gate Circuits• Floating-Gate Systems• Floating-Gate Adaptation
All of this in a standardCMOS process
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Floating-Gate Circuits
• Decrease Floating-Gate charge by hot-electron injection
• Increase Floating-Gate charge by electron tunneling
Capacitor-Based Circuits
• Resistors and Inductors define the circuit dynamics
• Capacitors are the natural elements on silicon ICs
Charge Modification
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Electron Tunneling
Increasing the applied voltage decreases the effective barrier width
The range of tunneling currents span many orders of magnitude.
(oxide voltage)-1
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pFET Hot-Electron Injection
The injected electrons are generated by hole impact ionizations.
**Injection current is proportional to source current, and is an exponential function of
dc.
Vinj = 430mV
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Offset elimination
-3 0 3-80
0
Differential Input Voltage
Diff
eren
tial O
utpu
t Cur
rent
(nA
)
Direction of offset due to hot-electron injection ontothe floating gate devices.
80
Small Linear Range
Huge Linear Range
Offset is less than 1 mV.
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Tunable Voltage Sources
SELECT UP DOWN
VOLTMETER
Cf
Vref
TunnelingCircuitry
Inject
Select
TunnelSelect
InjectionCircuitry
Output Voltage: (if selected)
• Decreased by Tunneling
• Increased by Injection
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Arrays of Prog.Voltage Sources•EPot elements are arranged in a linear array with a shift register selecting one element at a time
E Vout
tunnel
inject
select
E Vout
tunnel
inject
select
E Vout
tunnel
inject
selectSpeed used: ~1V/ms ( range is 100V/ms to very very slow)
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Translinear Element using Floating-Gate Devices
GND GND GND
Iout
I1 I2
VddVdd
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A Single-Ended Gm-C filter using Floating-Gate Devices
GND GND
I1 I2
VddVdd
-1
C
C
C
Vout
Vin
C
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0 50 100 150 200 250 300 350 400
0.1
1
10
100
Half-second pulse steps
Selected Synapse
Non-selected Synapse
Injection PhaseTunneling Phase
Programming / Selectivity in FG Array
V1 V2 V3 V4
• channel current (Gate voltage)•Large Source to drain voltage (high field for hot electrons)
2 conditions for injection
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Programming a Floating-gate Device
• Tunneling– Remove charge from floating-
gate– Less control per device– Used as “global” erase– Decrease current for a given
threshold
• Hot-electron injection– Add electrons to the floating-
gate– Isolate devices well– Program accurately– Increase current for a given
gate voltage
Vtun
Vin
+
I
+
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Basic Programming StructureV1 V2 V3 V4
Injection Gate: Column isolation Source-Drain: Row isolation
Both: Device isolation
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Programming a FGV
tun
Vin
+
A
+-
Offchip
Bring chip up to program voltageBring drain up to match Vds(run)Set Gate volt to read currentRead Current through deviceCalculate next pulse on drainPulse Drain voltageRinse and repeat
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Basic Programming Structure
DECODERGate Pin
Column
S
S
S
SSSS
S
S
S SS
Input Signals / Circuitry
(M. Kucic, P. Smith, P. Hasler, 2000-2001)
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Programming Board Interface
AdditionalUser
Circuits
ToDrain
CurrentMonitorBlock
DAC
SPI
Regu lator
ToGate
LevelShifters
Selection Logic
Programmin g Board Testing Board
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Programming Board, v0.1
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Answers to Typical Questions
Is storing analog charge levels on a floating-gate reliable?Yes, we have seen little to no movement over months (like 0.01mV in EPots)
Isn’t floating-gate programming is slow?We are currently programming in ms times, should get to 1-10s times as in EEPROM, and the process can operate in parallel.
Does this require specialized processes?Can be built in either Double Poly or Single Poly (i.e. digital) processes
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Automatic Floating-Gate Programming
0 10 20 30 40 50 60 700
2
4
6
8
10
12
Flo
atin
g-G
ate
Bia
s C
urr
en
t (n
A)
Position along the Array
cosine
-cosine
Measure Current
< target
Compute Drain V
Yes No
Inject Element
Select Next ElementSTART Get in Range
Programming ResultsProgramming Algorithm
(NSF ITR)
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Array Programming
V
VtunVtun
M1 M2Vfg1 Vfg2
I-I+
Vg2
Vd2
To Circuit
To Circuit
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Applications of Floating-Gate Circuits in Systems
• Programmable Filters / Adaptive Filters
• Auditory / Accoustical Signal Processing
• Image Processing
• ADCs, DACs, etc.
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Single-Transistor pFET Synapses
1. Store a weight value2. Input x stored W3. dW/dt = correlation of the f( input , a given error signal)
Vdd
Vtun1
C1
M1
M2Vb
Vg
VdProgrammable and Adaptive Analog Processing
(NSF CAREER)
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Fourier-Based Programmable Filters
Bandpass Filters, Exp Spaced (Hard in DSP)
Vin
W11 W12 W13 W14 W15 W1n
W21 W22 W23 W24 W25 W2n
Iout1
Iout2
FG tuning of bandpass filters as well as coefficients…
(M. Kucic, P. Hasler, et. al. 1999-2001)
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Analog Speech Front-End Blocks
Analog HMM ClassifierVQ Classifier
Analog Cepstrum
Outputs
Cepstrum
VQ
HM
M
Microphone
Digital S
ignalProcessing
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Transform Imager
Image Elements
Floating-GateElement
AnalogComputing
Array
Transformed Output Image
Ti m
e ba
s is
1
Ti m
e ba
s is
2T
i me
bas i
s 3
Ti m
e ba
s is
4
Ti m
e ba
sis
m
Imag
e Se
nsor
Iout
Vin
Basis Functions
Dig
ital
Con
trol
Our approach allows for
• Bio-inspired (Retina)
computation
• A programmable
architecture
• High-fill factor (~50%)
pixels like
CMOS imagers.
Can build in other neuromorphic designs into this structure
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Layout of Imager Cell
30 = 9m
39
= 1
1.7
m
• Fill Factor ~ 50%
• Fabricated in 0.5m CMOS
0.5m 0.25m
Photo 8mx6m 3.2mx2.4m
Array 128 x 128 512 x 512 (Size) (1.72mm2) (4.4mm2)
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Adaptive Floating-Gate Circuits• Full range of floating-gate circuits abilities• Continuously programming (tunneling / injecting) therefore, circuits at a slower timescale
Fundamental operation for adaptive systems: Adaptive Filters, Neural Networks, Neuromorphic Models of Learning
Equilibrium point: Tunneling current = Injection current
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AFGA Behavior
0 2 4 6 8 10 12 14 161.5
2
2.5
3
3.5
4
4.5
Input voltage (V)
Out
put v
olta
ge (
V)
Sine Wave + Voltage Step Input
Voltage Step InputV
Vout
Vdd
C1
Vin
Vtun1
Vfg
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Autozeroing Floating-Gate Amplifier (AFGA)
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Adaptive Diff-Pair
V1
Vtun
V2
Vtun
Vdd
Vdd
VCM
V
Vout1 Vout2
I1 I2
Common Mode Feedback
Vn
Can be directly extended to:• Multipliers / Mixers• “Bump” Circuits
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Translinear Element using Floating-Gate Devices
GND GND
Iout
Iin
Vdd
C
CV1
V2