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Practical Computer Architecture Education with RISC-VStefan WallentowitzProfessorMunich University of Applied Sciences@wallento

About Me

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•Graduated from RWTH Aachen and TU Munich, EE/Computer Engineering

•Research Interests: Manycore SoC, physical hardware security, verification

•Professor at Munich University of Applied Sciences since March 2019

Professional

•Long time user and contributor to OpenRISC, then RISC-V

•Many open source projects (HDL, Tools, …)

Hobbyist

•Director at Free and Open Source Silicon Foundation

Advocacy & Community

Munich University of Applied Sciences

► 18400 Students, 14 Departments

► Characteristics

• Primarily Bachelor and Masters Degrees

• Strong Focus on Practice and Application

• Application-oriented Research

• Small Class Sizes (5-40 students)

• Compulsory Industry Internship

• Professors: Min. 5 years industry experience

► (Comparable) Strategic Partners: Cal Poly (San Luis Obispo), TAMK (Tampere, Finland), UAS Vienna and Zurich

► My Faculty: Computer Science & Mathematics

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My First Course: Computer Architecture

► 4th Semester Bachelor

► Classic Curriculum

• Pipelining Basics

• How we got to large IPCs(BP, Superscalar, OoO)

• Memory, Interconnect, …

► Lecture & Integrated Laboratory

► … and all this cool open source stuff out there!

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How I see Computer Architecture

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The Lecture

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The Laboratory

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• Refresher in Computer Systems, RISCV Instruction Set and Assembly

• Tools: rv8, spike, Venus

RISC-V Basics

• DLX Pipeline: Ripes Simulator

• Simulators, Emulators, Levels of Abstraction

• RTL Simulations of popular open source CPUs(ibex, SCR-1, Rocket, Ariane, BOOM)

Computer Architecture

• Nexys A7 FPGA board with different open source CPUs

FPGA Platform

RISC-V Basics

► Refresh Assembly Skills

► Small programs, calling conventions etc.

► Venus simulator (JavaScript in Browser)

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Venus Simulator: https://www.kvakil.me/venus/

Basic DLX Pipeline

► Move away from pure functional (instruction accurate)

► Understand basic (DLX) pipeline principle

► Ripes simulator (awesome project!)

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Ripes Simulator: https://github.com/mortbopet/Ripes

Simulators, Emulators, Level of Abstraction

► Step from visual simulators to other types of simulation/emulation

► rv8: Different modes, understand user mode emulation etc.

► Understand levels of abstraction

► RTL simulation (Verilator) and gtkwave: Syntacore SCR-1

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Syntacore SCR-1: https://github.com/syntacore/scr1

Computer Architecture Insights

► Goal: Understand Computer Architecture concepts

► Insights into core implementations without waveforms etc.but with real processor cores!

► Example of existing tools: BOOM and gem5 O3 pipeline viewer

► THAT, but with much moreµ-architectural details!

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Pipeline Viewer

► Python: pip install pipeline-viewer

► Re-implementation of basic pipeline viewer, but with extra modes

► Extensions of core simulation environment with DPI

► Example: Ariane 64-bit core

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Testbench

Ariane

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Minimal extensions to ease tracking of instructions (may become obsolete)

Observe microarchitecture and trace events

Trace File

CTF (binary trace) or text file

pipeline-viewer

Pipeline Viewer: Instruction Trace

► Assignment: Observe instructions in pipeline, determine IPC

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Instruction lifecycle over time

Total retired instructions

DurationPC &

Disassembly

Pipeline Viewer: Branch Predictor

► Assignment: Compare expected behavior, impact of difference sizes

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Branch prediction and updates to the

predictor

Work-in-Progress: FPGA Integration

► Implement cores in FPGA and add micro-architecture trace

► Ran out of time in spring 2019, will be added in spring 2020

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FPGA

Core

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CTFpipeline-viewer

Open SoC Debug

Outlook: Computer System Basics

► Course in Computer System Fundamentals

► Currently MMIX & VMB

► Switch to RISC-V

► Plan: Extend Venus simulator for example with I/O visualization

► ETA: Summer 2020

► Also: Benchmarking with Embench

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Summary

► Computer Architecture Teaching with Real Processor Cores

► Accessible to non-EE students, no need to touch HDL/waveforms

► Reusable infrastructure, WIP even for FPGACores: lowRISC Ibex, Syntacore SCR-1, ETH Ariane, Berkeley BOOM

► Laboratory Curriculum

► Soon available online: https://github.com/wallento/riscv-ca-teaching

► Get in touch!

Stefan.Wallentowitz@hm.edu @wallento

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https://github.com/wallento/riscv-ca-teachingmailto:Stefan.Wallentowitz@hm.edu