~pplication and Design Ideas

RCA Solid State COSIMOS Application and Design Ideas

Table of Contents Page No.

Op-Amp to COSIMOS interface with common supply rail 24V Industrial logic swing t o COSIMOS interface circuit Split rail OpAmp to COSIMOS inprface Expanding COSIMOS inputs Power on reset circuit for CW047 Noise Discriminator using CW047 -, g. , k

, ' Simple pulse delays .a- ; r 7 " .

+.Digital frequency multiplier *Bendpas$ fi l ter ' Eigh>-bC,f adderlsubtrwter

ParityPit genereto! - *+- M p d e t e c t i o n &&tooth generators using CW029 Staircase generator Time slot expandek '

.,3 IIP excrdive OR gate,. Active low+ass fi l ter Touch set-wset bistable Monostasble using Schmitt-Triggr

:&hmitt-Trigger 6Scillator Pulse frequency doubler Edge triggered R S flip-flop

a Anti -Bynce push button switching DC motor control using the CD40107B 4-Bit ful l BCD add& 4-Digit display Multiplexer with BCD inpun Three-input NOR gate using thO CD4007 Thw- input NAND gate using the CD4007 Combination lpgic using the CD4007 Phase-locked loop using exclusive - OR gates Alarm system with low stand-by power Rsclrculating shift reglster i

CD4013 used as a Monosteble/Astable LC Oscillator BCD t o 9's complement logic 4-Bit gray code counter using the CM027 High speed gray code counter using the CW095B Digital Sine-Wave approximation Delayed load switching Line driving wi th the CD40107B Selective cycle deletion Divide by 60 counters Touch switch with latch Sevenregment t o BCD logic Digital controlled pulse with modulator Temporal priority 4channel latch COSIMOS to isolated triac interface + 12 circuitgiving truth table as TTL Part 7492

Information furnished by RCA is believed t o be accurate and reliable. However, no responsibilin/ is assumed by RCA for its Use: nor for any infringements o f patents or other rights o f third pahies which may result from its use. No license is granted by implication or othewicte under any

f patent or patent rights of RCA. ,

GS/3K/876 Printed in England18-76 !

i

1 OP-AMP AND COSIMOS WITH

I COMMON SUPPLY RAIL

I R 2

1 I 1

IIP I

i i I

1 1 I 1 I

i

/ 24" INDUSTRIAL LOGIC SWING TO I COSIMOS INTERFACE CIRCUIT I j VPO - - 0 + IOV VDD I I

I I 0 OIP I

1 114 CD4093B

1 i - - - 0 vss

METHOD A 1 l lP0 - - o+lOV VDD

i

IN914 I

I 00 lP I I

ZFlO 4NF

1

I14 CD4093

I 1

- - 4 vss METHOD B

SPLIT RAIL OP-AMP TO COSIMOS INTERFACE

OVDD +IOV

SIMPLE METHOD OF ACCOMMODATING EXTRA INPUTS TO COSIMOS CIRCUITS

I

IS44 I F-A-B I

R IS SELECTED I n I1 I

I I

FOR POWER- IS44 11 COSIMOS I

CONSUMPTION B o I I

AND SPEED 1\1 IS44

I I

REQUIREMENTS A0 hl 1 1 I I

IS44 COSlMOS I

B o I I I I

R I

F-A+B

POWER-ON RESET CIRCUIT

I RESET

ELIP-FLOPS COUNTERS

POWER ON Q = 0 LVSS

Flip-flops, counters and circuits containing these elements are not guaranteed to reset when the supply volt- age is applied. The above circuit shows a way of producing on automatic reset when power is turned on. This circuit is useful in connection with the CD4047 monostable which contains a flip-flop in the output stage.

Dl is included to isolate the CR network from any circuit connected to the reset input.

NOISE DISCRIMINATORS

CD4047A oOUTPUT

10 - - - +TR

NOISY INPUT SIGNAL 112 CD4013A

116 CD4069

TJl2.48CR I U.71, mn I 2-

3 %+, n

All input pulses with a pulse width shorter than that defined by the monostable time will not appear at the output.

The output will have its negative going edges coincident with the inputs. but will be reduced in pulse width by the monostable time. This circuit is useful in cleaning up transducer outputs, before being counted, so eliminating false counts due to noise spikes.

--- .

PULSE DELAYS ARE EASY WITH COSIMOS

C D4041A - - 0 A

C2 RI

INPUTJ-

- ' $ - - O B

A n t, Cl Rl

B n t e C 2 R2

00

r L r u - A 1 0 t l J u 1

I I I I I I I I I I I I t e CR

DIGITAL FREQUENCY MULTIPLIER

* OIP 12

7+12v VDD

C D 4 0 4 6 CD4017 Decade Cntr

II 41

- - 1291011

-

Multiplication factor :-

X9 connect pin 3 to pin 11 of CD4017 X8 connect pin 3 to pin 9 X7 connect pin 3 to pin 6 X6 connect pin 3 to pin 5 X5 connect pin 3 to pin 1 X4 connect pin 3 to pin 10 X3 connect pin 3 to pin 7 X2 connect pin 3 to pin 4 X I connect pin 3 to pin 2

With the component values shown aboveThe circuit will lock into input signals from 5Hz to 100Hz. Operation at other frequencies can be achieved by suitable choice of RC components in the phase locked loop. (See C W 0 4 6 data sheet and Application Note ICAN 6101 1.

22K In BAND-PASS FILTER

FILTER I 2OKHZ UPPER LIMIT +TR

X R E T

CD4001A

'F-INPUT

C D4047A

CD4013A -

O'F'OUTWT 47K In -D 0

+TR -+I RET -1 FILTER 2 s IOKHZ LOWER LIMIT

CD4047A

. .

I" EIGHT-BIT ADDERISUBTRACTER

Ya

Y7

Yb

Y5

Y4

Y3

Y2

YI

PARITY BIT GENERATOR

CD4070A x 2

8- BIT WORD PARITY BIT

'0'- EVEN

POSITIVE EDGE DETECTOR USING SCHMlTT TRIGGER CD4093B

A

t QCR

Jls

CD4070B EDGE DETECTOR USING CD4070B

A A I 4 t r

= B L

.

SAWTOOTH GENERATORS USING CD4029

CLOCK VDD

+VDD INPUT A = '0' INPUT B = '0' '4% INPUT C = '0'

CONTROL INPUTS

A = '0' RAMP DOWN C = '0' FREE RUN = '1' RAMP UP = '1' STOP RUN

B = '0' 10 STEP RAMP Suggested va lues = '1' 16 STEP RAMP for R = lOOK

TIME SLOT EXPANDER

'0' + tln 2c1 RI

*I. n *2' k t 2 4 t 2 a C2 R2

'3 n '4' n I t is an advantage in some logic systems to carry out operations

in a set sequence, controlled by a timing generator. If a larger time slot i s required, instead of gating together outputs

and so reducing the slots available from the C M 0 2 2 the pulse can be expanded by an amount' R2 C2.

By taking the clock enable input to a logic '1' the sequence can be arrested in any position.

I

3 I/P EXCLUSIVE OR GATE

CD 4069A CD4023A

A

B

C 3 IIP MCLUSIVE OR

ACTIVE LOW-PASS FILTER

'F' OUTPUT

'F'INPUT CD4047A

T 2.48CR

f = f CUTOFF

R C

OUTPUT FOLLOWS INPUT FOR FREOUENCI ES LESS THAN F CUTOFF

TOUCH SET-RESET BISTABLE

s TOUCH

0

R TOUCH

WHEN VDD = 10v CONTINUITY TOUCH WHEN VDD = 5v PROXIMITY ACTIVATION

MONOSTABLE USING SIGNAL SCHMITT OR VDD TRIGGER

CD4007, CD401078 OR TRANSISTOR

TRIGGER I I P

n I f C is large a discharge current limiting resistor may be required

when using the CD401078. For safe area of operation, see Data Sheet. File No.

'0' INHIBIT

SCHMITT-TRIGGER OSC I LLATO R

114 0 9 3 B k VERSIONS UNLIKE LIMITED LESS THAN TTL TO R 270 VALUES IS NOT OHMS

1 T AC ~n Vp + In VDD - V n ((4 (G I Vp and Vn = threshold voltages

PULSE FREQUENCY DOUBLER

0

INPUT OUTPUT

2 CD406BB - 3 CD4011A - 3 4

When a signal passes through the circuit each inverter introduces a small delay, typically 25'nS at 10V.

I f the input is gated with the input's inverted form, appearing after the third inverter a pulse is produced three gate delays long after the positive transition of the input.

A pulse on the negative input transition is obtained in a similar way, one inversion step along the inverter chain. These two outputs are then added together to give a pulse at the output every logic transition at the input.

The circuit will operate up t o r 5 . 5 MHz at 15V and down to near DC if a Schmitt trigger is used at the input.

-

ANTI-BOUNCE PUSH SWITCHING

ED R - S FLIP-FLOP

'1'WHEN SET

SET 0 ;

b INHIBIT

SET A

CLEAR A The use of an AND-OR-INVERT GATE with a J - K flip-flop enables expansion of the clock input. Feeding the outputs of the flip-flop back to the inputs a l l m only a single output transition direction

upon receipt of each successive clock pulre. This method makes the circuit operation independent of the initial state of the flip-flops. The outputs also select the earliest valid input signal for clocking the flip-flop.

A logic 'I' on the inhibit input can be used to lock out the SET and CLEAR inputs.

.

DC MOTOR CON'TROL

co '0' 'I '

With the addition of two PNP transistoo to the dual NAND buffer (CD40107BE) a complementary output drive is produced.

This is used t o drive the motor in the forward or reversa direction.with a logic input. The application of a logic '0' on B stops the motor irrespectively of input A, and provider a degree of dynamic braking.

CROSSCOUPLING ENABLES PULSE LOGIC CONTROL OF MOTOR + 12v

*,

- - 1 CD40107BE 1 CD40107BE 2 2

0 CONTROL INPUTS 0

A B

A B MOTOR FUNCTION

0 0 OFF 1 0 COUNTER CLOCK-WISE 1 1 AS PREVIOUS STATE 0 1 CLOCK-WISE 1 1 AS PREVIOUS STATE

L

f b . l b

12v

-

0

4-BIT FULL BCD ADDER

TO .dd tm BCD n s m h n with ordinw tvll bimry .d&n, 8 i x is .d&d f a u r n s thmt am wta Urn nlm.

4-DIGIT DISPLAY MULTIPLEXER WITH BCD INPUTS

CD4052B

CD4052B CD4511B

VDD - + 10V

Vss - ov

LOGIC FUNCTIONS USING THE CD4007A

14 VDD

-

A$'-,+: 8 2 - 0 D

11

13

1

C 0

B 3

a s- D THREE INPUT NOR GATE

- - 14 2 11

VDD

D

CD4007A

_(D-- D THREE INPUT NAND GATE

>

t-

12 t b

-4 9 - - VSS pin 7

L

COMBINA'TIONAL LOGIC

.I,-. +,- Q3

C W 0 0 7 Pin Connections (2, 13) (5.4. 9) (1. 12) (11, 14) (4, 7) Output p i n 12 Qg CD4007A

Q1 = p i n 6 02 = p i n 10 Q3 = p i n 3

PHASE-LOCKED LOOP CI

USING EXCLUSIVE O 0.0luF

OR GATES SQ. WAVE PlNUT " 1 lOOK

vss Filter

Phase comparator 0

OUTPUT lKpF

IN914 3 CD4070B *- lOOK 4

A complete phase-locked loop circuit, which i n c l u d ~ a VCO, phase comparator and filter, can be made from threequartem of a CD4070B EX - OR Gate.

The circuit produces a square-wave output in quadrature with the input signal. The lock and capture ranges are determined by the valuer of the filter, R,, R2 and C,.

For the circuit shown, the center frequency is nominally IOKHz. The loop can capture the input frequency over better than a 1.5 : 1 range and track over a 4 : 1 range.

The loop will also lock to input signals that are multiples of the VCO frequency.

I

',

i

TOUCH SWlTCH WITH LATCH

o OUTPUT 1 OM

470K I

I I

*L CD404 1 4

TOUCH CONTACTS

The circuit is switched by making a conductive path with the fingers across 2 contacts.

The circuit will remain in the new state until contacts are made again.

SEVENSEGMENT TO BCD DECODER

SEVENSEGMENT INPUT

a b c d e f

A

1 1 1 1 0 0 1 0 1 1 0 0 1 1 1 0 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1

B 1 1 1 1 0 1 1

A B C O 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0

C 0 0 1 0

1 CD4073B 2 w4011a 1 CD408B 1 CM012A

1 0 1 0 0 1 1 0 1 1 1 0

I o o o t 0 D 1 0 0 1

I BCD

CD4013A USED AS A MONOSTABLE

0 1s

-D Q 0 OUTPUT INPUT TRIG.

L t l 1WnS

1 - 2,

4 k - b R lN4148 CL n

R

0.66CR CD4013A

-

R range - 27K - 10M

C range - The lower limit is determined by the flip-flop's minimum reset pulse width, which is about 125nS at 10V - (5oonS at 5V). A typical value for C is 0.033uF. The upper limit can be quite large so long as the discharge current into the output does not exceed the package dissipation.

A reset during the timed period can be accomplished by raising the clock input to a logic '1'.

CD4013A USED AS AN ASTABLE

R. & C. Range limitations as for monostable.

T A - OUTPUT

R2 TB -

TA = 0.66 C2R2

Fout = 1 TA + TB

4 t

C l f c2== vss =

J

COSIMOS LC OSCl LLATOR

V OUT

R = 22K

F = 1

I I C2 Lcl

IN PRACTICE C1 = C2

2 r J m Cl+C2

BCD TO 9's COMPLEMENT LOGIC

D C B A

0

K LSB

CD4070B

CD4001 2 i'.

9's COMPLEMENT OUTPUT

L

4-BIT GRAY CODE COUNTERS

A B C D

- J Q

3 X CD4027

When binary s~gnals are AND ed together, CLOCK I 1 1 1 I I I I I I I 1 I I I 1 undesirable gl~tches can be generated at the output. (X) -

The output hnes of these Graycode (Y) n I I generators have no simultaneous signal transiston permitt~ng them to be AND ed

A-

together w ~ t h w t creating glitches B --A I I For co~rect operation all b~stables must be I

reset initially. C

D I L

HIGH SPEED GRAY CODE COUNTER GRAY CODE

5 X CD4095B A B C D

C

CD4095B - MAX TDGGLE FAE(1UENCY TYPICALLY 16 MHZ AT 10V V D ~

THE GRAY CODE A B C D A B C D

0 0 0 0 0 9 1 0 1 1 1 1 0 0 0 10 1 1 1 1 2 1 1 0 0 11 0 1 1 1 3 0 1 0 0 12 0 1 0 1 4 0 1 1 0 13 1 1 0 1 5 1 1 1 0 14 1 0 0 1 6 1 0 1 0 15 0 0 0 1 7 0 0 1 0 16 0 0 0 0 8 0 0 1 1

DIGITAL SINE-WAVE APPROXIMATION

- - (1 1 (1 13

11- VDD - 12" vs= 0"

2 8 D O L O F0"T

CMOl3A

llu FILTER VALUES FOR l K H z OUT CLOCK INPUT 3KHz

The ouOvr on IAI mpraximmn to 8 rinew.us, the f i m humonic of rrhieh is five timn the fundmaol. T b 1ap.s fiimr Ihm P r m i h a btmr rim-w.us at (81 if nquind.

CLOCK - 0

-4J-4 @

DELAYED LOAD SWITCHING

+ 10v

IN4148

TD O.8CR

--!-I- B

I

: TD LOAD ON

This circuit will give a delay to the switching of the I d , after a logic 'I' has been applied to the input.

Due to the high gain of this buffer below about 12 volts, long time constants can be used whilst maintaining an abrupt output transition.

LINE DRIVING

1 CD40107BE SN75108A 2

DATA OUTPUT

CYCLE DELETION

F Max 20KH

GENE RATOR

SELECT DUTYCYCLE

CLOCK & 11 5;UNTERIDIVIDER

5 v

DUTY CYCLE

Cycle, deleted Pin No. Thls circuit can prov~de a more realistic way of testing out of 10 CW017 audio ampl~fien on load. A t full output swings a

continuous sine wave can cause undue power dissipation 1 11 or supply voltage drop. 2 B 3 6 4 5

5 1 6 10 7 7 8 4 9 2

DIVIDE BY 60 WITH 7SEGMENT OUTPUTS

a b c d e f g a b c d e f g

INPUT

foe FIN 80

fo

with the edps at output A and B. A Y The clock input's positive edges coincide

B u DIVIDE BY 60

CD4017 CD4017

2 fo - FIN

CD4001 80

. CLOCK INPUT

n f OUTPUT

LOW STAND-BY POWER ALARM SYSTEM 1 W BATTERY

SECURiTY LOOP

'POWER4N' RESET

when opa circuit arsun in the acuriy imp the latch. asrollcoupled 3-input NAND pin, is mt. h i & en.bln the .I.nn. This will remain st even it the loop is now sanplemd.

ThsCD4020A 143- npple counmr is clocked by e d w runniw mcillmor. to produce ul oulprt simai to -1 the I.& amr h u t 25 rninua. and turn OH the alarm. The mlarm will m ly mrnain m if the Imp main1 own circuit.

CIRCULATING SHIFT REGISTER

DUAL 4STAGE REGISTER

CLOCK INPUT

Every clock period a logic 'I' is stepped along the eight outputs in sequence. Alternatively a '0' can be obtained by changing the NOR gate to a NAND gate (CD406BB)

and returning pin 12 to VSS.

h

DIGITAL CONTROLLED PULSE WIDTH MODULATOR

CLOCK INPUT

A B

OUTPUT

A B

BCD THUMWHEEL

A1 A4 A10 A40 SWITCHES The CD451BB is a dual BCD up counter. This is used to produce a digital ramp

at ia output when supplied with clock pulses. When this output is compared with a selected digital value by a pair of magni-

tude cwnparitors CD4063B's, a pulse is obtained at A B output that can be incre- mented from one clock period in width 1% dufy cycle, to 100% dufy cycle. The A B output appean as an inverted form of A 8.

TIME - PRIORITY 4CHANNEL LATCH

INPUTS OUTPUTS

CD40788

RESET 1 After a reset pulm has been applied dl M p u t s remain at zero. A pulse that occurs on any input line sea the bistable, which causes a positive transition at the clock input of the CD40768. This edge clocks Ihe data through to the respective a output.

I f any other pulses occur on the inpur lines after this pulm they will fail to clock the bistable and in wnmquenu, wilt nof'be transferred to the output. Thus Ihe four output lines will record which pulse war received first.

COS/MOS Application and Design Ideas