PPC Vers202 Book1 Public

8/8/2019 PPC Vers202 Book1 Public

1/230

i

Version 2.02

PowerPC User Instruction Set Architecture

Book I

Version 2.02

January 28, 2005

Manager:

Joe Wetzel/Poughkeepsie/IBM

Technical Content:

Ed Silha/Austin/IBM Cathy May/Watson/IBM Brad Frey/Austin/IBM

Junichi Furukawa/Austin/IBM Giles Frazier/Austin/IBM


2/230

Version 2.02

ii PowerPC User Instruction Set Architecture

The following paragraph does not apply to the UnitedKingdom or any country or state where such provisionsare inconsistent with local law.

The specifications in this manual are subject to change

without notice. This manual is provided AS IS. Inter-national Business Machines Corp. makes no warrantyof any kind, either expressed or implied, including, butnot limited to, the implied warranties of merchantabilityand fitness for a particular purpose.

International Business Machines Corp. does not war-rant that the contents of this publication or the accom-panying source code examples, whether individually oras one or more groups, will meet your requirements orthat the publication or the accompanying source codeexamples are error-free.

This publication could include technical inaccuracies or

typographical errors. Changes are periodically made tothe information herein; these changes will be incorpo-rated in new editions of the publication.

Address comments to IBM Corporation, Internal Zip9630, 11400 Burnett Road, Austin, Texas 78758-3493.IBM may use or distribute whatever information yousupply in any way it believes appropriate without incur-ring any obligation to you.

The following terms are trademarks of the InternationalBusiness Machines Corporation in the United Statesand/or other countries:

IBM PowerPC RISC/System 6000 POWERPOWER2 POWER4 POWER4+ IBM System/370

Notice to U.S. Government UsersDocumentationRelated to Restricted RightsUse, duplication or dis-closure is subject to restrictions set fourth in GSA ADPSchedule Contract with IBM Corporation.

Copyright International Business Machines Corpora-tion, 1994, 2003. All rights reserved.


3/230

Preface iii

Version 2.02

PrefaceThis document defines the PowerPC User InstructionSet Architecture. It covers the base instruction set andrelated facilities available to the application program-mer.

Other related documents define the PowerPC VirtualEnvironment Architecture, the PowerPC OperatingEnvironment Architecture, and PowerPC Implementa-tion Features. Book II, PowerPC Virtual Environment Architecture defines the storage model and relatedinstructions and facilities available to the applicationprogrammer, and the time-keeping facilities available tothe application programmer. Book III, PowerPC Oper- ating Environment Architecture defines the system(privileged) instructions and related facilities. Book IV,PowerPC Implementation Features defines the imple-mentation-dependent aspects of a particular implemen-tation.

As used in this document, the term PowerPC Architec-ture refers to the instructions and facilities described inBooks I, II, and III. The description of the instantiation ofthe PowerPC Architecture in a given implementationincludes also the material in Book IV for that implemen-tation.

Note: Change bars indicate changes from Version2.01.


4/230

Version 2.02

iv PowerPC User Instruction Set Architecture


5/230

Table of Contents v

Version 2.02

Table of Contents

Chapter 1. Introduction . . . . . . . . . . 11.1 Overview. . . . . . . . . . . . . . . . . . . . . . 11.2 Computation modes . . . . . . . . . . . . . 11.3 Instruction Mnemonics and Operands11.4 Compatibility with the POWER Archi-

tecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.5 Document Conventions . . . . . . . . . . 21.5.1 Definitions and Notation. . . . . . . . . 21.5.2 Reserved Fields and Reserved Val-

ues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.5.3 Description of Instruction Operation 41.6 Processor Overview . . . . . . . . . . . . . 61.7 Instruction formats . . . . . . . . . . . . . . 71.7.1 I-Form . . . . . . . . . . . . . . . . . . . . . . 81.7.2 B-Form. . . . . . . . . . . . . . . . . . . . . . 81.7.3 SC-Form . . . . . . . . . . . . . . . . . . . . 81.7.4 D-Form . . . . . . . . . . . . . . . . . . . . . 81.7.5 DS-FORM . . . . . . . . . . . . . . . . . . . 81.7.6 X-FORM . . . . . . . . . . . . . . . . . . . . 91.7.7 XL-FORM . . . . . . . . . . . . . . . . . . . 91.7.8 XFX-FORM . . . . . . . . . . . . . . . . . . 91.7.9 XFL-FORM . . . . . . . . . . . . . . . . . . 91.7.10 XS-FORM . . . . . . . . . . . . . . . . . . 9

1.7.11 XO-FORM . . . . . . . . . . . . . . . . . . 91.7.12 A-FORM . . . . . . . . . . . . . . . . . . 101.7.13 M-FORM . . . . . . . . . . . . . . . . . . 101.7.14 MD-FORM . . . . . . . . . . . . . . . . . 101.7.15 MDS-FORM. . . . . . . . . . . . . . . . 101.7.16 Instruction Fields . . . . . . . . . . . . 101.8 Classes of Instructions . . . . . . . . . . 121.8.1 Defined Instruction Class. . . . . . . 121.8.2 Illegal Instruction Class . . . . . . . . 121.8.3 Reserved Instruction Class . . . . . 121.9 Forms of Defined Instructions. . . . . 131.9.1 Preferred Instruction Forms . . . . . 131.9.2 Invalid Instruction Forms . . . . . . . 13

1.10 Optionality. . . . . . . . . . . . . . . . . . . 141.11 Exceptions . . . . . . . . . . . . . . . . . . 141.12 Storage Addressing . . . . . . . . . . . 141.12.1 Storage Operands . . . . . . . . . . . 141.12.2 Effective Address Calculation . . 15

Chapter 2. Branch Processor . . . . 172.1 Branch Processor Overview . . . . . . 172.2 Instruction Execution Order . . . . . . 172.3 Branch Processor Registers. . . . . . 18

2.3.1 Condition Register . . . . . . . . . . . . 182.3.2 Link Register . . . . . . . . . . . . . . . . 192.3.3 Count Register . . . . . . . . . . . . . . . 192.4 Branch Processor Instructions . . . . 202.4.1 Branch Instructions . . . . . . . . . . . 202.4.2 System Call Instruction . . . . . . . . 262.4.3 Condition Register Logical Instruc-

tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272.4.4 Condition Register Field

Instruction . . . . . . . . . . . . . . . . . . . . . . . 30

Chapter 3. Fixed-Point Processor . 313.1 Fixed-Point Processor Overview. . . 313.2 Fixed-Point Processor

Registers . . . . . . . . . . . . . . . . . . . . . . . . 313.2.1 General Purpose Registers . . . . . 313.2.2 Fixed-Point Exception Register . . 323.3 Fixed-Point Processor Instructions . 333.3.1 Fixed-Point Storage Access Instruc-

tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333.3.1.1 Storage Access Exceptions. . . . 333.3.2 Fixed-Point Load Instructions. . . . 333.3.3 Fixed-Point Store Instructions . . . 403.3.4 Fixed-Point Load and Store with Byte

Reversal Instructions . . . . . . . . . . . . . . . 443.3.5 Fixed-Point Load and Store Multiple

Instructions . . . . . . . . . . . . . . . . . . . . . . 463.3.6 Fixed-Point Move Assist Instruc-

tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473.3.7 Other Fixed-Point Instructions . . . 503.3.8 Fixed-Point Arithmetic Instructions513.3.9 Fixed-Point Compare Instructions 603.3.10 Fixed-Point Trap Instructions . . . 623.3.11 Fixed-Point Logical Instructions . 653.3.12 Fixed-Point Rotate and Shift

Instructions . . . . . . . . . . . . . . . . . . . . . . 71

3.3.12.1 Fixed-Point Rotate Instructions 713.3.12.2 Fixed-Point Shift Instructions . 773.3.13 Move To/From System Register

Instructions . . . . . . . . . . . . . . . . . . . . . . 81

Chapter 4. Floating-Point Processor.85

4.1 Floating-Point Processor Overview. 854.2 Floating-Point Processor Registers. 86


6/230

Version 2.02

vi PowerPC User Instruction Set Architecture

4.2.1 Floating-Point Registers . . . . . . . .864.2.2 Floating-Point Status and Control

Register . . . . . . . . . . . . . . . . . . . . . . . . .874.3 Floating-Point Data . . . . . . . . . . . . .894.3.1 Data Format . . . . . . . . . . . . . . . . .894.3.2 Value Representation . . . . . . . . . .904.3.3 Sign of Result . . . . . . . . . . . . . . . .914.3.4 Normalization and

Denormalization . . . . . . . . . . . . . . . . . . .924.3.5 Data Handling and Precision. . . . .924.3.5.1 Single-Precision Operands . . . .924.3.5.2 Integer-Valued Operands . . . . . .934.3.6 Rounding. . . . . . . . . . . . . . . . . . . .934.4 Floating-Point Exceptions . . . . . . . .944.4.1 Invalid Operation Exception . . . . .964.4.1.1 Definition . . . . . . . . . . . . . . . . . .964.4.1.2 Action . . . . . . . . . . . . . . . . . . . . .974.4.2 Zero Divide Exception. . . . . . . . . .974.4.2.1 Definition . . . . . . . . . . . . . . . . . .974.4.2.2 Action . . . . . . . . . . . . . . . . . . . . .97

4.4.3 Overflow Exception . . . . . . . . . . . .984.4.3.1 Definition . . . . . . . . . . . . . . . . . .984.4.3.2 Action . . . . . . . . . . . . . . . . . . . . .984.4.4 Underflow Exception . . . . . . . . . . .984.4.4.1 Definition . . . . . . . . . . . . . . . . . .984.4.4.2 Action . . . . . . . . . . . . . . . . . . . . .984.4.5 Inexact Exception . . . . . . . . . . . . .994.4.5.1 Definition . . . . . . . . . . . . . . . . . .994.4.5.2 Action . . . . . . . . . . . . . . . . . . . . .994.5 Floating-Point Execution Models . .1004.5.1 Execution Model for IEEE Opera-

tions . . . . . . . . . . . . . . . . . . . . . . . . . . .1004.5.2 Execution Model for

Multiply-Add Type Instructions . . . . . . .1014.6 Floating-Point Processor Instructions .103

4.6.1 Floating-Point Storage AccessInstructions . . . . . . . . . . . . . . . . . . . . . .103

4.6.1.1 Storage Access Exceptions . . .1034.6.2 Floating-Point Load Instructions .1034.6.3 Floating-Point Store Instructions .1064.6.4 Floating-Point Move Instructions.1104.6.5 Floating-Point Arithmetic Instructions

1114.6.5.1 Floating-Point Elementary Arith-

metic Instructions . . . . . . . . . . . . . . . . . 1114.6.5.2 Floating-Point Multiply-Add Instruc-

tions . . . . . . . . . . . . . . . . . . . . . . . . . . .1134.6.6 Floating-Point Rounding and Con-

version Instructions. . . . . . . . . . . . . . . .1154.6.7 Floating-Point Compare Instructions.

1194.6.8 Floating-Point Status and Control

Register Instructions. . . . . . . . . . . . . . .120

Chapter 5. Optional Facilities andInstructions . . . . . . . . . . . . . . . . . . 123

5.1 Fixed-Point Processor Instructions 1245.1.1 Move To/From System Register

Instructions . . . . . . . . . . . . . . . . . . . . . 1245.2 Floating-Point Processor Instructions.

1245.2.1 Floating-Point Arithmetic Instructions125

5.2.1.1 Floating-Point Elementary Arith-metic Instructions . . . . . . . . . . . . . . . . 125

5.2.2 Floating-Point Select Instruction 1265.3 Little-Endian . . . . . . . . . . . . . . . . . 1275.3.1 Byte Ordering . . . . . . . . . . . . . . 1275.3.2 Structure Mapping Examples. . . 1275.3.2.1 Big-Endian Mapping . . . . . . . . 1275.3.2.2 Little-Endian Mapping. . . . . . . 1285.3.3 PowerPC Byte Ordering . . . . . . 1285.3.3.1 Controlling PowerPC Byte Order-

ing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1285.3.3.2 PowerPC Little-Endian Byte Order-

ing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1285.3.4 PowerPC Data Addressing in Little-

Endian Mode. . . . . . . . . . . . . . . . . . . . 1305.3.4.1 Individual Aligned Scalars . . . 1305.3.4.2 Other Scalars . . . . . . . . . . . . . 1305.3.4.3 Page Table . . . . . . . . . . . . . . . 1315.3.5 PowerPC Instruction Addressing in

Little-Endian Mode . . . . . . . . . . . . . . . 1315.3.6 PowerPC Cache

Management Instructions inLittle-Endian Mode . . . . . . . . . . . . . . . 133

5.3.7 PowerPC I/O inLittle-Endian Mode . . . . . . . . . . . . . . . 133

5.3.8 Origin of Endian. . . . . . . . . . . . . 133

Chapter 6. Optional Facilities andInstructions that are being PhasedOut . . . . . . . . . . . . . . . . . . . . . . . . . 135

6.1 Move To Condition Register fromXER. . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Appendix A. Suggested Floating-Point Models . . . . . . . . . . . . . . . . . 137

A.1 Floating-Point Round to Single-Preci-sion Model. . . . . . . . . . . . . . . . . . . . . . 137

A.2 Floating-Point Convert to IntegerModel . . . . . . . . . . . . . . . . . . . . . . . . . 142

A.3 Floating-Point Convert from IntegerModel . . . . . . . . . . . . . . . . . . . . . . . . . 145

Appendix B. Assembler ExtendedMnemonics . . . . . . . . . . . . . . . . . . 151

B.1 Symbols . . . . . . . . . . . . . . . . . . . . 151


7/230

Table of Contents vii

Version 2.02

B.2 Branch Mnemonics . . . . . . . . . . . 152B.2.1 BO and BI Fields . . . . . . . . . . . . 152B.2.2 Simple Branch Mnemonics . . . . 152B.2.3 Branch Mnemonics Incorporating

Conditions . . . . . . . . . . . . . . . . . . . . . . 153B.2.4 Branch Prediction . . . . . . . . . . . 154B.3 Condition Register Logical Mnemonics

155B.4 Subtract Mnemonics . . . . . . . . . . 155B.4.1 Subtract Immediate . . . . . . . . . . 155B.4.2 Subtract. . . . . . . . . . . . . . . . . . . 156B.5 Compare Mnemonics . . . . . . . . . . 156B.5.1 Doubleword Comparisons . . . . . 157B.5.2 Word Comparisons . . . . . . . . . . 157B.6 Trap Mnemonics. . . . . . . . . . . . . . 158B.7 Rotate and Shift Mnemonics . . . . 159B.7.1 Operations on Doublewords . . . 159B.7.2 Operations on Words . . . . . . . . 160B.8 Move To/From Special Purpose Regis-

ter Mnemonics . . . . . . . . . . . . . . . . . . 162

B.9 Miscellaneous Mnemonics . . . . . . 162

Appendix C. Programming Examples167

C.1 Multiple-Precision Shifts. . . . . . . . 167C.2 Floating-Point Conversions . . . . . 170C.2.1 Conversion from

Floating-Point Number toFloating-Point Integer . . . . . . . . . . . . . 170

C.2.2 Conversion fromFloating-Point Number to Signed Fixed-Point Integer Doubleword . . . . . . . . . . 170

C.2.3 Conversion fromFloating-Point Number to Unsigned Fixed-Point Integer Doubleword . . . . . . . . . . 170

C.2.4 Conversion fromFloating-Point Number to Signed Fixed-Point Integer Word . . . . . . . . . . . . . . . 170

C.2.5 Conversion fromFloating-Point Number to Unsigned Fixed-Point Integer Word . . . . . . . . . . . . . . . 171

C.2.6 Conversion from Signed Fixed-PointInteger Doubleword to Floating-Point Num-ber. . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

C.2.7 Conversion from Unsigned Fixed-Point Integer Doubleword to Floating-Point

Number . . . . . . . . . . . . . . . . . . . . . . . . 171C.2.8 Conversion from Signed Fixed-PointInteger Word to Floating-Point Number 171

C.2.9 Conversion from Unsigned Fixed-Point Integer Word to Floating-Point Num-ber. . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

C.3 Floating-Point Selection . . . . . . . . 172C.3.1 Comparison to Zero . . . . . . . . . 172C.3.2 Minimum and Maximum . . . . . . 172

C.3.3 Simple if-then-elseConstructions. . . . . . . . . . . . . . . . . . . . 172

C.3.4 Notes . . . . . . . . . . . . . . . . . . . . . 172

Appendix D. Cross-Reference forChanged POWER Mnemonics . . . 173

Appendix E. Incompatibilities withthe POWER Architecture . . . . . . . . 175

E.1 New Instructions, Formerly PrivilegedInstructions . . . . . . . . . . . . . . . . . . . . . 175

E.2 Newly PrivilegedInstructions . . . . . . . . . . . . . . . . . . . . . 175

E.3 Reserved Fields inInstructions . . . . . . . . . . . . . . . . . . . . . 175

E.4 Reserved Bits in Registers . . . . . . 175E.5 Alignment Check. . . . . . . . . . . . . . 175E.6 Condition Register . . . . . . . . . . . . 176E.7 LK and Rc Bits . . . . . . . . . . . . . . . 176E.8 BO Field . . . . . . . . . . . . . . . . . . . . 176E.9 BH Field . . . . . . . . . . . . . . . . . . . . 176E.10 Branch Conditional to Count Register

176E.11 System Call. . . . . . . . . . . . . . . . . 176E.12 Fixed-Point Exception

Register (XER) . . . . . . . . . . . . . . . . . . 177E.13 Update Forms of Storage Access

Instructions . . . . . . . . . . . . . . . . . . . . . 177E.14 Multiple Register Loads . . . . . . . 177E.15 Load/Store Multiple Instructions . 177E.16 Move Assist Instructions. . . . . . . 178E.17 Move To/From SPR . . . . . . . . . . 178

E.18 Effects of Exceptions on FPSCR BitsFR and FI. . . . . . . . . . . . . . . . . . . . . . . 178E.19 Store Floating-Point Single Instruc-

tions . . . . . . . . . . . . . . . . . . . . . . . . . . . 178E.20 Move From FPSCR . . . . . . . . . . 178E.21 Zeroing Bytes in the Data Cache 178E.22 Synchronization . . . . . . . . . . . . . 179E.23 Move To Machine State Register

Instruction . . . . . . . . . . . . . . . . . . . . . . 179E.24 Direct-Store Segments . . . . . . . . 179E.25 Segment Register

Manipulation Instructions. . . . . . . . . . . 179E.26 TLB Entry Invalidation. . . . . . . . . 179E.27 Alignment Interrupts . . . . . . . . . . 179E.28 Floating-Point Interrupts . . . . . . . 179E.29 Timing Facilities . . . . . . . . . . . . . 180E.29.1 Real-Time Clock . . . . . . . . . . . 180E.29.2 Decrementer . . . . . . . . . . . . . . 180E.30 Deleted Instructions . . . . . . . . . . 181E.31 Discontinued Opcodes . . . . . . . . 181E.32 POWER2 Compatibility. . . . . . . . 181E.32.1 Cross-Reference for Changed

POWER2 Mnemonics . . . . . . . . . . . . . 182


8/230

Version 2.02

viii PowerPC User Instruction Set Architecture

E.32.2 Floating-Point Conversion to Inte-ger . . . . . . . . . . . . . . . . . . . . . . . . . . . .182

E.32.3 Floating-Point Interrupts . . . . . .182E.32.4 Trace. . . . . . . . . . . . . . . . . . . . .182E.32.5 Deleted Instructions . . . . . . . . .183E.32.6 Discontinued Opcodes . . . . . . .183

Appendix F. New Instructions . . . 185

Appendix G. Illegal Instructions . 187

Appendix H. Reserved Instructions .189

Appendix I. Opcode Maps . . . . . . 191

Appendix J. PowerPC Instruction SetSorted by Opcode . . . . . . . . . . . . . 203

Appendix K. PowerPC InstructionSet Sorted by Mnemonic . . . . . . . 209


9/230

Figures ix

Version 2.02

Figures1. Logical processing mode. . . . . . . . . . . . . . . . . . . 62. Power PC user register set . . . . . . . . . . . . . . . . . 73. I instruction format. . . . . . . . . . . . . . . . . . . . . . . . 84. B instruction format . . . . . . . . . . . . . . . . . . . . . . . 85. SC instruction format. . . . . . . . . . . . . . . . . . . . . . 86. D instruction format . . . . . . . . . . . . . . . . . . . . . . . 87. DS instruction format. . . . . . . . . . . . . . . . . . . . . . 88. X instruction format . . . . . . . . . . . . . . . . . . . . . . . 99. XL instruction format . . . . . . . . . . . . . . . . . . . . . . 910. XFX instruction format. . . . . . . . . . . . . . . . . . . . 911. XFL instruction format . . . . . . . . . . . . . . . . . . . . 912. XS instruction format . . . . . . . . . . . . . . . . . . . . . 913. XO instruction format. . . . . . . . . . . . . . . . . . . . . 914. A instruction format . . . . . . . . . . . . . . . . . . . . . 1015. M instruction format. . . . . . . . . . . . . . . . . . . . . 1016. MD instruction format . . . . . . . . . . . . . . . . . . . 1017. MDS instruction format . . . . . . . . . . . . . . . . . . 1018. Condition Register. . . . . . . . . . . . . . . . . . . . . . 1819. Link Register . . . . . . . . . . . . . . . . . . . . . . . . . . 1920. Count Register . . . . . . . . . . . . . . . . . . . . . . . . 1921. BO field encodings . . . . . . . . . . . . . . . . . . . . . 2022. at bit encodings. . . . . . . . . . . . . . . . . . . . . . . 2023. BH field encodings . . . . . . . . . . . . . . . . . . . . . 2124. General Purpose Registers . . . . . . . . . . . . . . . 31

25. Fixed-Point Exception Register . . . . . . . . . . . . 3226. Priority hint levels for or Rx,Rx,Rx. . . . . . . . . . 6527. Floating-Point Registers . . . . . . . . . . . . . . . . . 8728. Floating-Point Status and Control Register . . . 8729. Floating-Point Result Flags . . . . . . . . . . . . . . . 8930. Floating-point single format . . . . . . . . . . . . . . . 9031. Floating-point double format . . . . . . . . . . . . . . 9032. IEEE floating-point fields . . . . . . . . . . . . . . . . . 9033. Approximation to real numbers . . . . . . . . . . . . 9034. Selection of Z1 and Z2 . . . . . . . . . . . . . . . . . . 9435. IEEE 64-bit execution model . . . . . . . . . . . . . 10036. Interpretation of G, R, and X bits. . . . . . . . . . 10037. Location of the Guard, Round, and

Sticky bits in the IEEE execution model. . . 101

38. Multiply-add 64-bit execution model . . . . . . . 10139. Location of the Guard, Round, and Sticky bits in themultiply-add execution model . . . . . . . . . . 102

40. C structure s , showing values of elements . 12841. Big-Endian mapping of structure s . . . . . . . . 12842. Little-Endian mapping of structure s . . . . . . 12843. PowerPC Little-Endian, structure s

in storage subsystem. . . . . . . . . . . . . . . . . 12944. PowerPC Little-Endian, structure s

as seen by processor. . . . . . . . . . . . . . . . . 130

45. Little-Endian mapping of word w stored at address 5. . . . . . . . . . . . . . . . . . . 131

46. PowerPC Little-Endian, word w stored at address 5 in storage subsystem . 131

47. Assembly language program p. . . . . . . . . . . 13148. Big-Endian mapping of program p . . . . . . . . 13249. Little-Endian mapping of program p . . . . . . . 13250. PowerPC Little-Endian, program p

in storage subsystem . . . . . . . . . . . . . . . . . 132


10/230

Version 2.02

x PowerPC User Instruction Set Architecture


11/230

Chapter 1. Introduction 1

Version 2.02

Chapter 1. Introduction

1.1 Overview. . . . . . . . . . . . . . . . . . . . . . 11.2 Computation modes . . . . . . . . . . . . . 11.3 Instruction Mnemonics and Operands11.4 Compatibility with the POWER Archi-

tecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.5 Document Conventions . . . . . . . . . . 21.5.1 Definitions and Notation. . . . . . . . . 21.5.2 Reserved Fields and Reserved Val-

ues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.5.3 Description of Instruction Operation 41.6 Processor Overview . . . . . . . . . . . . . 61.7 Instruction formats . . . . . . . . . . . . . . 71.7.1 I-Form . . . . . . . . . . . . . . . . . . . . . . 81.7.2 B-Form. . . . . . . . . . . . . . . . . . . . . . 81.7.3 SC-Form . . . . . . . . . . . . . . . . . . . . 81.7.4 D-Form . . . . . . . . . . . . . . . . . . . . . 81.7.5 DS-FORM . . . . . . . . . . . . . . . . . . . 81.7.6 X-FORM . . . . . . . . . . . . . . . . . . . . 91.7.7 XL-FORM . . . . . . . . . . . . . . . . . . . 91.7.8 XFX-FORM . . . . . . . . . . . . . . . . . . 91.7.9 XFL-FORM . . . . . . . . . . . . . . . . . . 9

1.7.10 XS-FORM. . . . . . . . . . . . . . . . . . . 91.7.11 XO-FORM. . . . . . . . . . . . . . . . . . . 91.7.12 A-FORM. . . . . . . . . . . . . . . . . . . 101.7.13 M-FORM . . . . . . . . . . . . . . . . . . 101.7.14 MD-FORM . . . . . . . . . . . . . . . . . 101.7.15 MDS-FORM . . . . . . . . . . . . . . . . 101.7.16 Instruction Fields . . . . . . . . . . . . 101.8 Classes of Instructions . . . . . . . . . . 121.8.1 Defined Instruction Class . . . . . . . 121.8.2 Illegal Instruction Class . . . . . . . . 121.8.3 Reserved Instruction Class . . . . . 121.9 Forms of Defined Instructions . . . . . 131.9.1 Preferred Instruction Forms . . . . . 131.9.2 Invalid Instruction Forms . . . . . . . 131.10 Optionality . . . . . . . . . . . . . . . . . . . 141.11 Exceptions. . . . . . . . . . . . . . . . . . . 141.12 Storage Addressing. . . . . . . . . . . . 141.12.1 Storage Operands . . . . . . . . . . . 141.12.2 Effective Address Calculation. . . 15

1.1 OverviewThis chapter describes computation modes, compatibil-ity with the POWER Architecture, document conven-tions, a processor overview, instruction formats,storage addressing, and instruction fetching.

1.2 Computation modesProcessors provide two execution environments, 32-bitand 64-bit. In both of these environments (modes),instructions that set a 64-bit register affect all 64 bits,and the value placed into the register is independent ofmode.

1.3 Instruction Mnemonics andOperandsThe description of each instruction includes the mne-monic and a formatted list of operands. Some exam-ples are the following.

stw RS,D(RA)addis RT,RA,SI

PowerPC-compliant Assemblers will support the mne-

monics and operand lists exactly as shown. Theyshould also provide certain extended mnemonics, asdescribed in Appendix B, Assembler Extended Mne-monics on page 151.


12/230

Version 2.02

2 PowerPC User Instruction Set Architecture

1.4 Compatibility with thePOWER ArchitectureThe PowerPC Architecture provides binary compatibil-ity for POWER application programs, except asdescribed in Appendix E, Incompatibilities with the

POWER Architecture on page 175 .

Many of the PowerPC instructions are identical toPOWER instructions. For some of these the PowerPCinstruction name and/or mnemonic differs from that inPOWER. To assist readers familiar with the POWERArchitecture, POWER mnemonics are shown with theindividual instruction descriptions when they differ fromthe PowerPC mnemonics. Also, Appendix D,Cross-Reference for Changed POWER Mnemonics on page 173 provides a cross-reference from POWERmnemonics to PowerPC mnemonics for the instruc-tions in Books I, II, and III.

References to the POWER Architecture includePOWER2 implementations of the POWER Architectureunless otherwise stated.

1.5 Document Conventions

1.5.1 Definitions and Notation

The following definitions and notation are usedthroughout the PowerPC Architecture documents.

1 A program is a sequence of related instructions.1 An application program is a program that uses only

the instructions and resources described in BooksI and II.

1 Quadwords are 128 bits, doublewords are 64 bits,words are 32 bits, halfwords are 16 bits, and bytesare 8 bits.

1 All numbers are decimal unless specified in somespecial way.

- 0bnnnn means a number expressed in binaryformat.

- 0xnnnn means a number expressed in hexa-decimal format.

Underscores may be used between digits.1 RT, RA, R1, ... refer to General Purpose Registers.1 FRT, FRA, FR1, ... refer to Floating-Point Regis-

ters.1 (x) means the contents of register x, where x is the

name of an instruction field. For example, (RA)means the contents of register RA, and (FRA)means the contents of register FRA, where RA andFRA are instruction fields. Names such as LR andCTR denote registers, not fields, so parentheses

are not used with them. Parentheses are alsoomitted when register x is the register into whichthe result of an operation is placed.

1 (RA|0) means the contents of register RA if the RAfield has the value 1-31, or the value 0 if the RAfield is 0.

1

Bits in registers, instructions, and fields are speci-fied as follows.

- Bits are numbered left to right, starting with bit0.

- Ranges of bits are specified by two numbersseparated by a colon (:). The range p:q con-sists of bits p through q.

1 Xp means bit p of register/field X.1 Xp:q means bits p through q of register/field X.1 Xp q ... means bits p, q, ... of register/field X.1 (RA) means the one s complement of the con-

tents of register RA.1 Field i refers to bits 4 1 i through 4 1 i +3 of a regis-

ter.1 A period (.) as the last character of an instruction

mnemonic means that the instruction records sta-tus information in certain fields of the ConditionRegister as a side effect of execution, as describedin Chapter 2 through Chapter 4.

1 The symbol || is used to describe the concatena-tion of two values. For example, 010 || 111 is thesame as 010111.

1 xn means x raised to the n th power.1 nx means the replication of x, n times (i.e., x con-

catenated to itself n - 1 times). (n)0 and (n)1 arespecial cases:

- n0 means a field of n bits with each bit equal to0. Thus 50 is equivalent to 0b00000.

- n1 means a field of n bits with each bit equal to1. Thus 51 is equivalent to 0b11111.

1 Floating-point single format or simply single formatis used to refer to the representation of a sin-gle-precision binary floating-point value in a regis-ter or storage.

1 Floating-point double format or simply double for-mat is used to refer to the representation of a dou-ble-precision binary floating-point value in aregister or storage.

1 Positive means greater than zero.1 Negative means less than zero.1 A system library program is a component of the

system software that can be called by an applica-tion program using a Branch instruction.


13/230


Version 2.02

1 A system service program is a component of thesystem software that can be called by an applica-tion program using a System Call instruction.

1 The system trap handler is a component of thesystem software that receives control when theconditions specified in a Trap instruction are satis-fied.

1 The system error handler is a component of thesystem software that receives control when anerror occurs. The system error handler includes acomponent for each of the various kinds of error.These error-specific components are referred to asthe system alignment error handler, the systemdata storage error handler, etc.

1 Each bit and field in instructions, and in status andcontrol registers (e.g., XER, FPSCR) and SpecialPurpose Registers, is either defined or reserved.

1 /, //, ///, ... denotes a reserved field in an instruc-tion.

1 Latency refers to the interval from the time aninstruction begins execution until it produces aresult that is available for use by a subsequentinstruction.

1 Unavailable refers to a resource that cannot beused by the program. For example, storage isunavailable if access to it is denied. See Book III,PowerPC Operating Environment Architecture .

1 A value that is specified as being undefined mayvary between implementations, and between dif-ferent executions on the same implementation,and similarly for register contents, storage con-tents, etc., that are specified as being undefined.

1 The results of executing a given instruction aresaid to be boundedly undefined if they could havebeen achieved by executing an arbitrary finitesequence of instructions (none of which yieldsboundedly undefined results) in the state the pro-cessor was in before executing the given instruc-tion. Boundedly undefined results may include thepresentation of inconsistent state to the systemerror handler as described in the section entitledConcurrent Modification and Execution of Instruc-tions in Book II. Boundedly undefined results for agiven instruction may vary between implementa-tions, and between different executions on thesame implementation.

1 The sequential execution model is the model ofprogram execution described in Section 2.2,Instruction Execution Order on page 17 .

1.5.2 Reserved Fields andReserved Values

Reserved fields in instructions are ignored by the pro-cessor.

In some cases a defined field of an instruction has cer-tain values that are reserved. This includes cases inwhich the field is shown in the instruction layout as con-taining a particular value; in such cases all other valuesof the field are reserved. In general, if an instruction iscoded such that a defined field contains a reservedvalue the instruction form is invalid; see Section 1.9.2

on page 13. The only exception to the preceding rule isthat it does not apply to portions of defined fields thatare specified, in the instruction description, as beingtreated as a reserved field. References elsewhere inBooks I - III to a defined field that has reserved valuesassume the field does not contain a reserved value,unless otherwise stated or obvious from context.

To maximize compatibility with future architectureextensions, software must ensure that reserved fieldsin instructions contain zero and that defined fields ofinstructions do not contain reserved values.

The handling of reserved bits in System Registers (e.g.,

XER, FPSCR) is implementation-dependent. Unlessotherwise stated, software is permitted to write anyvalue to such a bit. A subsequent reading of the bitreturns 0 if the value last written to the bit was 0 andreturns an undefined value (0 or 1) otherwise.

Assemblers should report uses of reserved valuesof defined fields of instructions as errors.

Assembler Note


14/230

Version 2.02


1.5.3 Description of InstructionOperation

A formal description is given of the operation of eachinstruction. In addition, the operation of most instruc-

tions is described by a semiformal language at the reg-ister transfer level (RTL). This RTL uses the notationgiven below, in addition to the definitions and notationdescribed in Section 1.5.1, Definitions and Notation on page 2 . Some of this notation is also used in the for-mal descriptions of instructions. RTL notation not sum-marized here should be self-explanatory.

The RTL descriptions cover the normal execution of theinstruction, except that standard setting of the Condi-tion Register, Fixed-Point Exception Register, andFloating-Point Status and Control Register are notshown. ( Non-standard setting of these registers,such as the setting of the Condition Register by the

Compare instructions, is shown.) The RTL descriptionsdo not cover cases in which the system error handler isinvoked, or for which the results are boundedly unde-fined.

The RTL descriptions specify the architectural transfor-mation performed by the execution of an instruction.They do not imply any particular implementation.

Notation Meaning

1 Assignment1

iea Assignment of an instruction effectiveaddress. In 32-bit mode the high-order 32bits of the 64-bit target address are set to0.

NOT logical operator+ Twos complement addition

- Twos complement subtraction, unaryminus1 Multiplication2 Division (yielding quotient)1 Square root=, 3 Equals, Not Equals relations, 5 Signed comparison relationsu Unsigned comparison relations? Unordered comparison relation&, | AND, OR logical operators6 , 7 Exclusive OR, Equivalence logical opera-

tors ((a 7 b) = (a 6 b))ABS(x) Absolute value of xCEIL(x) Least integer > x 4

DOUBLE(x) Result of converting x from floating-pointsingle format to floating-point double for-mat, using the model shown on page 103

EXTS(x) Result of extending x on the left with signbits

FLOOR(x) Greatest integer 4 xGPR(x) General Purpose Register xMASK(x, y) Mask having 1s in positions x through y

(wrapping if x > y) and 0s elsewhereMEM(x, y) Contents of y bytes of storage starting at

address x. In 32-bit mode the high-order32 bits of the 64-bit value x are ignored.

ROTL64(x, y)Result of rotating the 64-bit value x left ypositions

ROTL32(x, y)Result of rotating the 64-bit value x||x left ypositions, where x is 32 bits long

SINGLE(x) Result of converting x from floating-pointdouble format to floating-point single for-mat, using the model shown on page 106

SPREG(x) Special Purpose Register xTRAP Invoke the system trap handlercharacterization

Reference to the setting of status bits, in astandard way that is explained in the text

undefined An undefined value.CIA Current Instruction Address, which is the

64-bit address of the instruction beingdescribed by a sequence of RTL. Used byrelative branches to set the Next Instruc-tion Address (NIA), and by Branch instruc-tions with LK=1 to set the Link Register. In32-bit mode the high-order 32 bits of CIAare always set to 0. Does not correspondto any architected register.

NIA Next Instruction Address, which is the64-bit address of the next instruction to beexecuted. For a successful branch, the

It is the responsibility of software to preserve bitsthat are now reserved in System Registers,because they may be assigned a meaning in somefuture version of the architecture.

In order to accomplish this preservation in imple-

mentation-independent fashion, software should dothe following.

1 Initialize each such register supplying zeros forall reserved bits.

1 Alter (defined) bit(s) in the register by readingthe register, altering only the desired bit(s),and then writing the new value back to the reg-ister.

The XER and FPSCR are partial exceptions to thisrecommendation. Software can alter the status bitsin these registers, preserving the reserved bits, byexecuting instructions that have the side effect ofaltering the status bits. Similarly, software can alter

any defined bit in the FPSCR by executing a Float-ing-Point Status and Control Register instruction.Using such instructions is likely to yield better per-formance than using the method described in thesecond item above.

Programming Note


15/230


Version 2.02

next instruction address is the branch tar-get address: in RTL, this is indicated byassigning a value to NIA. For otherinstructions that cause non-sequentialinstruction fetching (see Book III, Pow- erPC Operating Environment Architec- ture ), the RTL is similar. For instructions

that do not branch, and do not otherwisecause instruction fetching to benon-sequential, the next instructionaddress is CIA+4. In 32-bit mode thehigh-order 32 bits of NIA are always set to0. Does not correspond to any architectedregister.

if... then... else...Conditional execution, indenting showsrange; else is optional.

do Do loop, indenting shows range. To and/ or by clauses specify incrementing aniteration variable, and a while clausegives termination conditions.

leave Leave innermost do loop, or do loopdescribed in leave statement.for For loop, indenting shows range. Clause

after for specifies the entities for which toexecute the body of the loop.

The precedence rules for RTL operators are summa-rized in Table 1 . Operators higher in the table areapplied before those lower in the table. Operators atthe same level in the table associate from left to right,from right to left, or not at all, as shown. (For example,- associates from left to right, so a - b- c = (a - b)- c.)Parentheses are used to override the evaluation orderimplied by the table or to increase clarity; parenthe-sized expressions are evaluated before serving asoperands.

Table 1: Operator precedenceOperators Associativity

subscript, function evaluation left to rightpre-superscript (replication),

post-superscript (exponentiation)right to left

unary - , right to left 1 , 2 left to right+, - , left to right|| left to right

=, 3 , , 5 ,

u, ? left to right

&, 6 , 7 left to right| left to right: (range) none1 none


16/230

Version 2.02


1.6 Processor OverviewThe processor implements the instruction set, the stor-age model, and other facilities defined in this docu-ment. Instructions that the processor can execute fallinto three classes:

1 branch instructions1 fixed-point instructions1 floating-point instructions

Branch instructions are described in Section 2.4,Branch Processor Instructions on page 20 .Fixed-point instructions are described in Section 3.3,Fixed-Point Processor Instructions on page 33 . Float-ing-point instructions are described in Section 4.6,Floating-Point Processor Instructions on page 103 .

Fixed-point instructions operate on byte, halfword,word, and doubleword operands. Floating-pointinstructions operate on single-precision and dou-

ble-precision floating-point operands. The PowerPCArchitecture uses instructions that are four bytes longand word-aligned. It provides for byte, halfword, word,and doubleword operand fetches and stores betweenstorage and a set of 32 General Purpose Registers(GPRs). It also provides for word and doublewordoperand fetches and stores between storage and a setof 32 Floating-Point Registers (FPRs).

Signed integers are represented in two s complementform.

There are no computational instructions that modifystorage. To use a storage operand in a computationand then modify the same or another storage location,the contents of the storage operand must be loadedinto a register, modified, and then stored back to thetarget location. Figure 1 is a logical representation ofinstruction processing. Figure 2 shows the registers ofthe PowerPC User Instruction Set Architecture.

Figure 1. Logical processing mode

BranchProcessing

Storage

Float-PtProcessing

Fixed-PtProcessing

Fixed-Point and

Floating-PointInstructions

Data to/fromStorage

Instructionsfrom Storage


17/230


Version 2.02

Condition Register on page 18

Link Register on page 19

Count Register on page 19

General Purpose Registers on page 31

Fixed-Point Exception Register on page 32

Floating-Point Registers on page 87

Floating-Point Status and Control Register onpage 87

Figure 2. Power PC user register set

1.7 Instruction formatsAll instructions are four bytes long and word-aligned.Thus, whenever instruction addresses are presented tothe processor (as in Branch instructions) the low-ordertwo bits are ignored. Similarly, whenever the processordevelops an instruction address the low-order two bitsare zero.

Bits 0:5 always specify the opcode (OPCD, below).Many instructions also have an extended opcode (XO,below). The remaining bits of the instruction containone or more fields as shown below for the differentinstruction formats.

The format diagrams given below show horizontally allvalid combinations of instruction fields. The diagramsinclude instruction fields that are used only by instruc-tions defined in Book II, PowerPC Virtual Environment Architecture , or in Book III, PowerPC Operating Envi- ronment Architecture .

Split Field Notation

In some cases an instruction field occupies more thanone contiguous sequence of bits, or occupies one con-tiguous sequence of bits that are used in permutedorder. Such a field is called a split field . In the formatdiagrams given below and in the individual instructionlayouts, the name of a split field is shown in small let-ters, once for each of the contiguous sequences. In theRTL description of an instruction having a split field,and in certain other places where individual bits of asplit field are identified, the name of the field in smallletters represents the concatenation of the sequences

from left to right. In all other places, the name of thefield is capitalized and represents the concatenation ofthe sequences in some order, which need not be left toright, as described for each affected instruction.

CR0 31

LR0 63

CTR0 63

GPR 0

GPR 1

. . .

. . .

GPR 30

GPR 310 63

XER0 63

FPR 0

FPR 1

. . .

. . .

FPR 30

FPR 310 63

FPSCR0 31


18/230

Version 2.02


1.7.1 I-Form0 6 30 31

Figure 3. I instruction format

1.7.2 B-Form0 6 11 16 30 31

Figure 4. B instruction format

1.7.3 SC-Form0 6 11 16 20 27 30 31

Figure 5. SC instruction format

1.7.4 D-Form0 6 11 16 31

Figure 6. D instruction format

1.7.5 DS-FORM0 6 11 16 30 31

Figure 7. DS instruction format

OPCD LI AA LK

OPCD BO BI BD AA LK

OPCD /// /// // LEV // 1 /

OPCD RT RA DOPCD RT RA SIOPCD RS RA DOPCD RS RA UI

OPCD BF / L RA SIOPCD BF / L RA UIOPCD TO RA SIOPCD FRT RA DOPCD FRS RA D

OPCD RT RA DS XOOPCD RS RA DS XO


19/230


Version 2.02

1.7.6 X-FORM0 6 11 16 21 31

Figure 8. X instruction format

1.7.7 XL-FORM0 6 11 16 21 31

Figure 9. XL instruction format

1.7.8 XFX-FORM0 6 11 21 31

Figure 10. XFX instruction format

1.7.9 XFL-FORM0 6 7 15 16 21 31

Figure 11. XFL instruction format

1.7.10 XS-FORM0 6 11 16 21 30 31

Figure 12. XS instruction format

1.7.11 XO-FORM0 6 11 16 21 22 31

Figure 13. XO instruction format

OPCD RT RA RB XO / OPCD RT RA NB XO / OPCD RT / SR /// XO / OPCD RT /// RB XO /

OPCD RT /// /// XO / OPCD RS RA RB XO RcOPCD RS RA RB XO 1OPCD RS RA RB XO / OPCD RS RA NB XO / OPCD RS RA SH XO RcOPCD RS RA /// XO RcOPCD RS / SR /// XO / OPCD RS /// RB XO / OPCD RS /// /// XO / OPCD RS /// L /// XO / OPCD BF / L RA RB XO / OPCD BF // FRA FRB XO / OPCD BF // BFA // /// XO / OPCD BF // /// U / XO RcOPCD BF // /// /// XO / OPCD / TH RA RB XO / OPCD /// L RA RB XO / OPCD /// L /// RB XO / OPCD /// L /// /// XO / OPCD TO RA RB XO / OPCD FRT RA RB XO / OPCD FRT /// FRB XO Rc

OPCD FRT /// /// XO RcOPCD FRS RA RB XO / OPCD BT /// /// XO RcOPCD /// RA RB XO / OPCD /// /// RB XO / OPCD /// /// /// XO /

OPCD BT BA BB XO / OPCD BO BI /// BH XO LKOPCD BF // BFA // /// XO / OPCD /// /// /// XO /

OPCD RT spr XO / OPCD RT tbr XO / OPCD RT 0 /// XO / OPCD RT 1 FXM / XO / OPCD RS 0 FXM / XO / OPCD RS 1 FXM / XO / OPCD RS spr XO /

OPCD / FLM / FRB XO Rc

OPCD RS RA sh XO sh Rc

OPCD RT RA RB OE XO RcOPCD RT RA RB / XO RcOPCD RT RA /// OE XO Rc


20/230

Version 2.02


1.7.12 A-FORM0 6 11 16 21 26 31

Figure 14. A instruction format

1.7.13 M-FORM0 6 11 16 21 26 31

Figure 15. M instruction format

1.7.14 MD-FORM0 6 11 16 21 27 30 31

Figure 16. MD instruction format

1.7.15 MDS-FORM0 6 11 16 21 27 31

Figure 17. MDS instruction format

1.7.16 Instruction Fields

AA (30)Absolute Address bit.

0 The immediate field represents anaddress relative to the current instructionaddress. For I-form branches the effec-tive address of the branch target is thesum of the LI field sign-extended to 64 bitsand the address of the branch instruc-tion. For B-form branches the effectiveaddress of the branch target is the sum ofthe BD field sign-extended to 64 bits andthe address of the branch instruction.

1 The immediate field represents an abso-lute address. For I-form branches theeffective address of the branch target isthe LI field sign-extended to 64 bits. ForB-form branches the effective address ofthe branch target is the BD fieldsign-extended to 64 bits.

BA (11:15)Field used to specify a bit in the CR to be used asa source.

BB (16:20)Field used to specify a bit in the CR to be used asa source.

BD (16:29)Immediate field used to specify a 14-bit signedtwos complement branch displacement which isconcatenated on the right with 0b00 andsign-extended to 64 bits.

BF (6:8)Field used to specify one of the CR fields or one ofthe FPSCR fields to be used as a target.

BFA (11:13)Field used to specify one of the CR fields or one ofthe FPSCR fields to be used as a source.

BH (19:20)Field used to specify a hint in the Branch Condi- tional to Link Register and Branch Conditional to Count Register instructions. The encoding isdescribed in Section 2.4.1, Branch Instructions on page 20.

BI (11:15)Field used to specify a bit in the CR to be tested bya Branch Conditional instruction.

BO (6:10)Field used to specify options for the Branch Condi- tional instructions. The encoding is described inSection 2.4.1, Branch Instructions on page 20 .

OPCD FRT FRA FRB FRC XO RcOPCD FRT FRA FRB /// XO RcOPCD FRT FRA /// FRC XO RcOPCD FRT /// FRB /// XO Rc

OPCD RS RA RB MB ME RcOPCD RS RA SH MB ME Rc

OPCD RS RA sh mb XO sh RcOPCD RS RA sh me XO sh Rc

OPCD RS RA RB mb XO RcOPCD RS RA RB me XO Rc


21/230


Version 2.02

BT (6:10)Field used to specify a bit in the CR or in theFPSCR to be used as a target.

D (16:31)Immediate field used to specify a 16-bit signedtwos complement integer which is sign-extendedto 64 bits.

DS (16:29)Immediate field used to specify a 14-bit signedtwos complement integer which is concatenatedon the right with 0b00 and sign-extended to 64bits.

FLM (7:14)Field mask used to identify the FPSCR fields thatare to be updated by the mtfsf instruction.

FRA (11:15)Field used to specify an FPR to be used as asource.

FRB (16:20)Field used to specify an FPR to be used as asource.

FRC (21:25)Field used to specify an FPR to be used as asource.

FRS (6:10)Field used to specify an FPR to be used as asource.

FRT (6:10)Field used to specify an FPR to be used as a tar-get.

FXM (12:19)Field mask used to identify the CR fields that are tobe written by the mtcrf and mtocrf instructions, orread by the mfocrf instruction.

L (10 or 15)Field used to specify whether a fixed-point Com-pare instruction is to compare 64-bit numbers or32-bit numbers.

Field used by the optional version of the Data Cache Block Flush instruction (see Book II, Pow- erPC Virtual Environment Architecture).

Field used by the Move To Machine State Register and TLB Invalidate Entry instructions (see Book III,PowerPC Operating Environment Architecture ).

L (9:10)Field used by the Synchronize instruction (seeBook II, PowerPC Virtual Environment Architec- ture ).

LEV (20:26)Field used by the System Call instruction.

LI (6:29)Immediate field used to specify a 24-bit signedtwos complement integer which is concatenatedon the right with 0b00 and sign-extended to 64bits.

LK (31)LINK bit.

0 Do not set the Link Register.1 Set the Link Register. The address of the

instruction following the Branch instructionis placed into the Link Register.

MB (21:25) and ME (26:30)Fields used in M-form instructions to specify a64-bit mask consisting of 1-bits from bit MB+32through bit ME+32 inclusive and 0-bits elsewhere,as described in Section 3.3.12, Fixed-PointRotate and Shift Instructions on page 71 .

MB (21:26)Field used in MD-form and MDS-form instructions

to specify the first 1-bit of a 64-bit mask, asdescribed in Section 3.3.12, Fixed-Point Rotateand Shift Instructions on page 71 .

ME (21:26)Field used in MD-form and MDS-form instructionsto specify the last 1-bit of a 64-bit mask, asdescribed in Section 3.3.12, Fixed-Point Rotateand Shift Instructions on page 71 .

NB (16:20)Field used to specify the number of bytes to movein an immediate Move Assist instruction.

OPCD (0:5)

Primary opcode field.OE (21)

Field used by XO-form instructions to enable set-ting OV and SO in the XER.

RA (11:15)Field used to specify a GPR to be used as asource or as a target.

RB (16:20)Field used to specify a GPR to be used as asource.

Rc (31)

RECORD bit.0 Do not alter the Condition Register.1 Set Condition Register Field 0 or Field 1

as described in Section 2.3.1, ConditionRegister on page 18 .

RS (6:10)Field used to specify a GPR to be used as asource.

RT (6:10)


22/230

Version 2.02


Field used to specify a GPR to be used as a target.

SH (16:20, or 16:20 and 30)Field used to specify a shift amount.

SI (16:31)Immediate field used to specify a 16-bit signedinteger.

SPR (11:20)Field used to specify a Special Purpose Registerfor the mtspr and mfspr instructions.

SR (12:15)Field used by the Segment Register Manipulation instructions (see Book III, PowerPC Operating Environment Architecture ).

TBR (11:20)Field used by the Move From Time Base instruc-tion (see Book II, PowerPC Virtual Environment Architecture ).

TH (7:10)Field used by the optional data stream variant ofthe dcbt instruction (see Book II, PowerPC Virtual Environment Architecture ).

TO (6:10)Field used to specify the conditions on which totrap. The encoding is described in Section 3.3.10,Fixed-Point Trap Instructions on page 62.

U (16:19)Immediate field used as the data to be placed intoa field in the FPSCR.

UI (16:31)Immediate field used to specify a 16-bit unsignedinteger.

XO (21:29, 21:30, 22:30, 26:30, 27:29, 27:30, or30:31)

Extended opcode field.

1.8 Classes of InstructionsAn instruction falls into exactly one of the followingthree classes:

DefinedIllegalReserved

The class is determined by examining the opcode, andthe extended opcode if any. If the opcode, or combina-tion of opcode and extended opcode, is not that of adefined instruction or of a reserved instruction, theinstruction is illegal.

1.8.1 Defined Instruction Class

This class of instructions contains all the instructionsdefined in the PowerPC User Instruction Set Architec-ture, PowerPC Virtual Environment Architecture, andPowerPC Operating Environment Architecture.

In general, defined instructions are guaranteed to beprovided in all implementations. The only exceptionsare instructions that are optional instructions. Theseexceptions are identified in the instruction descriptions.

A defined instruction can have preferred and/or invalidforms, as described in Section 1.9.1, PreferredInstruction Forms and Section 1.9.2, Invalid Instruc-tion Forms .

1.8.2 Illegal Instruction Class

This class of instructions contains the set of instructions

described in Appendix G, Illegal Instructions onpage 187 . Illegal instructions are available for futureextensions of the PowerPC Architecture; that is, somefuture version of the PowerPC Architecture may defineany of these instructions to perform new functions.

Any attempt to execute an illegal instruction will causethe system illegal instruction error handler to beinvoked and will have no other effect.

An instruction consisting entirely of binary 0s is guaran-teed always to be an illegal instruction. This increasesthe probability that an attempt to execute data or unini-tialized storage will result in the invocation of the sys-

tem illegal instruction error handler.

1.8.3 Reserved Instruction Class

This class of instructions contains the set of instructionsdescribed in Appendix H, Reserved Instructions onpage 189 .

Reserved instructions are allocated to specific pur-poses that are outside the scope of the PowerPC Archi-tecture.

Any attempt to execute a reserved instruction will:

1 perform the actions described in Book IV, Pow- erPC Implementation Features for the implementa-tion if the instruction is implemented; or

1 cause the system illegal instruction error handler tobe invoked if the instruction is not implemented.


23/230


Version 2.02

1.9 Forms of Defined Instruc-tions

1.9.1 Preferred Instruction Forms

Some of the defined instructions have preferred forms.For such an instruction, the preferred form will executein an efficient manner, but any other form may take sig-nificantly longer to execute than the preferred form.

Instructions having preferred forms are:

1 the Condition Register Logical instructions1 the Load/Store Multiple instructions1 the Load/Store String instructions1 the Or Immediate instruction (preferred form of

no-op)1 the Move To Condition Register Fields instruction

1.9.2 Invalid Instruction FormsSome of the defined instructions can be coded in aform that is invalid. An instruction form is invalid if oneor more fields of the instruction, excluding the opcodefield(s), are coded incorrectly in a manner that can bededuced by examining only the instruction encoding.

In general, any attempt to execute an invalid form of aninstruction will either cause the system illegal instruc-tion error handler to be invoked or yield boundedlyundefined results. Exceptions to this rule are stated inthe instruction descriptions.

Some instruction forms are invalid because the instruc-tion contains a reserved value in a defined field (seeSection 1.5.2 on page 3 ); these invalid forms are notdiscussed further. All other invalid forms are identifiedin the instruction descriptions.

Assemblers should report uses of invalid instruc-tion forms as errors.

Assembler Note


24/230

Version 2.02


1.10 OptionalitySome of the defined instructions are optional. Theoptional instructions are defined in Chapter 5. OptionalFacilities and Instructions on page 123. Additionaloptional instructions may be defined in Books II and III(e.g., see the section entitled Lookaside Buffer Man-

agement in Book III, and the chapters entitledOptional Facilities and Instructions in Book II andBook III).

Any attempt to execute an optional instruction that isnot provided by the implementation will cause the sys-tem illegal instruction error handler to be invoked.

In addition to instructions, other kinds of optional facili-ties, such as registers, may be defined in Books II andIII. The effects of attempting to use an optional facilitythat is not provided by the implementation aredescribed in Books II and III as appropriate.

1.11 ExceptionsThere are two kinds of exception, those caused directlyby the execution of an instruction and those caused byan asynchronous event. In either case, the exceptionmay cause one of several components of the systemsoftware to be invoked.

The exceptions that can be caused directly by the exe-cution of an instruction include the following:

1 an attempt to execute an illegal instruction, or anattempt by an application program to execute aprivileged instruction (see Book III, PowerPC Operating Environment Architecture ) (system ille-

gal instruction error handler or system privilegedinstruction error handler)

1 the execution of a defined instruction using aninvalid form (system illegal instruction error han-dler or system privileged instruction error handler)

1 the execution of an optional instruction that is notprovided by the implementation (system illegalinstruction error handler)

1 an attempt to access a storage location that isunavailable (system instruction storage error han-dler or system data storage error handler)

1 an attempt to access storage with an effective

address alignment that is invalid for the instruction(system alignment error handler)1 the execution of a System Call instruction (system

service program)1 the execution of a Trap instruction that traps (sys-

tem trap handler)1 the execution of a floating-point instruction that

causes a floating-point enabled exception to exist

(system floating-point enabled exception errorhandler)

The exceptions that can be caused by an asynchro-nous event are described in Book III, PowerPC Operat- ing Environment Architecture .

The invocation of the system error handler is precise,except that if one of the imprecise modes for invokingthe system floating-point enabled exception error han-dler is in effect (see page 96 ) then the invocation of thesystem floating-point enabled exception error handlermay be imprecise. When the system error handler isinvoked imprecisely, the excepting instruction does notappear to complete before the next instruction starts(because one of the effects of the excepting instruction,namely the invocation of the system error handler, hasnot yet occurred).

Additional information about exception handling can befound in Book III, PowerPC Operating Environment

Architecture .

1.12 Storage AddressingA program references storage using the effectiveaddress computed by the processor when it executes aStorage Access or Branch instruction (or certain otherinstructions described in Book II, PowerPC Virtual Envi- ronment Architecture , and Book III, PowerPC Operat- ing Environment Architecture ), or when it fetches thenext sequential instruction.

1.12.1 Storage Operands

Bytes in storage are numbered consecutively startingwith 0. Each number is the address of the correspond-ing byte.

Storage operands may be bytes, halfwords, words, ordoublewords, or, for the Load/Store Multiple and Move Assist instructions, a sequence of bytes or words. Theaddress of a storage operand is the address of its firstbyte (i.e., of its lowest-numbered byte). Byte orderingis Big-Endian. However, if the optional Little-Endianfacility is implemented the system can be operated in amode in which byte ordering is Little-Endian; seeSection 5.3 .

Operand length is implicit for each instruction.

The operand of a single-register Storage Access instruction has a natural alignment boundary equal tothe operand length. In other words, the natural address of an operand is an integral multiple of theoperand length. A storage operand is said to bealigned if it is aligned at its natural boundary; otherwiseit is said to be unaligned .


25/230


Version 2.02

Storage operands for single-register Storage Access instructions have the following characteristics.(Although not permitted as storage operands, quad-words are shown because quadword alignment isdesirable for certain storage operands.)

The concept of alignment is also applied more gener-ally, to any datum in storage. For example, a 12-bytedatum in storage is said to be word-aligned if itsaddress is an integral multiple of 4.

Some instructions require their storage operands tohave certain alignments. In addition, alignment mayaffect performance. For single-register Storage Access instructions the best performance is obtained whenstorage operands are aligned. Additional effects ofdata placement on performance are described in BookII, PowerPC Virtual Environment Architecture .

Instructions are always four bytes long andword-aligned.

1.12.2 Effective Address Calcula-tion

An effective address is computed by the processorwhen executing a Storage Access or Branch instruction(or certain other instructions described in Book II, Pow- erPC Virtual Environment Architecture , and Book III,PowerPC Operating Environment Architecture ) orwhen fetching the next sequential instruction. The fol-lowing provides an overview of this process. Moredetail is provided in the individual instruction descrip-tions.

Effective address calculations, for both data andinstruction accesses, use 64-bit two s complementaddition. All 64 bits of each address component partic-ipate in the calculation regardless of mode (32-bit or64-bit). In this computation one operand is an address(which is by definition an unsigned number) and thesecond is a signed offset. Carries out of the most sig-nificant bit are ignored.

In 64-bit mode, the entire 64-bit result comprises the64-bit effective address. The effective address arith-

metic wraps around from the maximum address,264 - 1, to address 0.

In 32-bit mode, the low-order 32 bits of the 64-bit resultcomprise the effective address for the purpose ofaddressing storage. The high-order 32 bits of the64-bit effective address are ignored for the purpose of

accessing data, but are included whenever an effectiveaddress is placed into a GPR by Load with Update andStore with Update instructions. The high-order 32 bitsof the 64-bit effective address are effectively set to 0 forthe purpose of fetching instructions, and explicitly sowhenever an effective address is placed into the LinkRegister by Branch instructions having LK=1. Thehigh-order 32 bits of the 64-bit effective address are setto 0 in Special Purpose Registers when the systemerror handler is invoked. As used to address storage,the effective address arithmetic appears to wraparound from the maximum address, 2 32 - 1, to address0 in 32-bit mode.

The 64-bit current instruction address and next instruc-tion address are not affected by a change from 32-bitmode to 64-bit mode, but they are affected by a changefrom 64-bit mode to 32-bit mode. In the latter case, thehigh-order 32 bits are set to 0.

RA is a field in the instruction which specifies anaddress component in the computation of an effectiveaddress. A zero in the RA field indicates the absenceof the corresponding address component. A value ofzero is substituted for the absent component of theeffective address computation. This substitution isshown in the instruction descriptions as (RA|0).

Effective addresses are computed as follows. In thedescriptions below, it should be understood that thecontents of a GPR refers to the entire 64-bit contents,independent of mode, but that in 32-bit mode only bits32:63 of the 64-bit result of the computation are used toaddress storage.

1 With X-form instructions, in computing the effectiveaddress of a data element, the contents of theGPR designated by RB (or the value zero for lswi ,lsdi , stswi , and stsdi ) are added to the contentsof the GPR designated by RA or to zero if RA=0.

1 With D-form instructions, the 16-bit D field issign-extended to form a 64-bit address compo-nent. In computing the effective address of a dataelement, this address component is added to thecontents of the GPR designated by RA or to zero ifRA=0.

1 With DS-form instructions, the 14-bit DS field isconcatenated on the right with 0b00 andsign-extended to form a 64-bit address compo-nent. In computing the effective address of a dataelement, this address component is added to thecontents of the GPR designated by RA or to zero ifRA=0.

Operand Length Addr 60:63 if alignedByte 8 bits xxxxHalfword 2 bytes xxx0Word 4 bytes xx00Doubleword 8 bytes x000Quadword 16 bytes 0000

Note: An x in an address bit position indicates thatthe bit can be 0 or 1 independent of the state ofother bits in the address.


26/230

Version 2.02


1 With I-form Branch instructions, the 24-bit LI fieldis concatenated on the right with 0b00 andsign-extended to form a 64-bit address compo-nent. If AA=0, this address component is added tothe address of the Branch instruction to form theeffective address of the next instruction. If AA=1,this address component is the effective address of

the next instruction.1 With B-form Branch instructions, the 14-bit BD field

is concatenated on the right with 0b00 andsign-extended to form a 64-bit address compo-nent. If AA=0, this address component is added tothe address of the Branch instruction to form theeffective address of the next instruction. If AA=1,this address component is the effective address ofthe next instruction.

1 With XL-form Branch instructions, bits 0:61 of theLink Register or the Count Register are concate-nated on the right with 0b00 to form the effectiveaddress of the next instruction.

1 With sequential instruction fetching, the value 4 isadded to the address of the current instruction toform the effective address of the next instruction.(There is one exception to this rule, which involveschanging between 32-bit and 64-bit mode and isdescribed in the section entitled "Address Wrap-ping Combined with Changing MSR Bit SF" inBook III.)

If the size of the operand of a storage access instruc-tion is more than one byte, the effective address foreach byte after the first is computed by adding 1 to theeffective address of the preceding byte.


27/230

Chapter 2. Branch Processor 17

Version 2.02

Chapter 2. Branch Processor

2.1 Branch Processor Overview . . . . . . 172.2 Instruction Execution Order . . . . . . 172.3 Branch Processor Registers. . . . . . 182.3.1 Condition Register . . . . . . . . . . . . 182.3.2 Link Register . . . . . . . . . . . . . . . . 192.3.3 Count Register. . . . . . . . . . . . . . . 192.4 Branch Processor Instructions . . . . 20

2.4.1 Branch Instructions . . . . . . . . . . . 202.4.2 System Call Instruction . . . . . . . . 262.4.3 Condition Register Logical Instruc-

tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272.4.4 Condition Register Field

Instruction . . . . . . . . . . . . . . . . . . . . . . . 30

2.1 Branch Processor OverviewThis chapter describes the registers and instructionsthat make up the Branch Processor facility.Section 2.3, Branch Processor Registers on page 18describes the registers associated with the Branch Pro-cessor. Section 2.4, Branch Processor Instructions on page 20 describes the instructions associated withthe Branch Processor.

2.2 Instruction Execution OrderIn general, instructions appear to execute sequentially,in the order in which they appear in storage. Theexceptions to this rule are listed below.

1 Branch instructions for which the branch is takencause execution to continue at the target addressspecified by the Branch instruction.

1 Trap instructions for which the trap conditions aresatisfied, and System Call instructions, cause theappropriate system handler to be invoked.

1 Exceptions can cause the system error handler tobe invoked, as described in Section 1.11, Excep-tions on page 14 .

1 Returning from a system service program, systemtrap handler, or system error handler causes exe-cution to continue at a specified address.

The model of program execution in which the proces-sor appears to execute one instruction at a time, com-pleting each instruction before beginning to execute thenext instruction is called the sequential executionmodel . In general, the processor obeys the sequentialexecution model. For the instructions and facilities

defined in this Book, the only exceptions to this rule arethe following.

1 A floating-point exception occurs when the proces-sor is running in one of the Imprecise floating-pointexception modes ( see Section 4.4, Floating-PointExceptions on page 94 ). The instruction thatcauses the exception does not complete beforethe next instruction begins execution, with respectto setting exception bits and (if the exception isenabled) invoking the system error handler.

1 A Store instruction modifies one or more bytes inan area of storage that contains instructions that

will subsequently be executed. Before an instruc-tion in that area of storage is executed, softwaresynchronization is required to ensure that theinstructions executed are consistent with theresults produced by the Store instruction.

This software synchronization will generally beprovided by system library programs (see thesection entitled Instruction Storage in BookII). Application programs should call theappropriate system library program beforeattempting to execute modified instructions.

Programming Note


28/230

Version 2.02


2.3 Branch Processor Registers

2.3.1 Condition Register

The Condition Register (CR) is a 32-bit register whichreflects the result of certain operations, and provides amechanism for testing (and branching).

Figure 18. Condition Register

The bits in the Condition Register are grouped intoeight 4-bit fields, named CR Field 0 (CR0), ..., CR Field7 (CR7), which are set in one of the following ways.

1 Specified fields of the CR can be set by a move tothe CR from a GPR ( mtcrf , mtocrf ).

1 A specified field of the CR can be set by a move tothe CR from another CR field ( mcrf ), fromXER32:35 (mcrxr ), or from the FPSCR ( mcrfs ).

1 CR Field 0 can be set as the implicit result of afixed-point instruction.

1 CR Field 1 can be set as the implicit result of afloating-point instruction.

1 A specified CR field can be set as the result ofeither a fixed-point or a floating-point Compareinstruction.

Instructions are provided to perform logical operationson individual CR bits and to test individual CR bits.

For all fixed-point instructions in which Rc=1, and foraddic. , andi. , and andis. , the first three bits of CR Field0 (bits 0:2 of the Condition Register) are set by signedcomparison of the result to zero, and the fourth bit ofCR Field 0 (bit 3 of the Condition Register) is copiedfrom the SO field of the XER. Result here refers tothe entire 64-bit value placed into the target register in64-bit mode, and to bits 32:63 of the 64-bit value placedinto the target register in 32-bit mode.

if (64-bit mode)then M 1 0else M 1 32

if (target_register) M:63 < 0 then c 1 0b100else if (target_register) M:63 > 0 then c 1 0b010else c 1 0b001CR01 c || XER SO

If any portion of the result is undefined, then the valueplaced into the first three bits of CR Field 0 is unde-fined.

The bits of CR Field 0 are interpreted as follows.

Bit Description

0 Negative (LT)The result is negative.

1 Positive (GT)The result is positive.

2 Zero (EQ)The result is zero.

3 Summary Overflow (SO)This is a copy of the final state of XER SO at

the completion of the instruction.

The stwcx. and stdcx. instructions (see Book II, Pow- erPC Virtual Environment Architecture ) also set CRField 0.

For all floating-point instructions in which Rc=1, CRField 1 (bits 4:7 of the Condition Register) is set to theFloating-Point exception status, copied from bits 0:3 ofthe Floating-Point Status and Control Register. Thisoccurs regardless of whether any exceptions areenabled, and regardless of whether the writing of theresult is suppressed (see Section 4.4, Floating-PointExceptions on page 94 ). These bits are interpreted asfollows.

Bit Description

4 Floating-Point Exception Summary (FX)This is a copy of the final state of FPSCR FX atthe completion of the instruction.

5 Floating-Point Enabled Exception Sum- mary (FEX)This is a copy of the final state of FPSCR FEXat the completion of the instruction.

6 Floating-Point Invalid Operation Excep- tion Summary (VX)This is a copy of the final state of FPSCR VX atthe completion of the instruction.

7 Floating-Point Overflow Exception (OX)This is a copy of the final state of FPSCR OX atthe completion of the instruction.

For Compare instructions, a specified CR field is set toreflect the result of the comparison. The bits of thespecified CR field are interpreted as follows. A com-

plete description of how the bits are set is given in theinstruction descriptions in Section 3.3.9, Fixed-PointCompare Instructions on page 60 and Section 4.6.7,Floating-Point Compare Instructions on page 119.

Bit Description

0 Less Than, Floating-Point Less Than (LT,FL)For fixed-point Compare instructions, (RA) SI or (RB) (signed comparison) or (RA) > u UIor (RB) (unsigned comparison). For floating-point Compare instructions, (FRA) > (FRB).

2 Equal, Floating-Point Equal (EQ, FE)For fixed-point Compare instructions, (RA) =SI, UI, or (RB). For floating-point Compareinstructions, (FRA) = (FRB).

3 Summary Overflow, Floating-Point Unor- dered (SO,FU)For fixed-point Compare instructions, this is acopy of the final state of XER SO at the com-pletion of the instruction. For floating-pointCompare instructions, one or both of (FRA)and (FRB) is a NaN.

2.3.2 Link Register

The Link Register (LR) is a 64-bit register. It can beused to provide the branch target address for theBranch Conditional to Link Register instruction, and itholds the return address after Branch instructions forwhich LK=1.

Figure 19. Link Register

2.3.3 Count Register

The Count Register (CTR) is a 64-bit register. It can beused to hold a loop count that can be decremented dur-ing execution of Branch instructions that contain anappropriately coded BO field. If the value in the CountRegister is 0 before being decremented, it is - 1 after-ward. The Count Register can also be used to providethe branch target address for the Branch Conditional to Count Registe r instruction.

Figure 20. Count Register

LR0 63

CTR0 63


30/230

Version 2.02


2.4 Branch Processor Instructions

2.4.1 Branch Instructions

The sequence of instruction execution can be changedby the Branch instructions. Because all instructions areon word boundaries, bits 62 and 63 of the generatedbranch target address are ignored by the processor inperforming the branch.

The Branch instructions compute the effective address(EA) of the target in one of the following four ways, asdescribed in Section 1.12.2, Effective Address Calcu-lation on page 15.

1. Adding a displacement to the address of theBranch instruction ( Branch or Branch Conditiona lwith AA=0).

2. Specifying an absolute address ( Branch or Branch Conditional with AA=1).

3. Using the address contained in the Link Register(Branch Conditional to Link Register ).

4. Using the address contained in the Count Register(Branch Conditional to Count Register ).

In all four cases, in 32-bit mode the final step in theaddress computation is setting the high-order 32 bits ofthe target address to 0.

For the first two methods, the target addresses can becomputed sufficiently ahead of the Branch instructionthat instructions can be prefetched along the targetpath. For the third and fourth methods, prefetching

instructions along the target path is also possible pro-vided the Link Register or the Count Register is loadedsufficiently ahead of the Branch instruction.

Branching can be conditional or unconditional, and thereturn address can optionally be provided. If the returnaddress is to be provided (LK=1), the effective addressof the instruction following the Branch instruction isplaced into the Link Register after the branch targetaddress has been computed; this is done regardless ofwhether the branch is taken.

For Branch Conditional instructions, the BO field speci-fies the conditions under which the branch is taken, as

shown in Figure 21 . In the figure, M=0 in 64-bit modeand M=32 in 32-bit mode. If the BO field specifies thatthe CTR is to be decremented, the entire 64-bit CTR isdecremented regardless of the mode.

Figure 21. BO field encodings

The a and t bits of the BO field can be used by soft-ware to provide a hint about whether the branch islikely to be taken or is likely not to be taken, as shownin Figure 22 .

Figure 22. at bit encodings

For Branch Conditional to Link Register and Branch Conditional to Count Register instructions, the BH field

BO Description

0000z Decrement the CTR, then branch if thedecremented CTR M:633 0 and CR BI=00001z Decrement the CTR, then branch if the

decremented CTR M:63=0 and CR BI=0001at Branch if CR BI=00100z Decrement the CTR, then branch if the

decremented CTR M:633 0 and CR BI=10101z Decrement the CTR, then branch if the

decremented CTR M:63=0 and CR BI=1011at Branch if CR BI=11a00t Decrement the CTR, then branch if the

decremented CTR M:633 0

1a01t Decrement the CTR, then branch if thedecremented CTR M:63=01z1zz Branch alwaysNotes:

1. z denotes a bit that is ignored.2. The a and t bits are used as described below.

at Hint00 No hint is given01 Reserved10 The branch is very likely not to be taken11 The branch is very likely to be taken

Many implementations have dynamic mechanismsfor predicting whether a branch will be taken.Because the dynamic prediction is likely to be veryaccurate, and is likely to be overridden by any hint

provided by the at bits, the at bits should be setto 0b00 unless the static prediction implied byat=0b10 or at=0b11 is highly likely to be correct.

Programming Note


31/230


Version 2.02

provides a hint about the use of the instruction, asshown in Figure 23 .

Figure 23. BH field encodings

Extended mnemonics for branches

Many extended mnemonics are provided so thatBranch Conditional instructions can be coded with por-tions of the BO and BI fields as part of the mnemonicrather than as part of a numeric operand. Some ofthese are shown as examples with the Branch instruc-

tions. See Appendix B, Assembler Extended Mne-monics on page 151 for additional extendedmnemonics.

BH Hint00 bclr [l ]: The instruction is a subroutine

return

bcctr [l ]: The instruction is not a subroutinereturn; the target address is likely tobe the same as the target addressused the preceding time the branchwas taken

01 bclr [l ]: The instruction is not a subroutinereturn; the target address is likely tobe the same as the target addressused the preceding time the branchwas taken

bcctr [l ]: Reserved10 Reserved11 bclr [l ] and bcctr [l ]: The target address is not

predictable

The hint provided by the BH field is independent ofthe hint provided by the at bits (e.g., the BH fieldprovides no indication of whether the branch islikely to be taken).

Programming Note

The hints provided by the at bits and by the BHfield do not affect the results of executing theinstruction.

The z bits should be set to 0, because they maybe assigned a meaning in some future version ofthe architecture.

Programming Note


32/230

Version 2.02


Programming Note

Many implementations have dynamic mechanisms forpredicting the target addresses of bclr [l ] and bcctr [l ]instructions. These mechanisms may cache returnaddresses (i.e., Link Register values set by Branch

instructions for which LK=1 and for which the branchwas taken) and recently used branch target addresses.To obtain the best performance across the widest rangeof implementations, the programmer should obey thefollowing rules.

1 Use Branch instructions for which LK=1 only assubroutine calls (including function calls, etc.).

1 Pair each subroutine call (i.e., each Branch instruction for which LK=1 and the branch is taken)with a bclr instruction that returns from the subrou-tine and has BH=0b00.

1 Do not use bclrl as a subroutine call. (Someimplementations access the return address cacheat most once per instruction; such implementationsare likely to treat bclrl as a subroutine return, andnot as a subroutine call.)

1 For bclr [l ] and bcctr [l ], use the appropriate valuein the BH field.

The following are examples of programming conven-tions that obey these rules. In the examples, BH isassumed to contain 0b00 unless otherwise stated. Inaddition, the at bits are assumed to be coded appro-priately.

Let A, B, and Glue be specific programs.

1 Loop counts:Keep them in the Count Register, and use a bc instruction (LK=0) to decrement the count and tobranch back to the beginning of the loop if the dec-remented count is nonzero.

1 Computed goto s, case statements, etc.:Use the Count Register to hold the address tobranch to, and use a bcctr instruction (LK=0, andBH=0b11 if appropriate) to branch to the selectedaddress.

1 Direct subroutine linkage:Here A calls B and B returns to A. The twobranches should be as follows.- A calls B: use a bl or bcl instruction (LK=1).- B returns to A: use a bclr instruction (LK=0)(the return address is in, or can be restored to,

the Link Register).1 Indirect subroutine linkage:

Here A calls Glue, Glue calls B, and B returns to Arather than to Glue. (Such a calling sequence iscommon in linkage code used when the subroutinethat the programmer wants to call, here B, is in adifferent module from the caller; the Binder insertsglue code to mediate the branch.) The threebranches should be as follows.

- A calls Glue: use a bl or bcl instruction(LK=1).

-

Glue calls B: place the address of B into theCount Register, and use a bcctr instruction(LK=0).

- B returns to A: use a bclr instruction (LK=0)(the return address is in, or can be restored to,the Link Register).

1 Function call:Here A calls a function, the identity of which mayvary from one instance of the call to another,instead of calling a specific program B. This caseshould be handled using the conventions of thepreceding two bullets, depending on whether thecall is direct or indirect, with the following differ-ences.

- If the call is direct, place the address of thefunction into the Count Register, and use abcctrl instruction (LK=1) instead of a bl or bcl instruction.

- For the bcctr [l ] instruction that branches tothe function, use BH=0b11 if appropriate.


33/230


Version 2.02

The bits corresponding to the current a and tbits, and to the current z bits except in the branchalways BO encoding, had different meanings inversions of the architecture that precede Version2.00.

1

The bit corresponding to the t bit was calledthe y bit. The y bit indicated whether to usethe architected default prediction (y=0) or touse the complement of the default prediction(y=1). The default prediction was defined asfollows.

- If the instruction is bc [l ][a ] with a negativevalue in the displacement field, the branchis taken. (This is the only case in whichthe prediction corresponding to the y bitdiffers from the prediction correspondingto the t bit.)

- In all other cases ( bc [l ][a ] with a nonnega-tive value in the displacement field, bclr [l ],or bcctr [l ]), the branch is not taken.

1 The BO encodings that test both the CountRegister and the Condition Register had a ybit in place of the current z bit. The meaningof the y bit was as described in the precedingitem.

1 The a bit was a z bit.

Because these bits have always been definedeither to be ignored or to be treated as hints, agiven program will produce the same result on anyimplementation regardless of the values of the bits.Also, because even the y bit is ignored, in prac-tice, by most processors that implement versions ofthe architecture that precede Version 2.00, the per-formance of a given program on those processorswill not be affected by the values of the bits.

Compatibility Note


34/230

Version 2.02


Branch I-form

b target_addr (AA=0 LK=0)ba target_addr (AA=1 LK=0)bl target_addr (AA=0 LK=1)bla target_addr (AA=1 LK=1)

if AA then NIA 1 iea EXTS(LI || 0b00)else NIA 1 iea CIA + EXTS(LI || 0b00)if LK then LR 1 iea CIA + 4

target_addr specifies the branch target address.

If AA=0 then the branch target address is the sum ofLI || 0b00 sign-extended and the address of thisinstruction, with the high-order 32 bits of the branch tar-get address set to 0 in 32-bit mode.

If AA=1 then the branch target address is the valueLI || 0b00 sign-extended, with the high-order 32 bits ofthe branch target address set to 0 in 32-bit mode.

If LK=1 then the effective address of the instruction fol-lowing the Branch instruction is placed into the LinkRegister.

Special Registers Altered:LR (if LK=1)

Branch Conditional B-form

bc BO,BI,target_addr (AA=0 LK=0)bca BO,BI,target_addr (AA=1 LK=0)bcl BO,BI,target_addr (AA=0 LK=1)bcla BO,BI,target_addr (AA=1 LK=1)

if (64-bit mode)then M 1 0else M 1 32

PPC Vers202 Book1 Public

Documents

Transcript of PPC Vers202 Book1 Public