PowerPoint Overheads for Computer Architecture From Microprocessors To Supercomputers
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Transcript of PowerPoint Overheads for Computer Architecture From Microprocessors To Supercomputers
PowerPoint Overheads for
Computer ArchitectureFrom Microprocessors To Supercomputers
Behrooz Parhami
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Figure 1.1 Some basic elements of digital logic circuits, with operator signs used in this book highlighted.
1.1 Signals, Logic Operator, and Gates
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Figure 1.3 An AND gate and a tristate buffer can act as controlled switches or valves. An inverting buffer is logically the same as a NOT gate.
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1.2 Boolean Functions and Expressions
• Truth table– N-variable input: 2n
– x: don’t care. x in output column means no interest; x in input column means that function does not depend on the value of the particular variable involved.
• Logic expression– NOT takes precedence over AND– AND takes precedence over OR/XOR– Logic expression can be manipulated using laws of Boolean algebra in order to obtain an
equivalent logic expression for simpler or more suitable hardware realization.
• Word statement– Natural language
• Logic diagram– Graphical representation of a Boolean function that carries information about its
hardware realization.– Logic circuit synthesis: derive logic diagram from truth table, logic expression, or word
statement.– Logic circuit analysis: going backward from logic diagram to truth table, logic
expression, or word statement.
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Table 1.1 Three 7-variable Boolean functions specified in a compact truth table with don’t-care entries in both input and output columns.
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Figure 1.7 Seven-segment display of decimal digits. The three open segments may be optionally used. The digit 1 can be displayed intwo ways, with the more common right-side version shown.
BCD to 7-segment decoder
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x3x2x1x0 e0 e1 e2 e3 e4 e5 e6
0000 1
0001 0
0010 1
0011 1
0100 0
0101 1
0110 1
0111 0
1000 1
1001 0
012120201
0123012301230123012301233
xxxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxe
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Figure 1.8 The logic circuit that generates the enable signal for the lowermost segment (number 3) in a seven-segment display unit.
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1.4 Useful Combinational Parts• Multiplexer
– 2a input signals: x0, x0, …,xN (N=2a-1) – Single output z– a control signal (address signal): y0, …, ya-1
• Decoder– a input signals– 2a output signals– Assert one and only one of its 2a output lines
• Encoder: opposite of a decoder.– 2a input signals– a output signals– When one and only one of its 2a input lines is asserted, its a-bit
output supplies the index of the asserted input in the form of a binary number
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Figure 1.9 A multiplexer (mux), or selector, allows one of several inputs to be selected and routed to output depending on the binary value of a set of selection or address signals provided to it.
Multiplexer
Y z
0 x0
1 x1
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Figure 1.10 A decoder allows the selection of one of 2a options using an a-bit address as input. A demultiplexer (demux) is a decoder that only selects an output if its enable signal is asserted.
Decodery1y0 X3 x2 x1 x0
00 0 0 0 1
01 0 0 1 0
10 0 1 0 0
11 1 0 0 0
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Figure 1.11 A 2a-to-a encoder outputs an a-bit binary number equal to the index of the single 1 among its 2a inputs.
EncoderX3 x2 x1 x0 Active y1y0
0 0 0 1 1 00
0 0 1 0 1 01
0 1 0 0 1 10
1 0 0 0 1 11
0 0 0 0 0 xx
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Figure 1.13 Programmable combinational logic: general structure and two classes known as PAL and PLA devices. Not shown is PROM with fixed AND array (a decoder) and programmable OR array.
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PLD: Short for programmable logic device, a generic term for an integrated circuit that can be programmed in a laboratory to perform complex functions.
(i) PROMs (Programmable Read Only Memory) - offer high speed and low cost for relatively small designs (ii) PLAs (Programmable Logic Array) - offer flexible features for more complex designs (iii) PAL/GALs (Programmable Array Logic/Generic Array Logic) - offer good flexibility and are faster and less expensive than PLAs
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Figure 1.14 Timing diagram for a circuit that exhibits glitching.
Example: f = x + y + z, using circuit in Fig.13b
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A (Vin )
C B (Vout )
The CMOS transmission gate
P
N
s
s
MOS Circuit TG Symbol
The conduction path through TG is controlled bycomplementary signals & ss
A(Vin) S Tn Tp B (Vout)0 0 off off Z (high impedance state (blocks logic flow))
0 1 on off 0 (nMOS passes strong 0, pMOS off when Vout<Vthp)
1 0 off off Z (high impedance state (blocks logic flow))
1 1 off on 1 (pMOS passes strong 1, nMOS off when Vout>Vdd-Vthn )
B (Vout )
s
s
A (Vin )
B=A(or Z when S=0)
s
s
A In steady state