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Powerex, Inc., 200 Hillis Street, Youngwood, Pennsylvania 15697-1800 (724) 925-7272

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6.0 Introduction to Intellimod™Intelligent Power Modules

Powerex Intellimod™ IntelligentPower Modules (IPMs) areadvanced hybrid power devicesthat combine high speed, low lossIGBTs with optimized gate driveand protection circuitry. Highlyeffective over-current and short-circuit protection is realized throughthe use of advanced current senseIGBT chips that allow continuousmonitoring of power device current.System reliability is furtherenhanced by the IPM’s integratedover temperature and undervoltage lock out protection.Compact, automatically assembledIntelligent Power Modules aredesigned to reduce system size,cost, and time to market. Powerexin alliance with Mitsubishi Electricintroduced the first full line ofIntelligent Power Modules inNovember, 1991. Continuousimprovements in power chip,packaging, and control circuittechnology have lead to theIntellimod™ lineup shown inTable 6.1.

6.0.1 Third GenerationIntelligent Power Modules

The Powerex/Mitsubishi thirdgeneration intelligent powermodule family shown in Table 6.1represents the industries mostcomplete line of IPMs. Since theiroriginal introduction in 1993 theseries has been expanded toinclude 36 types with ratingsranging from 10A 600V to 800A1200V. The power semiconductorsused in these modules are basedon the field proven H-Series IGBTand diode processes. In Table 6.1the third generation family has

been divided into two groups, the“Low Profile Series” and “HighPower Series” based on thepackaging technology that is used.The third generation IPM has beenoptimized for minimum switchinglosses in order to meet industrydemands for acoustically noiselessinverters with carrier frequenciesup to 20kHz. The built in gate driveand protection has been carefullydesigned to minimize thecomponents required for the usersupplied interface circuit.

6.0.2 V-Series High Power IPMs

The V-Series IPM was developed inorder to address newly emerging

industry requirements for higherreliability, lower cost and reducedEMI. By utilizing the low inductancepackaging technology developedfor the U-Series IGBT module(described in Section 4.1.5)combined with an advanced supersoft free-wheel diode andoptimized gate drive and protectioncircuits the V-Series IPM familyachieves improved performance atreduced cost. The detaileddescriptions of IPM operation andinterface requirements presented inSections 6.1 through 6.8 apply toV-Series as well as third generationIPMs. The only exception beingthat V-Series IPMs have a unifiedshort circuit protection function that

Third Generation Low Profile Series - 600VPM10CSJ060 10 Six IGBTs

PM15CSJ060 5 Six IGBTs



PM50RSK060 50 Six IGBTs + Brake ckt.


Third Generation Low Profile Series - 1200VPM10CZF120 10 Six IGBTs

PM10RSH120 10 Six IGBTs + Brake ckt.

PM15CZF120 15 Six IGBTs

PM15RSH120 15 Six IGBTs + Brake ckt.


Third Generation High Power Series - 600VPM75RSA060 75 Six IGBTs + Brake ckt.

PM100CSA060 100 Six IGBTs

PM100RSA060 100 Six IGBTs + Brake ckt.





PM200DSA060 200 Two IGBTs: Half Bridge


PM400DAS060 400 Two IGBTs: Half Bridge


PM800HSA060 800 One IGBT

Third Generation High Power Series - 1200VPM25RSB120 25 Six IGBTs + Brake ckt.












V-Series High Power - 600VPM75RVA060 75 Six IGBTs + Brake ckt.

PM100CVA060 100 Six IGBTs




PM400DVA060 400 Two IGBTs: Half Bridge


V-Series High Power - 1200VPM50RVA120 50 Six IGBTs + Brake ckt.






Type Number Amps Power Circuit Type Number Amps Power Circuit

Table 6.1 Powerex Intelligent Power Modules


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takes the place of the separateshort circuit and over currentfunctions described in Sections6.4.4 and 6.4.5. The unifiedprotection was made possible byan advanced RTC (Real TimeControl) current clamping circuitthat eliminates the need for theover current protection function. InV-Series IPMs a unified shortcircuit protection with a delay toavoid unwanted operation replacesthe over current and short circuitmodes of the third generationdevices.

6.1 Structure of IntelligentPower Modules

Powerex Intelligent Power Modulesutilize many of the same fieldproven module packagingtechnologies used in PowerexIGBT modules. Cost effectiveimplementation of the built in gatedrive and protection circuits over awide range of current ratings wasachieved using two differentpackaging techniques. Low powerdevices use a multilayer epoxyisolation system while medium andhigh power devices use ceramicisolation. These packagingtechnologies are described in moredetail in Sections 6.1.1 and 6.1.2.Intellimods are available in fourpower circuit configurations, single(H), dual (D), six pack (C), andseven pack (R). Table 6.1 indicatesthe power circuit of each Intellimodand Figure 6.1 shows the powercircuit configurations.

6.1.1 Multilayer EpoxyConstruction

Low power Intellimods™ (10-50A,600V and 10-15A, 1200V) use a

multilayer epoxy based isolationsystem. In this system, alternatelayers of copper and epoxy areused to create a shielded printedcircuit directly on the aluminumbase plate. Power chips and gatecontrol circuit components are

soldered directly to the substrateeliminating the need for a separateprinted circuit board and ceramicisolation materials. Modulesconstructed using this techniqueare easily identified by theirextremely low profile packages.This package design is ideallysuited for consumer and industrialapplications where low cost andcompact size are important.Figure 6.2 shows a cross sectionof this type of Intellimod package.Figure 6.3 is a PM20CSJ060 20A,600V Intellimod™.

P

U V W

C2E1

C1

E2

E

C

N

TYPE C

TYPE D TYPE H

P

N

U

TYPE R

V WB

Figure 6.2 Multilayer EpoxyConstruction

Figure 6.1 Power CircuitConfiguration

Figure 6.3 PM20CSJ060

1.2.3.4.5.6.7.8.9.

10.11.

CaseEpoxy ResinInput Signal TerminalSMT ResistorGate Control ICSMT CapacitorIGBT ChipFree-wheel Diode ChipBond WireCopper BlockBaseplate with EpoxyBased Isolation

111098

67

12 3

45


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6.1.2 Ceramic IsolationConstruction

Higher power IPMs are constructedusing ceramic isolation material. Adirect bond copper process inwhich copper patterns are bondeddirectly to the ceramic substratewithout the use of solder is used inthese modules. This substrateprovides the improved thermalcharacteristics and greater currentcarrying capabilities that areneeded in these higher powerdevices. Gate drive and controlcircuits are contained on aseparate PCB mounted directlyabove the power devices. ThePCB is a multilayer constructionwith special shield layers forEMI noise immunity. Figure 6.4shows the structure of a ceramicisolated Intelligent Power Module.Figure 6.5 is a PM75RSA060 75 A,600V Intellimod™.

Figure 6.4 Ceramic Isolation Construction

Figure 6.5 PM75RSA060

SILICON CHIP

DBC PLATE

BASEPLATE

SILICON GEL

CASE

MAINTERMINAL

EPOXYRESIN

GUIDEPIN

INPUT SIGNALTERMINAL

INTERCONNECTTERMINALELECTRODE

ALUMINUM WIRE

SHIELDLAYER

RESISTOR

CONTROL BOARDPCB

SHIELDLAYER

SIGNALTRACE


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6.1.3 V-Series IPM Construction

V-Series IPMs are similar to theceramic isolated types describedin Section 6.1.2 except that aninsert molded case similar to theU-Series IGBT is used. Like theU-Series IGBT described inSection 4.1.5, the V-Series IPMhas lower internal inductance andimproved power cycle durability.Figure 6.6 is a cross sectiondrawing showing the constructionof the V-Series IPM. The insertmolded case makes the V-SeriesIPM is easier to manufacture andlower in cost. Figure 6.7 shows aPM150CVA120 which is a 150A1200V V-Series IPM.

6.1.4 Advantages of IntelligentPower Module

Intellimod™ Intelligent PowerModule products were designedand developed to provideadvantages to OEMs by reducingdesign, development, andmanufacturing costs as well asproviding improvement in system

performance and reliability overconventional IGBTs. Design anddevelopment effort is simplified andsuccessful drive coordination isassured by the integration of thedrive and protection circuitrydirectly into the IPM. Reduced timeto market is only one of theadditional benefits of using an IPM.Others include increased systemreliability through automated IPMassembly and test and reduction inthe number of components thatmust be purchased, stored, andassembled. Often the system sizecan be reduced through smallerheatsink requirements as a resultof lower on-state and switchinglosses. All IPMs use the samestandardized gate control interfacewith logic level control circuitsallowing extension of the productline without additional drive circuitdesign. Finally, the ability of theIPM to self protect in faultsituations reduce the chance ofdevice destruction duringdevelopment testing as well as infield stress situations.

6.2 IPM Ratings andCharacteristics

IPM datasheets are divided intothree sections:

• Maximum Ratings• Characteristics (electrical,

thermal, mechanical)• Recommended Operating

Conditions

The limits given as maximum ratingmust not be exceeded under anycircumstances, otherwisedestruction of the IPM may result.

Key parameters needed for systemdesign are indicated as electrical,thermal, and mechanicalcharacteristics.

The given recommended operatingconditions and application circuitsshould be considered as apreferable design guideline fittingmost applications.

POWER TERMINALS

SILICONE GEL

COVERINSERT MOLD CASE

DBC AIN CERAMIC SUBSTRATE

SILICON CHIPS BASE PLATE

PRINTED CIRCUITBOARD

ALUMINUM BOND WIRES

SIGNAL TERMINALS

Figure 6.6 V-Series IPM Construction Figure 6.7 PM150CVA120


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6.2.1 Maximum Ratings Symbol Parameter Definition

Inverter Part

VCC Supply Voltage Maximum DC bus voltage applied between P-N

VCES Collector-Emitter Voltage Maximum off-state collector-emitter voltage at applied control input off signal

±IC Collector-Current Maximum DC collector and FWDi current @ Tj ≤ 150°C ±ICP Collector-Current (peak) Maximum peak collector and FWDi current @ Tj ≤ 150°C PC Collector Dissipation Maximum power dissipation per IGBT switch at Tj = 25°C Tj Junction Temperature Range of IGBT junction temperature during operation

Brake Part

VR(DC) FWDi Reverse Voltage Maximum reverse voltage of FWDi

IF FWDi Forward Current Maximum FWDi DC current at Tj ≤ 150°C

Control Part

VD Supply Voltage Maximum control supply voltage

VCIN Input Voltage Maximum voltage between input (I) and ground (C) pins

VFO Fault Output Supply Voltage Maximum voltage between fault output (FO) and ground (C) pins

IFO Fault Output Current Maximum sink current of fault output (FO) pin

Total System

VCC(prot) Supply Voltage Protected Maximum DC bus voltage applied between P-N with guaranteed OC and SC protection

by OC & SC

TC Module Case Operating Range of allowable case temperature at specified reference point during operation

Temperature

Tstg Storage Temperature Range of allowable ambient temperature without voltage or current

Viso Isolation Voltage Maximum isolation voltage (AC 60Hz 1 min.) between baseplate and module terminals

(all main and signal terminals externally shorted together)

6.2.2 Thermal Resistance Symbol Parameter Definition

Rth(j-c) Junction to Case Maximum value of thermal resistance between junction and case per switch

Thermal Resistance

Rth(c-f) Contact Thermal Maximum value of thermal resistance between case and fin (heatsink) per IGBT/FWDi pair

Resistance with thermal grease applied according to mounting recommendations

6.2.3 Electrical Characteristics Symbol Parameter Definition

Inverter and Brake Part

VCE(SAT) Collector-Emitter IGBT on-state voltage at rated collector current under specified conditions

Saturation Voltage

VEC FWDi Forward Voltage FWDi forward voltage at rated current under specified conditions

ton Turn-on Time

trr FWDi Recovery Time Inductive load switching times under rated conditions

tc(on) Turn-on Crossover Time (See Figure 6.10)

toff Turn-off Time

tc(off) Turn-off Crossover Time

ICES Collector-Emitter Cutoff Collector-Emitter current in off-state at VCE = VCES under specified conditions


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The following test circuits are usedto evaluate the IPM characteristics.

1. VCE(SAT) and VEC

To ensure specified junctiontemperature, Tj, measurementsof VCE(SAT) and VEC must beperformed as low duty factorpulsed tests. (See Figures 6.8and 6.9)

6.2.3 Electrical Characteristics (continued) Symbol Parameter Definition

Control Part

VD Supply Voltage Range of allowable control supply voltage in switching operation

ID Circuit Current Control supply current in stand-by mode

VCIN(on) Input ON-Voltage A voltage applied between input (I) and ground (C) pins less than this value will turn on the IPM

VCIN(off) Input OFF-Voltage A voltage applied between input (I) and ground (C) pins higher than this value will turn off the IPM

fPWM PWM Input Frequency Range of PWM frequency for VVVF inverter operations

tDEAD Arm Shoot Through Time delay required between high and low side input off/on signals to prevent an

Blocking Time arm shoot through

OC Over-Current Trip Level Collector that will activate the over-current protection

SC Short-Circuit Trip Level Collector current that will activate the short-circuit protection

toff(OC) Over-Current Delay Time Time delay after collector current exceeds OC trip level until OC protection is activated

OT Over-Temperature Trip Level Baseplate temperature that will activate the over-temperature protection

OTr Over-Temperature Temperature that the baseplate must fall below to reset an over-temperature fault

Reset Level

UV Control Supply Control supply voltage below this value will activate the undervoltage protection

Undervoltage Trip Level

UVr Control Supply Control supply voltage that must exceed to reset an undervoltage fault

Undervoltage Reset Level

IFO(H) Fault Output Inactive Current Fault output sink current when no fault has occurred

IFO(L) Fault Output Active Current Fault Output sink current when a fault has occurred

tFO Fault Output Pulsed Width Duration of the generated fault output pulse

VSXR SXR Terminal Output Voltage Regulated power supply voltage on SXR terminal for driving the external optocoupler

6.2.4 Recommended Operation Conditions Symbol Parameter Definition

VCC Main Supply Voltage Recommended DC bus voltage range

VD Control Supply Voltage Recommended control supply voltage range

VCIN(on) Input ON-Voltage Recommended input voltage range to turn on the IPM

VCIN(off) Input OFF-Voltage Recommended input voltage range to turn off the IPM

fPWM PWM Input Frequency Recommended range of PWM carrier frequency using the recommended application circuit

tDEAD Arm Shoot Through Recommended time delay between high and low side off/on signals to the optocouplers

Blocking Time using the recommended application circuit

VX1

SXR

CX1

VXC

E1(E2)

C1(C2)

VD V IC

VX1

SXR

CX1

VXC

E1(E2)

C1(C2)

VD V IC

Figure 6.8 VCE(SAT) Test Figure 6.9 VEC Test

6.2.5 Test Circuits and Conditions


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2. Half-Bridge Test Circuit andSwitching Time Definitions.

Figure 6.10 shows thestandard half-bridge test circuitand switching waveforms.Switching times and FWDirecovery characteristics aredefined as shown in this figure.

3. Overcurrent andShort-Circuit Test

Itrip levels and timingspecifications in short circuitand overcurrent are defined asshown in Figure 6.11. By usinga fixed load resistance thesupply voltage, VCC, isgradually increased until OCand SC trip levels are reached.

Precautions:A. Before applying any main bus

voltage, VCC, the inputterminals should be pulled upby resistors to theircorresponding control supply(or SXR) pin, each input signalshould be kept in OFF state,and the control supply shouldbe provided. After this, thespecified ON and OFF level foreach input signal should beapplied. The control supplyshould also be applied to thenon-operating arm of themodule under test and inputsof these arms should be keptto their OFF state.

B. When performing OC and SCtests the applied voltage, VCC,must be less than VCC(prot)and the turn-off surge voltagespike must not be allowed torise above the VCES rating ofthe device. (These tests mustnot be attempted using acurve tracer.)

+

IC

INTEGRATEDGATE

CONTROLCIRCUIT

INTEGRATED GATE

CONTROLCIRCUIT

+

+

td (on)

ICIN

(t on = td (on) + tr)

tr td (off)

(t off = td (off) + tf)

tf

tc (off)tc (on)

10%

90%

10%

90%

IC

trr

IrrVCEIC

VCE

OFFSIGNAL

ONPULSE

VCC

VD

VD

Figure 6.10 Half-bridge Test Circuit and Switching Time Definitions

ONPULSE

SC

OC

INPUTSIGNAL

NORMALOPERATION

OVERCURRENT

SHORTCIRCUIT

VCON

PULSE

R*

R IS SIZED TO CAUSESC AND OC CONDITIONS

*

VCC+

toff (OC)

IC

INTEGRATEDGATE

CONTROLCIRCUIT

SC

OC

SC

OC

IC

IC

IC

Figure 6.11 Over-current and Short Circuit Test Circuit


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6.3 Area of Safe Operation forIntelligent Power Modules

The Intellimod™’s built-in gatedrive and protection circuits protectit from many of the operatingmodes that would violate the SafeOperation Area (SOA) of non-intelligent IGBT modules. Aconventional SOA definition thatcharacterizes all possiblecombinations of voltage, current,and time that would cause powerdevice failure is not required. Inorder to define the SOA for IPMs,the power device capability andcontrol circuit operation must bothbe considered. The resulting easyto use short circuit and switchingSOA definitions for IntelligentPower Modules are summarizedin this section.

6.3.1 Switching SOA

Switching or turn-off SOA isnormally defined in terms of themaximum allowable simultaneousvoltage and current duringrepetitive turn-off switchingoperations. In the case of the IPMthe built-in gate drive eliminatesmany of the dangerouscombinations of voltage andcurrent that are caused byimproper gate drive. In addition, themaximum operating current islimited by the over currentprotection circuit. Given theseconstraints the switching SOA canbe defined using the waveformshown in Figure 6.12. Thiswaveform shows that the IPM willoperate safely as long as the DCbus voltage is below the data sheetVCC(prot) specification, the turn-offtransient voltage across C-Eterminals of each IPM switch ismaintained below the VCES

specification, Tj is less than 125°C,and the control power supplyvoltage is between 13.5V and16.5V. In this waveform IOC is themaximum current that the IPM willallow without causing an OverCurrent (OC) fault to occur. In otherwords, it is just below the OC triplevel. This waveform defines theworst case for hard turn-offoperations because the IPM willinitiate a controlled slow shutdownfor currents higher than the OCtrip level.

6.3.2 Short Circuit SOA

The waveform in Figure 6.13depicts typical short circuitoperation. The standard testcondition uses a minimumimpedance short circuit whichcauses the maximum short circuitcurrent to flow in the device. In thistest, the short circuit current (ISC)is limited only by the devicecharacteristics. The IPM isguaranteed to survive non-repetitive short circuit and overcurrent conditions as long as theinitial DC bus voltage is less thanthe VCC(prot) specification, alltransient voltages across C-Eterminals of each IPM switch aremaintained less than the VCESspecification, Tj is less than 125°C,and the control supply voltage is

between 13.5V and 16.5V. Thewaveform shown depicts thecontrolled slow shutdown that isused by the IPM in order to helpminimize transient voltages.

Note:The condition VCE ≤ VCES has tobe carefully checked for each IPMswitch. For easing the designanother rating is given on the datasheets, VCC(surge), i.e., themaximum allowable switchingsurge voltage applied between theP and N terminals.

6.3.3 Active Region SOA

Like most IGBTs, the IGBTs usedin the IPM are not suitable for linearor active region operation. Normallydevice capabilities in this mode ofoperation are described in terms ofFBSOA (Forward Biased SafeOperating Area). The IPM’s internalgate drive forces the IGBT tooperate with a gate voltage ofeither zero for the off state or thecontrol supply voltage (VD) for theon state. The IPMs under-voltagelock out prevents any possibility ofactive or linear operation byautomatically turning the powerdevice off if VD drops to a levelthat could cause desaturation ofthe IGBT.

Figure 6.13 Short CircuitOperationFigure 6.12 Turn-off Waveform

IOC ≤VCES ≤VCC(PROT)

toff(OC)

≤VCES

≤VCES

≤VCC(PROT)

ISC


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6.4. IPM Self Protection

6.4.1 Self Protection Features

Intellimod™ Intelligent PowerModules have sophisticated built-inprotection circuits that prevent thepower devices from beingdamaged should the systemmalfunction or be over stressed.Our design and applicationsengineers have developed faultdetection and shut down schemesthat allow maximum utilization ofpower device capability withoutcompromising reliability. Controlsupply under-voltage, over-temperature, over-current, andshort-circuit protection are allprovided by the IPM's internal gatecontrol circuits. A fault output signalis provided to alert the systemcontroller if any of the protectioncircuits are activated. Figure 6.14 isa block diagram showing the IPM'sinternally integrated functions. Thisdiagram also shows the isolatedinterface circuits and control powersupply that must be provided bythe user. The internal gate controlcircuit requires only a simple +15VDC supply. Specially designed gatedrive circuits eliminate the need fora negative supply to off bias theIGBT. The Intellimod™'s controlinput is designed to interface withoptocoupled transistors with aminimum of external components.

The operation and timing of eachprotection feature is described inSections 6.4.2 through 6.4.5.

6.4.2 Control SupplyUnder-voltage Lock Out

The Intelligent Power Module'sinternal control circuits operatefrom an isolated 15V DC supply. If,for any reason, the voltage of thissupply drops below the specifiedunder-voltage trip level (UVt), thepower devices will be turned offand a fault signal will be generated.Small glitches less than thespecified tdUV in length will notaffect the operation of the controlcircuitry and will be ignored by theunder-voltage protection circuit. Inorder for normal operation toresume, the supply voltage mustexceed the under-voltage resetlevel (UVr). Operation of the under-voltage protection circuit will alsooccur during power up and powerdown of the control supply. Thisoperation is normal and the systemcontroller's program should takethe fault output delay (tfo) intoaccount. Figure 6.15 is a timingdiagram showing the operation ofthe under-voltage lock-outprotection circuit. In this diagram anactive low input signal is applied tothe input pin of the Intellimod™ bythe system controller. The effects ofcontrol supply power up, power

down and failure on the powerdevice gate drive and fault outputare shown.

Caution:1. Application of the main bus

voltage at a rate greater than20V/µs before the controlpower supply is on andstabilized may causedestruction of the powerdevices.

2. Voltage ripple on the controlpower supply with dv/dt inexcess of 5V/µs may cause afalse trip of the UV lock-out.

6.4.3 Over-temperatureProtection

The Intelligent Power Module has atemperature sensor mounted onthe isolating base plate near theIGBT chips. If the temperature ofthe base plate exceeds the over-temperature trip level (OT) theIntellimod™’s internal control circuitwill protect the power devices bydisabling the gate drive andignoring the control input signaluntil the over temperature conditionhas subsided. In six and sevenpack modules all three low sidedevices will be turned off and a lowside fault signal will be generated.High side switches are unaffectedand can still be turned on and offby the system controller. Similarly,in dual type modules only the lowside device is disabled. The faultoutput will remain as long as theover-temperature condition exists.When the temperature falls belowthe over-temperature reset level(OTr), and the control input is high(off-state) the power device will beenabled and normal operation willresume at the next low (on) inputsignal. Figure 6.16 is a timing

GATECONTROLCIRCUIT

GATE DRIVEOVER TEMPUV LOCK-OUTOVER CURRENTSHORT CIRCUIT

ISOLATEDPOWERSUPPLY

ISOLATINGINTERFACE

CIRCUIT

ISOLATINGINTERFACE

CIRCUIT

CURRENTSENSEIGBT

TEMPERATURESENSOR

SENSECURRENT

INTELLIGENT POWER MODULE

INPUTSIGNAL

FAULTOUTPUT

COLLECTOR

EMITTER

Figure 6.14 IPM Functional Diagram


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diagram showing the operation ofthe over-temperature protectioncircuit.

The over temperature functionprovides effective protectionagainst overloads and coolingsystem failures in mostapplications. However, it does notguarantee that the maximumjunction temperature rating of theIGBT chip will never be exceeded.In cases of abnormally high lossessuch as failure of the systemcontroller to properly regulatecurrent or excessively highswitching frequency it is possiblefor IGBT chip to exceed Tj(max)before the base plate reaches theOT trip level.

Caution:Tripping of the over-temperatureprotection is an indication ofstressful operation. Repetitivetripping should be avoided.

6.4.4 Over-current Protection

The IPM uses current sense IGBTchips to continuously monitorpower device current. If the currentthough the Intelligent PowerModule exceeds the specifiedovercurrent trip level (OC) for aperiod longer than toff(OC) theIPMs internal control circuit willprotect the power device bydisabling the gate drive andgenerating a fault output signal.The timing of the over-currentprotection is shown in Figure 6.17.The toff(OC) delay is implementedin order to avoid tripping of the OCprotection on short pulses ofcurrent above the OC level that arenot dangerous for the powerdevice. When an over-current isdetected a controlled shutdown is

initiated and a fault output isgenerated. The controlledshutdown lowers the turn-off di/dtwhich helps to control transientvoltages that can occur duringshut down from high fault currents.Most Intelligent Modules use thetwo step shutdown depicted inFigure 6.17. In the two stepshutdown, the gate voltage isreduced to an intermediate voltage

causing the current through thedevice to drop slowly to a low level.Then, about 5µs later, the gatevoltage is reduced to zerocompleting the shut down. Some ofthe large six and seven pack IPMsuse an active ramp of gate voltageto achieve the desired reduction inturn off di/dt under high faultcurrents. The oscillographs inFigure 6.18 illustrate the effect of

Figure 6.15 Operation of Under-Voltage Lockout

INPUTSIGNAL

BASE PLATETEMPERATURE

(Tb)

FAULT OUTPUTCURRENT

(IFO)

INTERNALGATE

VOLTAGEVGE

OTOTr

Figure 6.16 Operation of Over-Temperature

INPUTSIGNAL

CONTROLSUPPLY

VOLTAGE

FAULTOUTPUT

CURRENT(IFO)

INTERNALGATE

VOLTAGEVGE

CONTROL SUPPLY ON SHORTGLITCH

IGNORED

POWER SUPPLYFAULT AND RECOVERY

CONTROL SUPPLY OFF

UVrUVt

tFOtdUV tFO

tdUV


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the controlled shutdown (forobtaining the oscillograph in “A”the internal soft shutdown wasintentionally deactivated). TheIntellimod™ uses actual devicecurrent measurement to detect alltypes of over current conditions.

Even resistive and inductive shortsto ground that are often missed byconventional desaturation and buscurrent sensing protectionschemes will be detected by theIntellimod™’s current sense IGBTs.

Note:V-Series IPMs do not have an over-current protection function. Insteada unified short circuit protectionfunction that has a delay like theover current protection described inthis section is used.

NORMAL OPERATIONFWD RECOVERY CURRENT

IGNORED BY OC PROTECTION

OVER CURRENTFAULT ANDRECOVERY

SHORT CIRCUITFAULT ANDRECOVERY

NORMAL OPERATION

tFO tFO

tholdtholdtoff(OC)

INPUTSIGNAL

INTERNALGATE

VOLTAGE(VGE)

SHORT CIRCUITTRIP LEVEL

OVER CURRENTTRIP LEVEL

COLLECTORCURRENT

IFO

FAULT OUTPUTCURRENT

Figure 6.17 Operation of Over-Current and Short Circuit Protection

OC PROTECTION WITHOUT SOFT SHUTDOWN

VCE (surge)

OC PROTECTION WITH SOFT SHUTDOWN

IC VCEIC VCE

VCE (surge)

Figure 6.18 OC Operation of PM200DSA060 (IC: 100A/div; 100V/div; t: 1µs/div)


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6.4.5 Short Circuit Protection

If a load short circuit occurs or thesystem controller malfunctionscausing a shoot through, theIntellimod™’s built in short circuitprotection will prevent the IGBTsfrom being damaged. When thecurrent, through the IGBT exceedsthe short circuit trip level (SC), animmediate controlled shutdown isinitiated and a fault output isgenerated. The same controlledshutdown techniques used in theover current protection are used tohelp control transient voltagesduring short circuit shut down. Theshort circuit protection provided bythe Intellimod™ uses actual currentmeasurement to detect dangerousconditions. This type of protectionis faster and more reliable thanconventional out-of-saturationprotection schemes. Figure 6.17is a timing diagram showing theoperation of the short circuitprotection.

To reduce the response timebetween SC detection and SCshutdown, a real time currentcontrol circuit (RTC) has beenadopted. The RTC bypasses all butthe final stage of the IGBT driver inSC operation thereby reducing theresponse time to less than 100ns.The oscillographs in Figure 6.19illustrate the effectiveness of theRTC technique by comparing shortcircuit operation of secondgeneration IPM (without RTC) andthird generation IPM (with RTC).A significant improvement can beseen as the power stress is muchlower as the time in short circuitand the magnitude of the shortcircuit current are substantiallyreduced.

Note:The short circuit protection inV-Series IPMs has a delay similarto the third generation over currentprotection function described in6.4.4. The need for a quick trip hasbeen eliminated through the use ofa new advanced RTC circuit.

Caution:1. Tripping of the over current

and short circuit protectionindicates stressful operation ofthe IGBT. Repetitive trippingmust be avoided.

2. High surge voltages can occurduring emergency shutdown.Low inductance buswork andsnubbers are recommended.

6.5 IPM Selection

There are two key areas that mustbe coordinated for proper selectionof an IPM for a particular inverterapplication. These are peakcurrent coordination to the IPMovercurrent trip level and properthermal design to ensure thatpeak junction temperature isalways less than the maximumjunction temperature rating(150°C) and that the baseplatetemperature remains below theover-temperature trip level.

6.5.1 Coordination of OC Trip

Peak current is addressed byreference to the power rating of themotor. Tables 6.2, 6.3 and 6.4 giverecommended IPM types derivedfrom the OC trip level and the peakmotor current requirement basedon several assumptions for theinverter and motor operationregarding efficiency, power factor,maximum overload, and currentripple. For the purposes of thistable, the maximum motor currentis taken from the NEC table. Thisalready includes the motorefficiency and power factorappropriate to the particularmotor size. Peak inverter currentis then calculated using this RMScurrent, a 200% overloadrequirement, and a 20% ripplefactor. An IPM is then selectedwhich has a minimum overcurrenttrip level that is above thiscalculated peak operatingrequirement.

Figure 6.19 WaveformsShowing the Effectof the RTC Circuit

SHORT CIRCUIT OPERATION WITHOUT RTC CIRCUIT100A, 600V, IPM

SHORT CIRCUIT OPERATION WITH RTC CIRCUIT100A, 600V, IPM

800AVCE

IC

IC=200A/div, VCE=100V/div, t=1µs/div

VCET

ICT

410A

IC=200A/div, VCE=100V/div, t=1µs/div

T

T


A-84

Table 6.2 Motor Rating vs. OC Protection (230 VAC Line)Current

Motor Rating (HP) NEC Current Rating A(RMS)� Inverter Peak Current (A)* Applicable IPM Minimum OC Trip (A)

0.5 2.0 6.8 PM10CSJ060 12

0.75 2.8 9.5 PM10CSJ060 12

1 3.6 12.2 PM15CSJ060 18

1.5 5.2 17.6 PM15CSJ060 18

2 6.8 23 PM20CSJ060 28

3 9.6 32 PM30CSJ060, PM30RSF060 39

5 15.2 52 PM50RSA060, PM50RSK060 65

7.5 22 75 PM75RSA060, PM75RSK060 115

10 28 95 PM75RSA060, PM75RSK060 115

15 42 143 PM100CSA060, PM100RSA060 158

20 54 183 PM150CSA060, PM150RSA060 210

25 68 231 PM200CSA060, PM200RSA060, 310

PM200DSA060 x3

30 80 271 PM200CSA060, PM200RSA060, 310

PM200DSA060 x3

40 104 353 PM300DSA060 x3 390

50 130 441 PM400DSA060 x3 500

60 154 523 PM600DSA060 x3 740

75 192 652 PM600DSA060 x3 740

100 256 869 PM800HSA060 x6 1000� - From NEC Table 430-150* - Inverter peak current is based on 200% overload requirement and a 20% current ripple factor.

Table 6.3 Motor Rating vs. OC Protection (460 VAC Line)Current

Motor Rating (HP) NEC Current Rating A(RMS)� Inverter Peak Current (A)* Applicable IPM Minimum OC Trip (A)

0.5 1.0 3.4 PM10RSH120, PM10CZF120 15

0.75 1.4 4.8 PM10RSH120, PM10CZF120 15

1 1.8 6.1 PM10RSH120, PM10CZF120 15

1.5 2.6 8.8 PM10RSH120, PM10CZF120 15

2 3.4 12 PM10RSH120, PM10CZF120 15

3 4.8 16 PM15RSH120, PM15CZF120 22

5 7.6 26 PM25RSB120, PM25RSK120 32

7.5 11 37 PM50RSA120 59

10 14 48 PM50RSA120 59

15 21 71 PM75CSA120, PM75DSA120 x3 105

20 27 92 PM75CSA120, PM75DSA120 x3 105

25 34 115 PM100CSA120, PM100DSA120 x3 145

30 40 136 PM100CSA120, PM100DSA120 x3 145

40 52 176 PM150DSA120 x3 200

50 65 221 PM200DSA120 x3 240

60 77 261 PM300DSA120 x3 380

75 96 326 PM300DSA120 x3 380

100 124 421 PM400HSA120 x6 480

125 156 529 PM600HSA120 x6 740

150 180 611 PM600HSA120 x6 740

200 240 815 PM800HSA120 x6 1060

250 300 1020 PM800HSA120 x6 1060� - From NEC Table 430-150* - Inverter peak current is based on 200% overload requirement and a 20% current ripple factor.


A-85

6.5.2 Estimating Losses

Once the coordination of theOC trip with the applicationrequirements has been establishedthe next step is determining thecooling system requirements.Section 3.4 provides a generaldescription of the methodologyfor loss estimation and thermalsystem design. Figure 6.20shows the total switching energy(ESW(on)+ESW(off)) versus ICfor all third generation IPMs.Figure 6.21 shows total switchingenergy versus IC for V-Series IPMs.A detailed explanation of thesecurves and their use can be foundin Section 3.4.1. Figures 6.22through 6.34 show simulationresults calculating total power loss(switching and conduction) per armin a sinusoidal output PWM inverterapplication using V-Series IPMs.

Table 6.4 Motor Rating vs. SC Protection for V-Series IPMsCurrent

Motor Rating (HP) NEC Current Rating A(RMS)� Inverter Peak Current (A)* Applicable IPM Minimum SC Trip (A)

240VAC Line

10 28 95 PM75RVA060 115

15 42 143 PM100CVA060 158

20 54 183 PM150CVA060 210

30 80 271 PM200CVA060 310

40 104 353 PM300CVA060 396

50 130 441 PM400DVA060 650

75 192 652 PM600DVA060 1000

460VAC Line

10 14 48 PM50RVA120 59

20 27 92 PM75CVA120 105

30 40 136 PM100CVA120 145

40 52 176 PM150CVA120 200

50 65 221 PM200DVA120 240

75 96 326 PM300DVA120 380� - From NEC Table 430-150* - Inverter peak current is based on 200% overload requirement and a 20% current ripple factor.

100 101 102 103 10410-1

100

COLLECTOR CURRENT, IC, (AMPERES)

SW

ITC

HIN

TG

DIS

SIP

AT

ION

, (m

J/P

ULS

E)

101

103

102

CONDITIONS:INDUCTIVE LOADSWITCHING OPERATIONTj = 125oCVCC = 1/2 VCESVD = 15V

SWITCHING DISSIPATION = TURN-ON DISSIPATION + TURN-OFF DISSIPATIONCOMPATIBLE IC RANGE:RATED IC � 0.1 ~ 1.4

600V SERIES1200V SERIES

APPLICABLE TYPES: THIRD-GENERATION IPMPM200DSA060,PM75DSA120,PM300DSA120, PM75CSA120, PM20CSJ060,PM50RSK060,PM10RSH120,

PM300DSA060,PM100DSA120,PM100CSA060, PM100CSA120, PM300CSJ060,PM75RSA060,PM15RSH120,

PM400DSA060,PM150DSA120,PM150CSA060, PM10CSJ060, PM30RSF060,PM100RSA060,PM25RSB120,

PM600DSA060,PM200DSA120,PM200CSA060, PM15CSJ060, PM50RSA060,PM150RSA060,PM50RSA120

Figure 6.20 Switching Energy vs. IC for Third Generation IPMs


A-86

100 101 102 103 10410-1

100

COLLECTOR CURRENT, IC, (AMPERES)

SWITCHING ENERGY LOSS FOR V-SERIES IPMs

SW

ITC

HIN

G E

NE

RG

Y, (

mJ/

PU

LSE

)

101

103

102

CONDITIONS:INDUCTIVE LOADTj = 125oCVCC = 1/2 VCESVD = 15V

600V SERIES1200V SERIES

ESW (ON) + ESW (OFF)COMPATIBLE IC RANGE:RATED IC � 0.1 ~ 1.4

0 20 40 60 10080 1200

IO(ARMS)

50

P(W

)

100

150

200

250

DC LOSSSW LOSSTOTAL LOSS

VCC = 300VVD = 15VTj = 125°CP.F. = 0.8fc = 10kHz

Figure 6.21 Figure 6.22 Power LossSimulation ofPM75RVA060 (Typ.)

Figure 6.23 Power LossSimulation ofPM100CVA060 (Typ.)



Figure 6.27 Power LossSimulation ofPM400DVA060 (Typ.)



Figure 6.29 Power LossSimulation ofPM50RVA120(Typ.)

0 20 40 60 10080 1200

IO(ARMS)

50

P(W

)

100

150

200

250



0 20 40 60 10080 1200

IO(ARMS)

50

P(W

)

100

150

200

250



0 40 80 120 200160 2400

IO(ARMS)

50

P(W

)

100

150

200

250



0 40 80 120 200160 2400

IO(ARMS)

50

P(W

)

100

150

200

250



0 40 80 120 200160 2400

IO(ARMS)

50

P(W

)

100

150

200

250



0 40 80 120 200160 360320240 2800

IO(ARMS)

50

P(W

)

100

150

300

250

200

350



0 15 30 45 9075600

IO(ARMS)

50

P(W

)

100

150

300

250

200

350




A-87

6.6 Controlling the IntelligentPower Module

Intellimod™ Intelligent PowerModules are easy to operate. Theintegrated drive and protectioncircuits require only an isolatedpower supply and a low levelon/off control signal. A fault outputis provided for monitoring theoperation of the modules internalprotection circuits.

6.6.1 The Control Power Supply

Depending on the power circuitconfiguration of the module one,two, or four isolated power suppliesare required by the Intellimod™’sinternal drive and protectioncircuits. In high power 3-phaseinverters using single or dual typeIPMs it is good practice to use sixisolated power supplies. In thesehigh current applications each lowside device must have its ownisolated control power supply inorder to avoid ground loop noiseproblems. The control suppliesshould be regulated to 15V +/-10%in order to avoid over-voltagedamage or false tripping of theunder-voltage protection. Thesupplies should have an isolationvoltage rating of at least twotimes the IPM’s VCES rating(i.e. Viso = 2400V for 1200Vmodule). The current that must besupplied by the control powersupply is the sum of the quiescentcurrent needed to power theinternal control circuits and thecurrent required to drive theIGBT gate.

Table 6.5 summarizes the typicaland maximum control powersupply current requirements forthird generation Intelligent Power

Figure 6.30 Power LossSimulation ofPM75RVA120 (Typ.)





0 15 30 45 9075600

IO(ARMS)

50

P(W

)

100

150

300

250

200

350



0 20 40 60 10080 180160120 1400

IO(ARMS)

50

P(W

)

100

150

300

250

200

350



0 20 40 60 10080 180160120 1400

IO(ARMS)

50

P(W

)

100

150

300

250

200

350



0 20 40 60 10080 180160120 1400

IO(ARMS)

50

P(W

)

100

150

300

250

200

350



0 20 40 60 10080 180160120 1400

IO(ARMS)

50

P(W

)

100

150

300

250

200

350




A-88

Modules. Table 6.6 summarizescontrol supply requirements forV-Series IPMs. These tables givecontrol circuit currents for thequiescent (not switching) state andfor 20kHz switching. This data isprovided in order to help the userdesign appropriately sized controlpower supplies.

Power requirements for operatingfrequencies other than 20kHz canbe determined by scaling thefrequency dependent portion of thecontrol circuit current. For example,to determine the maximum controlcircuit current for a PM300DSA120operating at 7kHz the maximumquiescent control circuit current issubtracted from the maximum20kHz control circuit current:

70mA – 30mA = 40mA

40mA is the frequency dependentportion of the control circuit currentfor 20kHz operation. For 7kHzoperation the frequencydependent portion is:

40mA x (7kHz ÷ 20kHz) = 14mA

To get the total control powersupply current required, thequiescent current must be addedback:

30mA + 14mA = 44mA

44mA is the maximum controlcircuit current required for aPM300DSA120 operating at 7kHz.

Capacitive coupling betweenprimary and secondary sidesof isolated control supplies mustbe minimized as parasiticcapacitances in excess of 100pFcan cause noise that may trigger

Table 6.5 Control Power Requirements for Third Generation IPMs(VD = 15V, Duty = 50%) ma

N Side P Side (Each Supply)

DC 20kHz DC 20kHz

Type Name Typ. Max Typ. Max. Typ. Max. Typ. Max.

600V Series

PM10CSJ060 18 25 23 32 7 10 8 12

PM15CSJ060 18 25 23 32 7 10 8 12

PM20CSJ060 18 25 24 34 7 10 8 12

PM30CSJ060 18 25 24 34 7 10 9 13

PM100CSA060 40 55 78 100 13 18 25 34

PM150CSA060 40 55 80 110 13 18 25 38

PM200CSA060 40 55 85 120 13 18 27 40

PM30RSF060 25 30 32 45 7 10 9 13

PM50RSA060 44 60 70 100 13 18 23 32

PM50RSK060 44 60 70 100 13 18 23 32

PM75RSA060 44 60 75 100 13 18 24 35

PM100RSA060 44 60 78 105 13 18 25 36

PM150RSA060 52 72 72 113 13 18 26 38

PM200RSA060 52 72 85 115 13 18 26 40

PM200DSA060 19 26 30 42 19 26 30 42

PM300DSA060 19 26 35 48 19 26 35 48

PM400DSA060 23 30 40 60 23 30 40 60

PM600DSA060 23 30 50 70 23 30 50 70

PM800HSA060 23 30 50 70 – – – –

1200V SERIES

PM10RSH120 25 35 31 44 7 10 9 13

PM10CZF120 18 25 7 10 9 13

PM15RSH120 25 35 32 45 7 10 9 13

PM15CZF120 18 25 7 10 9 13

PM25RSB120 44 60 60 83 13 18 18 25

PM25RSK120 44 60 60 83 13 18 18 25

PM50RSA120 44 60 65 90 13 18 19 27

PM75CSA120 44 60 60 83 13 18 20 28

PM100CSA120 40 55 75 104 13 18 25 35

PM75DSA120 13 20 20 28 13 20 20 28

PM100DSA120 19 26 30 42 19 26 30 42

PM150DSA120 19 26 35 48 19 26 35 48

PM200DSA120 23 30 48 67 23 30 48 67

PM300DSA120 23 30 50 70 23 30 50 70

PM400HSA120 23 30 60 90 – – – –

PM600HSA120 23 30 60 90 – – – –

PM800HSA120 30 40 – – – – – –


A-89

the control circuits. An electrolyticor tantalum decoupling capacitorshould be connected across thecontrol power supply at theIntellimod™’s terminals. Thiscapacitor will help to filter commonnoise on the control power supplyand provide the high pulse currentsrequired by the Intellimod™’sinternal gate drive circuits. Isolatedcontrol power supplies can becreated using a variety oftechniques. Control power can bederived from the main input lineusing either a switching powersupply with multiple outputs or aline frequency transformer withmultiple secondaries. Controlpower supplies can also be derivedfrom the main logic power supplyusing DC-to-DC converters. Usinga compact DC-to-DC converter foreach isolated supply can help tosimplify the interface circuit layout.A distributed DC-to-DC converter inwhich a single oscillator is used todrive several small isolation

transformers can provide the layoutadvantages of separate DC-to-DCconverters at a lower cost.

In order to simplify the design ofthe required isolated powersupplies, Powerex has developedtwo DC-to-DC converter modulesto work with the IPMs. TheM57120L is a high input voltagestep down converter. Whensupplied with 113 to 400VDC theM57120L will produce a regulated20VDC output. The 20VDCcan then be connected to theM57140-01 to produce fourisolated 15VDC outputs to powerthe IPMs control circuits. TheM57140-01 can also be used as astand alone unit if 20VDC isavailable from another source suchas the main logic power supply.Figure 6.35 shows an isolatedinterface circuit for a seven packIPM using M57140-01. Figure 6.36shows a complete high inputvoltage isolated power supply

circuit for a dual type intelligentpower module.

Caution:Using bootstrap techniques is notrecommended because the voltageripple on VD may cause a false tripof the undervoltage protection incertain inverter PWM modes.

6.6.2 Interface CircuitRequirements

The IGBT power switches in theIntellimod™ are controlled by a lowlevel input signal. The active lowcontrol input will keep the powerdevices off when it is held high.Typically the input pin of theIntellimod™ is pulled high with aresistor connected to the positiveside of the control power supply. AnON signal is then generated bypulling the control input low. Thefault output is an open collectorwith its maximum sink currentinternally limited. When a faultcondition occurs the open collectordevice turns on allowing the faultoutput to sink current from thepositive side of the control supply.Fault and on/off control signals areusually transferred to and from thesystem controller using isolatinginterface circuits. Isolatinginterfaces allow high and low sidecontrol signals to be referenced toa common logic level. The isolationis usually provided by optocouplers.However, fiber optics, pulsetransformers, or level shiftingcircuits could be used. The mostimportant consideration in interfacecircuit design is layout. Shieldingand careful routing of printed circuitwiring is necessary in order toavoid coupling of dv/dt noise intocontrol circuits. Parasiticcapacitance between high side

Table 6.6 V-Series IPM Control Power Supply Current

N Side P Side (Each Supply)

DC 20kHz DC 20kHz

Type Name Typ. Max Typ. Max. Typ. Max. Typ. Max.

600V Series

PM75RVA060 44 60 72 94 13 18 21 27

PM100CVA060 40 55 68 88 13 18 22 29

PM150CVA060 40 55 72 94 13 18 23 30

PM200CVA060 40 55 84 110 13 18 28 36

PM300CVA060 52 72 130 170 17 24 43 56

PM400DVA060 23 30 56 73 23 30 56 73

PM600DVA060 23 30 56 73 23 30 56 73

1200V SERIES

PM50RVA120 44 60 73 95 13 18 21 27

PM75CVA120 40 55 70 92 13 18 24 31

PM100CVA120 40 55 80 104 13 18 26 34

PM150CVA120 72 100 128 166 24 34 42 55

PM200DVA120 37 48 52 68 37 48 52 68

PM300DVA120 37 48 52 68 37 48 52 68


A-90

1

HCPL4504

0.1�F

SEVEN PACK IPM

VUP1

UP

VUPC

UFOC1

20k

0.1�F20k

2

3

4

8

7

6

5

3PC817

4

2

1

1

HCPL4504

2

3

4

8

7

6

5

3PC817

4

1

2

3

4

5

-

+

+

6

7

8

9

10

11VIN

12

13

14

0+15

0+15

0+15

0+15

2

1

M57140-01

4

3

2

1

VVP1

VP

VVPC

VFO

VWP1

WP

VWPC

WFO

UN

BR

VNC

VNI

FO

VN

WN

8

7

6

5

12

11

10

9

16

15

14

13

19

18

17

1

HCPL4504

0.1�F

+

+

20k2

3

4

8

7

6

5

3PC817

4

2

1

C1

+

C1

+

1

HCPL4504

0.1�F

4.7k

C2

+

2

3

4

8

7

6

5

1PC817

2

4

3

1

HCPL4504

0.1�F2

3

4

8

7

6

5

1

HCPL4504

0.1�F

20k

20k

20k

2

3

4

8

7

6

5

3PC817

4

2

1

20V

330�F

FON

WN

VN

UN

B

WP

FOWP

VP

FOVP

UP

FOUP

NOTE: FOR C1 AND C2 SEE SECTION 6.6.3

Figure 6.35 Isolated Interface Circuit for Seven-Pack IPMs


A-91

interface circuits, high and low sideinterface circuits, or primary andsecondary sides of the isolatingdevices can cause noise problems.Careful layout of control powersupply and isolating circuit wiring isnecessary. The following is a list ofguidelines that should be followedwhen designing interface circuits.Figure 6.37 shows an exampleinterface circuit layout for dual typeIPMs. Figure 6.38 shows anexample interface circuit layout fora V-Series IPMs.The shielding andprinted circuit routing techniquesused in this example are intendedto illustrate a typical application ofthe layout guidelines.

INTERFACE CIRCUITLAYOUT GUIDELINES

I. Maintain maximum interfaceisolation. Avoid routing printedcircuit board traces from primaryand secondary sides of theisolation device near to or aboveand below each other. Any layoutthat increases the primary tosecondary capacitance of theisolating interface can causenoise problems.

II. Maintain maximum control powersupply isolation. Avoid routingprinted circuit board traces fromUP, VP, WP, and N side suppliesnear to each other. High dv/dtsexist between these suppliesand noise will be coupledthrough parasitic capacitances.If isolated power supplies arederived from a commontransformer interwindingcapacitance should beminimized.

III. Keep printed circuit board tracesbetween the interface circuit andIntellimod™ short. Long traceshave a tendency to pick up noisefrom other parts of the circuit.

IV. Use recommended decouplingcapacitors for power suppliesand optocouplers. Fast switchingIGBT power circuits generatedv/dt and di/dt noise. Everyprecaution should be taken toprotect the control circuits fromcoupled noise.

V. Use shielding. Printed circuitboard shield layers are helpfulfor controlling coupled dv/dt

noise. Figure 6.37 shows anexample of how the primary andsecondary sides of the isolatinginterface can be shielded.

VI. High speed optocouplers withhigh common mode rejection(CMR) should be used for signalinput:

tPLH,tPHL < 0.8µsCMR > 10kV/µs@ VCM = 1500V

Appropriate optocoupler typesare HCPL 4503, HCPL 4504(Hewlett Packard) and PS2041(NEC). Usually high speed optosrequire a 0.1µF decouplingcapacitor close to the opto.

VII. Select the control input pull-upresistor with a low enoughvalue to avoid noise pick-up bythe high impedance IPM inputand with a high enough valuethat the high speedoptotransistor can still pull theIPM safely below therecommended maximumVCIN(on).

Figure 6.36 Isolated Interface Circuit for Dual Intelligent Power Modules

1

HCPL4504

0.1�F

C1

V1 (+)

P

SR (+5)

CIN

FO

VC (-)

V1 (+)

N

C1

DUAL IPM

SR (+5)

CINCI

FO

VC (-)

+

6.8k

0.1�F6.8k

2

3

4

8

7

6

5

3PC817

4

2

1

1

HCPL4504

2

3

4

8

7

6

5

3PC817

4

3

22.2�F

47�F50V

330�F50V 1

7 5 2 112

113-400VDC

11

6

5

-

+

+

+

+

+

+

4

14

NFO

NIN

PFO

PIN

13

12

11

10VIN

9

8

7

+150

+150

+150

+150

2

1

M57140-01

M57120L

1

2

3

45

1

2

3

45


A-92

Figure 6.37 Interface Circuit Layout Example for Dual IPMs

WNVNUNWPVPUP

+-

+-

+-

+-

+-

+-FO

WN

FO

WP

FO

VN

VP

FO

UN

FO

UP

FO

SHIELDS GROUND TO NEGATIVE SIDE OF EACH CONTROL

POWER SUPPLY

DIGITAL GROUND

MID-LAYER SHIELD

TO CONTROL POWER SOURCE

W

V

U

LEGEND

TOP LAYER

MIDDLE LAYER

BOTTOM LAYER

SHIELD GROUND TO VUNC

SHIELD GROUND TO VUPC

SHIELD GROUND TO VVNC

SHIELD GROUND TO VVPC

SHIELD GROUND TO VWNC

SHIELD GROUND TO VWPC


A-93

VIII.If some IPM switches are notused in actual application theircontrol power supply must stillbe applied. The related signalinput terminals should bepulled up by resistors to thecontrol power supply (VD orVSXR) to keep the unusedswitches safely in off-state.

IX. Unused fault outputs must betied high in order to avoid noisepick up and unwantedactivation of internal protectioncircuits. Unused fault outputsshould be connected directly tothe +15V of local isolatedcontrol power supply.

6.6.3 Example Interface Circuits

Intellimod™ Intelligent PowerModules are designed to useoptocoupled transistors for controlinput and fault output interfaces. Inmost applications optocouplers willprovide a simple and inexpensiveisolated interface to the system

controller. Figures 6.39 through6.43 show example interfacecircuits for the four Intellimod™power circuit configurations. Thesecircuits use two types ofoptocoupled transistors. Thecontrol input on/off signals aretransferred from the systemcontroller using high speedoptocoupled transistors. Usuallyhigh speed optos require a 0.1µFfilm or ceramic decouplingcapacitor connected near their VCCand GND pins. The value of thecontrol input pull up resistor isselected low enough to avoid noisepick up by the high impedanceinput and high enough so that thehigh speed optotransistor with itsrelatively low current transfer ratiocan still pull the input low enoughto assure turn on. The circuitsshown use a Hewlett PackardHCPL-4504 optotransistor. Thisopto was chosen mainly for its highcommon mode transient immunityof 15,000V/µs. For reliableoperation in IGBT power circuits

optocouplers should have aminimum common mode noiseimmunity of 10,000 V/µs. Lowspeed optocoupled transistors canbe used for the fault output andbrake input. Slow optos have theadded advantages of lower costand higher current transfer ratios.The example interface circuits usea Sharp PC817 low speedoptocoupled transistor for thetransfer of brake and fault signals.Like most low speed optos thePC817 does not have internalshielding. Some switching noisewill be coupled through the opto.An RC filter with a time constant ofabout 10µs can be added to theopto’s output to remove this noise.The Intellimod™s 1.5ms long faultoutput signal will be almostunaffected by the addition of thisfilter. When designing interfacecircuits always follow the interfacecircuit layout guidelines given inSection 6.6.2.

Figure 6.38 Interface Circuit Layout for a V-Series IPMs

BPN

U V WIPM

IPM

INTERFACE CIRCUIT

PCB


A-94

Figure 6.39 Interface Circuit for Seven-Pack IPMs

N

P

B

U

V

W

LIN

EM

OT

OR

+

CS

VUPC

UFO

UP

VUP1

VVPC

VFO

VP

VVP1

VWPC

WFO

WP

VWP1

VNC

VN1

BR

UN

VN

WN

FO

7-P

AC

K T

HIR

D G

EN

ER

AT

ION

IPM

10µF

20k 0.1µF

15 V

+

FAULT

UP IN

TE

RF

AC

E

INPUT

15 V

+

15 V

+

15 V

+

VP IN

TE

RF

AC

EW

P IN

TE

RF

AC

EN

SID

E IN

TE

RF

AC

E

FAULT OUTPUT

INPUT

BRAKE

UN INPUT

VN INPUT

WN INPUT

FAULT

0.1µF

0.1µF

0.1µF

33µF

20k

4.7k

20k

20k

SAME AS

UP INTERFACE

CIRCUIT

SAME AS

UP INTERFACE

CIRCUIT

FAULT OUTPUT

INPUT

Rated Decoupling Applicable Current Capacitor Types (Amps) (CS)

600V Modules

PM30RSF060 30 0.3µF

PM50RSK060 55 0.47µF

PM50RSA060 50 0.47µF

PM75RSA060, 75 1.0µF

PM75RSK060,

PM75RVA060

PM100RSA060 100 1.0µF

PM150RSA060 150 1.5µF

PM200RSA060 200 2.0µF

1200V Modules

PM10RSH120 10 0.1µF

PM15RSH120 15 0.1µF

PM25RSB120, 25 0.22µF

PM25RSK120

PM50RSA120, 50 0.47µF

PM50RVA120

NOTE: If high side fault outputs are not used, theymust be connected to the +15V of the local powersupply.


A-95

Figure 6.40 Interface Circuit for Six-Pack IPMs

N

P

U

V

W

LIN

EM

OT

OR

+

CS

VUPC

UFO

UP

VUP1

VVPC

VFO

VP

VVP1

WFO

VWP1

VNC

VN1

UN

VN

WN

FO

6-P

AC

K T

HIR

D G

EN

ER

AT

ION

IPM

10µF

20k 0.1µF

15 V

+

FAULT

UP IN

TE

RF

AC

E

INPUT

15 V

+

15 V

+

15 V

+

VP IN

TE

RF

AC

EW

P IN

TE

RF

AC

EN

SID

E IN

TE

RF

AC

E

FAULTOUTPUT

INPUT

UN INPUT

VN INPUT

WN INPUT

FAULT

0.1µF

0.1µF

0.1µF

33µF

20k

20k

20k

SAME AS

UP INTERFACE

CIRCUIT

VWPC

WP

SAME AS

UP INTERFACE

CIRCUIT

FAULTOUTPUT

INPUT

Rated Decoupling Applicable Current Capacitor Types (Amps) (CS)

600V Modules

PM10CSJ060 10 0.1µF

PM15CSJ060 15 0.1µF

PM20CSJ060 20 0.1µF

PM30CSJ060 30 0.3µF

PM100CSA060, 100 1.0µF

PM100CVA060

PM150CSA060, 150 1.5µF

PM150CVA060

PM200CSA060, 200 2.2µF

PM200CVA060

PM300CVA060 300 3.0µF

1200V Modules

PM75CSA120, 75 1.0µF

PM75CVA120

PM100CSA120, 100 1.0µF

PM100CVA120

PM150CVA120 150 1.5µF

NOTE: Unused fault outputs must be connected tothe +15V of the local control supply.


A-96

Figure 6.41 Interface Circuit for Dual IPMs

C2

6.8k

+

C2 C2

15 V 15 V

15 V15 V15 V

VCCWVU

MOTOR

IPM

+

+++ +

IPMIPM

INPUT

FAULT

++

0.1µF

0.1µF

6.8k

C1 +

C1 +

15 V

FNO

VNC

CNI

SNR

VN1

FPO

VPC

CPI

SPR

VP1

FNO

VNC

CNI

SNR

VN1

FPO

VPC

CPI

SPR

VP1

FNO

VNC

CNI

SNR

VN1

FPO

VPC

CPI

SPR

VP1

E1C2 C1E2 E1C2 C1E2 E1C2 C1E2

INPUT

FAULT

Control PowerRated Decoupling Snubber

Applicable Current Capacitor Capacitor Types (Amps) (C1) (C2)

600V Modules

PM200DSA060 200 47µF 2.0µF

PM300DSA060 300 47µF 3.0µF

PM400DSA060, 400 68µF 4.0µF

PM400DVA060

PM600DSA060, 600 68µF 6.0µF*

PM600DVA060

1200V Modules

PM75DSA120 75 22µF 0.68µF

PM100DSA120 100 47µF 1.5µF

PM150DSA120 150 47µF 2.0µF

PM200DSA120, 200 68µF 3.0µF

PM200DVA120

PM300DSA120, 300 68µF 5.0µF

PM300DVA120

*Depending on maximum DC link voltage andmain circuit layout, an RCDi clamp may beneeded. (see Section 3.3)


A-97

Control Power Main BusRated Decoupling Snubber Decoupling

Applicable Current Capacitor Capacitor Capacitor Types (Amps) (C1) (C2) (C3) Snubber Diode

600V Modules

PM800HSA060 800 68µF 3.0µF 6.0µF RM50HG-12S (2 pc. parallel)

1200V Modules

PM400HSA120 400 68µF 1.5µF 4.0µF RM25HG-24S

PM600HSA120 600 68µF 2.0µF 6.0µF RM25HG -24S (2 pc. parallel)

PM800HSA120 800 68µF 3.0µF 6.0µF RM25HG-24S (3 pc. parallel)

Figure 6.42 Interface Circuit for Single IPMs

+

+15 V

6.8k

IPM

0.1µF

C1

INPUT

FAULT

V1

SR

C1

C2

VC

C

E

D

FO

+

+15 V

6.8k

IPM

0.1µF

C1

V1

SR

C1

VC

C

E

FO

C2

C3 C3 C3

D

IPM

V1

SR

C1

C2

VC

C

E

D

FO

IPM

V1

SR

C1

VC

C

E

FO

C2

D

IPM

V1

SR

C1

C2

VC

C

E

D

FO

IPM

V1

SR

C1

VC

C

E

FO

C2

D

+ +

+15V

+

VCC

+

MOTOR

U V W

INPUT

FAULT

15V

15V 15V


A-98

Figure 6.43 Interface Circuit for PM10CZF120 and PM15CZF120

0.1�

0.1�

10�+

–

20k

20k

VWP

WP

VWPC

UN

VN

WN

VN1

FO

VNC

IFVD3VD3

VD4

5V

10k

0.1�10�

+

–

20kVVP

VP

VVPC

IFVD2

0.1�10�

+

–

20kVUP

UP

VUPC

IFVD1

IF

0.1�

20k

IF

0.1�

20k

IF

33�+

–

M

CS

P

U

V

W

N

+

–

VCC


A-99

6.6.4 Connecting theInterface Circuit

The input pins of PowerexIntelligent Power Modules aredesigned to be connected directlyto a printed circuit board. Noisepick up can be minimized bybuilding the interface circuit on thePCB near the input pins of themodule. Low power modules havetin plated control and power pinsthat are designed to be soldereddirectly to the PCB. Higher powermodules have gold plated pins thatare designed to be connected tothe PCB using an inverse mountedheader receptacle. An example ofthis connection for a dual type IPMis shown in Figure 6.44. Thisconnection technique can also beadapted to large six and sevenpack modules. Table 6.7 shows thesuggested connection method andconnector for each ThirdGeneration IPM.

Table 6.8 shows the suggestedconnection method and connectorfor V-Series IPMs. Figure 6.45shows the PCB layout for V-Seriessix and seven pack connector.

Figure 6.44 Connection of the Interface Circuit

ABCDE

Hole for Header receptacle pinClearance Hole for Intellimod pinClearance Hole for Intellimod guide pinIntellimod pin spacingHeader Receptacle Pin Spacing

.040" Typ.

.070" Typ.

.090" Typ.0.10" Typ.

per connector mfg.

A

C

B

SIDE VIEW

END VIEW

E

D

HEADER RECEPTACLE

PRINTED CIRCUIT BOARD

INTELLIMOD'S GUIDE PINS

C1

PCB LAYOUT EXAMPLE FOR DUAL TYPE 3RD GENERATION IPM

Table 6.7 Third Generation Intellimod™ Connection Methods

Third Generation Intelligent Power Module Type Connection Method

PM10CSJ060, PM15CSJ060, PM20CSJ060, Solder to PCBPM30CSJ060, PM30RSF060, PM50RSK060,PM10RSH120, PM15RSH120

PM50RSA060, PM75RSA060, PM100CSA060, 31 Position 2mm Inverse HeaderPM100RSA060, PM150CSA060, PM150RSA060, ReceptaclePM200CSA060, PM25RSB120, PM50RSA120, Hirose P/N: DF10-31S-2DSA (59)PM75CSA120, PM100CSA120

PM200DSA060, PM300DSA060, PM400DSA060, 5 Position 2.54mm (0.1") InversePM600DSA060, PM75DSA120, PM100DSA120, Header ReceptaclePM150DSA120, PM200DSA120, PM300DSA120, Method P/N: 1000-205-2105PM400HSA120, PM600HSA120 Hirose P/N: MDF7-5S-2.54DSA


A-100

6.6.5 Dead Time (tDEAD)

In order to prevent arm shootthrough a dead time between highand low side input ON signals isrequired to be included in thesystem control logic. Two differentvalues are specified on thedatasheet:

A. tDEAD measured directly onthe IPM input terminals

B. tDEAD related to optocouplerinput signals using therecommended applicationcircuit

The specified type B dead time isrelated to standard high speedoptocouplers. (See Section 6.6.2)By using specially selected

optocouplers with narrowdistribution of switching timesthe required type B dead timecould be reduced.

6.6.6 Using the Fault Signal

In order to keep the interfacecircuits simple the Intellimod usesa single on/off output to alert thesystem controller of all faultconditions. The system controllercan easily determine whether thefault signal was caused by an overtemperature or over current/shortcircuit by examining its duration.Short circuit and over currentcondition fault signals will be tFO(nominal 1.5ms) in duration. Anover temperature fault signal will bemuch longer. The over temperaturefault starts when the base plate

Figure 6.45 PCB Layout for V-Series Connector

temperature exceeds the OT leveland does not reset until the baseplate cools below the OTR level.Typically this takes tens ofseconds.

Note:Unused fault outputs must beproperly terminated by connectingthem to the +15V on the localcontrol power supply. Failure toproperly terminate unused faultoutputs may result in unexpectedtripping of the modules internalprotection.

3 ± 0.05 3 ± 0.053 ± 0.05

3 ± 0.053 ± 0.05

43.57 ± 0.1

19 - ø1.2 +0.10

19 - ø0.9 +0.10

4 - ø3.2 +0.1-0.07

14.1 ± 0.0514.1 ± 0.052.54 ± 0.05

2.54 ± 0.05

14.1 ± 0.05

14.6 ± 0.1

Table 6.8 V-Series Intellimod™ Connection Methods

V-Series Intelligent Power Module Type Connection Method

PM75RVA060, PM100CVA060, PM150CVA060, 19 Position, 0.1" CompoundPM200CVA060, PM300CVA060, PM50RVA120, Inverse Header Receptacle,PM75CVA120, PM100CVA120, PM150CVA120 Hirose Part # MDF92-19S-2.54DSA

PM400DVA060, PM600DVA060, 5 Position, 0.1" (2.54mm)PM200DVA120, PM300DVA120 Inverse Header Receptacle,

Hirose Part # MDF7-5S-2.54DSA


A-101

6.7 Intellimod™ InverterExample

The Intellimod™’s integratedintelligence greatly simplifiesinverter design. The built inprotection circuits allow maximumutilization of power devicecapability without compromisingreliability. Figure 6.46 shows acomplete inverter constructedusing dual type IPMs. Inputcommon mode noise filtering andMOV surge suppression helps toprotect the input rectifier and IPMsfrom line transients. The mainpower bus is constructed usinglaminated plates in order tominimize parasitic inductance. Lowinductance bus designs arecovered in more detail in Sections3.2 and 3.3. An example of themechanical layout of the inverter isshown in Figure 6.47. The IPMsmust be mounted on a heatsinkwith suitable cooling capabilities.Thermal design and power lossestimation is covered in Section3.4. Powerex offers a completeline-up of diode modules that areideal for use as the input bridge ininverter applications.

Figure 6.46 Intellimod™ Inverter System

+

–

RECTIFIERBRIDGE

A

C

B

C

C

C

HEAT SINKGROUND

IPM

+

IPM IPM

PRINTED CIRCUIT BOARDCONTAINING INTERFACECIRCUITS AND ISOLATEDPOWER SUPPLIES

MICRO-CONTROLLERPWM GENERATOR

INPUT COMMON MODENOISE FILTER AND MOVSURGE PROTECTION

C ≈ 470pF STYLE 2 & 3C ≈ 2200pF STYLE 1

MAINFILTER

3-PHASE INPUTLAMINATEDBUSSTRUCTURE

U V W

TO LOAD (3-PHASE MOTOR)

S

SNUBBER

S S S

Figure 6.47 Power Circuit Layout for IPMs

CONTROL

PRINTED CIRCUIT

BOARD

SNUBBERCIRCUIT

HEAT SINK

INTELLIMODS

COPPER-INSULATOR-COPPER

SANDWICH

CAPACITOR


A-102

6.8 Handling Precautions forIntelligent Power Modules

Electrical Considerations:

I. Apply proper control voltagesand input signals before statictesting.

II. Carefully check wiring ofcontrol voltage sources andinput signals. Miswiring maydestroy the integrated gatecontrol circuit.

III. When measuring leakagecurrent always ramp the curvetracer voltage up from zero.Ramp voltage back downbefore disconnecting thedevice. Never apply a voltagegreater than the VCES ratingof the device.

IV. When measuring saturationvoltage low inductance testfixtures must be used.Inductive surge voltages canexceed device ratings.

Mechanical Considerations:

I. Avoid mechanical shock. Themodule uses ceramic isolationthat can be cracked if themodule is dropped.

II. Do not bend the powerterminals. Lifting or twisting thepower terminals may causestress cracks in the copper.

III. Do not over torque terminal ormounting screws. Maximumtorque specifications areprovided in device data sheets.

IV. Avoid uneven mounting stress.A heatsink with a flatness of0.001"/1" or better isrecommended. Avoid one sidedtightening stress. Figure 6.48shows the recommendedtorquing order for mountingscrews. Uneven mounting cancause the modules ceramicisolation to crack.

Thermal Considerations:

I. Do not put the module on a hotplate. Externally heating themodule's base plate at a rategreater than 15°C/min. willcause thermal stress that maydamage the module.

II. When soldering to the signalpins and fast on terminalsavoid excessive heat. Thesoldering time and temperatureshould not exceed 230°C for5 seconds.

III. Maximize base plate toheatsink contact area for goodheat transfer. Use a thermalinterface compound such aswhite silicon grease. Theheatsink should have a surfacefinish of 64 microinches or less.

Figure 6.48 Mounting Screws Torque Order

2

1

4

1

2

3

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