Power Systems 2005 Paper

FAST ACTING OVER CURRENT POWER CIRCUIT PROTECTION SCHEME

by

Todd Kazmirski President

IsoSense Inc.

Abstract A power circuit protection scheme is presented which utilizes a fast acting, digital output, Hall effect based over current detector. The scheme combines a pulse by pulse current limit with a pulse count shutdown. The pulse by pulse current limit provides a fast acting shutdown. The pulse count shutdown acts to distinguish a normal over current event from a hard failure, and latch off the circuit in the case of a hard failure. The effectiveness of the scheme is demonstrated by application to a low inductance power MOSFET circuit. In this demonstration circuit, a MOSFET is connected directly across a DC power source. A very fast rising, high current (comparable to a shoot through current on a bridge circuit) is generated when the MOSFET is turned on. Waveforms are presented showing the current, detector output, gate drive, and MOSFET switching waveforms. Introduction This paper presents a robust method for active over current protection in power electronic circuits. The method eliminates failures in power electronic circuits by protecting power transistors and other power semiconductors against over current events. It actively distinguishes between temporary events often caused by transient load conditions such as motor starting, and hard events caused by internal circuit failures or output load shorts. In both cases, the method prevents circuit failure by providing a fast acting pulse by pulse shutdown of power transistors. For temporary events, the circuit simply rides through the event on a pulse by pulse basis and returns to normal operation when the condition has cleared. When the event is hard, the circuit acts to latch off the power circuit to prevent any failure caused by continued power circuit operation. While this method can be incorporated using a variety of over current detection techniques, the key to its effectiveness is using a fast acting, noise immune, digital output Hall effect over current detector. This detector is a simple low cost implementation of the widely used Hall effect current sensing technique. The detector reacts in 1 µs, is highly immune to the noise prevalent in power switching circuits, and provides isolation allowing current to be detected at different voltage levels. The method is demonstrated with a circuit using a MOSFET operating into a direct short. The circuit is designed to demonstrate the operation of the protection scheme while operating under this worst case operating condition. The operation of this circuit is explained and operating waveforms are presented.

FAST ACTING OVER CURRENT POWER CIRCUIT PROTECTION SCHEME by Todd Kazmirski

Over Current Detector Description When engineers consider incorporating over current protection into their circuits, one of the first considerations is the technique to detect the over current condition. Among the popular techniques are current sense transformers, Hall effect current sensors, current sensing resistors, and de-sat sensing on power transistors. For each method, the engineer is faced with tradeoffs between cost, size, simplicity, isolation, noise immunity, power dissipation and robustness. The scheme presented in this paper uses a digital output Hall effect over current detector (OCD) to detect the over current condition. This detector, designed and manufactured by IsoSense, is a fully integrated detector with its output factory programmed to go low at a specific input current level. It is designed to be mounted directly to a printed circuit board and like other Hall effect current sensors provides isolation between the sensed current and the output. The OCD’s unique digital output is factory programmed to go low at a specific current level, and provides a fast response time (1 µs) and a high level of noise immunity. These features are critical to obtaining the robust protection provided by the implementation described here. Fast response time is critical for two reasons. First, the quicker an over current event is detected, the sooner a transistor shutdown can be initiated. This is important due to the various propagation delays present in shutdown caused by control logic and transistor drive circuits, and the transistor short circuit current ratings which are often 10 µs. By utilizing a fast response detector, sufficient margin can be maintained between the worst case shutdown time and the short circuit capability of the transistor. Second, an important yet often over looked consideration is the parasitic inductance in the high current circuit paths. These inductances store significant energy, particularly under high current conditions. The energy stored is proportional to the square of the current and this energy must be dealt with at the time of shutdown. In some cases, the circuit topology provides a commutating path that safely manages this energy. In other cases, the energy is dissipated in snubbers or through transistor avalanche at shutdown. In all cases, the energy present at the time of detection is dramatically higher with a detector having a 3 µs response time instead of a 1 µs response time. This energy can cause failure particularly when operating in a repetitive pulse by pulse current limiting mode. Using a fast response OCD minimizes this energy. The arguments presented for the importance of response time also apply to noise immunity. Filtering must be added to techniques that provide less immunity. This filtering slows the response time reducing shutdown margin time and increasing the parasitic energy that must be dealt with at shutdown. This same problem is typically encountered when utilizing a detection scheme that converts an analog sense signal to a digital over current signal. This method would be required with a linear Hall effect current sensor, current sense transformer, or current sense resistor. The digital output Hall effect technique provides excellent noise immunity and eliminates the need for any significant filtering which would slow the response of the detector circuit.


A photograph of an OCD is shown in figure 1. The device provides a simple interface to the circuit having both an input side and an output side. The current to be sensed is passed through the input side of the detector. The output side has three connections. Two of the connections are used to provide logic power to the detector, typically 5 to 12 VDC. This supply must be properly decoupled in order to insure noise immunity and fast response time. The third output connection is a simple open collector pin. A 4.7 kO resistor is used to pull the pin high. The detector forces the pin low when a current exceeding the trip level of the detector is passed through the input.

Figure 1 – TD Series OCD

Protection Scheme A functional block diagram for the protection scheme is shown in figure 2. The implementation uses two levels of shutdown. The first level is a fast response pulse by pulse shutdown. This level is designed to provide a quick response without distinguishing between temporary and hard events. The second level of protection is provided by a pulse counter circuit. This level is designed to distinguish between transient and hard events, and latch off the power circuit in the case of the hard event.


Figure 2 – Protection Scheme Functional Block Diagram

In the demonstration circuit, the first level shutdown is implemented using a D flip-flop and a shutdown input to the gate drive circuit for the power MOSFET. This minimizes the propagation delay, providing a fast response shutdown. A microcontroller is used to implement the second level shutdown in the demonstration circuit. This microcontroller is used to implement the demonstration circuit general control logic. An available pulse count input is used for the second level shutdown. Over current pulses are accumulated over a window of time. If a set count limit is exceeded before the window of time ends, the controller latches off the power MOSFET via the gate drive circuit. If the set count limit is not exceeded at the end of the time window, the count is reset to zero. The set count limit is designed to be set by the engineer. The limit should be set to distinguish between temporary and hard events. For instance, a motor starting may generate 100 over current pulses in a motor drive circuit. Setting the pulse count limit above the count achieved with all temporary events would distinguish temporary events from hard events. Demonstration Circuit Description A schematic-block diagram for the demonstration circuit is shown in figure 3 and a photograph of the set up is shown in figure 4. The circuit can be split into two sections. The first section is the power or high current portion of the circuit. The second section is the control or logic section of the circuit. The power section consists of a 20 volt DC power supply connected in series with an N-channel MOSFET, a shunt, and a 50 Amp OCD. This circuit creates a short across the power supply when the MOSFET is turned on, creating a fast rising fault current. For this demonstration, a IRFZ44E is used for the MOSFET. This is a 60 volt, 48 amp, 23 m? device. It is considered to be representative of 40-60 amp, 60 volt MOSFET’s which have been available for several years. The connections between the power supply and the rest of the circuit consist of 20 gage leads 8 inches long. In order to maximize the rise time of the short circuit current, a 3300? F

Control Circuit

OCD

Power

Circuit

L1 – Fast

Shutdown

L2 – Pulse Count

Shutdown


capacitor is included directly on the printed circuit board. The total length of the power traces and leads in the demonstration circuit connecting the MOSFET to the capacitor, and OCD is 5 inches.

IsoSense9001-050

+-

O

20 VDC3300 uF

IRFZ44E

Shunt

DFlip-Flop

426 FET Driver

M icro Controller

Figure 3 - Demonstration Circuit Schematic - Block Diagram As described in the protection scheme, the logic section of the circuit consists of a microcontroller driving the clock input of a D flip flop with the output of the flip flop driving a MOSFET gate driver. The output of the OCD is fed back to clear the flip flop which turns the MOSFET gate drive off when an over current event is detected.

Figure 4 – Demonstration Setup


Demonstration Circuit Waveforms The MOSFET and OCD operating waveforms are shown in figures 5 through 7 with the circuit operating at 30 kHz. In these plots, waveforms are numbered R1 – R4 from the bottom to the top. Trace R1 is the gate to source voltage at 10 V/div. Trace R2 is the drain current measured by measuring the voltage across the 10 m? shunt at 1 volt/div (=100 amps/div). Trace R3 is the OCD output at 5 volts/div. Trace R4 is the drain to source voltage at 20 V/div. Figure 5 is a low resolution view of the waveforms intended to show three successive turn on – shutdown sequences at 30 kHz. Figure 6 provides a high resolution (1 µs/div) of one turn on – shutdown sequence. The figures demonstrate the fast response of the OCD output and the turn off of the MOSFET within 1 µs of the fault current event. The shunt used for current measurement contributes a measurement error to trace R2. Although a low inductance shunt is used, it does have 10 nH of inductance which adds a voltage drop not representative of the current value. In this case, this inductance provides a 1 volt drop at a current rise rate of 100 A/µs. This can be seen at the turn on of the MOSFET where the voltage across the shunt instantaneously jumps to 1 volt, and during the turn off phase when the voltage instantaneously goes negative. Figure 7 provides a complete view of a pulse count shutdown sequence at 1 ms/div. Although the waveforms are distorted by aliasing, they provide a view of the pulse count shutdown level of protection. In this case, the pulse count limit is set for 250, and the count window 1 second. The circuit latches off after 8.33 ms.

Figure 5 - Demonstration Waveforms at 30 kHz, 10 ? s per Division


Figure 6 - Demonstration Waveforms at 30 kHz, 1 ? s per Division

Figure 7 - Demonstration Waveforms at 30 kHz, 1 ms per Division

Conclusion Design engineers face tradeoffs between cost, size, simplicity, isolation, noise immunity, power dissipation and robustness when incorporating over current protection in their circuits. This paper presents a simple, robust, and low cost method of incorporating over


current protection in power electronic circuits to eliminate circuit failures. The method uses a digital output Hall effect OCD to detect the over current condition and two levels of shutdown to protect against temporary and hard over current events. The implementation of the protection scheme is explained by application to a demonstration circuit. In this circuit, a power MOSFET is turned on repetitively into a direct short. This action creates a short circuit current and results in a repetitive sequence of turn on – detection – shutdown. This circuit is operated at frequencies up to 30 kHz demonstrating its effectiveness. Waveforms for the circuit are also presented to aid in the explanation of the operation of the protection scheme.

Power Systems 2005 Paper

Documents

Transcript of Power Systems 2005 Paper