Power Semiconductor Device Reliability - Power · PDF fileUnderpinning Research Power...

Underpinning Research

Power Semiconductor Device Reliability

Dr O AlatiseAssociate Professor of Power Electronic Devices

University of Warwick

26th November 2015


Contents

1. Introduction to Power Devices

2. Power Reliability tests (JEDEC and AEC101)

HTRB, HTGB, TMCL, THBS, Hot- Storage, Unbiased Stress tests,

Negative Gate bias Stress tests, Thermal Fatigue, Power Cycling etc.

3. Unclamped Inductive Switching Tests

4. Repetitive Avalanche Stress Tests

5. Linear Mode Stress Tests

6. Short Circuit Stress Tests

7. Body Diode Commutation Stress Tests

8. Electrothermal Imbalance in Parallel Devices


Power Semiconductor Devices

Transistors• MOSFETs• BJTs• IGBTs• Thyristors

Diodes• PiN diodes• Schottky diodes

Unipolar Devices• MOSFETs• Schottky diodes

Bipolar Devices• BJTs• IGBTs• Thyristors• PiN diodes


Power Semiconductors

Electric Vehicles > 10 kW

HVDC, FACTS >1MW

Consumer Electronics < 500 W

Power Semiconductors

Si, SiC, GaN

Inverter Modules for Drives

Grid Connected Converters

Switched Mode Power Supplies


N+ Substrate

N- Epi-layer

Power MOSFET Process Flow

P-body

N+ Source

TEOS

Poly

Source Metal

Trench Etch

Polysilicon deposition

P-body doping implant

n+ Source implant

TEOS Etch for source metal

Source metal sputtering

Nitride

Passivation

Gate Oxidation

Polysilicon etch

TEOS Isolation deposition


P+ Substrate

N- Epi-layer

Non-punch-Through Trench IGBT

P-body

N+ Source

TEOS

Poly

Source Metal

Nitride• The primary

difference between a MOSFET and an IGBT is the starting substrate

• IGBTs have a p+ substrate while MOSFETs have an n+ substrate

• P+ substrate is for minority carrier injection to enable conductivity modulation

• Good for conduction losses but bad for switching losses


P+ Substrate

N- Epi-layer

Punch-Through Trench IGBT

P-body

N+ Source

TEOS

Poly

Source Metal

Nitride• The difference

between PT and NPT IGBTs is an additional n+ buffer layer

• This improves minority carrier injection efficiency and lowers the conduction losses

• However, PT-IGBTs usually exhibit an on-state resistance with a negative temperature coefficient

• Not good for paralleling devices.

N+ buffer layer


MOSFET Edge termination

Process Flow

Silicon Substrate

Deep P implant

Field OxidePoly

TEOS

C

Source MetalGateMetal

Nitride Passivation


Cross-Sectional SEM of Trench

MOSFET

• There are different losses associated with driving power MOSFETs• These include device losses and gate drive losses• These losses are associated with the on-state resistance of the device

and the parasitic capacitances.


Contents



HTRB, HTGB, TMCL, Thermal Shock, THBS, Hot-Storage,

Unbiased Stress tests, Negative Gate bias Stress tests, Thermal

Fatigue, Power Cycling etc.








JEDEC and AEC101

● JEDEC means the Joint Electron Device Engineering

Council and AEC means the Automotive Electronics

Council

● Both regulate the standards for device tests and

reliability

● All commercially available devices must pass these tests

● The tests include

HTGB (High Temperature Gate Bias)

HTRB (High Temperature Reverse Bias)

THBS (Temperature Humidity Bias Stress Test)

HS (Hot Storage)

TMCL Temperature Cycling

Thermal Fatigue (Otherwise known as Power Cycling)

UHST (Unbiased Humidity Stress Test)


High Temperature Gate Bias

● MOSFETs and IGBTs have MOS gates

● The MOS gate stands for Metal-Oxide-Semiconductor

● The Oxide should be a perfect Insulator

● However, defects in the oxide can cause conduction through the oxide

● All MOSFETs must pass 1000 hours of the rated gate voltage at 150 °C

● Electrical Parameters (Threshold Voltage) must not shift by more than

25% otherwise it is classified as a fail

Lateral DMOS



• The energy band diagram of the MOS interface shows the band-offsets between

the semiconductor and the insulator

• Carrier’s can tunnel through the oxide, if the electric field is high enough

• Carriers can surmount the band-offset (Field emission)

EG : Energy Bandgap

qχ : Electron Affinity of the Semiconductor

EC : Conduction Band

EV : Valence Band

EF: Fermi Level



Fowler Nordhiem Tunnelling Direct Tunnelling

• Tunnelling can occur by field emission over the oxide barrier (FN Tunelling)

• Tunnelling can occur directly through the oxide at high electric fields

• Tunnelling can also occur via interface traps in the oxide


OX

BAsi

B

OX

FMSTH

C

Nq

C

QV

222


• Under high temperature gate bias, traps can form in the oxide

• The traps form through a diffusion process, hence, is temperature sensitive

• These oxide traps increase the fixed oxide trap in the gate insulator

• This can change the threshold voltage of the MOSFET depending on the polarity

of the trapped charge

A reduced threshold voltage is a

circuit hazard because of short

circuits especially at elevated

temperatures



Band offsets of different semiconductors

• Because of the wide bandgap (3.4 eV), SiC has a smaller barrier height with SiO2

and is therefore more susceptible to FN tunnelling

• Si has a smaller bandgap and therefore has larger barrier heights with SiO2.

• For most power electronics engineers, SiC still has to prove itself on HTGB

SiC/SiO2 band diagram,


High Temperature Reverse Bias

● Mobile ions can lodge in the gate oxide and shift the threshold voltage

● However, defects in the oxide can cause conduction through the oxide

● All MOSFETs must pass 1000 hours at 80% of the rated blocking

voltage at 150 °C

● Electrical Parameters (Threshold Voltage) must not shift by more than

25% otherwise it is classified as a fail



● HTGB is an important test

for detecting ionic

contaminants.

● These contaminants will

diffuse into the active area

under the influence of

temperature and high

electric fields

● This occurs in metallisation

processes with defects

● Ionic contaminants can

diffuse into the active area

and cause localised

threshold voltage shifting



Gate Voltage (V)

Dra

in C

urr

en

t (A

)

● Devices that fail under HTRB exhibit significant

subthreshold conduction

● Eventually, the devices dissipate significant off-

state power dissipation

Dra

in C

urr

en

t (A

)

Gate Voltage (V)

Subthreshold

conduction


Power Device Packaging

Through-hole SMD LeadlessThrough-hole SMD Leadless Wafer-scale

D H

eyes 0

6-D

ec-7

3

DIRECT & ENABLE

MarketingSTRATEGY &

InnovationInnovationBL Power

Copper Leadframe

PlasticAluminium wire

Chip

Solder

Current Packages -

Standard TO-220/TO-247Surface Mount Devices

(SOT404)

● The reliability of the power device under temperature cycling depends more on the

packaging than the device

● Different packages perform in different ways


Power Device Packaging

D H

eyes 0

6-D

ec-7

5

DIRECT & ENABLE

MarketingSTRATEGY &

InnovationInnovationBL Power

NiFe Leadframe

Plastic

Gold wireChip

Eutectic bondSOT23

PlasticGold wire

Chip

Epoxy die-attachSO8

Current Packages -

Fully Encapsulated Packages

Power SO8 Package

● SO-8 package has

its advantages

regarding module

integration, but its

poor transient

thermal impedance

degrades it

temperature cycling

performance.

● Alternative

packaging

techniques can

improve the

performance under

power cycling


Power Packaging Tests

DBC Substrate structure for high power applications

Thermal resistance as a function of the number of cycles during power cycling

● For some high power applications, custom made DBC substrates are required

● Packaging tests are part of the JEDEC and AEC requirements

● These tests include Temperature cycling, Thermal Shock, Unbiased humidity

stress tests, Thermal Fatigue and Temperature Humidity Bias Stress Tests.


Power Packaging Tests

Wire-bond lift-off resulting from power cycling

Solder voiding

● The primary indicator of failed

packaging is the thermal

resistance, on-state resistance and

the gate resistance.

● The thermo-mechanical stress tests

(TMCL, TFAT and TS) probe the

integrity of the wire-bonds and die-

attach.

● The humidity tests (UHST, THBS)

probe the integrity of the hermetic

sealing of the package.

● Power modules are subject to

additional tests depending on the

application requirements.


Contents












Unclamped Inductive Switching

● In most applications, there is a

free-wheeling diode to protect the

MOSFET from off-state conduction

● In some applications, MOSFETs

can be forced to conduct in the off-

state, through avalanche mode.

● An example is a Fly-back

converter.

● The Failure mode of a power

MOSFET under UIS is parasitic

BJT latch-up

● IGBTs typically are not avalanche

rugged. There is a parasitic

thyristor.The parasitic BJT in the MOSFET can

latch with destructive results

Flyback Converter



● When the parasitic BJT latches, thermal runaway

destroys the MOSFET.

● The maximum avalanche energy a MOSFET can

sustain depends on the temperature and

avalanche duration i.e. size of the inductance

MOSFET destroyed under UIS

SiC MOSFET fails UIS at high Temps

Avalanche current characteristics Determining the maximum Current before failure



● The avalanche stress test

circuit comprises of the power

supply, inductor and DUT

● The DUT is used to charge

the inductor

● The inductor dissipates

energy into the DUT after it is

switched off

● The peak avalanche current

depends on the inductor

charging duration

UIS test circuit

UIS test waveforms



X

YZ

Forward mode conduction

Avalanche Conduction through the p-body

BJT Latch-up

Simulated Avalanche current characteristics


Devices fail under

UIS


● The maximum avalanche current as a function of avalanche duration and

temperature is specified on datasheets

● The maximum current reduces with both temperature and avalanche duration

● Low current-long duration avalanche failure modes are thought to be

temperature activated

● High current-short duration avalanche failure modes are though to be parasitic

BJT activated.

Maximum Avalanche Energy as a Function of Temperature

Transient Avalanche Characteristics of the SiC MOSFETs



MOSFET

IGBT

• IGBTs are significantly less

rugged than MOSFETs

• This is because there is no

internal body diode in IGBTs

• IGBTs have a parasitic

thyristor while MOSFETs

have a parasitic BJT

• Hence, IGBTs are not

considered avalanche

capable

• The avalanche ruggedness

capability of IGBTs

significantly reduce with

temperature IGBT with Parasitic Thyristor


Repetitive Avalanche Stress Tests

• In spite of having small active area, SiC MOSFETs are the most electrothermally

rugged of all the tested high voltage devices.


Contents













● MOSFETs can be destroyed by UIS

through parasitic BJT latch-up

intrinsic carrier temperature limits

● Single shot UIS is protected against

by quoting safe-operating-area

(SOA) on datasheets.

● However, other failure modes exist

with repetitive avalanche cycling of

power pulses within the SOA.

● Some applications require

MOSFETs to conduct in avalanche

millions of times over the system

lifetime.

● Hot-carrier injection has been

identified as an observation in

repetitively avalanched MOSFETs.

Repetitive UIS waveforms. (a) Gate pulse VGS, (b) Drain-source voltage (VDS) and repetitive avalanche current (IAR) (C) Repetitive Avalanche Power (d) Transient Junction Temperature


Hot Carrier Injection

● HCI occurs as a result of impact ionisation during avalanche conduction

● Hot holes are injected into the oxide

MAX

BDSG

EqII

exp

MAX

iDSB

EqII

exp

where IG is the gate current, IB is the substrate current, IDS is the drain-source current, Фi is the minimum energy for impact ionization, ФB is the Si/SiO2

energy barrier, q is the electric charge, λ is the hot-electron mean free path and EMAX is the maximum electric field in the channel.


Threshold Voltage Shifting

n

GSTX NAV

● Threshold voltage is shown to reduce

with increased avalanche cycling.

● This indicates an injection of positive

charge (holes).

● The change in threshold voltage

(ΔVGSTX) relates with the number of

cycles through a power law relation.

where A is the power law pre-factor, N is the number of avalanche cycles and n is the power law exponent.

Threshold voltage as a function of the number of avalanche cycles in the linear

and power law form.


Source Metal Reconstruction

● The Aluminium source metal is severely degraded

during the repetitive avalanche process

● High temperatures cycles cause the continuous

expansion and contraction of the Aluminium

source metal

● This results in increased on-state resistance and

weaker wirebond contacts

The on-state resistance of the MOSFET as a function of the number of cycles in avalanche.



● The degraded Aluminium source

metal causes the wire-bonds to

weaken

● There is CTE mismatch between the

wire-bonds and the silicon die

● Cross-sectional images show

significant wire-bond cracking as the

number of avalanche cycles

increases.

Cross-sectional images showing wire-bond liftoff.


Transconductance degradation with increasing avalanche cycles

● SiC MOSFETs are more avalanche

rugged and can go through more cycles

without failure

● SiC MOSFETs exhibit less drift in

electrical parameters with number of

avalanche cycles

SiC MOSFETsSi MOSFETs



Contents












Linear Mode Stress Test

• MOSFETs usually operate in the switch mode i.e. the MOSFET moves between point A and C on the load-line

• Operation at point C, is unusual, although occurs in some applications. This is called linear mode operation

• High current MOSFETs with large Miller capacitances and high internal gate resistances can spend a few microseconds in the linear region where power dissipation is high because of simultaneously high IDS and VDS.

• This can be a reliability hazard since thermal runaway can result

• MOSFETs usually undergo linear mode stress tests to ensure thermal runaway does not occur during the switching transient

MOSFET load-line and output characteristics

MOSFET destroyed under linear mode operation


Linear Mode Stress Tests

Drain Voltage, VDS (V)

Drain

Cu

rren

t, I

DS

(A

)

• An example of an application where the MOSFET is used in the linear mode is the linear regulator

• Here, the MOSFET is used as a current source to control a load, like a fan.

• The MOSFET can also be used as a fuse to limit inrush currents.

MOSFETs used as current controllers operate in the linear mode.


Linear Mode Stress Tests

• The ZTC point of a semiconductor is the point in the transfer characteristics that is temperature invariant

• Operation above this point is recommended because of the positive temperature coefficient of the on-state resistance

• Operation below this point is not recommended because of the negative temperature coefficient of the on-state resistance.

MOSFET Output CharacteristicsMOSFET Transfer Characteristics



• Thermal runaway in a MOSFET or diode occurs when the generated power exceeds the dissipated power

• The generated power is given by

• The dissipated power is given by

• The condition of thermal runaway is given by

Example of Linear Mode SOA on a datasheet

Examples of MOSFETs destroyed by thermal runaway



SiC Schottky

diode

Silicon PiN

diodes

• SiC Schottky diodes exhibit a lower ZTC than PiN diodes

• This causes higher conduction losses compared to PiN diodes

• However, this means SiC Schottky diodes are more electro-thermally stable and can be paralleled more easily than PiN diodes

Case temperature transient for the diodes


Contents












Short Circuit Stress Tests

• Unintentional short circuits occur in power electronic converters

• This subjects the transistor to simultaneously high forward voltages and high output currents

• This means high instantaneous output power that can easily destroy the device if the short circuit occurs long enough to raise the junction temperature beyond its rated temperature

• Short circuits can occur if

• Cross-talk between complimenting devices in a phase leg causes both Q1 and Q2 to turn on simultaneously

• The diode reverse recovery current in Q2 is in phase with a complimenting transistor Q1 current


Crosstalk induced Short Circuits

Si IGBT Si IGBT

SiC SiC

• Parasitic turn-on gate voltages and short circuit currents are shown for Si IGBT and SiC MOSFET power modules.

• The larger Miller capacitance in Si IGBTs makes the short circuit current larger compared with the SiC MOSFET module.

• Short circuit currents increase with Miller capacitance, parasitic gate resistance and turn-on dVDS/dt.


Si IGBT SiC

Crosstalk induced Short Circuits

• Significant temperature excursions can occur due short circuits

• The thermal images and temperature graphs show significant temperature rise in the Si IGBT and SiC MOSFET power modules

• SiC devices are smaller and hence, usually have higher thermal impedances, thus making them prone to higher junction temperatures

Thermal images show temperature rise in the SiC MOSFET and Si IGBT power modules

Temperature rise graphs in Si-IGBT and SiC MOSFET modules


Contents












Body Diode Commutation Failure

• Body-diodes are an integral part of power MOSFETs

• They may be used for intentional reverse current conduction or sometimes can conduct reverse currents un-intentionally

• The body diode is usually a PiN diode and therefore has significant reverse recovery currents

MOSFET schematics showing the body diodes and parasitic BJTs



• When the body diode conducts in forward mode, there is considerable charge storage in the MOSFET drift region

• As the diode is turned off, the turn-off dV/dt combined with the drain-to-body capacitance causes a current to flow

• If the capacitor discharge current and the reverse recovery current is large enough to forward bias the parasitic BJT, then the device can latch with destructive consequences.

MOSFET schematics showing the body diodes and parasitic BJTs

MOSFET body diode forward and reverse recovery characteristics



• The test circuit used for assessing the commutation reliability of the MOSFET body diode is shown here

• It comprises of a high side MOSFET with its body diode used as a free-wheeling diode in a clamped inductive switching set-up.

• As the body diode is commutated, the reverse recovery characteristics are assessed.



• The rate at which the body diode of the MOSFET is switched will determine the peak reverse recovery current

• The peak reverse current of the CoolMOS device is the highest, followed by the silicon MOSFET and the SiC MOSFET

Silicon MOSFET body diode reverse recovery characteristics for different dIDS/dt

SiC MOSFET body diode reverse recovery characteristics for different dIDS/dt

CoolMOS body diode reverse recovery characteristics for different dIDS/dt



• The total reverse recovery charge increases with temperature due to minority carrier lifetime

• This happens for the silicon MOSFET and CoolMOS device but not the SiC MOSFET

• SiC MOSFET body diodes have the least switching energy

SiC MOSFET body diode reverse characteristics at different temperatures

Si MOSFET body diode reverse characteristics at different temperatures

CoolMOS body diode reverse characteristics at different temperatures



• The maximum forward current sustainable before latch-up during body diode commutation can be determined experimentally.

• The maximum current decreases with increasing temperature and dIDS/dt.

SiC MOSFET body diode failure

CoolMOS body diode failureSi MOSFET body diode failure



• The reverse recovery characteristics of the MOSFET body diodes have a significant impact on the device voltage overshoot.

• Voltage overshoots as high as 2.5 kV can occur with a DC link voltage of just 800 V

Drain-source voltage overshoots resulting from body diode commutation

Body diode reverse recovery characteristics for different technologies


Contents












Electrothermal Imbalance

Si-IGBT half bridge module showing single die

SiC MOSFET half bridge module showing several parallel dies

• Power modules are usually comprised of several dies connected in parallel.

• Ensuring electro-thermal balance between the parallel dies at high power densities is becoming increasingly critical

• Differences in junction temperature and switching rates can cause severe electro-thermal imbalances thereby reducing reliability.

Turn-off transient of parallel connected SiC MOSFETs with

different switching rates

Turn-off transient of parallel connected CoolMOS with different switching rates


Switching Rate Mismatch

• Parallel connected SiC MOSFETs and CoolMOS devices have been tested under clamped repetitive switching conditions.

• Electrothermal imbalance is induced by switching the parallel devices with different gate resistances.

• The slower switching device has a higher turn-off energy and hence, a higher case temperature.

• The difference between the devices is lower in the SiC MOSFETs compared to CoolMOS


Junction Temperature Mismatch

• Electrothermal imbalance is also induced by switching the parallel devices at different ambient temperatures.

• The device with the lower junction temperature has a higher turn-on energy.

• The difference between the devices is lower in the SiC MOSFETs compared to CoolMOS


Temperature Imbalance under UIS

Avalanche current characteristics for parallel connected MOSFETs with different temperatures

2D Current density contour plots for the parallel connected devices at different junction temperatures

W

ZX




RG Imbalance under UIS

Avalanche current characteristics for parallel connected MOSFETs with different switching rates

2D Current density contour plots for the parallel connected devices at different switching rates

X

ZY




Paralleling Diodes

Parallel diodes under UIS

Parallel diodes under CIS

• Parallel diodes are tested under unclamped inductive switching and clamped inductive switching

• Electro-thermal imbalance is introduced by heating the diodes to different junction temperatures

• This test is performed for Schottky and PiN diodes.

• For clamped inductive switching, repetitive and double pulse measurements are performed


Paralleling Diodes

Parallel Silicon PiN diodes at turn ON and turn OFF

Parallel SiC Schottky diodes at turn ON and turn OFF

Silicon PiN diodes

SiC Schottky

• Parallel diodes are tested for both silicon PiN and SiC Schottky diodes

• The hotter PiN diode takes more current i.e. prone to thermal runaway

• The hotter SiC Schottky diodes takes less current i.e. good for paralleling


Acknowledgements

● Jose Angel Ortiz Gonzalez (RA/PhD/Technician)

● Ji Hu (PhD)

● Saeed Jahdi (PhD)

● Petros Alexakis (PhD)

● Zarina Davletzhanova (PhD)

● Prof Li Ran (PI)


Thank You

Any Questions

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