Power Semiconductor Applications Philips Semiconductors

Preface Power Semiconductor ApplicationsPhilips Semiconductors

Preface

This book was prepared by the Power Semiconductor Applications Laboratory of the Philips Semiconductors productdivision, Hazel Grove. The book is intended as a guide to using power semiconductors both efficiently and reliably in powerconversion applications. It is made up of eight main chapters each of which contains a number of application notes aimedat making it easier to select and use power semiconductors.

CHAPTER 1 forms an introduction to power semiconductors concentrating particularly on the two major power transistortechnologies, Power MOSFETs and High Voltage Bipolar Transistors.

CHAPTER 2 is devoted to Switched Mode Power Supplies. It begins with a basic description of the most commonly usedtopologies and discusses the major issues surrounding the use of power semiconductors including rectifiers. Specificdesign examples are given as well as a look at designing the magnetic components. The end of this chapter describesresonant power supply technology.

CHAPTER 3 describes motion control in terms of ac, dc and stepper motor operation and control. This chapter looks onlyat transistor controls, phase control using thyristors and triacs is discussed separately in chapter 6.

CHAPTER 4 looks at television and monitor applications. A description of the operation of horizontal deflection circuits isgiven followed by transistor selection guides for both deflection and power supply applications. Deflection and power supplycircuitexamples arealso given basedon circuitsdesigned by the Product Concept andApplication Laboratories (Eindhoven).

CHAPTER 5 concentrates on automotive electronics looking in detail at the requirements for the electronic switches takinginto consideration the harsh environment in which they must operate.

CHAPTER 6 reviews thyristor and triac applications from the basics of device technology and operation to the simple designrules which should be followed to achieve maximum reliability. Specific examples are given in this chapter for a numberof the common applications.

CHAPTER 7 looks at the thermal considerations for power semiconductors in terms of power dissipation and junctiontemperature limits. Part of this chapter is devoted to worked examples showing how junction temperatures can be calculatedto ensure the limits are not exceeded. Heatsink requirements and designs are also discussed in the second half of thischapter.

CHAPTER 8 is an introduction to the use of high voltage bipolar transistors in electronic lighting ballasts. Many of thepossible topologies are described.

Preface Power Semiconductor ApplicationsPhilips Semiconductors

Acknowledgments

We are grateful for all the contributions from our colleagues within Philips and to the Application Laboratories in Eindhovenand Hamburg.

We would also like to thank Dr.P.H.Mellor of the University of Sheffield for contributing the application note of section 3.1.5.

The authors thank Mrs.R.Hayes for her considerable help in the preparation of this book.

The authors also thank Mr.D.F.Haslam for his assistance in the formatting and printing of the manuscripts.

Contributing Authors

N.Bennett

M.Bennion

D.Brown

C.Buethker

L.Burley

G.M.Fry

R.P.Gant

J.Gilliam

D.Grant

N.J.Ham

C.J.Hammerton

D.J.Harper

W.Hettersheid

J.v.d.Hooff

J.Houldsworth

M.J.Humphreys

P.H.Mellor

R.Miller

H.Misdom

P.Moody

S.A.Mulder

E.B.G. Nijhof

J.Oosterling

N.Pichowicz

W.B.Rosink

D.C. de Ruiter

D.Sharples

H.Simons

T.Stork

D.Tebb

H.Verhees

F.A.Woodworth

T.van de Wouw

This book was originally prepared by the Power Semiconductor Applications Laboratory, of the Philips Semiconductorsproduct division, Hazel Grove:

M.J.Humphreys

C.J.Hammerton

D.Brown

R.Miller

L.Burley

It was revised and updated, in 1994, by:

N.J.Ham C.J.Hammerton D.Sharples

Contents Power Semiconductor ApplicationsPhilips Semiconductors

Table of Contents

CHAPTER 1 Introduction to Power Semiconductors 1

General 3

1.1.1 An Introduction To Power Devices ............................................................ 5

Power MOSFET 17

1.2.1 PowerMOS Introduction ............................................................................. 19

1.2.2 Understanding Power MOSFET Switching Behaviour ............................... 29

1.2.3 Power MOSFET Drive Circuits .................................................................. 39

1.2.4 Parallel Operation of Power MOSFETs ..................................................... 49

1.2.5 Series Operation of Power MOSFETs ....................................................... 53

1.2.6 Logic Level FETS ...................................................................................... 57

1.2.7 Avalanche Ruggedness ............................................................................. 61

1.2.8 Electrostatic Discharge (ESD) Considerations .......................................... 67

1.2.9 Understanding the Data Sheet: PowerMOS .............................................. 69

High Voltage Bipolar Transistor 77

1.3.1 Introduction To High Voltage Bipolar Transistors ...................................... 79

1.3.2 Effects of Base Drive on Switching Times ................................................. 83

1.3.3 Using High Voltage Bipolar Transistors ..................................................... 91

1.3.4 Understanding The Data Sheet: High Voltage Transistors ....................... 97

CHAPTER 2 Switched Mode Power Supplies 103

Using Power Semiconductors in Switched Mode Topologies 105

2.1.1 An Introduction to Switched Mode Power Supply Topologies ................... 107

2.1.2 The Power Supply Designer’s Guide to High Voltage Transistors ............ 129

2.1.3 Base Circuit Design for High Voltage Bipolar Transistors in PowerConverters ........................................................................................................... 141

2.1.4 Isolated Power Semiconductors for High Frequency Power SupplyApplications ......................................................................................................... 153

Output Rectification 159

2.2.1 Fast Recovery Epitaxial Diodes for use in High Frequency Rectification 161

2.2.2 Schottky Diodes from Philips Semiconductors .......................................... 173

2.2.3 An Introduction to Synchronous Rectifier Circuits using PowerMOSTransistors ........................................................................................................... 179

i


Design Examples 185

2.3.1 Mains Input 100 W Forward Converter SMPS: MOSFET and BipolarTransistor Solutions featuring ETD Cores ........................................................... 187

2.3.2 Flexible, Low Cost, Self-Oscillating Power Supply using an ETD34Two-Part Coil Former and 3C85 Ferrite .............................................................. 199

Magnetics Design 205

2.4.1 Improved Ferrite Materials and Core Outlines for High Frequency PowerSupplies ............................................................................................................... 207

Resonant Power Supplies 217

2.5.1. An Introduction To Resonant Power Supplies .......................................... 219

2.5.2. Resonant Power Supply Converters - The Solution For Mains PollutionProblems .............................................................................................................. 225

CHAPTER 3 Motor Control 241

AC Motor Control 243

3.1.1 Noiseless A.C. Motor Control: Introduction to a 20 kHz System ............... 245

3.1.2 The Effect of a MOSFET’s Peak to Average Current Rating on InvertorEfficiency ............................................................................................................. 251

3.1.3 MOSFETs and FREDFETs for Motor Drive Equipment ............................. 253

3.1.4 A Designers Guide to PowerMOS Devices for Motor Control ................... 259

3.1.5 A 300V, 40A High Frequency Inverter Pole Using Paralleled FREDFETModules ............................................................................................................... 273

DC Motor Control 283

3.2.1 Chopper circuits for DC motor control ....................................................... 285

3.2.2 A switched-mode controller for DC motors ................................................ 293

3.2.3 Brushless DC Motor Systems .................................................................... 301

Stepper Motor Control 307

3.3.1 Stepper Motor Control ............................................................................... 309

CHAPTER 4 Televisions and Monitors 317

Power Devices in TV & Monitor Applications (including selectionguides) 319

4.1.1 An Introduction to Horizontal Deflection .................................................... 321

4.1.2 The BU25XXA/D Range of Deflection Transistors .................................... 331ii


4.1.3 Philips HVT’s for TV & Monitor Applications .............................................. 339

4.1.4 TV and Monitor Damper Diodes ................................................................ 345

TV Deflection Circuit Examples 349

4.2.1 Application Information for the 16 kHz Black Line Picture Tubes .............. 351

4.2.2 32 kHz / 100 Hz Deflection Circuits for the 66FS Black Line Picture Tube 361

SMPS Circuit Examples 377

4.3.1 A 70W Full Performance TV SMPS Using The TDA8380 ......................... 379

4.3.2 A Synchronous 200W SMPS for 16 and 32 kHz TV .................................. 389

Monitor Deflection Circuit Example 397

4.4.1 A Versatile 30 - 64 kHz Autosync Monitor ................................................. 399

CHAPTER 5 Automotive Power Electronics 421

Automotive Motor Control (including selection guides) 423

5.1.1 Automotive Motor Control With Philips MOSFETS .................................... 425

Automotive Lamp Control (including selection guides) 433

5.2.1 Automotive Lamp Control With Philips MOSFETS .................................... 435

The TOPFET 443

5.3.1 An Introduction to the 3 pin TOPFET ......................................................... 445

5.3.2 An Introduction to the 5 pin TOPFET ......................................................... 447

5.3.3 BUK101-50DL - a Microcontroller compatible TOPFET ............................ 449

5.3.4 Protection with 5 pin TOPFETs ................................................................. 451

5.3.5 Driving TOPFETs ....................................................................................... 453

5.3.6 High Side PWM Lamp Dimmer using TOPFET ......................................... 455

5.3.7 Linear Control with TOPFET ...................................................................... 457

5.3.8 PWM Control with TOPFET ....................................................................... 459

5.3.9 Isolated Drive for TOPFET ........................................................................ 461

5.3.10 3 pin and 5 pin TOPFET Leadforms ........................................................ 463

5.3.11 TOPFET Input Voltage ............................................................................ 465

5.3.12 Negative Input and TOPFET ................................................................... 467

5.3.13 Switching Inductive Loads with TOPFET ................................................. 469

5.3.14 Driving DC Motors with TOPFET ............................................................. 471

5.3.15 An Introduction to the High Side TOPFET ............................................... 473

5.3.16 High Side Linear Drive with TOPFET ...................................................... 475iii


Automotive Ignition 477

5.4.1 An Introduction to Electronic Automotive Ignition ...................................... 479

5.4.2 IGBTs for Automotive Ignition .................................................................... 481

5.4.3 Electronic Switches for Automotive Ignition ............................................... 483

CHAPTER 6 Power Control with Thyristors and Triacs 485

Using Thyristors and Triacs 487

6.1.1 Introduction to Thyristors and Triacs ......................................................... 489

6.1.2 Using Thyristors and Triacs ....................................................................... 497

6.1.3 The Peak Current Handling Capability of Thyristors .................................. 505

6.1.4 Understanding Thyristor and Triac Data .................................................... 509

Thyristor and Triac Applications 521

6.2.1 Triac Control of DC Inductive Loads .......................................................... 523

6.2.2 Domestic Power Control with Triacs and Thyristors .................................. 527

6.2.3 Design of a Time Proportional Temperature Controller ............................. 537

Hi-Com Triacs 547

6.3.1 Understanding Hi-Com Triacs ................................................................... 549

6.3.2 Using Hi-Com Triacs .................................................................................. 551

CHAPTER 7 Thermal Management 553

Thermal Considerations 555

7.1.1 Thermal Considerations for Power Semiconductors ................................. 557

7.1.2 Heat Dissipation ......................................................................................... 567

CHAPTER 8 Lighting 575

Fluorescent Lamp Control 577

8.1.1 Efficient Fluorescent Lighting using Electronic Ballasts ............................. 579

8.1.2 Electronic Ballasts - Philips Transistor Selection Guide ............................ 587

8.1.3 An Electronic Ballast - Base Drive Optimisation ........................................ 589

iv

Introduction Power Semiconductor ApplicationsPhilips Semiconductors

CHAPTER 1

Introduction to Power Semiconductors

1.1 General

1.2 Power MOSFETS

1.3 High Voltage Bipolar Transistors

1


General

3


1.1.1 An Introduction To Power Devices

Today’s mains-fed switching applications make use of awide variety of active power semiconductor switches. Thischapter considers the range of power devices on the markettoday, making comparisons both in terms of their operationand their general areas of application. The P-N diode willbe considered first since this is the basis of all activeswitches. This will be followed by a look at both 3 layer and4 layer switches.

Before looking at the switches let’s briefly consider thevarious applications in which they are used. Virtually allmains fed power applications switch a current through aninductive load. This is the case even for resonant systemswhere the operating point is usually on the "inductive" sideof the resonance curve. The voltage that the switch isnormally required to block is, in the majority of cases, oneor two times the maximum rectified input voltage dependingon the configuration used. Resonant applications are theexception to this rule with higher voltages being generatedby the circuit. For 110-240 V mains, the required voltageratings for the switch can vary from 200 V to 1600 V.

Under normal operating conditions the off-state losses inthe switch are practically zero. For square wave systems,the on-state losses (occurring during the on-time), areprimarily determined by the on-state resistance which givesrise to an on-state voltage drop, VON. The (static) on-statelosses may be calculated from:

At the end of the "ON" time the switch is turned off. Theturn-off current is normally high which gives rise to a lossdependent on the turn-off properties of the switch. Theprocess of turn-on will also involve a degree of power lossso it is important not to neglect the turn-on properties either.Most applications either involve a high turn-on current orthe current reaching its final value very quickly (high dI/dt).The total dynamic power loss is proportional to both thefrequency and to the turn-on and turn-off energies.

The total losses are the sum of the on-state and dynamiclosses.

The balance of these losses is primarily determined by theswitch used. If the on-state loss dominates, operatingfrequency will have little influence and the maximumfrequency of the device is limited only by its total delay time(the sum of all its switching times). At the other extreme adevice whose on-state loss is negligible compared with theswitching loss, will be limited in frequency due to theincreasing dynamic losses.

Fig.1 Cross section of a silicon P-N diode

High frequency switching When considering frequencylimitation it is important to realise that the real issue is notjust the frequency, but also the minimum on-time required.For example, an SMPS working at 100 kHz with an almostconstant output power, will have a pulse on-time tP of about2-5 µs. This can be compared with a high performance UPSworking at 10 kHz with low distortion which also requires aminimum on-time of 2 µs. Since the 10 kHz and 100 kHzapplications considered here, require similar shorton-times, both may be considered high frequencyapplications.

Resonant systems have the advantage of relaxing turn-onor turn-off or both. This however tends to be at the expenseof V-A product of the switch. The relaxed switchingconditions imply that in resonant systems switches can beused at higher frequencies than in non resonant systems.When evaluating switches this should be taken intoaccount.

P

N

CATHODE

ANODE

PSTATIC= δ.VON.ION (1)

PDYNAMIC = f .(EON + EOFF) (2)

PTOT = δ.VON.ION + f .(EON + EOFF) (3)

5


Fig.2 Field distribution in the N- layer

E

HIGH RESISTIVITY

Thickness

E

Thickness

LOW RESITIVITY

E

INTERMEDIATE CASE

Thickness

Case 1 Case 2 Case 3

At higher values of throughput power, the physical size ofcircuits increases and as a consequence, the strayinductances will also tend to increase. Since the requiredcurrents are higher, the energy stored in the strayinductances rises significantly, which in turn means theinduced peak voltages also rise. As a result suchapplications force the use of longer pulse times, to keeplosses down, and protection networks to limit overshoot ornetworks to slow down switching speeds. In addition theuse of larger switches will also have consequences in termsof increasing the energy required to turn them on and offand drive energy is very important.

So, apart from the voltage and current capabilities ofdevices, it is necessary to consider static and dynamiclosses, drive energy, dV/dt, dI/dt and Safe Operating Areas.

The silicon diodeSilicon is the semiconductor material used for all powerswitching devices. Lightly doped N- silicon is usually takenas the starting material. The resistance of this materialdepends upon its resistivity, thickness and total area.

A resistor as such does not constitute an active switch, thisrequires an extra step which is the addition of a P-layer.The result is a diode of which a cross section is drawn inFig.1

The blocking diodeSince all active devices contain a diode it is worthconsidering its structure in a little more detail. To achievethe high blocking voltages required for active powerswitches necessitates the presence of a thick N- layer. Towithstand a given voltage the N- layer must have the right

combination of thickness and resistivity. Some flexibilityexists as to what that combination is allowed to be, theeffects of varying the combination are described below.

Case 1: Wide N- layer and low resistivity

Figure 2 gives the field profile in the N- layer, assuming thejunction formed with the P layer is at the left. The maximumfield at the P-N junction is limited to 22 kV/cm by thebreakdown properties of the silicon. The field at the otherend is zero. The slope of the line is determined by theresistivity. The total voltage across the N- layer is equal tothe area underneath the curve. Please note that increasingthe thickness of the device would not contribute to itsvoltage capability in this instance. This is the normal fieldprofile when there is another P-layer at the back as in 4layer devices (described later).

Case 2: Intermediate balance

In this case the higher resistivity material reduces the slopeof the profile. The field at the junction is the same so thesame blocking voltage capability (area under the profile)can be achieved with a thinner device.The very steep profile at the right hand side of the profileindicates the presence of an N+ layer which often requiredto ensure a good electrical contact

Case 3: High resistivity material

With sufficiently high resistivity material a near horizontalslope to the electric field is obtained. It is this scenario whichwill give rise to the thinnest possible devices for the samerequired breakdown voltage. Again an N+ layer is requiredat the back.

An optimum thickness and resistivity exists which will givethe lowest possible resistance for a given voltagecapability.Both case 1 (very thick device) and case 3 (high resistivity)give high resistances, the table below shows the thicknessand resistivity combinations possible for a 1000 V diode.

R = ρ.lA

(4)

6


The column named RA gives the resistance area product.(A device thickness of less than 50 µm will never yield1000 V and the same goes for a resistivity of less than26 Ωcm.) The first specification is for the thinnest devicepossible and the last one is for the thickest device, (requiredwhen a P layer is present at the back). It can be seen thatthe lowest resistance is obtained with an intermediate valueof resistivity and material thickness.

Thickness Resistivity RA Comments

(µm) (Ωcm) Ωcm2

50 80 0.400 case 3

60 34 0.204

65 30 0.195

70 27 0.189 min. R

75 26 0.195

80 26 0.208

90 26 0.234

100 26 0.260 case 1

To summarise, a designer of high voltage devices has onlya limited choice of material resistivity and thickness withwhich to work. The lowest series resistance is obtained fora material thickness and resistivity intermediate betweenthe possible extremes. This solution is the optimum for allmajority carrier devices such as the PowerMOSFET andthe J-FET where the on-resistance is uniquely defined bythe series resistance. Other devices make use of chargestorage effects to lower their on-state voltage.Consequently to optimise switching performance in thesedevices the best choice will be the thinnest layer such thatthe volume of stored charge is kept to a minimum. Finallyas mentioned earlier, the design of a 4 layer device requiresthe thickest, low resistivity solution.

The forward biased diodeWhen a diode is forward biased, a forward current will flow.Internally this current will have two components: an electroncurrent which flows from the N layer to the P layer and ahole current in the other direction. Both currents willgenerate a charge in the opposite layer (indicated with QP

and QN in Fig.3). The highest doped region will deliver mostof the current and generate most of the charge. Thus in aP+ N- diode the current will primarily be made up of holesflowing from P to N and there will be a significant volumeof hole charge in the N- layer. This point is important whendiscussing active devices: whenever a diode is forwardbiased (such as a base-emitter diode) there will be a chargestored in the lowest doped region.

Fig. 3 Diode in forward conduction

The exact volume of charge that will result is dependentamongst other things on the minority carrier lifetime, τ.Using platinum or gold doping or by irradiation techniquesthe value of τ can be decreased. This has the effect ofreducing the volume of stored charge and causing it todisappear more quickly at turn-off. A side effect is that theresistivity will increase slightly.

Three Layer devices

The three basic designs, which form the basis for all derived3 layer devices, are given in Fig.4. It should be emphasisedhere that the discussion is restricted to high voltage devicesonly as indicated in the first section. This means that allrelevantdevices will have a vertical structure, characterisedby a wide N--layer.

The figure shows how a three layer device can be formedby adding an N type layer to the P-N diode structure. Twoback to back P-N diodes thus form the basis of the device,where the P layer provides a means to control the currentwhen the device is in the on-state.

There are three ways to use this P-layer as a controlterminal. The first is to feed current into the terminal itself.The current through the main terminals is now proportionalto the drive current. This device is called a High VoltageTransistor or HVT.

The second one is to have openings in the P-layer andpermit the main current to flow between them. Whenreverse biasing the gate-source, a field is generated whichblocks the opening and pinches off the main current. Thisdevice is known as the J-FET (junction FET) or SIT (StaticInduction Transistor).

P

CATHODE

ANODE

Ip IN

QP

QN

N

N

-

+

7


Fig.4 The three basic three layer devices

P

N

EMITTER

COLLECTOR

-

N

BASE

P

N

SOURCE

DRAIN

-

N

GATE

P

N

SOURCE

DRAIN

-

N

GATE

BIPOLAR TRANSISTOR J-FET (SIT) MOS

N N N

The third version has an electrode (gate) placed very closeto the P-layer. The voltage on this gate pushes away theholes in the P-area and attracts electrons to the surfacebeneath the gate. A channel is thus formed between themain terminals so current can flow. The well known namefor this device is MOS transistor.

In practice however, devices bear little resemblance to theconstructions of Fig.4. In virtually all cases a planarconstruction is chosen i.e. the construction is such that onemain terminal (emitter or source) and the drive contact areon the surface of the device. Each of the devices will nowbe considered in some more detail.

The High Voltage Transistor (HVT)The High Voltage Transistor uses a positive base currentto control the main collector current. The relation is:IC = HFE * IB. Thebase drive forward biases the base emitterP-N junction and charge (holes and electrons) will passthrough it. Now the base of a transistor is so thin that themost of the electrons do not flow to the base but into thecollector - giving rise to a collector current. As explainedpreviously, the ratio between the holes and electronsdepend on the doping. So by correctly doping the baseemitter junction, the electron current can be made muchlarger than the hole current, which means that IC can bemuch larger than IB.

When enough base drive is provided it is possible to forwardbias the base-collector P-N junction also. This has asignificant impact on the resistance of the N- layer; holesnow injected from the P type base constitute stored chargecausing a substantial reduction in on-state resistance,much lower than predicted by equation 4. Under theseconditions the collector is an effective extension of the base.Unfortunately the base current required to maintain this

Fig.5 The HVT

condition causes the current gain to drop. For this reasonone cannot use a HVT at a very high current densitybecause then the gain would become impractically low.

The on-state voltage of an HVT will be considerably lowerthan for a MOS or J-FET. This is its main advantage, butthe resulting charge stored in the N- layer has to bedelivered and also to be removed. This takes time and thespeed of a bipolar transistor is therefore not optimal. Toimprove speed requires optimisation of a fine emitterstructure in the form of fingers or cells.

Both at turn-on and turn-off considerable losses may occurunless care is taken to optimise drive conditions. At turn-ona short peak base current is normally required. At turn-offa negative base current is required and negative drive hasto be provided.

P

COLLECTOR

B B BE E

N

N

-

+

N+ N+

IB

Electrons

8


A serious limitation of the HVT is the occurrence of secondbreakdown during switch off. The current contracts towardsthe middle of the emitter fingers and the current density canbecome very high. The RBSOAR (Reverse Bias SafeOperating Area) graph specifies where the device can beused safely. Device damage may result if the device is notproperly used and one normally needs a snubber (dV/dtnetwork) to protect the device. The price of such a snubberis normally in the order of the price of the transistor itself.In resonant applications it is possible to use the resonantproperties of the circuit to have a slow dV/dt.

So, the bipolar transistor has the advantage of a very lowforward voltage drop, at the cost of lower speed, aconsiderable energy is required to drive it and there arealso limitations in the RBSOAR.

The J-FET.

The J-FET (Junction Field Effect Transistor) has a directresistance between the Source and the Drain via theopening in the P-layer. When the gate-source voltage iszero the device is on. Its on-resistance is determined by theresistance of the silicon and no charge is present to makethe resistance lower as in the case of the bipolar transistor.When a negative voltage is applied between Gate andSource, a depletion layer is formed which pinches off thecurrent path. So, the current through the switch isdetermined by the voltage on the gate. The drive energy islow, it consists mainly of the charging and discharging ofthe gate-source diode capacitance. This sort of device isnormally very fast.

Fig.6 The J-FET

Its main difficulty is the opening in the P-layer. In order tospeed up performance and increase current density, it isnecessary to make a number of openings and this impliesfine geometries which are difficult to manufacture. Asolution exists in having the P-layer effectively on thesurface, basically a diffused grid as shown in Fig.6.Unfortunately the voltages now required to turn the deviceoff may be very large: it is not uncommon that a voltage of25 V negative is needed. This is a major disadvantagewhich, when combined with its "normally-on" property andthe difficulty to manufacture, means that this type of deviceis not in mass production.

The MOS transistor.The MOS (Metal Oxide Semiconductor) transistor isnormally off: a positive voltage is required to induce achannel in the P-layer. When a positive voltage is appliedto the gate, electrons are attracted to the surface beneaththe gate area. In this way an "inverted" N-type layer isforced in the P-material providing a current path betweendrain and source.

Fig.7 The MOS transistor

Modern technology allows a planar structure with verynarrow cells as shown in Fig.7. The properties are quitelike the J-FET with the exception that the charge is nowacross the (normally very thin) gate oxide. Charging anddischarging the gate oxide capacitance requires drivecurrents when turning on and off. Switching speeds canbe controlled by controlling the amount of drive chargeduring the switching interval. Unlike the J-FET it does notrequire a negative voltage although a negative voltage mayhelp switch the device off quicker.

The MOSFET is the preferred device for higher frequencyswitching since it combines fast speed, easy drive and widecommercial availability.

DRAIN

S G

N

N

-

+

S

N+ N+P P

DRAIN

G G GS S

P PPN+ N+

N

N

-

+

9


Refinements to the basic structureA number of techniques are possible to improve uponbehaviour of the basic device.

First, the use of finer geometries can give lower on-statevoltages, speed up devices and extend their energyhandling capabilities. This has led to improved"Generation 3" devices for bipolars and to lower RDS(ON) forPowerMOS. Secondly, killing the lifetime τ in the devicecan also yield improvements. For bipolar devices, thispositively effects the switching times. The gain, however,will drop, and this sets a maximum to the amount of lifetimekilling. For MOS a lower value for τ yields the so-calledFREDFETs, with an intrinsic diode fast enough for manyhalf bridge applications such as in AC Motor Controllers.The penalty here is that RDS(ON) is adversely effected(slightly). Total losses, however, are decreasedconsiderably.

Four layer devicesThe three basic designs from the previous section can beextended with a P+-layer at the back, thereby generatingthree basic Four Layer Devices. The addition of this extralayer creates a PNP transistor from the P+-N--P-layers. Inall cases the 3 layer NPN device will now deliver an electroncurrent into the back P+-layer which acts as an emitter. ThePNP transistor will thus become active which results in ahole current flowing from the P+-layer into the high resistiveregion. This in its turn will lead to a hole charge in the highresistive region which lowers the on-state voltageconsiderably, as outlined above for High VoltageTransistors. Again, the penalty is in the switching timeswhich will increase.

All the devices with an added P+-layer at the back will injectholes into the N--layer. Since the P+-layer is much heavierdoped than the N--layer, this hole current will be the majorcontributor to the main current. This means that the chargein the N--layer, especially near the N--P+-junction, will belarge. Under normal operation the hole current will be largeenough to influence the injection of electrons from the topN+-layer. This results in extra electron current beinginjected from the top, leading to extra hole current from theback etc. This situation is represented in the schematic ofFig.8.

An important point is latching. This happens when theinternal currents are such that we are not able to turn offthe device using the control electrode. The only way to turnit off is by externally removing the current from the device.

The switching behaviour of all these devices is affected bythe behaviour of the PNP: as long as a current is flowingthrough the device, the back will inject holes into theN--layer. This leads to switching tails which contributeheavily to switching losses. The tail is strongly affected bythe lifetime τ and by the application of negative drive current

when possible. As previously explained, adjustment of thelifetime affects the on-state voltage. Carefully adjusting thelifetime τ will balance the on-state losses with the switchinglosses.

All four layer devices show this trade-off between switchinglosses and on-state losses. When minimising switchinglosses, the devices are optimised for high frequencyapplications. When the on-state losses are lowest thecurrent density is normally highest, but the device is onlyuseful at low frequencies. So two variants of the four layerdevice generally exist. In some cases intermediate speedsare also useful as in the case of very high power GTOs.

The Thyristor

A thyristor (or SCR, Silicon Controlled Rectifier) isessentially an HVT with an added P+-layer. The resultingP--N--P+ transistor is on when the whole device is on andprovides enough base current to the N+-P-N- transistor tostay on. So after an initial kick-on, no further drive energyis required.

Fig.8 Thyristor

The classical thyristor is thus a latching device. Itsconstruction is normally not very fine and as a result thegate contact is too far away from the centre of the activearea to be able to switch it off. Also the current density ismuchhigher than ina bipolar transistor. The switching timeshowever are very long. Its turn-on is hampered by itsstructure since it takes quite a while for the whole crystalto become active. This seriously limits its dI/dt.

Once a thyristor is on it will only turn-off after having zerocurrent for a few microseconds. This is done by temporarilyforcing the current via a so-called commutation circuit.

P

ANODE

G GC

P+

N-

N+

Ip2

Ip1

10


The charge in the device originates from two sources: Thestandard NPN transistor structure injects holes in theN--layer (IP1 in Fig.8) and the PNP transistor injects a chargefrom the back (IP2 in Fig.8). Therefore the total charge is bigand switching performance is very poor. Due to its slowswitching a normal thyristor is only suitable up to a few kHz.

A major variation on the thyristor is the GTO (Gate Turn OffThyristor). This is a thyristor where the structure has beentailored to give better speed by techniques suchas accuratelifetime killing, fine finger or cell structures and "anodeshorts" (short circuiting P+ and N- at the back in order todecrease the current gain of the PNP transistor).As a result,the product of the gain of both NPN and PNP is just sufficientto keep the GTO conductive. A negative gate current isenough to sink the hole current from the PNP and turn thedevice off.

Fig.9 The GTO

A GTO shows much improved switching behaviour but stillhas the tail as described above. Lower power applications,especially resonant systems, are particularly attractive forthe GTO because the turn-off losses are virtually zero.

The SIThThe SITh (Static Induction Thyristor) sometimes alsoreferred to as FCT (Field Controlled Thyristor) is essentiallya J-FET with an added P+ back layer. In contrast to thestandard thyristor, charge is normally only injected from theback, so the total amount of charge is limited. However, apositive gate drive is possible which will reduce on-stateresistance.

Active extraction of charge via the gate contact is possibleand switching speeds may be reduced considerably byapplying an appropriate negative drive as in the case of anHVT. As for the SIT the technological complexity is a severe

Fig.10 The SITh

drawback, as is its negative drive requirements.Consequently mass production of this device is notavailable yet.

The IGBT

An IGBT (Insulated Gate Bipolar Transistor) is an MOStransistor with P+ at the back. Charge is injected from theback only, which limits the total amount of charge. Activecharge extraction is not possible, so the carrier lifetime τshould be chosen carefully, since that determines theswitching losses. Again two ranges are available with bothfast and slow IGBTs.

Fig.11 The IGBT

ANODE

G G GC C

P PPN+ N+

N

P

-

+

P

ANODE

G G GC C

N

P

-

+

N+ N+

N+ N+

COLLECTOR

E G

N-

E

N+ N+P P

P+

11


The speed of the fast IGBT is somewhat better than that ofa GTO because a similar technology is used to optimisethe IGBT but only the back P+-layer is responsible for thecharge.

The IGBT is gaining rapidly in popularity since itsmanufacturing is similar to producing PowerMOS and anincreasing market availability exists. Although the latchingof IGBTswas seen as aproblem,modern optimised devicesdon’t suffer from latch-up in practical conditions.

Refinements to the basic structure

The refinements outlined for 3 layer devices also apply to4 layer structures. In addition to these, an N+-layer may beinserted between the P+ and N--layer. Without such a layerthe designer is limited in choice of starting material to Case3 as explained in the diode section. Adding the extraN+-layer allows another combination of resistivity andthickness to be used, improving device performance. Anexample of this is the ASCR, the Asymmetric SCR, whichis much faster than normal thyristors. The reverse blockingcapability, however, is now reduced to a value of 10-20 V.

Comparison of the Basic Devices.It is important to consider the properties of devicesmentioned when choosing the optimum switch for aparticular application. Table 2 gives a survey of theessential device properties of devices capable ofwithstanding 1000 V. IGBTs have been classed in termsof fast and slow devices, however only the fast GTO andslow thyristor are represented. The fast devices areoptimised for speed, the slow devices are optimised for Onvoltage.

Comments

This table is valid for1000 V devices. Lowervoltagedeviceswill always perform better, higher voltage devices areworse.

A dot means an average value in between "+" and "-"

The "(--)" for a thyristor means a "--" in cases where forcedcommutation is used; in case of natural commutation it is"+"

Most figures are for reference only: in exceptional casesbetter performance has been achieved, but the figuresquoted represent the state of the art.

HVT J-FET MOS THY GTO IGBT IGBT Unitslow fast

V(ON) 1 10 5 1.5 3 2 4 V

Positive Drive Requirement - + + + + + + + = Simple toimplement

Turn-Off requirement - - + (--) - + + + = Simple toimplement

Drive circuit complexity - . + (-) . + + - = complex

Technology Complexity + . . + - - - - = complex

Device Protection - . + + - - - + = Simple toimplement

Delay time (ts, tq) 2 0.1 0.1 5 1 2 0.5 µs

Switching Losses . ++ ++ -- - - . + = good

Current Density 50 12 20 200 100 50 50 A/cm2

Max dv/dt (Vin = 0) 3 20 10 0.5 1.5 3 10 V/ns

dI/dt 1 10 10 1 0.3 10 10 A/ns

Vmax 1500 1000 1000 5000 4000 1000 1000 V

Imax 1000 10 100 5000 3000 400 400 A

Over Current factor 5 3 5 15 10 3 3

12


Merged devicesMerged devices are the class of devices composed of twoor more of the above mentioned basic types. They don’toffer any breakthrough in device performance. This isunderstandable since the basic properties of the discusseddevices are not or are hardly effected. They may bebeneficial for the user though, primarily because they mayresult in lower positive and/or negative drive requirements.

Darlingtons and BiMOSA darlington consists of two bipolar transistors. The emittercurrent of the first (the driver) forms the base current of theoutput transistor. The advantages of darlingtons may besummarised as follows. A darlington has a higher gain thana single transistor. It also switches faster because the inputtransistor desaturates the output transistor and lowerswitching losses are the result. However, the resultingVCE(sat) is higher. The main issue, especially for higherpowers is the savings in drive energy. This means thatdarlingtons can be used at considerably higher outputpowers than standard transistors. Modern darlingtons inhigh power packages can be used in 20 kHz motor drivesand power supplies.

A BiMOS consists of a MOS driver and a bipolar outputtransistor. The positive drive is the same as MOS butturn-off is generally not so good. Adding a "speed-up" diodecoupled with some negative drive improves things.

Fig.12 The MCT

MCTMCT stands for MOS Controlled Thyristor. This device iseffectively a GTO with narrow tolerances, plus a P-MOStransistor between gate and source (P+-N-P MOS, the lefthand gate in Fig.12) and an extra N-MOS to turn it on, theN-P-N--MOS shown underneath the right hand gate.

Where the GTO would like to be switched off with a negativegate, the internal GTO in an MCT can turn off by shortcircuiting its gate-cathode, due to its fine structure. Its drivetherefore is like a MOS transistor and its behaviour similarto a GTO. Looking closely at the device it is obvious thata GTO using similar fine geometries with a suitable externaldrive can always perform better, at the cost of some drivecircuitry. The only plus point seems to be its ease of drive.

Application areas of the various devices

The following section gives an indication of where thevarious devices are best placed in terms of applications. Itis possible for circuit designers to use various tricks tointegrate devices and systems in innovative manners,applying devices far outside their ’normal’ operatingconditions. As an example, it is generally agreed that above100 kHz bipolars are too difficult to use. However, a450 kHz converter using bipolars has been alreadydescribed in the literature.

As far as the maximum frequency is concerned a numberof arguments must be taken into account.

First the delay times, either occurring at turn-on or atturn-off, will limit the maximum operating frequency. Areasonable rule of thumb for this is fMAX = 3 / tDELAY. (Thereis a danger here for confusion: switching times tend todepend heavily on circuit conditions, drive of the device andon current density. This may lead to a very optimistic orpessimistic expectation and care should be taken toconsider reasonable conditions.)

Another factor is the switching losseswhich areproportionalto the frequency. These power losses may be influencedby optimising the drive or by the addition of external circuitssuch as dV/dt or dI/dt networks. Alternatively the heatsinksize may be increased or one may choose to operatedevices at a lower current density in order to decreasepower losses. It isclear that thisargument isvery subjective.

A third point is manufacturability. The use of fine structuresfor example, which improves switching performance, ispossible only for small silicon chip sizes: larger chips withvery fine MOS-like structures will suffer from unacceptablelow factory yields. Therefore high power systems requiringlarge chip areas are bound to be made with less finestructures and will consequently be slower.

The operating current density of the device will influenceits physical size. A low current density device aimed at highpower systems would need a large outline which tends tobeexpensive. Large outlines also increase the physical sizeof the circuit, which leads to bigger parasitic inductancesand associated problems.

ANODE

N

P

-

+

N

G C G

P+P+N N+

P

13


Fig.13 Comparison of device operating regions

10 MHz

1 MHz

100 kHz

10 kHz

1 kHz

100 Hz100VA 1kVA 10kVA 100kVA 1MVA 10MVA 100MVA

DARLINGTONSHVT

RESONANT SYSTEMS

SQUARE WAVE SYSTEMS

THYRISTOR

(fast)

(fast)-IGBT-(slow)

SITr SITh

MOS

GTO (slow)

High power systems will, because of the mechanical size,be restricted in speed as explained earlier in the text . Thiscoincides well with the previously mentioned slowercharacter of higher power devices.

Last but not least it is necessary to take the applicationtopology into account. Resonant systems allow the use ofconsiderably higher frequencies, since switching lossesareminimised. Square wave systems cause more losses in thedevices and thus restrict the maximum frequency. To makea comparison of devices and provide insight into whichpowers are realistic for which devices we have to take allthe above mentioned criteria into account.

Figure 13 shows the optimum working areas of the variousswitching devices as a function of switchable power andfrequency. The switchable power is defined as IAV timesVMAX as seen by the device.

As an example, darlingtons will work at powers up to 1 MVAi.e. 1000 V devices will switch 1000 A. The frequency isthen limited to 2.5 kHz. At lower powers higher frequencies

can be achieved however above 50 kHz, darlingtons arenot expected to be used. One should use this table only asguidance;usingspecial circuit techniques,darlingtons haveactually been used at higher frequencies. Clearly operationat lower powers and frequencies is always possible.

Conclusions

The starting material for active devices aimed at highvoltageswitching are made on silicon of which the minimumresistivity and thickness are limited. This essentiallydetermines device performance, since all active switchesincorporate such a layer. Optimisation can be performedfor either minimum thickness, as required in the case ofHVTs, or for minimum resistance, as required for MOS andJ-FETs.The thickest variation (lowest resistivity) is requiredin the case of some 4 layer devices.

Basically three ways exist to control current through thedevices: feeding a base current into a P-layer (transistor),

14


using a voltage to pinch-off the current through openingsin the P-layer (J-FET) and by applying a voltage onto a gatewhich inverts the underlying P-layer (MOS).

The HVT is severely limited in operating frequency due toits stored hole charge, but this at the same time allows agreater current density and a lower on-state voltage. It alsorequires more drive energy than both MOS and J-FET.

When we add a P+-layer at the back of the three basic threelayer devices we make three basic four layer devices. TheP+-layer produces a PNP transistor at the back whichexhibits hole storage. This leads to much improved currentdensities and lower on-state losses, at the cost of switchingspeed. The four layer devices can be optimised for lowon-state losses, in which case the switching will be poor,or for fast switching, in which case the on-state voltage will

be high.

The properties of all six derived basic devices aredetermined to a large extent by the design of the highresistive area and can be optimised by applyingtechnological features in the devices such as lifetime killingand fine geometries.

Resonant systems allow devices to be used at much higherfrequencies due to the lower switching losses and theminimum on-times which may be longer, compared tosquare wave switching systems. Figure 13 gives theexpected maximum frequency and switching power for thediscussed devices. Thedifference for square wavesystemsand resonant systems is about a factor of 10.

15


Power MOSFET

17


1.2.1 PowerMOS Introduction

Device structure and fabricationThe idea of a vertical channel MOSFET has been knownsince the 1930s but it was not until the mid 1970s that thetechnology of diffusion, ion implantation and materialtreatment had reached the level necessary to produceDMOS on a commercial scale. The vertical diffusiontechnique uses technology more commonly associatedwith the manufacture of large scale integrated circuits thanwith traditional power devices. Figure 1(a) shows thevertical double implanted (DIMOS) channel structure whichis the basis for all Philips power MOSFET devices.

An N-channel PowerMOS transistor is fabricated on anN+substrate with a drain metallization applied to its’underside. Above the N+substrate is an N- epi layer, thethickness and resistivity of which depends on the requireddrain-source breakdown voltage. The channel structure,formed from a double implant in to the surface epi material,is laid down in a cellular pattern such that many thousandsof cells go to make a single transistor. The N+polysilicongate which is embedded in an isolating silicon dioxide layer,is a single structure which runs between the cells acrossthe entire active region of the device. The sourcemetallization also covers the entire structure and thus

parallels all the individual transistor cells on the chip. Thelayout of a typical low voltage chip is shown in Fig.1(b). Thepolysilicon gate is contacted by bonding to the defined padarea while the source wires are bonded directly to thealuminium over the cell array. The back of the chip ismetallized with a triple layer of titanium/nickel/silver and thisenables the drain connection to be formed using a standardalloy bond process.

The active part of the device consists of many cellsconnected in parallel to give a high current handlingcapability where the current flow is vertical through the chip.Cell density is determined by photolithographic tolerancerequirements in defining windows in the polysilicon andgate-source oxide and also by the width of the polysilicontrack between adjacent cells. The optimum value forpolysilicon track width and hence cell density varies as afunction of device drain-source voltage rating, this isexplained in more detail further in the section. Typical celldensitiesare 1.6 million cells per square inch for low voltagetypes and 350,000 cells per square inch for high voltagetypes. The cell array is surrounded by an edge terminationstructure to control the surface electric field distribution inthe device off-state.

Fig.1(a) Power MOSFET cell structure.

19


Fig.1(b) Plan view of a low voltage Power MOS chip

20


A cross-section through a single cell of the array is shownin Fig.2. The channel length is approximately 1.5 micronsand is defined by the difference in the sideways diffusionof the N+ source and the P-body. Both these diffusions areauto-aligned to the edge of the polysilicon gate during thefabrication process. All diffusions are formed by ionimplantation followed by high temperature anneal/drive-into give good parameter reproducibility. The gate iselectrically isolated from the silicon by an 800 Angstromlayer of gate oxide (for standard types, 500 Angstrom forLogic level and from the overlying aluminium by a thick layerof phosphorus doped oxide. Windows are defined in thelatter oxide layer to enable the aluminium layer to contactthe N+ source and the P+ diffusion in the centre of each cell.The P+ diffusion provides a low resistance connectionbetween the P- body and ground potential, thus inhibitingturn-on of the inherent parasitic NPN bipolar structure.

Fig.2 Cross-section of a single cell.

Device operationCurrent flow in an enhancement mode power MOSFET iscontrolled by the voltage applied between the gate andsource terminals. The P- body isolates the source and drainregions and forms two P-N junctions connectedback-to-back. With both the gate and source at zero voltsthere is no source-drain current flow and the drain sits atthe positive supply voltage. The only current which can flowfrom source to drain is the reverse leakage current.

As the gate voltage is gradually made more positive withrespect to the source, holes are repelled and a depletedregion of silicon is formed in the P- body below thesilicon-gate oxide interface. The silicon is now in a’depleted’ state, but there is still no significant current flowbetween the source and drain.

When the gate voltage is further increased a very thin layerof electrons is formed at the interface between the P- bodyand the gate oxide. This conductive N-type channelenhanced by the positive gate-source voltage, now permitscurrent to flow from drain to source. The silicon in the P-

body is referred to as being in an ’inverted’ state. A slightincrease in gate voltage will result in a very significantincrease in drain current and a corresponding rapiddecrease in drain voltage, assuming a normal resistive loadis present.

Eventually the drain current will be limited by the combinedresistances of the load resistor and the RDS(ON) of theMOSFET. The MOSFET resistance reaches a minimumwhen VGS = +10 volts (assuming a standard type).Subsequently reducing the gate voltage to zero voltsreverses the above sequence of events. There are nostored charge effects since power MOSFETS are majoritycarrier devices.

Power MOSFET parameters

Threshold voltageThe threshold voltage is normally measured by connectingthe gate to the drain and then determining the voltage whichmust be applied across the devices to achieve a draincurrent of 1.0 mA. This method is simple to implement andprovides a ready indication of the point at which channelinversion occurs in the device.

The P- body is formed by the implantation of boron throughthe tapered edge of the polysilicon followed by an annealand drive-in. The main factors controlling threshold voltageare gate oxide thickness and peak surface concentrationin the channel, which is determined by the P-body implantdose. To allow for slight process variation a window isusually defined which is 2.1 to 4.0 volts for standard typesand 1.0 to 2.0 volts for logic level types.

Positive charges in the gate oxide, for example due tosodium, can cause the threshold voltage to drift. Tominimise this effect it is essential that the gate oxide isgrown under ultra clean conditions. In addition thepolysilicon gate and phosphorus doped oxide layer providea good barrier to mobile ions such as sodium and thus helpto ensure good threshold voltage stability.

Drain-source on-state resistanceThe overall drain-source resistance, RDS(ON), of a powerMOSFET is composed of several elements, as shown inFig.3.

The relative contribution from each of the elements varieswith the drain-source voltage rating. For low voltagedevices the channel resistance is very important while for

N- EPI Layer

N+ Substrate

DRAIN

SOURCE

P- P-P+

N+ N+

GATE

20 um

21


Fig.3 Power MOSFET components of RDS(ON).

the high voltage devices the resistivity and thickness of theepitaxial layer dominates. The properties of the variousresistive components will now be discussed:

Channel . The unit channel resistance is determined by thechannel length, gate oxide thickness, carrier mobility,threshold voltage, and the actual gate voltage applied tothe device. The channel resistance for a given gate voltagecan be significantly reduced by lowering the thickness ofthe gate oxide. This approach is used to fabricate the LogicLevel MOSFET transistors and enables a similar valueRDS(ON) to be achieved with only 5 volts applied to the gate.Of course, the gate-source voltage rating must be reducedto allow for the lower dielectric breakdown of the thinneroxide layer.

The overall channel resistance of a device is inverselyproportional to channel width, determined by the totalperiphery of the cell windows. Channel width is over200 cm for a 20 mm2 low voltage chip. The overall channelresistance can be significantly reduced by going to highercell densities, since the cell periphery per unit area isreduced.

Accumulation layer . The silicon interface under the centreof the gate track is ’accumulated’ when the gate is biasedabove the threshold voltage. Thisprovides a low resistancepath for the electrons when they leave the channel, prior toentering the bulk silicon. This effect makes a significantcontribution towards reducing the overall RDS(ON).

Parasitic JFET . After leaving the accumulation layer theelectrons flow vertically down between the cells into thebulk of the silicon. Associated with each P-N junction thereis a depletion region which, in the case of the high voltagedevices,extends severalmicrons into the N epitaxial region,even under zero bias conditions. Consequently the currentpath for the electrons is restricted by this parasitic JFETstructure. The resistance of the JFET structure can bereduced by increasing the polysilicon track width. Howeverthis reduces the cell density. The need for compromise

leads to an optimum value for the polysilicon track width fora given drain-source voltage rating. Since the zero-biasdepletion width is greater for low doped material, then awider polysilicon track width is used for high voltage chipdesigns.

Spreading resistance . As the electrons move further intothe bulk of the silicon they are able to spread sideways andflow under the cells. Eventually paths overlap under thecentre of each cell.

Epitaxial layer . The drain-source voltage ratingrequirements determine the resistivity and thickness of theepitaxial layer. For high voltage devices the resistance ofthe epitaxial layer dominates the overall value of RDS(ON).

Substrate. The resistance of the N+ substrate is onlysignificant in the case of 50 V devices.

Wires and leads . In a completed device the wire and leadresistances contribute a few milli-ohms to the overallresistance.

For all the above components the actual level of resistanceis a function of the mobility of the current carrier. Since themobility of holes is much lower than that of electrons theresistance of P-Channel MOSFETs is significantly higherthan that of N-Channel devices. For this reason P-Channeltypes tend to be unattractive for most applications.

Drain-source breakdown voltage

The voltage blocking junction in the PowerMOS transistoris formed between the P-body diffusion and the N- epi layer.For any P-N junction there exists a maximum theoreticalbreakdown voltage, which is dependent on doping profilesand material thickness. For the case of the N-channelPowerMOS transistor nearly all the blocking voltage issupported by the N- epi layer. The ability of the N- epi layertosupport voltage is a function of its resistivity and thicknesswhere both must increase to accommodate a higherbreakdown voltage. This has obvious consequences interms of drain-source resistance with RDS(ON) beingapproximately proportional to BVDSS

2.5. It is thereforeimportant to design PowerMOS devices such that thebreakdown voltage is as close as possible to the theoreticalmaximum otherwise thicker, higher resistivity material hasto be used. Computer models are used to investigate theinfluence of cell design and layout on breakdown voltage.Since these factors also influence the ’on-state’ andswitching performances a degree of compromise isnecessary.

To achieve a high percentage of the theoretical breakdownmaximum it is necessary to build edge structures aroundthe active area of the device. These are designed to reducethe electric fields which would otherwise be higher in theseregions and cause premature breakdown.

22


For low voltage devices this structure consists of a fieldplate design, Fig.4. The plates reduce the electric fieldintensity at the corner of the P+ guard ring which surroundsthe active cell area, and spread the field laterally along thesurface of the device. The polysilicon gate is extended toform the first field plate, whilst the aluminium sourcemetallization forms the second plate. The polysilicontermination plate which is shorted to the drain in the cornersof the chip (not shown on the diagram) operates as achannel stopper. This prevents any accumulation ofpositive charge at the surface of the epi layer and thusimproves stability. Aluminium overlaps the terminationplate and provides a complete electrostatic screen againstany external ionic charges, hence ensuring good stabilityof blocking performance.

Fig.4 Field plate structure for low voltage devices.

For high voltage devices a set of floating P+ rings, see Fig.5,is used to control the electric field distribution around thedevice periphery. The number of rings in the structuredepends on the voltage rating of the device, eight rings areused for a 1000 volt type such as the BUK456-1000A. Athree dimensional computer model enables the optimumringspacing to be determined so that each ring experiencesa similar field intensity as the structure approachesavalanche breakdown. The rings are passivated withpolydox which acts as an electrostatic screen and preventsexternal ionic charges inverting the lightly doped N-

interface to form P- channels between the rings. Thepolydox is coated with layers of silicon nitride andphosphorus doped oxide.

All types have a final passivation layer of plasma nitride,which acts as a further barrier to mobile charge and alsogives anti-scratch protection to the top surface.

Fig.5 Ring structure for high voltage devices.

Electrical characteristics

The DC characteristicIf a dc voltage source is connected across the drain andsource terminals of an N channel enhancement modeMOSFET, with the positive terminal connected to the drain,the following characteristics can be observed. With the gateto source voltage held below the threshold level negligiblecurrent will flow when sweeping the drain source voltagepositive from zero. If the gate to source voltage is takenabove the threshold level, increasing the drain to sourcevoltage will cause current to flow in the drain. This currentwill increase as the drain-source voltage is increased up toa point known as the pinch off voltage. Increasing thedrain-source terminal voltage above this value will notproduce any significant increase in drain current.

The pinch off voltage arises from a rapid increase inresistance which for any particular MOSFET will dependon the combination of gate voltage and drain current. In itssimplest form, pinch off will occur when the ohmic dropacross the channel region directly beneath the gatebecomes comparable to the gate to source voltage. Anyfurther increase in drain current would now reduce the netvoltage across the gate oxide to a level which is no longersufficient to induce a channel. The channel is thus pinchedoff at its edge furthest from the source N+ (see Fig.6).

A typical set of output characteristics is shown in Fig.7. Thetwo regions of operation either side of the pinch off voltagecan be seen clearly. The region at voltages lower than thepinch off value is usually known as the ohmic region.Saturation region is the term used to describe that part ofthe characteristic above the pinch-off voltage. (NB Thisdefinition of saturation is different to that used for bipolardevices.)

N- EPI Layer

P+

N+

P-

LOPOX

LPCVD NITRIDE

POLYDOX

P+P+P+P+

SourceGuardRing

Floating Guard Rings

N- EPI Layer

N+ Substrate

P+

P-

N+

Guard Ring

Polysilicon

SourceMetallization

Gate RingSource RingPolysiliconTerminationPlate

(Source)

23


Fig.6 Pinch off in a Power MOSFET

Fig.7 A typical dc characteristic for an N-channelenhancement mode MOSFET.

The switching characteristics

The switching characteristics of a Power MOSFET aredetermined largely by the various capacitances inherent inits’ structure. These are shown in Fig.8.

To turn the device on and off the capacitances have to becharged and discharged, the rate at which this can beachieved is dependent on the impedance and the currentsinking/sourcing capability of the drive circuit. Since it isonly the majority carriers that are involved in the conductionprocess, MOSFETs do not suffer from the same storagetime problems which limit bipolar devices where minoritycarriers have to be removed during turn-off. For mostapplications therefore the switching times of the Power

Fig.8. The internal capacitances of a Power MOSFET.

MOSFET are limited only by the drive circuit and can bevery fast. Temperature has only a small effect on devicecapacitances therefore switching times are independent oftemperature.

In Fig.9 typical gate-source and drain-source voltages fora MOSFET switching current through a resistive load areshown. The gate source capacitance needs to be chargedup to a threshold voltage of about 3 V before the MOSFETbegins to turn on. The time constant for this is CGS(RDR+RG)and the time taken is called the turn-on delay time (tD(ON)).As VGS starts to exceed the threshold voltage the MOSFETbegins to turn on and VDS begins to fall. CGD now needs tobe discharged as well as CGS being charged so the timeconstant is increased and the gradient of VGS is reduced.As VDS becomes less than VGS the value of CGD increasessharply since it is depletion dependent. A plateau thusoccurs in the VGS characteristic as the drive current goesinto the charging of CGD.

VGS10 V

Ohmic Drop7 V

3 V Net Gate to Channel10 V Gate to Channel

Polysilicon Gate

Gate Oxide

P-Source

ChannelN-

Pinch Off

Id

+

D

S

G

Cgs

Cgd

Cds

0VDS / V

ID / A BUK4y8-800A20

15

10

5

0

4

5

6

4.5

5.5

10

10 20 30

VGS / V =

24


Fig.9. The switching waveforms for a MOSFET.

0 0.2 0.4 0.6 0.8 1 1.2

50

40

30

20

10

0

Time (Microseconds)

Vol

tage

(V

olts

)

Drain-Source Voltage

Gate-Source Voltage

Turn-on Turn-off

When VDS has collapsed VGS continues to rise as overdriveis applied. Gate overdrive is necessary to reduce theon-resistance of the MOSFET and thereby keep power lossto a minimum.

To turn the MOSFET off the overdrive has first to beremoved. The charging path for CGD and CDS now containsthe load resistor (RL) and so the turn-off time will begenerally longer than the turn-on time.

The Safe Operating AreaUnlike bipolar devices Power MOSFETs do not suffer fromsecond breakdown phenomena when operated within theirvoltage rating. Essentially therefore the safe operating areaof a Power MOSFET is determined only by the power

necessary to raise its junction temperature to the ratedmaximum of 150 ˚C or 175 ˚C (which TJMAX depends onpackage and voltage rating). Whether a MOSFET is beingoperated safely with respect to thermal stress can thus bedetermined directly from knowledge of the power functionapplied and the thermal impedance characteristics.

Asafe operating areacalculated assumingamounting basetemperature of 25 ˚C is shown in Fig.10 for a BUK438-800device. This plot shows the constant power curves for avariety of pulse durations ranging from dc to 10 µs. Thesecurves represent the power levels which will raise Tj up tothe maximum rating. Clearly for mounting basetemperatures higher than 25 ˚C the safe operating area issmaller. In addition it is not usually desirable to operate the

25


device at its TJMAX rating. These factors can be taken intoaccount quite simply where maximum power capability fora particular application is calculated from:

Tj is the desired operating junction temperature (must beless than Tjmax)Tmb is the mounting base temperatureZth is the thermal impedance taken from the data curves

The safe operating area is bounded by a peak pulse currentlimit and a maximum voltage. The peak pulse current isbased on a current above which internal connections maybe damaged. The maximum voltage is an upper limit abovewhich the device may go into avalanche breakdown.

Fig.10. The Safe Operating Area of the BUK438-800.

In a real application the case temperature will be greaterthan 25 ˚C because of the finite thermal impedance ofpracticalheatsinks. Alsoa junction temperature of between80 ˚C and 125 ˚C would be preferable since this improvesreliability. If a nominal junction temperature of 80 ˚Cinstead of 150 ˚C is used then the ability of the MOSFETto withstand current spikes is improved.

Causes of Power Loss

There are four main causes of power dissipation inMOSFETs.

Conduction losses - The conduction losses (PC) are givenby equation (1).

It is important to note that the on-resistance of the MOSFETwhen it is operated in the Ohmic region is dependent onthe junction temperature. On-resistance roughly doublesbetween 25 ˚C and 150 ˚C, the exact characteristics areshown in the data sheets for each device.

Switching losses - When a MOSFET is turned on or off itcarries a large current and sustains a large voltage at thesame time. There is therefore a large power dissipationduring the switching interval. Switching losses arenegligible at low frequencies but are dominant at highfrequencies. The cross-over frequency depends on thecircuit configuration. For reasons explained in the sectionon switching characteristics, a MOSFET usually turns offmore slowly than it turns on so the losses at turn-off will belarger than at turn-on. Switching losses are very dependenton circuit configuration since the turn-off time is affected bythe load impedance.

Turn-off losses may be reduced by the use of snubbercomponents connected across the MOSFET which limit therate of rise of voltage. Inductors can be connected in serieswith the MOSFET to limit the rate of rise of current at turn-onand reduce turn-on losses. With resonant loads switchingcan take place at zero crossing of voltage or current soswitching losses are very much reduced.

Diode losses - These losses only occur in circuits whichmake use of the antiparallel diode inherent in the MOSFETstructure. A good approximation to the dissipation in thediode is the product of the diode voltage drop which istypically less than 1.5 V and the average current carried bythe diode. Diode conduction can be useful in such circuitsas pulse width modulated circuits used for motor control, insome stepper motor drive circuits and in voltage fed circuitsfeeding a series resonant load.

Gate losses - The losses in the gate are given in equation2whereRG is the internal gate resistance, RDR is the externaldrive resistance, VGSD is the gate drive voltage and CIP isthe capacitance seen at the input to the gate of theMOSFET.

The input capacitance varies greatly with the gate drainvoltage so the expression in equation 3 is more useful.

(3)

Where QG is the peak gate charge.

Parallel OperationIf power requirements exceed those of available devicesthen increased power levels can be achieved by parallellingdevices. Parallelling of devices is made easier using

Pmax =(Tj − Tmb)

Zth

10 1000VDS / V

ID / A100

10

1

0.1

100 us

1 ms

10 ms

RDS(ON) =

VDS/ID

100 ms DC

10 us

tp =

BUK438-800

100

A

B

PG =CIP.VGSD

2 .f .RG

(RG + RDR)(2)

PG =QG.VGSD.f .RG

(RG + RDR)(3)

PC = ID2.RDS(ON) (1)

26


MOSFETs because they have a positive temperaturecoefficient of resistance. If one parallelled MOSFET carriesmore current than the others it becomes hotter. Thiscauses the on-resistance of that particular device tobecome greater than that of the others and so the currentin it reduces. This mechanism opposes thermal runawayin one of the devices. The positive temperature coefficientalso helps to prevent hot spots within the MOSFET itself.

Applications of Power MOSFETsPower MOSFETs are ideally suited for use in manyapplications, some of which are listed below. Furtherinformation on the major applications is presented in

subsequent chapters.

Chapter 2: Switched mode power supplies (SMPS)

Chapter 3: Variable speed motor control.

Chapter 5: Automotive switching applications.

ConclusionsIt can be seen that the operation of the Power MOSFET isrelatively easy to understand. The advantages of fastswitching times, ease of parallelling and low drive powerrequirements make the device attractive for use in manyapplications.

27


1.2.2 Understanding Power MOSFET Switching Behaviour

Power MOSFETs are well known for their ease of drive andfast switching behaviour. Being majority carrier devicesmeans they are free of the charge storage effects whichinhibit the switching performance of bipolar products. Howfast a Power MOSFET will switch is determined by thespeed at which its internal capacitances can be chargedand discharged by the drive circuit. MOSFET switchingtimes are often quoted as part of the device data howeveras an indication as to the true switching capability of thedevice, these figures are largely irrelevant. The quotedvalues are only a snapshot showing what will be achievedunder the stated conditions.

This report sets out to explain the switching characteristicsof Power MOSFETs. It will consider the main features ofthe switching cycle distinguishing between what is devicedeterminant and what can be controlled by the drive circuit.The requirements for the drive circuit are discussed in termsof the energy that it must supply as well as the currents itis required to deliver. Finally, how the drive circuitinfluences switching performance, in terms of switchingtimes, dV/dt and dI/dt will be reviewed.

Voltage dependent capacitanceThe switching characteristics of the Power MOSFET aredetermined by its capacitances. These capacitances arenot fixed but are a function of the relative voltages betweeneach of the terminals. To fully appreciate Power MOSFETswitching, it is necessary to understand what gives rise tothis voltage dependency.

Parallel plate capacitance is expressed by the well knownequation

where ’a’ is the area of the plates, d is the separatingdistance and Ε is the permittivity of the insulating materialbetween them. For a parallel plate capacitor, the plates aresurfaces on which charge accumulation / depletion occursin response to a change in the voltage applied across them.In a semiconductor, static charge accumulation / depletioncan occur either across a PN junction or at semiconductorinterfaces either side of a separating oxide layer.

i) P-N junction capacitanceThe voltage supporting capability of most powersemiconductors is provided by a reverse biased P-Njunction. The voltage is supported either side of the junctionby a region of charge which is exposed by the appliedvoltage. (Usually referred to as the depletion regionbecause it is depleted of majority carriers.) Fig.1 showshow the electric field varies across a typical P-N- junction

for a fixed dc voltage. The shaded area beneath the curvemust be equal to the applied voltage. The electric fieldgradient is fixed, independent of the applied voltage,according to the concentration of exposed charge. (This isequal to the background doping concentration used duringdevice manufacture.) A slight increase in voltage abovethis dc level will require an extensionof the depletion region,and hence more charge to be exposed at its edges, this isillustrated in Fig.1. Conversely a slight reduction in voltagewill cause the depletion region to contract with a removalof exposed charge at its edge. Superimposing a small acsignal on the dc voltage thus causes charge to be addedand subtracted at either side of the depletion region of widthd1. The effective capacitance per unit area is

Since the depletion region width is voltage dependent it canbe seen from Fig.1 that if the dc bias is raised to say V2,the junction capacitance becomes

Junction capacitance is thus dependent on applied voltagewith an inverse relationship.

Fig.1 Voltage dependence of a PN junctioncapacitance

ii) Oxide capacitanceFig.2 shows two semiconductor layers separated by aninsulating oxide. In this case the surface layer is polysilicon(representative of the PowerMOS gate structure) and thelower layer is a P-type substrate. Applying a negativevoltage to the upper layer with respect to the lower will causepositive charge accumulation at the surface of the P-doped

C1 =Εd1

2

C2 =Εd2

3

E

xd1d2

V1

V2

N type siliconP type silicon

C = Εad

1

29


material (positively charged holes of the P material areattracted by the negative voltage). Any changes in thisapplied voltage will cause a corresponding change in theaccumulation layer charge. The capacitance per unit areais thus

where t = oxide thickness

Applying a positive voltage to the gate will cause a depletionlayer to form beneath the oxide, (ie the positively chargedholes of the P-material are repelled by the positive voltage).The capacitance will now decrease with increasing positivegate voltage as a result of widening of the depletion layer.Increasing the voltage beyond a certain point results in aprocess known as inversion; electrons pulled into theconduction band by the electric field accumulate at thesurface of the P-type semiconductor. (The voltage at whichthis occurs is the threshold voltage of the power MOSFET.)Once the inversion layer forms, the depletion layer widthwill not increase with additional dc bias and the capacitanceis thus at its minimum value. (NB the electron chargeaccumulation at the inversion layer cannot follow a highfrequency ac signal in the structure of Fig.2, so highfrequency capacitance is still determined by the depletionlayer width.) The solid line of Fig.3 represents thecapacitance-voltage characteristic of an MOS capacitor.

Fig.2 Oxide capacitance

In a power MOSFET the solid line is not actually observed;the formation of the inversion layer in the P-type materialallows electrons to move from the neighbouring N+-source,the inversion layer can therefore respond to a highfrequency gate signal and the capacitance returns to itsmaximum value, dashed line of Fig.3.

Fig.3 C-V plot for MOS capacitance

Power MOSFET capacitances

Fig.4 Parasitic capacitance model

The circuit model of Fig.4 illustrates the parasiticcapacitances of the Power MOSFET. Most PowerMOSdata sheets do not refer to these components but to inputcapacitance Ciss, output capacitance Coss and feedbackcapacitance Crss. The data sheet capacitances relate tothe primary parasitic capacitances of Fig.4 as follows:

Ciss: Parallel combination of Cgs and CgdCoss: Parallel combination of Cds and CgdCrss: Equivalent to Cgd

Fig.5 shows the cross section of a power MOSFET cellindicatingwhere the parasiticcapacitances occur internally.

Cox

C

Bias Voltage

(Polysilicon to P-type silicon)

Cox =Εt

4

Cgd

Cds

Cgs

G

S

D

toxide

P type silicon

Polysilicon

30


Fig.5 Cross section of a single PowerMOS cell showinginternal capacitance

Thecapacitancebetween drain andsource is aP-N junctioncapacitance, varying in accordance with the width of thedepletion layer, which in turn depends on the voltage beingsupported by the device. The gate source capacitanceconsists of the three components, CgsN+, CgsP and CgsM.Of these CgsP is across the oxide which will vary accordingto the applied gate source voltage as described above.

Of particular interest is the feedback capacitance Cgd. Itis this capacitance which plays a dominant role duringswitching and which is also the most voltage dependent.Cgd is essentially two capacitors in series such that

CgsN+

CgsM OxidePolysilicon

N+P-

P

N-

N+

MetalizationSource

Drain

Gate

Cgdbulk

CgdoxCgsP

Cds Depletion Layer

1Cgd

=1

Cgdox+

1Cgdbulk

5

Fig.6 How Cgd is affected by voltage

OxidePolysilicon

N+P-

P

N-

N+

Metalization

Source

Drain

Gate

Depletion Layer Widths

Area of Oxide Capacitance Exposedfor Voltages V1 & V2

For Three Applied Voltages

Width for Cgdbulk

at Voltage V3

V3

V2V1

31


Fig.6 illustrateshow this capacitance is affected by the drainto gate voltage. With a large voltage drain to gate, Cgdbulkis very small due to the wide depletion region and thusmaintains Cgd at a low value. As the voltage is reducedthe depletion region shrinks until eventually the oxidesemiconductor interface is exposed. This occurs as Vdgapproaches 0 V. Cgdox now dominates Cgd. As Vdg isfurther reduced the drain will become negative with respectto the gate (normal on-state condition) an increasing areaof the oxide-semiconductor interface is exposed and anaccumulation layer forms at the semiconductor surface.Thenow large area of exposed oxide results in a large valuefor Cgdox and hence Cgd. Fig.7 shows Cgd plotted as afunction of drain to gate voltage. This illustrates the almoststep increase in capacitance at the point where Vgs = Vgd.

Fig.7 How Cgd varies with drain to gate voltage

Charging cycle - The Gate ChargeOscillogramThe switching cycle of a power MOSFET can be clearlyobserved by applying a constant current to the gate andusing a constant current source as the load, Fig.8. In thiscircuit the MOSFET is turned on by feeding a constantcurrent of 1 mA on to the gate, conversely the device isturned off by extracting a constant current of 1 mA from thegate. The gate and drain voltages with respect to sourcecan be monitored on an oscilloscope as a function of time.Since Q = it, a 1 µsec period equates to 1 nc of chargeapplied to the gate. The gate source voltage can thus beplotted as a function of charge on the gate. Fig.9 showssuch a plot for the turn-on of a BUK555-100A, also shownis the drain to source voltage. This gate voltage plot showsthe characteristic shape which results from charging of thepower MOSFETs input capacitance. This shape arises asfollows: (NB the following analysis uses the two circuitmodels of Fig.10 to represent a MOSFET operating in theactive region (a) and the ohmic region (b). In the active

region the MOSFET is a constant current source where thecurrent is a function of the gate-source voltage. In the ohmicregion the MOSFET is in effect just a resistance.)

Fig.8 Gate charge circuit

At time, t0 (Fig.9), the gate drive is activated. Current flowsinto the gate as indicated in Fig.11(a), charging both Cgsand Cgd. After a short period the threshold voltage isreached and current begins to rise in the MOSFET. Theequivalent circuit is now as shown in Fig.11(b). The drainsource voltage remains at the supply level as long as id < I0and the free wheeling diode D is conducting.

Fig.9 Gate charge plot for a BUK555-100A (Logic LevelFET)

Vdd

Vdg0

Cdg

0 10 20 30 40

26

24

22

20

18

16

14

12

10

8

6

4

2

0

(V)

(us)(1us = 1 nc for Vgs plot)

Vds

Vgs

BUK555-100A(@ Id = 25 A)

t0 t1 t2

32


The current in the MOSFET continues to rise until id = I0,since the device is still in its active region, the gate voltagebecomes clamped at this point, (t1). The entire gate currentnow flows through Cgd causing the drain-source voltage todrop as Cgd is discharged, Fig.11(c). The rate at whichVds falls is given by:

As Vdg approaches zero, Cgd starts to increasedramatically, reaching its maximum as Vdg becomesnegative. dVds/dt is now greatly reduced giving rise to thevoltage tail.

Once the drain-source voltage has completed its drop tothe on-state value of I0.RDS(ON), (point t2), the gate sourcevoltage becomes unclamped and continues to rise,Fig.11(d). (NB dVgs/dQ in regions 1 and 3 indicates the

input capacitance values.)

Fig.10 Equivalent circuits for a Power MOSFET duringswitching

G

D

S

Cgd

Cgs

id = f(Vgs)

G

D

S

Cgd

Cgs

Rds(on)

(a) (b)

dVdsdt

=dVdg

dt=

igCgd

6

Fig.11 Charging the parasitic capacitance during turn-on

Vdd

Cgd

Cgs

Io

(a) Vdd

Cgd

Cgs

id = f(Vgs)

Io

(b)

Vdd

Cgd

Cgs

id = f(Vgs)

Io

(c) Vdd

Cgd

Cgs

Rds(on)

Io

(d)

33


The gate charge oscillogram can be found in the data forall Philips PowerMOS devices. This plot can be used todetermine the required average gate drive current for aparticular switching speed. The speed is set by how fastthe charge is supplied to the MOSFET.

Energy consumed by the switching eventIn the majority of applications the power MOSFET will bedriven not from a constant current source but via a fixed

gate drive impedance from a voltage source. Fig.13 showsthe voltageon avoltage independentcapacitor as a functionof charge. The area beneath the charge vs voltage curveequals the stored energy (E = Q.V/2). The area above thecharge vs voltage curve (bounded by the supply voltage)is the amount of energy dissipated during the charging cyclefrom a fixed voltage source. The total energy delivered bythe supply is therefore Q.V, where 1/2 Q.V is stored on thecapacitor to be dissipated during the discharge phase.

Fig.12 Gate charging cycle

t0 t1 t2 t3 t4 t5 t6

1a 2a 3a

1b 2b3b

4a

4b

Vgg

Vdd

Out

put C

apac

itanc

e

34


Although the voltage vs charge relationship for theMOSFETs gate is not linear, energy loss is easily identified.The following discussion assumes a simple drive circuitconsisting of a voltage source and drive resistance.

From t0 to t1 energy is stored in the gate capacitance whichis equal to the area of region 1a. Since this charge hasfallen through a voltage Vgg - Vgs(t), the area of region 1brepresents the energy dissipated in the drive resistanceduring its delivery. Between t1 and t2 all charge entersCgd, the area of region 2a represents the energy stored inCgd while 2b again corresponds with the energy dissipationin the drive resistor. Finally, between t2 and t3 additionalenergy is stored by the input capacitance equal to the areaof region 3a.

Fig.13 Energy stored on a capacitor

The total energy dissipated in the drive resistance at turn-onis therefore equal to the area 1b + 2b + 3b. Thecorresponding energy stored on the input capacitance is1a + 2a + 3a, this energy will be dissipated in the driveresistance at turn-off. The total energy expended by thegate drive for the switching cycle is Q.Vgg.

As well as energy expended by the drive circuit, a switchingcycle will also require energy to be expended by the draincircuit due to the charging and discharging of Cgd and Cdsbetween the supply rail and VDS(ON). Moving from t5 to t6the drain side of Cgd is charged from Io.RDS(ON) to Vdd. Thedrain circuit must therefore supply sufficient current for thischarging event. The total charge requirement is given bythe plateau region, Q6 - Q5. The area 4a (Fig.12) underthe drain-source voltage curve represents the energystored by the drain circuit on Cgd during turn-on. Region4b represents the corresponding energy delivered to theload during this period. The energy consumed from thedrain supply to charge and discharge Cgd over oneswitching cycle is thus given by:

(The energy stored on Cgd during turn-off is dissipatedinternally in the MOSFET during turn-on.) Additional energyis also stored on Cds during turn-off which again isdissipated in the MOSFET at turn-on.

The energy lost by both the gate and drain supplies in thecharging and discharging of the capacitances is very smallover 1 cycle; Fig.9 indicates 40 nc is required to raise thegate voltage to 10 V, delivered from a 10 V supply thisequates to 400 nJ; to charge Cgd to 80 V from an 80 Vsupply will consume 12 nc x 80 V = 1.4 µJ. Only asswitching frequencies approach 1 MHz will this energy lossstart to become significant. (NB these losses only apply tosquare wave switching, the case for resonant switching issome-what different.)

Switching performance

1) Turn-on

The parameters likely to be of most importance during theturn-on phase are,

turn-on timeturn-on losspeak dV/dtpeak dI/dt.

Turn-on time is simply a matter of how quickly the specifiedcharge can be applied to the gate. The average currentthat must be supplied over the turn-on period is

For repetitive switching the average current requirement ofthe drive is

where f = frequency of the input signal

Turn-on loss occurs during the initial phase when currentflows in the MOSFET while the drain source voltage is stillhigh. To minimise this loss, a necessary requirement ofhigh frequency circuits, requires the turn-on time to be assmall as possible. To achieve fast switching the drive circuitmust be able to supply the initial peak current, given byequation 10.

Voltage

Charge

Stored Energy

Supply Voltage

Ion =Qton

8

I = Q.f 9

WDD = (Q6 − Q5).(VDD − VDS(ON)) 7

35


Fig.14 Bridge Circuit

One of the main problems associated with very fastswitching MOSFETs is the high rates of change in voltageand current. High values of dV/dt can couple throughparasitic capacitances to give unwanted noise on signallines. Similarly a high dI/dt may react with circuit inductanceto give problematic transients and overshoot voltages in thepower circuit. dI/dt is controlled by the time taken to chargethe input capacitance up to the plateau voltage, while dV/dtis governed by the rate at which the plateau region is movedthrough.

Particular care is required regarding dV/dt when switchingin bridge circuits, (Fig.14). The free wheeling diode willhave associated with it a reverse recovery current. Whenthe opposing MOSFET switches on, the drain current risesbeyond the load current value Io to a value Io + Irr.Consequently Vgs increases beyond Vgt(Io) to Vgt(Io + Irr)as shown in Fig.15. Once the diode has recovered thereis a rapid decrease in Vgs to Vgt(Io) and this rapid decreaseprovides additional current to Cgd on top of that beingsupplied by the gate drive. This in turn causes Vdg andVds to decrease very rapidly during this recovery period.

The dV/dt in this period is determined by the recoveryproperties of the diode in relation to the dI/dt imposed uponit by the turn-on of the MOSFET, (reducing dI/dt will reducethis dV/dt, however it is best to use soft recovery diodes).

Fig.15 Gate charging cycle for a bridge circuit

ii) Turn-off

The parameters of most importance during the turn-offphase are,

turn-off timeturn-off losspeak dVds/dtpeak dId/dt.

Turn-off of a power MOSFET is more or less the inverse ofthe turn-on process. The main difference is that thecharging current for Cgd during turn-off must flow throughboth the gate circuit impedance and the load impedance.A high load impedance will thus slow down the turn-offspeed.

The speed at which the plateau region is moved throughdetermines the voltage rise time. In most applications thecharging current for Cgd will be limited by the gate drivecircuitry. The charging current,assuming no negative drive,is simply

and the length of the plateau region will be

T1

T2

D1

D2

Load

Vdd

0

Vdd

0

0

Vgt(Io)Vgt(Io + Irr)Gate Source Voltage

Drain Source Voltage

MOSFET Current

0

IoIo + Irr

Diode Current0

Io

Irr

t

Ipk =VGG

Rg

10

dVdsdt

=ig

Cgd=

VGG − VGT

RG.Cgd11

i =VgtRG

12

tp =Q.RG

Vgt13

36


The implications for low threshold (Logic Level) MOSFETsare clear from the above equations. The lower value of Vgtwill mean a slower turn-off for a given gate impedance whencompared to an equivalent standard threshold device.Equivalent switching therefore requires a lower driveimpedance to be used.

ConclusionsIn theory the speed of a power MOSFET is limited only bythe parasitic inductances of its internal bond wires. The

speed is essentially determined by how fast the internalcapacitances can be charged and discharged by the drivecircuit. Switching speeds quoted in data should be treatedwith caution since they only reflect performance for oneparticular drive condition. The gate charge plot is a moreuseful way of looking at switching capability since itindicates how much charge needs to be supplied by thedrive to turn the device on. How fast that charge should beapplied depends on the application and circuit performancerequirements.

37


1.2.3 Power MOSFET Drive Circuits

MOSFETs are being increasingly used in many switchingapplications because of their fast switching times and lowdrive power requirements. The fast switching times caneasily be realised by driving MOSFETs with relativelysimple drive circuits. The following paragraphs outline therequirementsof MOSFET drive circuits and present variouscircuit examples. A look at the special requirements of veryfast switching circuits is also presented, this can be foundin the latter part of this article.

The requirements of the drive circuit

The switching of a MOSFET involves the charging anddischarging of the capacitance between the gate andsource terminals. This capacitance is related to the size ofthe MOSFET chip used typically about 1-2 nF. Agate-source voltage of 6V is usually sufficient to turn astandard MOSFET fully on. However further increases ingate-to-source voltage are usually employed to reduce theMOSFETs on-resistance. Therefore for switching times ofabout 50 ns, applying a 10 V gate drive voltage to aMOSFET with a 2 nF gate-source capacitance wouldrequire the drive circuit to sink and source peak currents ofabout 0.5 A. However it is only necessary to carry thiscurrent during the switching intervals.

The gate drive power requirements are given in equation(1)

where QG is the peak gate charge, VGS is the peak gatesource voltage and f is the switching frequency.

In circuits which use a bridge configuration, the gateterminals of the MOSFETs in the circuit need to float relativeto each other. The gate drive circuitry then needs toincorporatesome isolation.The impedance of the gatedrivecircuit should not be so large that there is a possibility ofdV/dt turn on. dV/dt turn on can be caused by rapid changesof drain to source voltage. The charging current for thegate-drain capacitance CGD flows through the gate drivecircuit. This charging current can cause a voltage dropacross the gate drive impedance large enough to turn theMOSFET on.

Non-isolated drive circuitsMOSFETs can be driven directly from a CMOS logic IC asshown in Fig.1.

Fig.1 A very simple drive circuit utilizing a standardCMOS IC

Faster switching speeds can be achieved by parallellingCMOS hex inverting (4049) or non-inverting (4050) buffersas shown in Fig.2.

Fig.2 Driving Philips PowerMOS with 6 parallelledbuffered inverters.

A push pull circuit can also be used as shown in Fig.3.

Theconnections between the drive circuit and the MOSFETshould be kept as short as possible and twisted together ifthe shortest switching times are required. If both the drivecircuit and the terminals of the MOSFET are on the samePCB, then the inductance of tracks, between the drivetransistors and the terminals of the MOSFETs, should bekept as small as possible. This is necessary to reduce theimpedance of the drive circuit in order to reduce theswitching times and lessen the susceptibility of the circuit

4011

4049

0 V

15 V

PG = QG.VGS.f 1

39


Fig.3 A drive circuit using a two transistor push pullcircuit.

to dV/dt turn-on of the MOSFET. Attention to layout alsoimproves the immunity to spurious switching byinterference.

One of the advantages of MOSFETs is that their switchingtimes can be easily controlled. For example it may berequired to limit the rate of change of drain current to reduceovershoot on the drain source voltage waveform. Theovershoot may be caused by switching current in parasiticlead or transformer leakage inductance. The slowerswitching can be achieved by increasing the value of thegate drive resistor.

The supply rails should be decoupled near to fast switchingelements such as the push-pull transistors in Fig.3. Anelectrolytic capacitor in parallel with a ceramic capacitor arerecommended since the electrolytic capacitor will not be alow enough impedance to the fast edges of the MOSFETdrive pulse.

Isolated drive circuitsSome circuits demand that the gate and source terminalsof MOSFETs are floating with respect to those of otherMOSFETs in the circuit. Isolated drive to these MOSFETscan be provided in the following way:

(a) Opto-isolators.

A drive circuit using an opto-isolator is shown in Fig.4.

A diode in the primary side of the opto-isolator emitsphotons when it is forward biased. These photons impingeon the base region of a transistor in the secondary side.This causes photogeneration of carriers sufficient to satisfythe base requirement for turn-on. In this way theopto-isolator provides isolation between the primary andsecondary of the opto-isolator. An isolated supply isrequired for the circuitry on the secondary side of theopto-isolator. This supply can be derived, in some cases,from the drain-to-source voltage across the MOSFET beingdriven as shown in Fig.5. This is made possible by the lowdrive power requirements of MOSFETs.

Fig.4. An isolated drive circuit using an opto-isolator.

4049

0 V

15 V

Opto-Isolator

5 V

40


Fig.5. An opto-isolated drive circuit with the isolated power supply for the secondary derived from the drain sourcevoltage of the MOSFET.

4049

0 V

15 V

Opto-Isolator

5 V

Some opto-isolators incorporate an internal screen toimprove the common mode transient immunity. Values ashigh as 1000 V/µs are quoted for common mode rejectionwhich is equivalent to rejecting a 300V peak-to-peaksinewave.

The faster opto-isolators work off a maximum collectorvoltage on the secondary side of 5V so some form of levelshifting may be required.

(b) Pulse transformers .

A circuit using a pulse transformer for isolation is shown inFig.6(a).

When T2 switches on, voltage is applied across the primaryof the pulse transformer. The current through T2 consistsof the sum of the gate drive current for T1 and themagnetising current of the pulse transformer. From thewaveforms of current and voltage around the circuit shownin Fig.6(b), it can be seen that after the turn off of T2 thevoltage across it rises to VD + VZ, where VZ is the voltageacross the zener diode ZD. The zener voltage VZ appliedacross the pulse transformer causes the flux in the core tobe reset. Thus the net volt second area across the pulsetransformer is zero over a switching cycle. The minimumnumber of turns on the primary is given by equation (2).

where B is the maximum flux density, Ae is the effectivecross sectional area of the core and t is the time that T2 ison for.

The circuit in Fig.6(a) is best suited for fixed duty cycleoperation. The zener diode has to be large enough so thatthe flux in the core will be reset during operation with themaximum duty cycle. For any duty cycle less than themaximum there will be a period when the voltage acrossthe secondary is zero as shown in Fig.7.

In Fig.8 a capacitor is used to block the dc components ofthe drive signal.

Drive circuits using pulse transformers have problems if awidely varying duty cycle is required. This causes widelyvarying gate drive voltages when the MOSFET is off. Inconsequence there are variable switching times andvarying levels of immunity to dV/dt turn on and interference.There are several possible solutions to this problem, someexamples are given in Figs.9 - 12.

N =V.tB.Ae

2

41


Fig.6(a) A circuit using a pulse transformer for isolation.

Fig.6(b) Waveforms associated with pulse transformer.

Fig.7. The voltage waveforms associated with the circuitin Fig.6(a) with varying duty cycles.

In the circuit shown in Fig.9 when A is positive with respectto B the input capacitance of T1 is charged through theparasitic diode of T2. The voltage across the secondary ofthe pulse transformer can then fall to zero and the inputcapacitance of T1 will remain charged. (It is sometimesnecessary to raise the effective input capacitance with anexternal capacitor as indicated by the dashed lines.) WhenB becomes positive with respect to A T2 will turn on andthe input capacitance of T2 will be discharged. The noiseimmunity of the circuit can be increased by using anotherMOSFET as shown in Fig.10.

Fig.8. A drive circuit using a capacitor to block the dccomponent of the drive waveforms.

Fig.9. A drive circuit that uses a pulse transformer forisolation which copes well with widely varying duty

cycles.

Fig.10. An isolated drive circuit with good performancewith varying duty cycles and increased noise immunity.

In Fig.10 the potential at A relative to B has to be sufficientto charge the input capacitance of T3 and so turn T3 onbefore T1 can begin to turn on.

T1

T2

ZD

Vd

0 V

T1

PrimaryVoltage

VoltageAcross T2

time

time

T1

A

B

T2

time

time

HighDutyCycle

LowDutyCycle

SecondaryVoltage

T1

A

B

T2

T3

42


Fig.11. A drive circuit that reduces the size of the pulse transformer.

T1Q1

h.f. clock

drive signal

In Fig.11 the drive signal is ANDed with a hf clock. If theclock has a frequency much higher than the switchingfrequency of T1 then the size of the pulse transformer isreduced. The hf signal on the secondary of the pulse

transformer is rectified. Q1 provides a low impedance pathfor discharging the input capacitance of T1 when the hfsignal on the secondary of the pulse transformer is absent.

Fig.12 Example of pulse transformer isolated drive with a latching buffer

15 V

Z

HEF40097

2k22k2

10T 20T

47 pF18 k

1 k c18v

DC Link

O V

100R

FX3848

8 uF2n2

43


Figure 12 shows a hex non-inverting buffer connected onthe secondary side, with one of the six buffers configuredas a latch. The circuit operates such that the positive goingedge of the drive pulse will cause the buffers to latch intothe high state. Conversely the negative going edge of thedrive pulse causes the buffers to latch into the low state.With the component values indicated on the diagram thiscircuit can operate with pulse on-times as low as 1 µs. Theimpedance Z represents either the low side switch in abridge circuit (which can be a MOSFET configured withidentical drive) or a low side load.

The impedance of the gate drive circuit may be used tocontrol the switching times of the MOSFET. Increasing gatedrive impedance however can increase the risk of dV/dtturn-on. To try and overcome this problem it may benecessary to configure the drive as outlined in Fig.13.

(a)

(b)Fig.13. Two circuits that reduce the risk of dV/dt turn on.

The diode in Fig.13(a) reduces the gate drive impedancewhen the MOSFET is turned off. In Fig.13(b) when the drivepulse is taken away, the pnp transistor is turned on. Whenthe pnp transistor is on it short-circuits the gate to the sourceand so reduces the gate drive impedance.

High side drive circuitsThe isolated drive circuits in the previous section can beused for either high or low side applications. Not all highside applications however require an isolated drive. Twoexamples showing how a high side drive can be achievedsimply with a boot strap capacitor are shown in Fig.14. Boththese circuits depend upon the topping up of the charge on

the boot strap capacitor while the MOSFET is off. For thisreason these circuits cannot be used for dc switching. Theminimum operating frequency is determined by the size ofthe boot strap capacitor (and R1 in circuit (a)), as theoperating frequency is increased so the value of thecapacitor can be reduced. The circuit example in Fig. 14(a)has a minimum operating frequency of 500 Hz.

Fig.14(a) Drive circuit for a low voltage half bridgecircuit.

At high frequencies it may be necessary to replace R1 withthe transistor T3 as shown in Fig.14(b). This enables veryfast turn-off times which would be difficult to achieve withcircuit (a) since reducing R1 to a low value would cause theboot strap capacitor to discharge during the on-period. Theimpedance Z represents either the low side switch part ofthe bridge or the load.

Fig.14(b) Modification for fast turn-off.

Very fast drive circuits for frequencies upto 1 MHz

The following drive circuits can charge the gate sourcecapacitance particularly fast and so realise extremely shortswitching times. These fast transition times are necessaryto reduce the switching losses. Switching losses are directlyproportional to the switching frequency and are greater thanconduction losses above a frequency of about 500 kHz,

VinT1

T2

C 6.8uF

R1 47R

10k

22k

1k0

Z

24V

0V

T1

D1R1

R2

T1

24V

VinT1

T2

C

T3

Z

0V

44


although this crossover frequency is dependent on circuitconfiguration. Thus for operation above 500 kHz it isimportant to have fast transition times.

At frequencies below 500 kHz the circuit in Fig.15 is oftenused. Above 500 kHz the use of the DS0026 instead of the4049 is recommended. The DS0026 has a high currentsinking and sourcing capability of 2.5 A. It is a NationalSemiconductor device and is capable of charging acapacitance of 100 pF in as short a time as 25 ns.

Fig.15 A MOSFET drive circuit using a hex CMOSbuffered inverter IC

In Fig.16 the value of capacitor C1 is made approximatelyequal to the input capacitance of the driven MOSFET. Thusthe RC time constant for the charging circuit isapproximately halved. The disadvantage of thisarrangement is that a drive voltage of 30V instead of 15Vis needed because of the potential divider action of C1 andthe input capacitance of the driven MOSFET. A small valueof C1 would be ideal for a fast turn on time and a large valueof C1 would produce a fast turn off. The circuit in Fig.17replaces C1 by two capacitors and enables fast turn on andfast turn off.

Fig.16 A simple drive circuit with reduced effectiveinput capacitance

For the circuit in Fig.17 when MOSFET T1 is turned on thedriven MOSFET T3 is driven initially by a voltage VDD

feeding three capacitors in series, namely C1, C2 and theinput capacitance of T3. Since the capacitors are in seriestheir equivalent capacitance will be low and so the RC timeconstant of the charging circuit will be low. C1 is made lowto make the turn on time very fast.

Fig.17 A drive circuit with reduced effective inputcapacitance and prolonged reverse bias at turn off.

The voltage across C2 will then settle down to(VDD - VZD1) R2/(R1 + R2). Therefore the inclusion ofresistors R1 and R2 means that C2 can be made largerthan C1 and still have a large voltage across it before theturn off of T3. Thus C2 can sustain a reverse voltage acrossthe gate source of T3 for the whole of the turn off time. Theinitial discharging current will be given by Equation 3,

Making VDD large will make turn on and turn off times verysmall.

Fast switching speeds can be achieved with the push pullcircuit of Fig.19. A further improvement can be made byreplacing the bipolar devices by MOSFETs as shown inFig.20. The positions of the P and N channel MOSFETsmay be interchanged and connected in the alternativearrangement of Fig.21. However it is likely that oneMOSFET will turn on faster than the other turns off and sothe circuit in Fig.21 may cause a current spike during theswitching interval. The peak to average current rating ofMOSFETs is excellent so this current spike is not usuallya problem. In the circuit of Fig.20 the input capacitance ofthe driven MOSFET is charged up to VDD - VT, where VT isthe threshold voltage, at which point the MOSFET T1 turnsoff. Therefore when T2 turns on there is no current spike.

Vdd

T1

T2

T3

ZD1

C2R1 C1

ZD2

R2

4049

0 V

15 V

I =VZD1 +

R2.(VDD − VZD1)

(R1 + R2)

RSTRAY+ RDS(ON)T2

3

30 V

0 V

C1 = 2 nF

45


Fig.18 A comparison of the switching times forMOSFETs driven from a constant current source and a

constant voltage source.

Fig.19 A push-pull drive circuit using bipolar transistors

There may well be some advantages in charging the inputcapacitance of the MOSFET from a constant current sourcerather than a constant voltage source. For a given drainsource voltage a fixed amount of charge has to betransferred to the input capacitance of a MOSFET to turnit on. As illustrated in Fig.18 this charge can be transferredmore quickly with a constant current of magnitude equal tothe peak current from a constant voltage source.

A few other points are worthy of note when discussing veryfast drive circuits.

(1) SMPS working in the 1 - 15 MHz range sometimes useresonant drive circuits. These SMPS are typically QRC(Quasi Resonant Circuits). The resonant drive circuits donot achieve faster switching by the fact that they areresonant. But by being resonant, they recoup some of thedrive energy and reduce the gate drive power. There aretwo main types of QRC - zero voltage and zero currentswitching circuits. In one of these types, fall times are notcritical and in the other, rise times are not critical. On the

critical switching edge, a normal, fast switching edge isprovided by using a circuit similar to those given above. Forthe non-critical edge there is a resonant transfer of energy.Thus drive losses of QG.VGS.f become 0.5.QG.VGS.f.

Fig.20 A push-pull drive circuit using MOSFETs in thecommon drain connection.

Fig.21 A push-pull drive circuit using MOSFETs in thecommon source connection

(2) It is usual toprovide overdrive of the gatesource voltage.This means charging the input capacitance to a voltagewhich is more than sufficient to turn the MOSFET fully on.This has advantages in achieving lower on-resistance andincreasing noise immunity. The gate power requirementsare however increased when overdrive is applied. It maywell be a good idea therefore to drive the gate with only12 V say instead of 15 V.

(3) It is recommended that a zener diode be connectedacross the gate source terminals of a MOSFET to protectagainst over voltage. This zener can have a capacitancewhich is not insignificant compared to the input capacitanceof small MOSFETs. The zener can thus affect switchingtimes.

Constant

Current

Constant

Voltage

A1

A2

A1 = A2T1

T2

time

time

I

I

Vdd

T1

T2

Vdd

T1

T2

46


Parallel operation

Power MOSFETs lend themselves readily to operation inparallel since their positive temperature coefficient ofresistance opposes thermal runaway. Since MOSFETshave low gate drive power requirements it is not normallynecessary to increase the rating of drive circuit componentsif more MOSFETs are connected in parallel. It is howeverrecommended that differential resistors are used in thedrive circuits as shown in Fig.22.

Fig.22. A drive circuit suitable for successful parallellingof Philips MOSFETs incorporating differential resistors.

These differential resistors (RD) damp down possibleoscillations between reactive components in the device andin connections around the MOSFETs, with the MOSFETsthemselves, which have a high gain even up to 200 MHz.

Protection against gate-sourceovervoltagesIt is recommended that zener diodes are connected acrossthe gate-source terminals of the MOSFET to protect againstvoltage spikes. One zener diode or two back-to-back zenerdiodes are necessary dependent on whether thegate-source is unipolar or bipolar, as shown in Fig.23.

The zener diodes should be connected close to theterminals of the MOSFET to reduce the inductance of theconnecting leads. If the inductance of the connecting leadsis too large it can support sufficient voltage to cause anovervoltage across the gate-source oxide.

In conclusion the low drive power requirement of PhilipsPowerMOS make provision of gate drive circuitry arelatively straightforward process as long as the fewguide-lines outlined in this note are heeded.

RdRd

Fig.23. Zener diodes used to suppress voltage spikes across the gate-source terminals of the MOSFET.

T1

4011

47


1.2.4 Parallel Operation of Power MOSFETs

This section is intended as a guide to the successfulparallelling of Power MOSFETs in switching circuits.

Advantages of operating devices inparallel

Increased power handling capabilityIf power requirements exceed those of available devicesthen increased power levels can be achieved by parallellingdevices. The alternative means of meeting the powerrequirements would be to increase the area of die. Theprocessing of the larger die would have a lower yield andso the relative cost of the die would be increased. The largerdie may also require a more expensive package.

StandardisationParallelling devices can mean that only one package, saythe TO220 package, needs to be used. This can result inreduced production costs.

Increased operating frequencyPackages are commercially available which contain uptofive die connected in parallel. The switching capabilities ofthese packages are typically greater than 10 kVA. Theparasitic inductances of connections to the parallelled diesare different for each die. This means that the current ratingof the package has to be derated at high frequencies toallow for unequal current sharing. The voltage rating of themultiple die package has to be derated for higher switchingspeeds. This is because the relatively large inductances ofconnections within the package sustain appreciablevoltages during the switching intervals. This means that thevoltages at the drain connections to the dice will beappreciably greater than voltages at the terminals of thepackage. By parallelling discrete devices these problemscan be overcome.

Faster switching speeds are achieved using parallelleddevices than using a multiple die package. This is becauseswitching times are adversely affected by the impedanceof the gate drive circuit. When devices are parallelled theseimpedances are parallelled and so their effect is reduced.Hence faster switching times and so reduced switchinglosses can be achieved.

Faster switching speeds improve parallelling. Duringswitching intervals one MOSFET may carry more currentthan other MOSFETs in parallel with it. This is caused bydifferences in electrical parameters between the parallelledMOSFETs themselves or between their drive circuits. Theincreased power dissipation in the MOSFET which carriesmore current will be minimised if switching speeds are

increased. The inevitable inductance in the sourceconnection, caused by leads within the package, causes anegative feedback effect during switching. If the rate of riseof current in one parallelled MOSFET is greater than in theothers then the voltage drop across inductances in its drainand source terminals will be greater. This will oppose thebuild up of current in this MOSFET and so have a balancingeffect. This balancing effect will be greater if switchingspeeds are faster. This negative feedback effect reducesthe deleterious effect of unequal impedances of drive circuitconnections to parallelled MOSFETs. The faster theswitching speeds then the greater will be the balancingeffect of the negative feedback. Parallelling devicesenables higher operating frequencies to be achieved thanusing multiple die packages. The faster switching speedspossible by parallelling at the device level promote bettercurrent sharing during switching intervals.

Increased power dissipation capability

If two devices, each rated for half the total required current,are parallelled then the sum of their individual powerdissipationcapabilities will be more than the possible powerdissipation in a single device rated for the total requiredcurrent. This is especially useful for circuits operating above100 kHz where switching losses predominate.

Fig.1. A typical graph of on resistance versustemperature for a Power MOSFET

-60 -20 20 60 100 140 180

2

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

Nor

mal

ised

Res

ista

nce

Junction Temperature ( C)

49


Advantages of power MOSFETs forparallel operation

Reduced likelihood of thermal runawayIf one of the parallelled devices carries more current thenthe power dissipation in this device will be greater and itsjunction temperature will increase. The temperaturecoefficient of RDS(ON) for Power MOSFETs is positive asshown in Fig.1. Therefore there will be a rise in RDS(ON) forthe device carrying more current. This mechanism willoppose thermal runaway in parallelled devices and also inparallelled cells in the device.

Low Drive Power RequirementsThe low drive power requirements of power MOSFETsmean that many devices can be driven from the same gatedrive that would be used for one MOSFET.

Very good tolerance of dynamicunbalanceThe peak to average current carrying capability of powerMOSFETs is very good. A device rated at 8A continuousdrain current can typically withstand a peak current of about30A. Therefore, for the case of three 8A devices in parallel,if one of the devices switches on slightly before the othersno damage will result since it will be able to carry the fullload current for a short time.

Design points

DeratingSince there is a spread in on-resistance between devicesfrom different batches it is necessary to derate thecontinuous current rating of parallelled devices by about20%.

LayoutThere are two aspects to successful parallelling which arestatic and dynamic balance. Static balance refers to equalsharing of current between parallelled devices when theyhave been turned on. Dynamic balance means equalsharing of current between parallelled transistors duringswitching intervals.

Unsymmetrical layout of the circuit causes static imbalance.If the connections between individual MOSFETs and therest of the power circuit have different impedances thenthere will be static imbalance. The connections need to bekept as short as possible to keep their inductance as smallas possible. Symmetrical layout is particularly important inresonant circuits where MOSFETs carry a sinusoidalcurrent e.g. in a voltage fed inverter feeding a seriesresonant circuit. In a current fed inverter, where switchingin the inversion stage causes a rectangular wave of current

to be passed through a parallel resonant tank circuit, thevoltage sustained by MOSFETs when they are off will behalf sinusoid. A component of the current carried byMOSFETs will be a charging current for snubber capacitorswhich will be sinusoidal so again symmetrical layout will beimportant.

Fig.2. The waveforms of current through two parallelledBUK453-50A MOSFETs with symmetrical layout.

Fig.3. The waveforms of current through two parallelledBUK453-50A MOSFETS with 50 nH connected in the

source connection on one MOSFET.

Unsymmetrical layout of the gate drive circuitry causesdynamic imbalance. Connections between the gate drivecircuitry and the MOSFETs need to be kept short andtwisted together to reduce their inductance. Further to this

-500 -300 -100 100 300 500

50

40

30

20

10

0

-10

time (ns)

Cur

rent

(A

)

-500 -300 -100 100 300 500

50

40

30

20

10

0

-10

time (ns)

Cur

rent

(A

)

50


the connections between the gate drive circuit andparallelled MOSFETs need to be approximately the samelength.

Figures 2 and 3 illustrate the effect of unsymmetrical layouton the current sharing of two parallelled MOSFETs. Thepresence of 50 nH in the source connection of one of thetwo parallelled BUK453-50A MOSFETs causes noticeableimbalance. A square shaped loop of 1 mm diameter wireand side dimension only 25 mm is sufficient to produce aninductance of 50 nH.

Symmetrical layout becomes more important if moreMOSFETs are parallelled, e.g. if a MOSFET with an RDS(ON)

of 0.7 Ohm was connected in parallel with a MOSFET withan RDS(ON) of 1 Ohm then the MOSFET with the lower RDS(ON)

would carry 18% more current that if both MOSFETs hadan RDS(ON) of 1 ohm. If the MOSFET with an RDS(ON) of 0.7ohm was connected in parallel with a hundred MOSFETswith RDS(ON) of 1 ohm it would carry 42% more current thanif all the MOSFETs had an RDS(ON) 1 Ohm.

Good Thermal Coupling

There should be good thermal coupling between parallelledMOSFETs. This is achieved by mounting parallelledMOSFETs on the same heatsink or on separate heatsinkswhich are in good thermal contact with each other.

If poor thermal coupling existed between parallelledMOSFETs and the positive temperature coefficient ofresistance was relied on to promote static balance, then thetotal current carried by the MOSFETs would be less thanwith good thermal coupling. Some MOSFETs would alsohave relatively high junction temperatures and so theirreliability would be reduced. The temperature coefficient ofMOSFETs is not large enough to make poor thermalcoupling tolerable.

The Suppression of Parasitic Oscillations

Parasitic oscillations can occur. MOSFETs have transitionfrequencies typically in excess of 200 MHz and parasiticreactances are present both in the MOSFET package andcircuit connections, so the necessary feedback conditionsfor parasitic oscillations exist. These oscillations typicallyoccur at frequencies above 100 MHz so a high bandwidthoscilloscope is necessary to investigate them. Thelikelihood of these parasitic oscillations occurring is verymuch reduced if small differential resistors are connectedin the leads to each parallelled MOSFET. A common gatedrive resistor of between 10 and 100 Ohms with differentialresistors of about 10 Ohm are recommended as shown inFig.4.

Fig.4. Differential gate drive resistors

The suppression of parasitic oscillations betweenparallelled MOSFETs can also be aided by passing theconnections from the gate drive circuit through ferritebeads. The effect of these beads below 1 MHz is negligible.The ferrite beads however damp the parasitic oscillationswhich occur at frequencies typically above 100 MHz. Anexample of parasitic oscillations is shown in Fig.5.

Fig.5. Parasitic oscillations on the voltage waveforms ofa MOSFET

If separate drive circuits with closely decoupled powersupplies are used for each parallelled device then parasiticoscillations will be prevented. This condition could besatisfied by driving each parallelled MOSFET from 3 buffersin a CMOS Hex buffer ic.

To take this one stage further, separate push pull transistordrivers could be used for each MOSFET. (A separate baseresistor is needed for each push-pull driver to avoid aMOSFET with a low threshold voltage clamping the drivevoltage to all the push pull drivers). This arrangement alsohas the advantage that the drive circuits can be positionedvery close to the terminals of each MOSFET. Theimpedance of connections from the drive circuits to theMOSFETs will be minimised and so there will be a reduced

10 Ohm10 Ohm

50 Ohm

0

5

10

15

0

10

20

30

40

Vds

(V

)V

gs (

V)

0 400 800 1200 1600 2000time (ns)

51


likelihood of spurious turn on. Spurious turn on can occurwhen there is a fast change in the drain to source voltage.Thechargingcurrent for the gate drain capacitance inherentin the MOSFET structure can cause a voltage drop acrossthe gate drive impedance large enough to turn the MOSFETon. The gate drive impedance needs to be kept as low aspossible to reduce the likelihood of spurious turn on.

Resonant power suppliesIf a resonant circuit is used then there will be reducedinterference and switching losses. The reducedinterference is achieved because sinusoidal waveforms arepresent in resonant circuits rather than rectangularwaveforms. Rectangular waveforms have large highfrequency harmonic components.

MOSFETs are able to switch at a zero crossing of eitherthe voltage or the current waveform and so switching lossesare ideally zero. For example, in the case of a current fedinverter feeding a parallel resonant load switching can takeplace at a zero crossing of voltage so switching losses arenegligible. In this case the sinusoidal drain source voltagesustained by MOSFETs reduces the likelihood of spuriousdv/dt turn on. This is because the peak charging current forthe internal gate to drain capacitance of the MOSFET isreduced.

The current fed approachSwitch mode power supplies using the current fed topologyhave a d.c. link which contains a choke to smooth thecurrent in the link. Thus a high impedance supply ispresented to the inversion stage. Switching in the inversionstage causes a rectangular wave of current to be passedthrough the load. The current fed approach has manyadvantages for switch mode power supplies. It causesreduced stress on devices caused by the slow reverserecovery time of the parasitic diode inherent in the structureof MOSFETs.

Thecurrent fed approach canalso reduce problems causedby dynamic imbalance. If more than three MOSFETs areparallelled then it is advantageous to use more than onechoke in the d.c. link rather than wind a single choke out ofthicker gauge wire. One of the connections to each choke

is connected to the output of the rectification stage. Theother connection of each choke is connected to a group ofthree MOSFETs. This means that if one MOSFET switcheson before the others it will carry a current less than its peakpulse value even when many MOSFETs are parallelled.

The parallel operation of MOSFETs in thelinear mode

The problems of parallelling MOSFETs which are beingused in the linear mode are listed below.

(a) The parallelled devices have different thresholdvoltages and transconductances. This leads to poorsharing.

(b) MOSFETs have a positive temperature coefficient ofgain at low values of gate to source voltage. This can leadto thermal runaway.

The imbalance caused by differences in threshold voltageand transconductance can be reduced by connectingresistors (RS) in the source connections. These resistorsare in the gate drive circuit and so provide negativefeedback. The negative feedback reduces the effect ofdifferent values of VT and gm. The effectivetransconductance gm of the MOSFET is given inEquation 1.

RS must be large compared to 1/gm to reduce the effects ofdifferences in gm. Values of 1/gm typically vary between 0.1and 1.0 Ohm. Therefore values of RS between 1 ohm and10 ohm are recommended.

Differential heating usually has a detrimental effect onsharing and so good thermal coupling is advisable.

Conclusions

Power MOSFETs can successfully be parallelled to realisehigher power handling capability if a few guidelines arefollowed.

gm =1

Rs + 1

gm

1

52


1.2.5 Series Operation of Power MOSFETs

The need for high voltage switches can be well illustratedby considering the following examples. In flybackconverters the leakage inductance of an isolatingtransformer can cause a large voltage spike across theswitch when it switches off. If high voltage MOSFETs areused the snubber components can be reduced in size andin some cases dispensed with altogether.

For industrial equipment operation from a supply of 415 V,550 V or 660 V is required. Rectification of these supplyvoltages produces d.c. rails of approximately 550 V, 700 Vand 800 V. The need for high voltage switches in thesecases is clear.

Resonant topologies are being increasingly used inswitching circuits. These circuits have advantages ofreduced RFI and reduced switching losses. To reduce thesize of magnetic components and capacitors the switchingfrequency ofpower supplies is increased. RFIandswitchinglosses become more important at high frequencies soresonant topologies are more attractive. Resonant circuitshave the disadvantage that the ratio of peak to averagevoltage can be large. For example a Parallel ResonantPower Supply for a microwave oven operating off a 240 Vsupply can be designed most easily using a switch with avoltage rating of over 1000 V.

In high frequency induction heating power suppliescapacitors are used to resonate the heating coil. The useof high voltage switches in the inversion bridge can resultinbetter utilisation of the kVAr capabilityof thesecapacitors.This is advantageous since capacitors rated at tens of kVArabove 100 kHz are very expensive.

In most TV deflection and monitor circuits peak voltages ofup to 1300 V have to be sustained by the switch during theflyback period. This high voltage is necessary to reset thecurrent in the horizontal deflection coil. If the EHT flashesover, the switch will have to sustain a higher voltage so1500 V devices are typically required.

The Philips range of PowerMOS includes devices rated atvoltages up to 1000 V to cater for these requirements.However in circuits, particularly in resonant applicationswhere voltages higher than this are required, it may benecessary to operate devices in series.

Series operation can be attractive for the following reasons:

Firstly, the voltage rating of a PowerMOS transistorcannot be exceeded. A limited amount of energy can beabsorbed by a device specified with a ruggedness rating

(eg device can survive some overvoltage transients), buta 1000 V device cannot block voltages in excess of1000 V.

Secondly, series operation allows flexibility as regardson-resistance and so conduction losses.

The following are problems that have to be overcome forsuccessful operation of MOSFETs in series. If one deviceturns off before another it may be asked to block a voltagegreater than its breakdown voltage. This will cause areduction in the lifetime of the MOSFET. Also there is arequirement for twice as many isolated gate drive circuitsin many circuits.

The low drive power requirements of Philips PowerMOSmean that the provision of more isolated gate drive circuitsis made easier. Resonant circuits can have advantages inreducing the problems encountered if one MOSFET turnsoff before another. The current fed full bridge inverter is onesuch circuit.

To illustrate how devices can be operated in series, acurrent fed full bridge inverter is described where the peakvoltage requirement is greater than 1200 V.

The current fed inverterA circuit diagram of the full bridge current fed inverter isshown in Fig.1. A choke in the d.c. link smooths the linkcurrent. Switching in the inversion bridge causes arectangular wave of current to be passed through the load.The load is a parallel resonant tank circuit. Since the Q ofthe tank circuit is relatively high the voltage across the loadis a sinewave. MOSFETs sustain a half sinusoid of voltagewhen they are off. Thus series operation of MOSFETs ismade easier because if one MOSFET turns off beforeanother it only has to sustain a small voltage. To achievethe best sharing, the gate drive to MOSFETs connected inseries should be as similar as possible. In particular thezerocrossings should be synchronised.The MOSFETdrivecircuit shown in Fig.2 has been found to be excellent in thisrespect. For current fed resonant circuits in which the dutycyclevaries over large ranges the circuit in Fig.3 will performwell. A short pulse applied to the primary of the pulsetransformer is sufficient to turn MOSFET M4 on. This shortpulse can be achieved by designing the pulse transformerso that it saturates during the time that M1 is on. The gatesource capacitance of M4 will remain charged until M2 isturned on. M3 will then be turned on and the gate sourcecapacitance of M4 will be discharged and so

53


Fig.1. Circuit diagram of the full bridge current-fed inverter feeding a parallel resonant load.

LEG 1

LEG 2

LEG 3LEG 4

Drive

Circuit

Crowbar

Circuit

Hall Effect

Current Sense

Semiconductor

Fuse

120 uH

2.2 nF

M4 is turned off. Thus this circuit overcomes problems ofresetting the flux in the core of the pulse transformer forlarge duty cycles.

Each leg of the inverter consists of two MOSFETs, typeBUK456-800B, connected in series. The ideal rating of thetwo switches in each leg is therefore 1600 V and 3.5 A. Theinverter is fed into a parallel resonant circuit with values ofL = 120 µH (Q = 24 at 150 kHz) and C = 2.2 nF.

Fig.2. The MOSFET drive circuit.

Capacitors are shown connected across the drain sourceterminals of MOSFETs. The value of the capacitor acrossthe drain to source of each MOSFET is 6.6 nF. (Six 10 nFpolypropylene capacitors, type 2222 376 92103.) Thisgives a peak voltage rating of about 850 V at 150 kHz forthe capacitor combination across each MOSFET. (Thisvoltage rating takes into account that the capacitors will onlyhave to sustain voltage when the MOSFET is off). Thefunction of these capacitors is twofold. Firstly they suppressspikes caused by switching off current in parasitic leadinductance. Secondly they improve the sharing of voltagebetween the MOSFETs connected in series. Thesecapacitors are effectively in parallel with the tank circuitcapacitor. However only half of the capacitors acrossMOSFETs are in circuit at any one time. This is becausehalf of the capacitors are shorted out by MOSFETs whichhave been turned on. The resonant frequency of the tankcircuit and drain source capacitors is given by Equation 1.

Where Ctot is the equivalent capacitance of the tank circuitcapacitor and the drain source capacitors and is given byEquation 2.

T1

T2

15 V

0 V

0.68 uF

FX3434

30 turns secondary

15 turns primary

33 Ohm

33 Ohm

33 Ohm

f =1

2π√L .Ctot

1

54


Therefore the resonant frequency of the tank circuit is155 kHz.

An expression for the impedance at resonance of theparallel resonant circuit (ZD) is given in Equation 3.

The Q of the circuit is given by Equation 4.

Substituting Equation 3.

Thus ZD for the parallel resonant load was 2.7 kOhms.

In a conventional rectangular switching circuit theconnection of capacitors across MOSFETs will causeadditional losses. These losses are caused because whena MOSFET turns on, the energy stored in the drain sourcecapacitance is dissipated in the MOSFET and in a seriesresistor. This series resistor is necessary to limit the current

spike in the MOSFET at turn on. These losses areappreciable at 150 kHz, e.g. the connection of 1 nF acrossa MOSFET switching 600 V would cause losses of morethan 25 W at 150 kHz. In the current fed inverter describedin this article the MOSFETs turn on when the voltage acrossthe capacitor is ideally zero. Thus there is no need for aseries resistor and the turn on losses are ideally zero.

In this case the supply to the inverter was 470 V rms. Thismeans that the peak voltage in the d.c. link was 650 V.

Equating the power flowing in the d.c. link to the powerdissipated in the tank circuit produces an expression for thepeak voltage across the tank circuit (VT) as given inEquation 6.

Therefore the peak to peak voltage across the tank circuitwas ideally 2050 V

The voltage across each MOSFET should be 512 V.

Circuit performanceThe switching frequency of this circuit is 120 kHz. Thus theload is fed slightly below its resonant frequency. This meansthat the load looks inductive andensures that the MOSFETsdo not switch on when the capacitors connected acrosstheir drain source terminals are charged.

Ctot = Ct + CDS 2

ZD =L

Ctot.R3

Q =1R

.√ LCtot

4

VT = 2× √2×1.11× Vdclink 6

ZD = Q.√ LCtot

5

Fig.3. Drive circuit with good performance over widely varying duty cycles.

15 V

0 V

0.68 uF

33 Ohm

33 Ohm

33 Ohm

M1

M2

M3 M4

55


The waveforms of the voltage across two MOSFETs inseries in a leg of the inversion bridge are shown in Fig.4. Itcan be seen that the sharing is excellent. The peak voltageacross each MOSFET is 600 V. This is higher than 512 Vbecause of ringing between parasitic lead inductance andthe drain source capacitance of MOSFETs when theyswitch off.

The MOSFETs carry two components of current. The firstcomponent is the d.c. link current. The second componentis a fraction of the circulating current of the tank circuit. Thesize of the second component is dependent on the relativesizes of the drain source capacitance connected acrossMOSFETs and the tank circuit capacitor.

In this circuit the peak value of charging current for drainsource capacitors, which is carried by the MOSFET, is 4 A.The on-resistance of the BUK456-800B is about 5 Ohmsat 80 ˚C. This explains the rise in VDS(ON) of about 20 V seenin Fig.4 just above the turn off of the MOSFETs.

The sharing of Philips PowerMOS in this configuration isso good that the value of drain source capacitance is notdetermined by its beneficial effect on sharing. Therefore,the value can be selected solely on the need to controlringing which in turn is dependent on power output andlayout. (The increased current level associated withincreased power output makes the ringing worse).

In any given configuration there is a maximum output powerthat single MOSFETs can handle and there will be a valueof drain source capacitance associated with it. This value

Fig.4. The drain-source voltage waveforms for twoMOSFETs connected in series in a leg of the inversion

bridge.

can be used as the ’capacitance per MOSFET’ in higherpower circuits where it becomes necessary to useMOSFETs connected in parallel. A value of between 5 and10 nF is probably sufficient given a sensible layout.

ConclusionsIt has been shown that MOSFETs can be connected inseries to realise a switch that is as high as 90% of the sumof the voltage sustaining capabilities of the individualtransistors.

0 13 26 39 52 65 78 91 104 117 1300

80

160

240

320

400

480

560

640

Dra

in-S

ourc

e V

olta

ge (

V)

time (us)

56


1.2.6 Logic Level FETS

Standard Power MOSFETs require a gate-source voltageof 10 V to be fully ON. With Logic Level FETs (L2FETs)however, the same level of conduction is possible with agate-source voltage of only 5 V. They can, therefore, bedriven directly from 5 V TTL/CMOS ICs without the needfor the level shifting stages required for standardMOSFETs, see Fig.1. This makes them ideal for today’ssophisticated electrical systems, where microprocessorsare used to drive switching circuits.

Fig.1 Drive circuit for a standard MOSFET and anL2FET

This characteristic of L2FETs is achieved by reducing thegate oxide thickness from - 800 Angstroms to - 500Angstroms, which reduces the threshold voltage of thedevice from the standard 2.1-4.0 V to 1.0-2.0 V. Howeverthe result is a reduction in gate-source voltage ratings,from ±30 V for a standard MOSFET to ±15 V for the L2FET.The ±15 V rating is an improvement over the ’industrystandard’ of ±10 V, and permits Philips L2FETs to be usedin demanding applications such as automotive.

Although a 5 V gate-drive is ideal for L2FETs, they can beused in circuits with gate-drive voltages of up to 10 V. Using

a 10 V gate-drive results in a reduced RDS(ON) (see Fig.2)but the turn-off delay time is increased. This is due toexcessive charging of the L2FET’s input capacitance.

Fig.2 RDS(ON) as a function of VGS for a standardBUK453-100B MOSFET and a BUK553-100B L2FET. Tj

= 25 ˚C; VGS = 10 V

Capacitances, Transconductance andGate Charge

Figure3 shows the parasitic capacitances areas of a typicalPower MOSFET cell. Both the gate-source capacitanceCgs and the gate-drain capacitance Cgd increase due to thereduction in gate oxide thickness, although the increasein Cgd is only significant at low values of VDS, when thedepletion layer is narrow. Increases of the order of 25% ininput capacitance Ciss, output capacitance Coss and reversetransfer capacitance Crss result for the L2FET, comparedwith a similar standard type, at VDS = 0 V. However at thestandard measurement condition of VDS = 25 V thedifferences are virtually negligible.

Forward transconductance gfs is a function of the oxidethickness so the gfs of an L2FET is typically 40% - 50%higher than a standard MOSFET. This increase in gfs morethan offsets the increase in capacitance of an L2FET, sothe turn on charge requirement of the L2FET is lower thanthe standard type see Fig.4. For example, the standardBUK453-100B MOSFET requires about 17 nC to be fullyswitched on (at a gate voltage of 10 V) while theBUK553-100B L2FET only needs about 12 nC (at a gatesource voltage of 5 V).

input

TTL / CMOS

+10 V

VDD

StandardMOSFET

Standard MOSFET drive

input

TTL / CMOS

VDD

L FET drive2

L FET2

+5 V

57


Fig.3 Parasitic capacitances of a typical PowerMOSFET cell

Fig.4 Turn-on gate charge curves of a standardBUK453-100B and a BUK553-100B L2FET. VDD = 20 V;

ID = 12 A

Switching speed.

Figure5 compares the turn-on performance of the standardBUK453-100B MOSFET and the BUK553-100B L2FET,under identical drive conditions of 5 V from a 50 Ωgenerator using identical loads. Thanks to its lower gatethreshold voltage VGST, the L2FET can be seen to turn onin a much shorter time from the low level drive.

Figure 6 shows the turn-off performance of the standardBUK453-100B MOSFET and the BUK553-100B L2FET,again with the same drive. This time the L2FET is slowerto switch. The turn-off times are determined mainly by thetime required for Cgd to discharge. The Cgd is higher for theL2FET at low VDS, and the lower value of VGST leads to alower discharging current. The net result is an increasein turn off time.

Fig.5 Comparison of (a) gate-source voltage and (b)drain-source voltage waveforms during turn-on of a

standard BUK453-100B MOSFET and a BUK553-100BL2FET. VGS is 5 V, ID is 3 A and VDD is 30 V.

Fast switching in many applications, for exampleautomotive circuits, is not important. In areas where it isimportant however the drive conditions should beexamined. For example, for a given drive power, a 10 Vdrive with a 50 Ω source impedance is equivalent to a 5 Vdrive with a source impedance of only 12 Ω. This results infaster switching for the L2FET compared with standardMOSFETs.

Ruggedness and reliabilityMOSFETs are frequently required to be able to withstandthe energy of an unclamped inductive load turn-off. Sincethis energy is dissipated in the bulk of the silicon, stressis avoided in the gate oxide. This means that theruggedness performance of L2FETs is comparable withthat of standard MOSFETs. The use of thinner gate oxidein no way compromises reliability. Good control of keyprocess parameters such as pinhole density, mobile ioncontent, interface state density ensures good oxide quality.The projected MTBF is 2070 years at 90˚C, at a 60%confidence level.

58


Fig.6 Comparison of (a) gate-source voltage and (b)drain-source voltage waveforms during turn-off of a

standard BUK453-100B MOSFET and a BUK553-100BL2FET. VGS is 5 V, ID is 3 A and VDD is 30 V.

The VGS rating of an L2FET is about half that of a standardMOSFET,but thisdoes not affect the VDS rating. In principle,an L2FET version of any standard MOSFET is feasible.

Temperature stabilityIn general threshold voltage decreases with increasingtemperature. Although the threshold voltage of L2FETs islower than that of standard MOSFETs, so is theirtemperature coefficient of threshold voltage (about half infact), so their temperature stability compares favourablywith standard MOSFETs. Philips low voltage L2FETs(≤200v) in TO220 all feature Tjmax of 175˚C, rather thanthe industry standard of 150˚C.

ApplicationsThe Philips Components range of rugged Logic LevelMOSFETs enable cost effective drive circuit designwithout compromising ruggedness or reliability. Since theyenable power loads to be driven directly from ICs they maybe considered to be the first step towards intelligent powerswitching. Thanks to their good reliability and 175˚C Tjmax

temperature rating, they are displacing mechanical relaysin automotive body electrical functions and are beingdesigned in to such safety critical areas as ABS.

59


1.2.7 Avalanche Ruggedness

Recent advances in power MOS processing technologynow enables power MOS transistors to dissipate energywhile operating in the avalanche mode. This feature resultsin transistors able to survive in-circuit momentaryovervoltage conditions, presenting circuit designers withincreased flexibility when choosing device voltage gradeagainst required safety margins.

This paper considers the avalanche characteristics of’rugged’ power MOSFETs and presents results frominvestigations into the physical constraints which ultimatelylimit avalanche energy dissipation in the VDMOS structure.Results suggest that the maximum sustainable energy is afunction of the applied power density waveform,independent of device voltage grade and chip size.

The ability of a rugged device to operate reliably in a circuitsubject to extreme interference is also demonstrated.

Introduction.Susceptibility to secondary breakdown is a phenomenonwhich limits the power handling capability of a bipolartransistor to below its full potential. For a power MOSFET,power handling capability is a simple function of thermalresistance and operating temperature since the device isnot vulnerable to a second breakdown mechanism. Theprevious statement holds true provided the device isoperated at or below its breakdown voltage rating (BVDSS)and not subject to overvoltage. Should the transistor beforced into avalanche by a voltage surge the structure ofthe device permits possible activation of a parasitic bipolartransistor which may then suffer the consequences ofsecond breakdown. In the past this mechanism was typicalof failure in circuits where the device became exposed toovervoltage. To reduce the risk of device failure duringmomentaryoverloads improvements have been introducedto the Power MOS design which enable it to dissipateenergy while operating in the avalanche condition. The termcommonly used to describe this ability is ’Ruggedness’,however before discussing in further detail the merits of arugged Power MOSFET it is worth considering the failuremechanism of non-rugged devices.

Failure mechanism of a non-rugged PowerMOS.A power MOS transistor is made up of many thousands ofcells, identical in structure. The cross section of a typicalcell is shown in Fig. 1. When in the off-state or operating insaturation, voltage is supported across the p-n junction asshown by the shaded region. If the device is subjected toover-voltage (greater than the avalanche value of the

device), the peak electric field, located at the p-n junction,rises to the critical value (approx. 200 kV / cm ) at whichavalanche multiplication commences.

Computer modelling has shown that the maximum electricfield occurs at the corners of the P diffusions. Theelectron-hole plasma generated by the avalanche processin these regions gives rise to a source of electrons, whichare swept across the drain, and a source of holes, whichflow through the P- and P regions towards the source metalcontact.

Fig. 1 Cross section of a typical Power MOS cell.

Clearly the P- region constitutes a resistance which will giverise to a potential drop beneath the n+. If this resistance istoo large the p-n junction may become forward biased forrelatively low avalanche currents.

Also if the manufacturing process does not yield a uniformcell structure across the device or if defects are present inthe silicon then multiplication may be a local event withinthe crystal. This would give rise to a high avalanche currentdensity flowing beneath the source n+ and cause arelatively large potential drop sufficient to forward bias thep-n junction and hence activate the parasitic npn bipolartransistor inherent in the MOSFET structure. Due to thepositive temperature coefficient associated with a forwardbiased p-n junction, current crowding will rapidly ensue withthe likely result of second breakdown and eventual devicedestruction.

N+ Substrate

N- Layer

P

P-P-

N+ N+

Source Contact Metal

Polysilicon Gate

Drain

SourceParasitic

Bipolar

Transistor

61


In order that a power MOS transistor may survive transitoryexcursions into avalanche it is necessary to manufacture adevice with uniform cell structure, free from defectsthroughout the crystal and that within the cell the resistancebeneath the n+ should be kept to a minimum. In this way aforward biasing potential across the p-n junction is avoided.

Definition of ruggedness.The term ’Ruggedness’ when applied to a power MOStransistor, describes the ability of that device to dissipateenergy while operating in the avalanche condition. To testruggedness of a device it is usual to use the method ofunclamped inductive load turn-off using the circuit drawn inFig. 2.

Fig. 2 Unclamped inductive load test circuit forruggedness evaluation.

Fig. 3 Typical waveforms taken from the unclampedinductive load test circuit.

Circuit operation:-

A pulse is applied to the gate such that the transistor turnson and load current ramps up according to the inductorvalue, L and drain supply voltage, VDD. At the end of thegate pulse, channel current in the power MOS begins to fallwhile voltage on the drain terminal rises rapidly inaccordance with equation 1.

The voltage on the drain terminal is clamped by theavalanche voltage of the Power MOS for a duration equalto that necessary for dissipation of all energy stored in theinductor. Typical waveforms showing drain voltage andsource current for a device undergoing successful test areshown in Fig. 3.

The energy stored in the inductor is given by equation 2where ID is the peak load current at the point of turn-off ofthe transistor.

All this energy is dissipated by the Power MOS while thedevice is in avalanche.

Provided the supply rail is kept below 50 % of the avalanchevoltage, equation 2 approximates closely to the total energydissipation by the device during turn-off. However a moreexact expression which takes account of additional energydelivered from the power supply is given by equation 3.

Clearly the energy dissipated is a function of both theinductor value and the load current ID, the latter being setby the duration of the gate pulse. The 50 Ohm resistorbetween gate and source is necessary to ensure a fastturn-off such that the device is forced into avalanche.

The performance of a non-rugged device in response to theavalanche test is shown in Fig. 4. The drain voltage risesto the avalanche value followed by an immediate collapseto approximately 30 V. This voltage is typical of thesustaining voltage during Second Breakdown of a bipolartransistor, [1]. The subsequent collapse to zero volts after12 µS signifies failure of the device. The transistor shownhere was only able to dissipate a few micro joules at a verylow current if a failure of this type was to be avoided.

dvdt

= Ld2I

dt2(1)

L

T.U.T.

VDD

RGSR 01

VDS

-ID/100

+

-

shunt

VGS

0 WDSS= 0.5LID2 (2)

WDSS=BVDSS

BVDSS− VDD

0.5LID2 (3)

62


Fig. 4 Failure waveforms of a non rugged Power MOStransistor.

Fig. 5 Power and energy waveforms prior to failure for atypical BUK627-500B

Characteristics of a rugged Power MOS.

i) The energy limitation of a rugged deviceThe power waveform for a BUK627-500B (500 V, 0.8 Ohm)tested at a peak current of 15 A is presented in Fig. 5.

The area within the triangle represents the maximumenergy that this particular device type may sustain withoutfailure at the above current. Figure 6 shows the junctiontemperature variation in response to the power pulse,calculated from the convolution integral as shown inequation 4.

where transient thermal impedance.

Fig. 6 Junction temperature during the power pulse forthe avalanche ruggedness test on a Philips

BUK627-500B.

Equation 4 predicts that the junction temperature will passthrough a maximum of 325 ˚C during the test. Thecalculation of Zth(t) assumes that the power dissipation isuniform across the active area of the device. When thedevice operates in the avalanche mode the power will bedissipated more locally in the region of the p-n junctionwhere the multiplication takes place. Consequently a localtemperature above that predicted by equation 4 is likely tobe present within the device.

Work on bipolar transistors [2] has shown that at atemperature of the order of 400 ˚C, the voltage supportingp-n region becomes effectively intrinsic as a result ofthermal multiplication, resulting in a rapid collapse in theterminal voltage. It is probable that a similar mechanism isresponsible for failure of the Power MOS with a localtemperature approaching 400 ˚C resulting in a device shortcircuit. A subsequent rapid rise in internal temperature willresult in eventual device destruction.

Clearly the rise in Tj is a function of the applied powerwaveform which is in turn related to circuit current,avalanche voltage of the device and duration of the energypulse.Thus the energy required to bringabout device failurewill vary as a function of each of these parameters. Theruggedness of Power MOSFETS of varying crystal size andvoltage specification together with dependence on circuitcurrent is considered below.

ii) Sustainable avalanche energy as afunction of current.The typical avalanche energy required to cause devicefailure is plotted as a function of peak current in Fig. 7 fora BUK553-60A (60 V, 0.085 Ohm Logic Level device). Thisresult was obtained through destructive device testingusing the circuit of Fig. 2 and a variety of inductor values.

Tj(t) = ⌠⌡τ = 0

τ = t

P(t − τ)Zth(τ)dτ (4)

Zth(τ) =

63


Fig. 7 Avalanche energy against current for a typicalPhilips BUK553-60A

Fig. 8(a) Temperature during avalanche test for aBUK553-60A; ID = 10 A

Fig. 8(b) Temperature during avalanche test for aBUK553-60A; ID = 22 A

Theplot shows that the effectof reducing current is to permitgreater energy dissipation during avalanche prior to failure.This is an expected result since lower currents result inreduced power dissipation enabling avalanche to besustained over a longer period. Temperature plots (Fig. 8)calculated for the 10 A and 22 A failure points confirm thatthe maximum junction temperature reached in each caseis the same despite the different energy values. (N.B. Thecritical temperature is again underestimated as previouslystated.)

iii) Effect of crystal size.To enable a fair comparison of ruggedness betweendevices of various chip size it is necessary to normalise theresults. Therefore instead of plotting avalanche energyagainst current, avalanche energy density and currentdensitybecome more appropriate axes. Figure 9 shows theavalanche energy density against current density failurelocus for two 100 V Philips Power MOS types which aredifferent only in silicon area. Also shown on this plot aretwo competitor devices of different chip areas (BVDSS = 100V). This result demonstrates two points:a) the rise in Tj to the critical value for failure is dependenton the power density dissipated within the device as afunction of time,b) the sustainable avalanche energy scales proportional tochip size.

KEY: x Philips BUK553-100A (6.25 mm2 chip)+ Philips BUK555-100A (13 mm2 chip)

Competitor Devices (100 V)Fig. 9 Avalanche energy density against current density

iv) Dependence on the drain sourcebreakdown voltage rating.Energy density against current density failure loci areshown for devices of several different breakdown voltagesin Fig. 10.

64


KEY: x Philips BUK553-60A+ Philips BUK555-100A

Philips BUK627-500BFig. 10 Avalanche energy density against current

density

Presented in this form it is difficult to assess the relativeruggedness of each device since the current density isreduced for increasing voltage. If instead of peak currentdensity, peak power density is used for the x-axis thencomparison is made very simple. The data of Fig. 10 hasbeen replotted in Fig. 11 in the above manner. Representedin this fashion the ruggedness of each chip appears verysimilar highlighting that the maximum energy dissipation ofa device while in avalanche is dependent only on the powerdensity function.

KEY: x Philips BUK553-60A+ Philips BUK555-100A

Philips BUK627-500BFig. 11 Avalanche energy density against peak power

density

Ruggedness ratings.

It should be stressed that the avalanche energiespresentedin the previous section result in a rise of the junctiontemperature far in excessof the device rating and in practiceenergies should be kept within the specification.Ruggedness is specified in data for each device in termsof an unclamped inductive load test maximum condition;recommended energy dissipation at a particular current(usually the rated current of the device).

DEVICE RDSON VDS ID WDSS

TYPE (Ω) (V) (A) (mJ)

BUK552-60A 0.15 60 14 30

BUK552-100A 0.28 100 10 30

BUK553-60A 0.085 60 20 45

BUK553-100A 0.18 100 13 70

Table 1 Ruggedness Ratings

The ruggedness rating is chosen to protect against a risein Tj above the maximum rating. Examples of ruggednessratings for asmall selection ofdevices are shown in Table 1.

Fig. 12 Normalised temperature derating curve

This data is applicable for Tj = 25 C. For higher operatingtemperatures the permissible rise in junction temperatureduring the energy test is reduced. Consequentlyruggedness needs to be derated with increasing operatingtemperature. A normalised derating curve for devices withTj max 175 ˚C is presented in Fig. 12.

20 40 60 80 100 120 140 160 180Tmb / C

120

110

100

90

80

70

60

50

40

30

20

10

0

WDSS%

65


Fig. 13(a) Test circuit

Fig. 13(b) Output from transient generator.

Performance of a rugged Power MOSdevice.The ability of a rugged Power MOS transistor to survivemomentary power surges results in excellent devicereliability. The response of a BUK553-60A to interferencespikes while switching a load is presented below. The test

circuit is shown in Fig. 13(a) together with the profile of theinterference spike in Fig. 13(b).

The interference generator produces pulses asynchronousto the switching frequency of the Power MOS. Figure 14shows the drain voltage and load current response at fourinstances in the switching cycle. Devices were subjectedto 5000 interference spikes at a frequency of 5 Hz. Nodegradation in device performance was recorded.

Conclusions.The ability of power MOS devices to dissipate energy in theavalanche mode has been made possible by processoptimisation to remove the possibility of turn-on of theparasitic bipolar structure. The failure mechanism of arugged device is one of excessive junction temperatureinitiating a collapse in the terminal voltage as the junctionarea becomes intrinsic. The rise in junction temperature isdictated by the power density dissipation which is a functionof crystal size, breakdown voltage and circuit current.

Ruggedness ratings for Philips PowerMOS are chosen toensure that the specified maximum junction temperature ofthe device is not exceeded.

References.1. DUNN and NUTTALL, An investigation of the voltage

sustained by epitaxial bipolar transistors in currentmode second breakdown. Int.J.Electronics, 1978,vol.45, no.4, 353-372

2. DOW and NUTTALL, A study of the current distributionestablished in npn epitaxial transistors during currentmode second breakdown. Int.J.Electronics, 1981,vol.50, no.2, 93-108

T.U.T.

50 R

VDS

7.5 V

014 V DC

SOURCE

TRANSIENT

GENERATOR

14 V38 WLAMP

20 R

100 Hz - 1 kHz

50 % DUTY CYCLE

SQUARE WAVE

t1 = point of turn-on of PowerMOSt2 = point of turn-off of PowerMOS

Fig. 14 VDS and ID waveforms for the circuit in Fig. 13(a)

66


1.2.8 Electrostatic Discharge (ESD) Considerations

Charge accumulates on insulating bodies and voltages ashighas 20,000 Vcan be developedby, forexample, walkingacross a nylon carpet. Electrically the insulator can berepresented by many capacitors and resistors connectedas shown in Fig. 1. The value of the resistors is large andas a consequence it is not possible to dischargean insulatorby connecting it straight to ground. An ion source isnecessary to discharge an insulator.

Fig. 1. An electrical representation of a chargedinsulator.

Since MOSFETs have a very high input impedance,typically > 109 Ohms at dc, there is a danger of staticelectricity building up on the gate source capacitance of theMOSFET. This can lead to damage of the thin gate oxide.There are two ways in which the voltage across the gatesource terminals of a MOSFET can be increased to itsbreakdown voltage by static electricity.

Firstly a charged object can be brought into contact withthe MOSFET terminals or with tracks electrically connectedto the terminals. This is represented electrically by Fig. 2.Secondly charge can be induced onto the terminals of theMOSFET. Electrically this can be represented by the circuitin Fig. 3.

Fig. 2. The gate source terminals of a MOSFETconnected to a charged insulator.

From Figs. 2 and 3, it can be seen that, as the total area ofthe gate source region increases then the sensitivity of thedevices to ESD will decrease. Hence power MOSFETsare less prone to ESD than CMOS ICs. Also, for a given

voltage rating, MOSFETs with a larger die area (i.e. thedevices with lower on-resistance) are less probe to ESDthan smaller dice.

To prevent the destruction of MOSFETs through ESD a twopronged approach is necessary. Firstly it is important tominimise the build up of static electricity. Secondlymeasures need to be taken to prevent the charging up ofthe input capacitance of MOSFETs by static electriccharges.

Fig. 3. A charged insulator inducing charge on theterminals of a MOSFET.

In the Philips manufacturing facilities many precautions aretaken to prevent ESD damage and these are summarisedbelow.

Precautions taken to prevent the build upof static electricity1. It is important to ensure that personnel working withMOSFETs are aware of the problems and procedures thathave to be followed. This involves the training of staff.Areas in which MOSFETs are handled are designatedSpecial Handling Areas (SHA) and are clearly marked assuch. Checks are made every month that anti-static rulesare being rigourously implemented.

2. Some materials are more prone to the build up of staticelectricity than others (e.g. polyester is worse than cotton).Therefore it is important to minimise the use of materialsthat enhance the likelihood of build up of static electricity.Materials best avoided are acetate, rayon and polyester.The wearing of overclothing made from polycotton with 1%stainless steel fibre is one solution. In clean rooms nylonoveralls which have been antistatically treated are worn.The use of insulating materials is avoided.

3. Work benches and floors are covered in a staticdissipative material and connected to a common earth. Ahigh conductive material is not used since it would createan electric shock hazard and cause too rapid a dischargeof charged material. From the point of view of ESDmaterials can be classified according to their conductivityas shown below.

Insulator

++

+

- - -

C11 C12 C13 C1n

R11 R12 R(1n-1)

C11 C12

R11 R12

C1n CgsVgs

Ct

C11 C12

R11 R12

C1n CgsVgs

67


insulator (>1014 ohm/square)

antistatic (109 - 1014 Ohm/square)

static dissipative (105 - 109 Ohm/square)

conductor (<105 Ohm/square).

4. Conducting straps are used to electrically connectpersonnel to the point of common earthing. This preventsthe build up of static charge on staff. The connection isstatic dissipative to prevent an electric shock hazard.

5. Air plays an important part in the build up of staticelectricity.

This is particularly troublesome in a dry atmosphere.

Many of the techniques mentioned above are referred to inBS5783.

Precautions taken to prevent damage toMOSFETs by electrostatic build up ofcharge1. When MOSFETs are being transported or stored they

should be in antistatic containers. These containers shouldbe totally enclosed to prevent charges being induced ontothe terminals of devices.

2. If MOSFETs have to be left out on the bench, e.g. duringa test sequence, they should be in sockets which have thegate and source pins electrically connected together.

The precautions that should be taken at the customers’premises are the sameas above. It should be rememberedthat whenever a MOSFET is touched by someone there isa danger of damage. The precautions should be taken inevery area in which MOSFETs are tested or handled. Inaddition where devices are soldered into circuits with asoldering iron an earthed bit should always be used.

The probability of device destruction caused by ESD is loweven if only the most rudimentary precautions are taken.However without such precautions and with large numbersof PowerMOS devices now being designed into equipmenta few failures would be inevitable. The adoption of theprecautions outlined will mean that ESD will no longer bea problem.

68


1.2.9 Understanding the Data Sheet: PowerMOS

All manufacturers of power MOSFETs provide a data sheetfor every type produced. The purpose of the data sheet isprimarily to give an indication as to the capabilities of aparticular product. It is also useful for the purpose ofselecting device equivalents between differentmanufacturers. In some cases however data on a numberof parameters may be quoted under subtly differentconditions by different manufacturers, particularly onsecond order parameters such as switching times. Inaddition the information contained within the data sheetdoes not always appear relevant for the application. Usingdata sheets and selecting device equivalents thereforerequires caution and an understanding of exactly what thedata means and how it can be interpreted. Throughout thischapter the BUK553-100A is used as an example, thisdevice is a 100 V logic level MOSFET.

Information contained in the Philips datasheet

The data sheet is divided into 8 sections as follows:

* Quick reference data

* Limiting values

* Thermal resistances

* Static characteristics

* Dynamic characteristics

* Reverse diode limiting values and characteristics

* Avalanche limiting value

* Graphical data

The information contained within each of these sections isnow described.

Quick reference data

This data is presented for the purpose of quick selection. Itlists what is considered to be the key parameters of thedevice such that a designer can decide at a glance whetherthe device is likely to be the correct one for the applicationor not. Five parameters are listed, the two most importantare the drain-source voltage VDS and drain-source on-stateresistance, RDS(ON). VDS is the maximum voltage the devicewill support between drain and source terminals in theoff-state. RDS(ON) is the maximum on-state resistance at thequoted gate voltage, VGS, and a junction temperature of25 ˚C. (NB RDS(ON) is temperature dependent, see staticcharacteristics). It is these two parameters which providea first order indication of the devices capability.

A drain current value (ID) and a figure for total powerdissipation are also given in this section. These figuresshould be treated with caution since they are quoted forconditions that are rarely attainable in real applications.(See limiting values.) For most applications the usable dccurrent will be less than the quoted figure in the quickreference data. Typical power dissipations that can betolerated by the majority of designers are less than 20 W(for discrete devices), depending on the heatsinkingarrangement used. The junction temperature (TJ) is usuallygiven as either 150 ˚C or 175 ˚C. It is not recommendedthat the internal device temperature be allowed to exceedthis figure.

Limiting valuesThis table lists the absolute maximum values of sixparameters. The device may be operated right up to thesemaximum levels however they must not be exceeded, todo so may incur damage to the device.

Drain-source voltageand drain-gate voltage have the samevalue. The figure given is the maximum voltage that maybe applied between the respective terminals. Gate-sourcevoltage, ±VGS, gives the maximum value that may beallowed between the gate and source terminals. To exceedthis voltage, even for the shortest period can causepermanent damage to the gate oxide. Two values for thedc drain current, ID, are quoted, one at a mounting basetemperature of 25 ˚C and one at a mounting basetemperature of 100 ˚C. Again these currents do notrepresent attainable operating levels. These currents arethe values that will cause the junction temperature to reachits maximum value when the mounting base is held at thequoted value. The maximum current rating is therefore afunction of the mounting base temperature and the quotedfigures are just two points on the derating curve ,see Fig.1.

The third current level quoted is the pulse peak value, IDM.PowerMOS devices generally speaking have a very highpeak current handling capability. It is the internal bond wireswhich connect to the chip that provide the final limitation.The pulse width for which IDM can be applied depends uponthe thermal considerations (see section on calculatingcurrents.) The total power dissipation, Ptot, and maximumjunction temperature are also stated as for the quickreference data. The Ptot figure is calculated from the simplequotient given in equation 1 (see section on safe operatingarea). It is quoted for the conditionwhere the mounting basetemperature is maintained at 25 ˚C. As an example, for theBUK553-100A the Ptot figure is 75 W, dissipating thisamount of power while maintaining the mounting base at25 ˚C would be a challenge! For higher mounting basetemperatures the total power that can be dissipated is less.

69


Fig.1 Normalised continuous drain current.ID% = 100 . ID/ID25 ˚C = f(Tmb); conditions: VGS ≥ 5 V

Obviously if the mounting base temperature was madeequal to the max permitted junction temperature, then nopower could be dissipated internally. A derating curve isgiven as part of the graphical data, an example is shown inFig.2 for a device with a limiting Tj of 175 ˚C.

Fig.2 Normalised power dissipation.PD% = 100 PD/PD 25 ˚C = f(Tmb)

Storage temperature limits are also quoted, usuallybetween -40 /-55 ˚C and +150 /+175 ˚C. Both the storagetemperature limits and the junction temperature limit arefigures at which extensive reliability work is performed byour Quality department. To exceed these figures will causea reduction in long-term reliability.

Thermal resistance.For non-isolated packages two thermal resistance valuesare given. The value from junction to mounting base (Rthj-mb)indicates how much the junction temperature will be raisedabove the temperature of the mounting base whendissipating a given power. Eg a BUK553-100A has a Rthj-mb

of 2 K/W, dissipating 10 W, the junction temperature will be20 ˚C above the temperature of its mounting base. Theother figure quoted is from junction to ambient. This is amuch larger figure and indicates how the junctiontemperature will rise if the device is NOT mounted on aheatsink but operated in free air. Eg for a BUK553-100A,Rthj-a = 60 K/W, dissipating 1 W while mounted in free airwill produce a junction temperature 60 ˚C above theambient air temperature.

For isolated packages, (F-packs) the mounting base (themetal plate upon which the silicon chip is mounted) is fullyencapsulated in plastic. Therefore it is not possible to givea thermal resistance figure junction to mounting base.Instead a figure is quoted from junction to heatsink, Rthj-hs,which assumes the use of heatsink compound. Care shouldbe taken when comparing thermal resistances of isolatedand non-isolated types. Consider the following example:

The non-isolated BUK553-100A has a Rthj-mb of 2 K/W. Theisolated BUK543-100A has a Rthj-hs of 5 K/W. These deviceshave identical crystals but mounted in different packages.At first glance the non-isolated type might be expected tooffer much higher power (and hence current) handlingcapability. However for the BUK553-100A the thermalresistance junction to heatsink has to be calculated, thisinvolves adding the extra thermal resistance betweenmounting base and heatsink. For most applications someisolation is used, such as a mica washer. The thermalresistance mounting base to heatsink is then of the order2 K/W. The total thermal resistance junction to heatsink istherefore

Rthj-hs (non isolated type) = Rthj-mb + Rthmb-hs = 4 K/W

It can be seen that the real performance difference betweenthe isolated and non isolated types will not be significant.

Static CharacteristicsThe parameters in this section characterise breakdownvoltage, threshold voltage, leakage currents andon-resistance.

A drain-source breakdown voltage is specified as greaterthan the limiting value of drain-source voltage. It can bemeasured on a curve tracer, with gate terminal shorted tothe source terminal, it is the voltage at which a drain currentof 250 µA is observed. Gate threshold voltage, VGS(TO),indicates the voltage required on the gate (with respect tothe source) to bring the device into its conducting state. Forlogic level devices this is usually between 1.0 and 2.0 Vand for standard devices between 2.1 and 4 V.

0 20 40 60 80 100 120 140 160 180Tmb / C

ID% Normalised Current Derating120

110

100

90

80

70

60

50

40

30

20

10

0

0 20 40 60 80 100 120 140 160 180Tmb / C

PD% Normalised Power Derating120

110

100

90

80

70

60

50

40

30

20

10

0

70


Fig.3 Typical transfer characteristics.ID = f(VGS); conditions: VDS = 25 V; parameter Tj

Useful plots in the graphical data are the typical transfercharacteristics (Fig.3) showing drain current as a functionof VGS and the gate threshold voltage variation with junctiontemperature (Fig.4). An additional plot also provided is thesub-threshold conduction, showing how the drain currentvaries with gate-source voltage below the threshold level(Fig.5).

Off-state leakage currents are specified for both thedrain-source and gate-source under their respectivemaximum voltage conditions. Note, although gate-sourceleakage current is specified in nano-amps, values aretypically of the order of a few pico-amps.

Fig.4 Gate threshold voltage.VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS

Fig.5 Sub-threshold drain current.ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS

Fig.6 Typical output characteristics, Tj = 25 ˚C.ID = f(VDS); parameter VGS

The drain-source on-resistance is very important. It isspecifiedat a gate-source voltage of 5 V for logic level FETsand 10 V for a standard device. The on-resistance for astandard MOSFET cannot be reduced significantly byincreasing the gate source voltage above 10 V. Reducingthe gate voltage will however increase the on-resistance.For the logic level FET, the on-resistance is given for a gatevoltage of 5 V, a further reduction is possible however atgate voltages up to 10 V, this is demonstrated by the outputcharacteristics, Fig.6 and on-resistance characteristics,Fig.7 for a BUK553-100A. .

0 2 4 6 8

BUK543-100A

VGS / V

15

10

5

0

ID / A

Tj / C = 25 150

0 0.4 0.8 1.2 1.6 2 2.4VGS / V

ID / A1E-01

1E-02

1E-03

1E-04

1E-05

1E-06

SUB-THRESHOLD CONDUCTION

2 % typ 98 %

0 2 4 6 8 10

BUK553-100A

VDS / V

24

20

16

12

8

4

0 2

3

4

57

10ID / A

VGS / V =

-60 -20 20 60 100 140 180Tj / C

VGS(TO) / V

2

1

0

max.

typ.

min.

71


The on-resistance is a temperature sensitive parameter,between 25 ˚C and 150 ˚C it approximately doubles invalue. A plot of normalised RDS(ON) versus temperature(Fig.8) is included in each data sheet. Since the MOSFETwill normally operate at a Tj higher than 25 ˚C, when makingestimates of power dissipation in the MOSFET, it isimportant to take into account the higher RDS(ON).

Fig.7 Typical on-state resistance, Tj = 25 ˚C.RDS(ON) = f(ID); parameter VGS

Fig.8 Normalised drain-source on-state resistance.a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 6.5 A; VGS = 5 V

Dynamic Characteristics

These include transconductance, capacitance andswitching times. Forward transconductance, gfs, isessentially the gain parameter which indicates the changein drain current that will result from a fluctuation in gatevoltage when the device is saturated. (NB saturation of a

MOSFET refers to the flat portion of the outputcharacteristics.) Fig.9 shows how gfs varies as a function ofthe drain current for a BUK553-100A.

Fig.9 Typical transconductance, Tj = 25 ˚C.gfs = f(ID); conditions: VDS = 25 V

Fig.10 Typical capacitances, Ciss, Coss, Crss.C = f(VDS); conditions: VGS = 0 V; f = 1 MHz

Capacitances are specified by most manufacturers, usuallyin terms of input, output and feedback capacitance. Thevalues quoted are for a drain-source voltage of 25 V.However this is only part of the story as the MOSFETcapacitances are strongly voltage dependent, increasingasdrain-source voltage is reduced. Fig.10showshow thesecapacitances vary with voltage. The usefulness of thecapacitance figures is limited. The input capacitance valuegives only a rough indication of the charging required bythe drive circuit. Perhaps more useful is the gate chargeinformation an example of which is shown in Fig.11. Thisplot shows how much charge has to be input to the gate to

0 2 4 6 8 10 12 14 16 18 20

BUK543-100A

ID / A

gfs / S10

9

8

7

6

5

4

3

2

1

0

0 4 8 12 16 20 24 28

BUK553-100A

ID / A

0.5

0.4

0.3

0.2

0.1

0

2.5 3 3.5 44.5

5

10

RDS(ON) / Ohm

VGS / V =

0 20 40VDS / V

C / pF

Ciss

Coss

Crss

10

100

1000

10000BUK5y3-100

-60 -20 20 60 100 140 180Tj / C

Normalised RDS(ON) = f(Tj)2.4

2.2

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

a

72


reach a particular gate-source voltage. Eg. to charge aBUK553-100A to VGS = 5 V, starting from a drain-sourcevoltage of 80 V, requires 12.4 nc. The speed at which thischarge is to be applied will give the gate circuit currentrequirements. More information on MOSFET capacitanceis given in chapter 1.2.2.

Resistive load switching times are also quoted by mostmanufacturers, however extreme care should be takenwhen making comparisons between differentmanufacturers data. The speed at which a power MOSFETcan be switched is essentially limited only by circuit andpackage inductances. The actual speed in a circuit isdetermined by how fast the internal capacitances of theMOSFET are charged and discharged by the drive circuit.The switching times are therefore extremely dependent onthe circuit conditions employed; a low gate drive resistancewill provide for faster switching and vice-versa. The Philipsdata sheet presents the switching times for all PowerMOSwith a resistor between gate and source of 50 Ω. The deviceis switched from apulse generator with a source impedancealso of 50 Ω. The overall impedance of the gate drive circuitis therefore 25 Ω.

Fig.11 Typical turn-on gate-charge characteristics.VGS = f(QG); conditions: ID = 13 A; parameter VDS

Also presented under dynamic characteristics are thetypical inductances of the package. These inductancesbecome important when very high switching speeds areemployed such that large dI/dt values exist in the circuit.Eg. turning-on 30 A within 60 ns gives a dI/dt of 0.5 A/ns.The typical inductance of the source lead is 7.5 nH, fromV = -L*dI/dt the potential drop from the source bond pad(point where the source bond wire connects to the chipinternally) to the bottom of the source lead would be 3.75 V.Normallya standarddevice will be driven with agate-sourcevoltage of 10 V applied across the gate and sourceterminals, the actual voltage gate to source on the

semiconductor however would only be 6.25 V during theturn-on period! The switching speed is therefore ultimatelylimited by package inductance.

Reverse diode limiting values andcharacteristicsThe reverse diode is inherent in the vertical structure of thepower MOSFET. In some circuits this diode is required toperformauseful function. For this reasonthe characteristicsof the diode are specified. The forward currents permissiblein the diode are specified as ’continuous reverse draincurrent’ and ’pulsed reverse drain current’. The forwardvoltage drop of the diode is also provided together with aplot of the diode characteristic, Fig.12. The switchingcapability of the diode is given in terms of the reverserecovery parameters, trr and Qrr.

Fig.12 Typical reverse diode current.IF = f(VSDS); conditions: VGS = ) V; parameter Tj

Because the diode operates as a bipolar device it is subjectto charge storage effects. This charge must be removed forthe diode to turn-off. The amount of charge stored is givenby Qrr, the reverse recovery charge, the time taken to extractthe charge is given by trr, the reverse recovery time. NB. trrdepends very much on the -dIf/dt in the circuit, trr is specifiedin data at 100 A/µs.

Avalanche limiting valueThis parameter is an indication as to the ruggedness of theproduct in terms of its ability to handle a transientovervoltage, ie the voltage exceeds the drain-sourcevoltage limiting value and causes the device to operate inan avalanche condition. The ruggedness is specified interms of a drain-source non-repetitive unclamped inductiveturn-off energy at a mounting base temperature of 25 ˚C.This energy level must be derated at higher mounting basetemperatures as shown in Fig.13. NB. this rating is

0 1 2

BUK553-100A

VSDS / V

30

20

10

0

IF / A

Tj / C = 150 25

0 2 4 6 8 10 12 14 16 18 20QG / nC

VGS / V12

10

8

6

4

2

0

VDS / V =20

80

BUK553-100

73


non-repetitive which means the circuit should not bedesigned to force the PowerMOS repeatedly intoavalanche. This rating is only to permit the device to surviveif exceptional circuit conditions arise such that a transientovervoltage occurs.

The new generation of Philips Medium Voltage MOSFETsalso feature a repetitive ruggedness rating. This rating isspecified in terms of a drain-source repetitive unclampedinductive turn-off energy at a mounting base temperatureof25 ˚C, and indicates that the devices are able to withstandrepeated momentary excursions into avalanchebreakdown provided the maximum junction temperature isnot exceeded. (A more detailed explanation of Ruggednessis given in chapter 1.2.7.)

Fig.13. Normalised avalanche energy rating.WDSS% = f(Tmb); conditions: ID = 13 A

Safe Operating AreaA plot of the safe operating area is presented for everyPowerMOS type. Unlike bipolar transistors a PowerMOSexhibits no second breakdown mechanism. The safeoperating area is therefore simply defined from the powerdissipation that will cause the junction temperature to reachthe maximum permitted value.

Fig.14 shows the SOA for a BUK553-100. The area isbounded by the limiting drain source voltage, limitingcurrent values and a set of constant power curves forvarious pulse durations. The plots in data are all for amounting base temperature of 25 ˚C. The constant powercurves therefore represent the power that raises thejunction temperature by an amount Tjmax - Tmb, ie. 150 ˚Cfor a device with a limiting Tj of 175 ˚C and 125 ˚C for adevice with a limiting Tj of 150 ˚C. . Clearly in mostapplications the mounting base temperature will be higherthan 25 ˚C, the SOA would therefore need to be reduced.The maximum power curves are calculated very simply.

Fig.14 Safe operating area. Tmb = 25 ˚CID & IDM = f(VDS); IDM single pulse; parameter tp

The dc curve is based upon the thermal resistance junctiontomounting base (junction to heatsink in the caseof isolatedpackages), which is substituted into equation 1. The curvesforpulsed operation assumea single shot pulseand insteadof thermal resistance, a value for transient thermalimpedance is used. Transient thermal impedance issupplied as graphical data for each type, an example isshown in Fig.15. For calculation of the single shot powerdissipation capability, a value at the required pulse width isread from the D = 0 curve and substituted in to equation 2.(A more detailed explanation of transient thermalimpedance and how to use the curves can be found inchapter 7.)

Examples of how to calculate the maximum powerdissipation for a 1 ms pulse are shown below. Example 1calculates the maximum power assuming a Tj of 175 ˚C andTmb of 25 ˚C. This power equates to the 1 ms curve on theSOA plot of Fig.14. Example 2 illustrates how the powercapability is reduced if Tmb is greater than 25 ˚C.

Example 1: 1 ms pulse at 25 ˚C for a BUK553-100A

Zth = 0.32 K/W, Tjmax = 175 ˚C, Tmb = 25 ˚C

1 100VDS / V

ID / A100

10

1

0.1

10 us

100 us

1 ms

10 ms

RDS(ON) =

VDS/ID

100 ms DC

tp =

BUK553-100

10

B

A

20 40 60 80 100 120 140 160 180Tmb / C

120

110

100

90

80

70

60

50

40

30

20

10

0

WDSS%

Ptot (dc) =Tjmax − Tmb

Rthj − mb

1

Ptot (pulse) =Tjmax − Tmb

Zthj − mb

2

74


Fig.15 Transient thermal impedance.Zthj-mb = f(t); parameter D = tp/T

The 469 W line is observed on Fig.13, (4.69 A @ 100 V and15.6 A @ 30 V etc)

Example 2: 1 ms pulse at 75 ˚C for a BUK553-100A

Zth = 0.32 K/W, Tjmax = 175 ˚C, Tmb = 75 ˚C

Therefore with a mounting base temperature of 75 ˚C themaximum permissible power dissipation is reduced by onethird compared with the 25 ˚C value on the SOA plot.

Calculating CurrentsThe current ratings quoted in the data sheet are deriveddirectly from the maximum power dissipation.

substituting for Ptot from equation 1

To calculate a more realistic current it is necessary toreplace Tjmax in equation 4 with the desired operatingjunction temperature and Tmb with a realistic working value.It is generally recommended that devices are not operatedcontinuously at Tjmax. For reasons of long term reliability,125 ˚C is a more suitable junction operating temperature.A value of Tmb between 75 ˚C and 110 ˚C is also a moretypical figure.

As an example a BUK553-100A is quoted as having a dccurrent rating of 13 A. Assuming a Tmb of 100 ˚C andoperating Tj of 125 ˚C the device current is calculated asfollows:

From Fig.8

Rthj-mb = 2 K/W, using equation 4

The device could therefore conduct 6.3 A under theseconditions which equates to a 12.5 W power dissipation.

Conclusions

The most important information presented in the data sheetis the on-resistance and the maximum voltagedrain-source. Current values and maximum powerdissipation values should be viewed carefully since theyare only achievable if the mounting base temperature isheld to 25 ˚C. Switching times are applicable only for thespecific conditions described in the data sheet, whenmaking comparisons between devices from differentmanufacturers, particular attention should be paid to theseconditions.

ID(@Tmb) =

Tjmax − Tmb

Rthj − mb ⋅ RDS(ON)(@Tjmax)

1

2

4

1E-07 1E-05 1E-03 1E-01 1E+01t / s

Zth j-mb / (K/W)1E+01

1E+00

1E-01

1E-02

1E-03

0

0.5

0.20.1

0.05

0.02

BUKx53-lv

D = tp tp

T

TP

t

D

D =

RDS(ON)(@125oC) = 1.75⋅ RDS(ON)(@25oC) = 1.75⋅ 0.18= 0.315ΩPmax(1ms pulse) =

175− 250.32

= 469W

ID =

252 ⋅ 0.315

1

2

= 6.3A

Pmax(1ms pulse) =175− 75

0.32= 312W

ID(@Tmb)2 ⋅ RDS(ON)(@Tjmax) = Ptot 3

75


High Voltage Bipolar Transistor

77


1.3.1 Introduction To High Voltage Bipolar Transistors

This section introduces the high voltage bipolar transistorand discusses its construction and technology. Specifictransistor properties will be analysed in more detail insubsequent sections and in Chapter 2, section 2.1.2.

Basic CharacteristicsHigh voltage transistors are almost exclusively used aselectronic switches. Therefore, the characteristics of thesedevices are given for the on state, the off state and thetransition between the two i.e. turn-on and turn-off.

The relative importance of the VCES and VCEO ratings usuallydepends on the application. In a half bridge converter, forinstance, the rated VCEO is the dominant factor, whilst in aforward converter VCES is important. Which rating is mostapplicable may also depend on whether a slow rise networkor snubber is applied (see section 1.3.3).

The saturation properties in the on state and the switchingtimes are given at a specific collector current called thecollector saturation current, ICsat. It is this current which isnormally considered to be the practical working current ofthe device. If this device is used at higher currents the totaldissipation may be too high, while at low currents thestorage time is long. At ICsat the best compromise is presentfor the total spread of products. The value of the basecurrent used to specify the saturation and switchingproperties of the device is called IBsat which is also animportant design parameter. As the device requirementscan differ per application a universal IBsat cannot be quoted.

Device ConstructionA drawing of a high voltage transistor, in this case a fullyisolated SOT186 F-pack, is shown in Fig. 1 with the plasticencapsulation stripped away. This figure shows the threeleads, two of which are connected with wires to thetransistor chip. The third lead makes contact with themounting base on which the crystal is soldered, enablinggood thermal contact with a heatsink. It is the transistorpackage which basically determines the thermal propertiesof the device. The electrical properties are mainlydetermined by the design of the chip inside.

A cross-section of a transistor chip is given in Fig. 2. Herethe transistor structure can be recognised with the emitterand the base contacts at the top surface and the collectorconnected to the mounting base. The thickest part in thedrawing is the collector n- region across which the highvoltage will be supported in the off state. This layer is of

Fig. 1 Cut-away View of a High Voltage Transistor

prime importance in the determination of the characteristicsof the device. Below the n- region is an extra n+ layer,needed for a good electrical contact to the heatsink.

Fig. 2 Cross-section of a High Voltage Transistor

Above the collector is the base p layer, and the emitter n+layer with their respective metallic contacts on top. It isimportant to realise that the characteristics of the deviceare determined by the active area, this is the areaunderneath the emitter where the collector current flowsand the high voltage can be developed. The active area oftwo devices with the same chip size may not be the same.

nickel-platedcopper leadframe

passivatedchip

aluminiumwires

tinned copperleads

ultrasonicwire bonds

Base Collector Emitter

base emitter

250V

600V

850V

1150V

n-

n+

n+ p n+

n-

special glass

79


Fig. 3 Maximum Voltages vs. n- Collector Thickness

N+

P

N-

N+

N+

P

N-

N+

N+

P

N-

N+

TIP49450 V

BUT11850 V

BU2508A1500 V

In addition to the basic collector-base-emitter structuremanufacturers have to add electrical contacts, and specialmeasures are needed at the edges of the crystal to sustainthe design voltage. This introduces another very importantfeature, the high voltage passivation. The function of thepassivation, (theexample shown here is referred to as glasspassivation), is to ensure that the breakdown voltage of thedevice is determined by the collector-base structure andnot by the construction at the edges. If no specialpassivation was used the breakdown voltage might be aslow as 50% of the maximum value. Manufacturers optimisethe high voltage passivation and much work has also beendone to ensure that its properties do not change in time.

Process TechnologyThere are several ways to make the above structure. Thestarting material can be an n- wafer where first an n+diffusion is made in the back, followed by the base (p) andemitter (n+) diffusions. This is the well known triple diffusedprocess.

Another way is to start with an n+ wafer onto which an n-layer is deposited using epitaxial growth techniques. Afurther two diffusions (base and emitter) forms the basictransistor structure. This is called a double diffusedepitaxial process.

Another little used technology is to grow, epitaxially, thebase p-type layer onto an n-/n+ wafer and then diffuse ann+ emitter. This is referred to as a single diffused epi-basetransistor.

The question often asked is which is the best technologyfor high voltage bipolar transistors ? The basic differencein the technologies is the concentration profile at the n-/n+junction. For epitaxial wafers the concentration gradient ismuch more steeper from n- to n+ than it is for back diffusedwafers. There are more applications where a smootherconcentration gradient gives the better performance.Manufacturers utilising epitaxial techniques tend to usebuffer layers between the n- and n+ to give smoother

concentration gradients. Another disadvantage of epitaxialprocessing is cost: back diffused wafers are much cheaperthan equivalent high voltage epitaxial wafers.

The process technology used to create the edgepassivation is also diverse. The expression "planar" is usedto indicate the passivation technique which is mostcommonly used in semiconductors. This involves thediffusion of additional n-type rings around the active areaof the device which give an even electric field distributionat the edge. However, for high voltage bipolar transistorsplanar passivation is relatively new and the long termreliability has yet to be completely optimised. For highvoltage bipolar transistors the most common passivationsystems employ a deep trough etched, or cut, into thedevice with a special glass coating. Like the planarpassivation, the glass passivation ensures an evendistribution of the electric field around the active area.

Maximum Voltage and Characteristics

Fig. 4 Switching Times and hFE vs. VCEO

200 400 800

15

25

5010

5

2.5

30 60 120hFEsat hFE0Width of n- layer (um)

0.8

0.4

0.2 1.5

3

6

tf ts

Vceo (V)

(us)

hFE

ts, tf

80


High voltage and low voltage transistors differ primarily inthe thickness and resistivity of the n- layer. As the thicknessand resistivity of this layer is increased, the breakdownvoltage goes up. The difference over the range of Philipshigh voltage transistors of different voltages is illustrated inFig. 3. The TIP49 has a VCBO = 450 V, the BUT11 has aVCES = 850 V, while the BU2508A can be used up tovoltages of 1500 V.

The penalty for increasing the n- layer is a decrease in highcurrent hFE and an in switching times. The graph in Fig. 4points this out by giving both switching times and hFE as afunctionof the breakdown voltage. The values given shouldbe used as a guide to illustrate the effect. The effect canbe compensated for by having a bigger chip.

Applications of High Voltage TransistorsHigh voltage transistors are mainly used as the powerswitch in energy conversion systems. What is common to

all thesesystems, is thatacurrent flows through an inductor,thus storing energy in its core. When the current isinterrupted by turning off the power switch, the energy mustbe transferred one way or another. Very often the energyis converted into an electrical output e.g. in switched modepower supplies and battery chargers.

Two special applications are electronic fluorescent lampballasts and horizontal deflection of the electron beam inTV’sand monitors. In the ballast,an ac voltage is generatedto deliver energy to a fluorescent lamp. In the TV andmonitor a sawtooth current in the deflection coil sweeps thebeam across the screen from left to right and back again ina much shorter blanking, or flyback, period

Other ways to transfer the energy are ac and dc motorcontrol where the output is delivered as movement, orinduction heating where the output is delivered in the formof heat.

81


1.3.2 Effects of Base Drive on Switching Times

Introduction

The switching processes that take place within a highvoltage transistor are quite different from those in a smallsignal transistor. This section describes, figuratively, whathappens within high voltage transistors under various basedrive conditions. After an analysis of the charges that arepresent in a high voltage transistor, the switch-off processis described. Then comparisons are made of switching forvarious forward and reverse base drive conditions. Afundamental knowledge of basic semiconductor physics isassumed.

Charge distribution within a transistor

An off-state transistor has no excess charge, but to enabletransistor conduction in the on-state excess charge buildup within the device takes place. There are three distinctcharge distributions to consider that control the currentthrough the device, see Fig. 1. These charge distributionsare influenced by the level of collector-emitter bias, VCE,and collector current, IC, as shown in Fig. 2.

Forward biasing the base-emitter (BE) junction causes adepletion layer to form across the junction. As the biasexceeds the potential energy barrier (work function) for thatjunction, current will flow. Electrons will flow out of theemitter into the base and out of the base contact. For highvoltage transistors the level of BE bias is much in excessof the forward bias for a small signal transistor. The biasgenerates free electron-hole pairs in the base-emitterleading to a concentration of electrons in the base in excessof the residualhole concentration. This produces an excesscharge in the base, Qb, concentrated underneath theemitter.

Fig. 1. On-state Charge Flow

Not only is there an excess charge in the base near theemitter junction but the injection and base width ensure thatthis excess charge is also present at the collector junction.Applying a load in series with the collector and a dc supplybetween load and emitter will trigger some sort of collectorcurrent, IC. The level of IC is dependent on the base current,IB, the load and supply voltage. For a certain IB, low voltagesupply and high impedance load there will be a small IC. Asthe supply voltage rises and/or the load impedance falls soIC will rise. As IC rises so the collector-emitter voltage, VCE,falls. The IC is composed mainly of the excess emitterelectrons that reach the base-collector junction (BC). Thiselectron concentration will continue into the collectorinducing an excess charge in the collector, Qc.

The concentration of electrons decreases only slightly fromthe emitter-base junction to some way into the collector. Ineffect, the base width extends into the collector. DecreasingVCE below VBE causes the BC junction to become forwardbiased throughout. This creates a path for electrons fromthe collector to be driven back into the base and out of thebase contact. This electron flow is in direct opposition tothe established IC. With no change in base drive, theultimate effect is a reduction in IC. This is the classical‘saturation’ region of transistor operation. As VCE falls sothe BC forward bias increases leading to an excess ofelectrons at the depletion layer edge in the collectorbeneath the base contact. This concentration of electronsleads to an excess charge, Qd.

The charge flows and excess charges Qb, Qc and Qd areshown in Fig. 1. An example of the excess chargedistributions for fixed IC and IB are shown in Fig. 2.

Fig. 2. On-state Charge Distribution (example)

The switching process of a transistorRemoving the bias voltage, VBE, will cause the electron-holepairs to recombine and the excess charge regions todisappear. Allowing this to happen just by removing VBE

QQd

Qc

Qb

Vce (V)

Ic = 5 A

Ib = 1 A

B E B

Qd Qc

QbP

N+

N-

N+

C

83


takes a long time so usually turn-off is assisted in someway. It is common practice to apply a negative bias(typically 5V) to the base, via a resistor and/or inductor,inducing a negative current that draws the charge out ofthe transistor. In the sequence that follows, four phases ofturn-off can be distinguished (see Fig. 3).

1. First the applied negative bias tries to force a negativebias across the BC junction. The BC electron flow nowstops and the charge Qd dissipates as the bias now causesthe base holes out through the base contact and thecollector electrons back into the bulk collector. When theBC was forward biased this current had the effect ofreducing the total collector current, so now the negative VBE

can cause the total collector current to increase (this alsodependson the load). Although the base hasbeen switchedoff the load current is maintained by the stored chargeeffects; this is called the transistor storage time, ts.

During this stage the applied negative bias appears as apositive VBE at the device terminals as the internal chargedistributions create an effective battery voltage. Depletingthe charge, of course, lowers this effective battery voltage.

2. The next phase produces a reduction in both Qb, Qcand, consequently, IC. The BC junction is no longer forwardbiased and Qd has dissipated to provide the negative basecurrent. The inductance in series in the base path requiresacontinuation in the base current. The injection of electronsinto the base opposes the established electron flow fromemitter to collector via the base. At first the opposingelectron flows cancel at the edge of the emitter nearest thebase contacts. This reduces both Qb and Qc in this region.Qband Qc become concentrated in the centre of the emitterarea. The decrease in IC is called the fall time, tf.

3. Now there is an extra resistance to the negative basecurrent as the electrons flow through the base under theemitter area. This increase in resistance limits the increasein amplitude of the negative base current. As Qb and Qcreduce further so the resistance increases and the negativebase current reaches its maximum value.

As Qb and Qc tend to zero the series inductance ensuresthat negative base current must be continued by othermeans. The actual mechanism is by avalanche breakdownof the base-emitter junction. This now induces a negativeVBE which is larger than the bias resulting in a reverse inpolarity of the voltage across the inductance. This in turntriggers a positive rate of change in base current. Thenegative base current now quickly rises to zero while thebase-emitter junction is in avalanche breakdown.Avalanche breakdown ceases when the base current tendsto zero and the VBE becomes equal to the bias voltage. Fig. 3. Phases during turn-off

B E B

Qd Qc

QbP

N+

N-

N+

C

B E B

Qc

QbP

N+

N-

N+

C

B E B

P

N+

N-

N+

C

0Qb

Qc 0

B E B

P

N+

N-

N+

C

Qr

84


4. If a very small series base inductor is used with the 5Vreverse bias then the base current will have a very fast rateof change. This will speed up the phases 1 to 3 and,therefore, the switching times of the transistor. However,there is a point when reducing the inductor furtherintroduces another phase to the turn-off process. Highreverse base currents will draw the charges out closest tothe base contact and leave a residual charge trapped deepin the collector regions furthest away from the base. Thischarge, Qr, must be removed before the transistor returnsfully to the off-state. This is detected as a tail to IC at theend of turn-off with a corresponding tail to the base currentas it tends to zero.

The switching waveforms for a BUT11 in a forwardconverter are given in Fig. 4 where the four phases caneasily be recognised. (Because of the small base coil usedboth phases in the fall time appear clearly!).

1 - Removal of Qd until t ≈ 0.7 µs ts

2 - Qc and Qb decrease until t ≈ 1.7 µs ts

3 - Removal of Qb and Qc until t ≈ 1.75 µs tf

4 - Removal of Qr until t ≈ 1.85 µs tf

Note the course of VBE: first the decrease in voltage due tothe base resistance during current contraction and second(because a base coil has been used) the value of VBE isclamped by the emitter-base breakdown voltage of thetransistor. It should be remembered that becausebreakdown takes place near the surface and not in theactive region no harm comes to the transistor.

Fig. 4. BUT11 waveforms at turn-off

The influence of forward drive on storedchargeFig. 5 shows how, for a transistor in the on-state, at a fixedvalue of IC and IB the three charges Qb, Qc and Qd dependupon VCE. The base charge, Qb, is independent of VCE, itprimarily depends upon VBE. For normal base drive

conditions, a satisfactory value for VCEsat is obtained,indicated by N in Fig. 5, and moderate values for Qc andQd result.

Fig. 5. Charges as a function of VCE

With the transistor operating in the active region, forVCE ≥ 1V, there will be a charge Qc but no charge Qd. Thisis indicated by D in Fig. 5. At the other extreme, with thetransistoroperating in the saturation region Qcwill be higherand Qd will be higher than Qc. This is indicated by O inFig. 5. In this condition there are more excess electron-holepairs to recombine at switch off.

Increasing IB causes Qb to increase. Also, for a given IC,Qc and Qd will be higher as VCE reduces. Therefore, for agiven IC, the storedcharge in the transistor can be controlledby the level of IB. If the IB is too low the VCE will be high withlow Qc and zero Qd, as D in Fig. 5. This condition is calledunderdrive . If the IB is too high the VCE will be low with highQc and Qd, as O in Fig. 5. This condition is calledoverdrive . The overdrive condition (high forward drive)gives high stored charge and the underdrive condition (lowforward drive) gives low stored charge.

Deep-hole storage

As the high free electron concentration extends into thebase and collector regions ther must be an equivalent holeconcentration. Fig. 6 shows results obtained from acomputer model which illustrates charge storage as afunction of VCE. Here the hole density, p(x), is given as afunction of depth inside the active area; the doping profileis also indicated. It can be seen that overdrive, O, causesholes to be stored deep in the collector at the collector -substrate junction known as "deep-hole storage", this is themain reason for the increase in residual charge, Qr.

QQd

Qc

Qb

0.2 0.5 1.0 Vce (V)

O N D

Ic

Vce

Ib Vbe

1 A/div

1 A/div

200 V/div

5 V/div

0.5 us/div

85


During overdrive not only Qd becomes very big but alsoholes are stored far away from the junction: this thus leadsnot only to a longer storage time, but also to a large Qrresulting in tails in the turn-off current.

Fig. 6. Deep hole storage in the collector region

Desaturation networksA desaturation network, as shown in Fig. 7, limits the storedcharge in the transistor and, hence, aids switching. Theseries base diode, D1 means that the applied drive voltagenow has to be VBE plus the VF of D1. The anti-parallel diode,D2 is necessary for the negative IB at turn-off. As VCE

reduces below VBE + VF so the external BC diode, D3,becomes forward biased. D3 now conducts any furtherincrease in drive current away from the base and into thecollector. Transistor saturation is avoided.

With a desaturation network the charge Qd equals zero andthe charge Qc is minimised. When examining thedistribution of the charge in the collector region (see Fig. 6)it can be seen that deep hole storage does not appear.Desaturation networks are a common technique forreducing switching times.

It should be realised that there is a drawback attached tooperating out of saturation: increased dissipation during theon-state. Base drive design often requires a trade-offbetween switching and on-state losses.

Fig. 7. Desaturation network(Baker clamp)

Breakdown voltage vs. switching times

For a higher breakdown voltage transistor the n- layer (seeFig. 1) will be thicker and of higher resistivity (ie a lowerdonor atom concentration). This means that whencomparing identical devices the values for Qd and Qc willbe higher, for a given IC, in the device with the higherbreakdown voltage.

In general:

- the higher BVCEO the larger Qd and Qc will be;

- during overdrive Qd is very high and there is a chargelocated deep in the collector region (deep hole storage);

- when desaturated Qd equals zero and there is no deephole storage: Qc is minimised for the IC.

Turn-off conditions

Various ways of turning off a high voltage transistor areused but the base should always be switched to a negativesupply via an appropriate impedance. If this is not done,(ie turn-off is attempted by simply interrupting the basecurrent), very long storage times result and the collectorvoltage increases, while the collector current falls onlyslowly. A very high dissipation and thus a short lifetime ofthe transistor are the result. The charges must be removedusing a negative base current.

a) Hard turn-off

The technique widely used, especially for low voltagetransistors, is to switch directly to a negative voltage, (seeFig. 8a). In the absence of a negative supply, this can beachieved with an appropriate R-C network (Fig. 8b). Alsoapplying an "emitter-drive" (Fig. 8c) with a large basecapacitor in fact is identical to hard-turn-off.

The main drawback for high voltage transistors is that thebase charge Qb is removed too quickly, leaving a highresidual charge. This leads to current tails (long fall times)and high dissipation. It depends upon what state thetransistor is in (overdriven or desaturated),whether this wayof turn-off is best. It also depends upon the kind of transistorthat must be switched off. If it is a lower voltage transistor(BVCEO ≤ 200V) then this will work very well because thecharges Qc and Qd will be rather low. For transistors witha higher breakdown voltage, hard turn-off will yield theshortest storage time at the cost, however, of higher turn-offdissipation (longer tf).

b) Smooth turn-off

To properly turn-off a high voltage transistor a storage timetominimiseQd andQc is required,and thena large negativebase current to give a short fall time.

0 80 1604020 60 120100 140

20

10

12

14

16

18

10

10

10

10

10

10

Vce = 1 V 0.5 V 0.2 V

p(x) at J = 140 A / cm2

p(x)

x (um)

E BC

D N O

B

C

E

D3

D1

D2

86


Fig. 8. Hard turn-off

-V

+Ib

++

Lc

++

Lc+V

C

R

++

Lc

+V

+I

R

C

(a) (b) (c)

The easiest way to obtain these turn-off requirements is toswitch the base to a negative supply via a base coil, seeFig. 9.

The base coil gives a constant dIB/dt (approx.) during thestorage time. When the fall time begins the negative basecurrent reaches its maximum and the Lb induces the BEjunction into breakdown (see Fig. 4).

An optimum value exists for the base coil: if Lb = 0 we havethe hard turn-off condition which is not optimum for standardhigh voltage transistors. If the value of Lb is too high it slowsthe switching process so that the transistor desaturates.The VCE increases too much during the storage time andso higher losses result (see Fig. 10).

For high voltage transistors in typical applications (f = 15 to40 kHz, standard base drive, not overdriven, notdesaturated) the following equations give a good indicationfor the value of Lb.

Using - Vdr = 5V, VBEsat = 1V and transistors havingBVCEO = 400V it follows that:

c) Other ways of turn-off

Of course, other ways of turn-off are applicable but ingeneral these can be reduced to one of the methodsdescribed above, or something in between. The BVCEO hasa strong influence on the method used: the higher BVCEO

the longer the storage time required to achieve properturn-off. For transistors having a BVCEO of 200V or less hardturn-off and the use of a base coil yield comparable losses,so hard turn-off works well. For transistors having BVCEO

more than 400V hard turn-off is unacceptable because ofthe resulting tails.

Fig. 9. A base coil to aid turn-off.

+Ib

++

Lc

-Vdr

LB =(−Vdr + VBEsat)

dIB

dt

withdIBdt

≈ 0.5⋅ IC (A/µs) for BVCEO = 400V, BVCES = 800V

anddIBdt

≈ 0.15⋅ IC (A/µs) for BVCEO = 700V, BVCES = 1500V

LB =12IC

H (IC in Amps)

87


Fig. 10. Variations of Lb on IC and VCE waveforms at turn-off

Ic Vce Ic Vce IcVce

Lb = 0 Lb = opt Lb > Lb opt

Turn-off for various forward driveconditionsUsing the BUT11 as an example, turn-off characteristicsare discussed for optimum drive, underdrive and overdrivewith hard and smooth turn-off.

a) Optimum driveThe optimum IB and Lb for a range of IC is given in Fig. 11for the BUT11. The IB referred to is IBend which is the valueof IB at the end of the on-state of the applied base drivesignal. In most applications during the on-state the IB willnot be constant, hence the term IBend rather than IBon. Foroptimumdrive the level of IBend increases with IC. For smoothturn-off the level of Lb decreases with increasing IC.

Fig. 11. IBend and Lb for the BUT11

Deviations from Fig. 11 will generally lead to higher powerdissipation. If a short storage time is a must in a certainapplication then Lb can be reduced but this will lead tolonger fall times and current tails.

With hard turn-off IB reaches its peak negative value as allthe charge is removed from the base. For continuity thiscurrentmust be sourced fromelsewhere. It hasbeen shownthat the BE junction now avalanches, giving instantaneouscontinuity followed by a positive dIB/dt. However, for hardturn-off the current is sourced by the residual collectorcharge without BE avalanche, see Fig. 12. The smallnegative VBE ensures a long tail to IC and IB.

b) Underdrive (Desaturated drive)As has been indicated previously, desaturating, orunderdriving, a transistor results in less internal charge. Qdwill be zero and Qc is low and located near the junction.

If the application requires such a drive then steps shouldbe taken to optimise the characteristics. One simple wayof obtaining underdrive is to increase the series baseresistance with smooth turn-off. The same effect can beachieved with optimum IBend and a base coil having half thevalue used for optimum drive, ie hard turn-off. Bothmethods give shorter ts and tf. For 400V BVCEO devices (likethe Philips BUT range) such a harder turn-off can lead toreasonable results.

Fig. 13 compares the use of the optimum base coil withhard turn-off for an undriven BUT11. For underdrive thefinal IC is less and hence the collector charge is less.Therefore, underdrive and hard turn-off gives less of a tailthan for a higher IBend. Underdrive with smooth turn-off giveslonger ts but reduced losses.

c) OverdriveWhen a transistor is severely overdriven the BC charge,Qd, becomes so large that a considerable tail will resulteven with smooth turn-off. In general, deliberatelydesigning a drive circuit to overdrive a transistor is not done:it has no real value. However, most circuits do have variablecollector loads which can result in extreme conditions whenthe circuit is required to operate with the transistor inoverdrive.

88


Fig. 12. Optimum drive with hard turn-off (top)and smooth turn-off (bottom) for BUT11

Fig. 13. Underdrive with hard turn-off (top)and smooth turn-off (bottom) for BUT11

Fig. 14. Overdrive with hard turn-off (top)and smooth turn-off (bottom) for BUT11

Fig. 14 compares the use of the optimum base coil withhard turn-off for an overdriven BUT11. For overdrive thereis more base charge, also the final collector current will behigher and, hence, there will be more collector charge. Theoverdriven transistor is then certain tohave longerswitchingtimes as there are more electron-hole pairs in the devicethat need to recombine before the off-state is reached.

ConclusionsTwo ways of turning off a high voltage transistor, hardturn-off and the use of a base coil, were examined in threeconditions of the on-state: optimum drive, overdrive andunderdrive.

For transistors having BVCEO ~ 400 V the use of a base coilyields low losses compared to hard turn-off. As a goodapproximation the base coil should have the value:

for optimum drive.

When using a desaturation circuit the value for Lb can behalved with acceptable results.

Overdrive should be prevented as much as possiblebecause considerable tails in the collector current causeunacceptable losses.

Ic Vce

Ib

Vbe

1 A/div

1 A/div

200 V/div

5 V/div

0.5 us/div

Ic Vce

Ib

Vbe

1 A/div

1 A/div

200 V/div

5 V/div

0.5 us/div

Ic

Vce

Ib Vbe

1 A/div

1 A/div

200 V/div

5 V/div

0.5 us/div

Ic Vce

Ib Vbe

1 A/div

1 A/div

200 V/div

5 V/div

0.5 us/div

Ic Vce

Ib

Vbe

1 A/div

1 A/div

200 V/div

5 V/div

0.5 us/div

Ic Vce

Ib Vbe

1 A/div

1 A/div

200 V/div

5 V/div

0.5 us/div

LB =12IC

µH

89


1.3.3 Using High Voltage Bipolar Transistors

This section looks at some aspects of using high voltagebipolar transistors in switching circuits. It highlights pointssuchas switching, both turn-on and turn-off, Safe OperatingAreas and the need for snubber circuits. Base drive designcurves for the BUT11, BUW12 and BUW13 are discussedunder ’Application Information’ at the end of this section.

Transistor switching: turn-on

To make optimum use of today’s high voltage transistors,one should carefully choose the correct value for both thepositive base current when the transistor is on and thenegative base current when the device is switched off (seeApplication Information section).

When a transistor is in the off-state, there are no carriersin the thick n- collector, effectively there is a resistor with arelatively high value in the collector. To obtain a lowon-state voltage, a base current is applied such that thecollector area is quickly filled with electron - hole pairscausing the collector resistance to decrease. In thetransition time, the so called turn-on time, the voltage andcurrent may both be high, especially in forward converters,and high turn-on losses may result. Initially, all the carriersin the collector will be delivered via the base contact and,therefore, the base current waveform should have a peakat the beginning. In this way the carriers quickly fill thecollector area so the voltage is lower and the lossesdecrease.

In flyback converters the current to be turned on is normallylow, but in forward converters this current is normally high.Thecollector current, IC, reaches its on-state value in ashorttime which is normally determined by the leakageinductance of the transformer.

Fig. 1 Turn-on of a high voltage bipolar transistor

In Fig. 1 the characteristic ‘hump’ which often occurs atturn-on in forward converters due to the effect of thecollector series resistance is observed.

The turn-on losses are strongly dependent on the value ofthe leakage inductance and the applied base drive. It isgenerally advised to apply a high initial +IB for a short timein order to minimise turn on losses.

A deeper analysis can be found in sections 1.3.2, 2.1.2 and2.1.3. Turn on losses are generally low for flybackconverters but are the most important factor in forwardconverter types.

Turn-off of high voltage transistorsAll charge stored in the collector when the transistor is onshould be removed again at turn-off. To ensure a quickturn-offa negative base current is applied. The time neededto remove the base - collector charge is called the storagetime. A short storage time is needed to minimise problemswithin the control loop in SMPS and deflection applications.

Fig. 2 Effects of -IB on turn-off

Care is needed to implement the optimum drive. Firstoverdriveshould be prevented by keeping+IB to aminimum.Overdrive results in current tails and long storage times.But, decreasing IB too much results in high on-state losses.

Second, the negative base current should be chosencarefully. A small negative base current (-IB) will give a longstorage time and a high VCEsat at the end of the storage time,while the current is still high. As a consequence, the turn-offlosses will be high. If, however, a large negative basecurrent is used, the danger exists that tails will occur in thecollector current, again resulting in high losses. There isan optimum as shown in Fig. 2.

A circuit which is worth considering, especially for higherfrequencies, is the Baker Clamp or desaturation circuit.This circuit prevents saturation of the transistor and, hence,faster switching times are achieved.

Ic Vce Ic Vce IcVce

-Ib is too high -Ib is optimum -Ib is too low

Ic

Vce

Ic = 1 A/div

Vce = 50 V/div

91


The total losses depend on the base drive and the collectorcurrent. In Fig.3 the total losses are shown for a BUW133as a function of the positive base current, for both thesaturated and the desaturated case. Note that whendifferent conditions are being used the picture will change.The application defines the acceptable storage time whichthen determines the base drive requirements.

Fig. 3 BUW133 losses versus base drive

The total number of variables is too large to give uniquebase drive advice for each application. As a first hint thedevice data sheets give IC and IB values for VCEsat, VBEsat andswitching. However, it is more important to appreciate theways to influence base drive and the consequences of anon-optimised circuit.

For a flyback converter the best value of IBend to start withis about 2/3 of the IB value given in data for VCEsat and VBEsat.In this application the forward base current is proportionalto the collector current (triangular shaped waveforms) andthis IBend value will give low on-state losses and fastswitching.

The best turn-off base current depends on the breakdownvoltage of the transistor. As a guide, Table 1 givesreasonable values for the target storage time and may beused to begin optimising the base drive:

f (kHz) tp (µs) target ts (µs)

25 20 2.0

150 10 1.5

100 5 1.0

Table 1 Target ts for varying frequency and pulse width

The above table holds for transistors with a VCEOmax ratingof 400-450V and VCESmax between 850-1000V. Transistorswith higher voltages require longer storage times, eg.

transistors with VCEOmax = 700V and VCESmax = 1500V needa storage time which is approximately double the value inthe table.

A recommended way to control the storage time is byswitching the base to a negative voltage rail via a base coil.The leakage inductance of a driver transformer may serveas an excellent base coil. As a guide, the base coil shouldbe chosen such that the peak value of the negative basecurrent equals half the value of the collector current.

Specific problems and solutionsA high voltage transistor needs protection circuits to ensurethat the device will survive all the currents and voltages itwill see during its life in an application.

a) Over Current

Exceeding current ratings normally does not lead toimmediate transistor failure. In the case of a short circuit,the protection is normally fast enough for problems to beavoided. Most devices are capable of carrying very highcurrents for short periods of time. High currents will raisethe junction temperature and if Tjmax is exceeded thereliability of the device may be weakened.

b) Over Voltage

In contrast with over current, it is NOT allowed to exceedthe published voltage ratings for VCEO and VCES (or VCBO).In switching applications it is common for the base - emitterjunction to be taken into avalanche, this does not harm thedevice. For this reason VEBO limits are not given in data.

Exceeding VCEO and VCES causes high currents to flow invery small areas of the device. These currents may causeimmediate damage to the device in very short times(nanoseconds). So, even for very short times it is notallowed to have voltages above data for the device.

In reality VCEO and VCES are unlikely to occur in a circuit. IfVBE = 0V the there will probably still be a path between thebase and the emitter. In fact the situation is VCEX where Xis the impedance of this path. To cover for all values of X,the limit is X=∞, ie VCEO. For all VBE < 0V, ie VCEV, the limitcase is VBE = 0V, ie VCES.

If voltage transients that exceed the voltage limits aredetected then a snubber circuit may limit the voltage to asafe value. If the over voltage states last greater than afew µs a higher voltage device is required.

c) Forward Bias Safe Operating Areas (FBSOA)

The FBSOA is valid for positive values of VBE. There is atime limit to VCE - IC operating points beyond which devicefailure becomes a risk. At certain values of VCE and IC thereis a risk of secondary breakdown; this is likely to lead to theimmediate failure of the device. The FBSOA curve shouldonly be considered during drastic change sequences; forexample, start-up, s/c or o/c load.

With Baker Clamp

Saturated

100

200

300

400

500

600

700

Etot (uJ)

1 2 3 4

Ib (A)

Forward Converter

Ic = 10 A

92


d) Reverse Bias Safe Operating Area (RBSOA)

The RBSOA is valid for negative values of VBE. Duringturn-off with an inductive load the VCE will rise as the IC falls.For each device type there is a VCE - IC boundary which, ifexceeded, will lead to the immediate failure of the device.To limit the VCE - IC path at turn-off snubber circuits are used,see Fig. 4.

Fig. 4 HVT with inductive load and typical snubber

At turn-off, as the VCE rises the diode starts conductingcharging the capacitor. The additional diode current meansthat the total load current does not decrease so fast atturn-off. This slower current tail in turn ensures a slowerVCE rise. The slower VCE rise takes the transistor througha safer VCE - IC path away from the limit, see Fig. 5.

As a handy guide, the snubber capacitor in a 20-40 kHzconverter is about 1nF for each 100W of throughput power(this is the power which is being transferred via thetransformer). This value may be reduced empirically asrequired.

Fig. 5 BUW13A RBSOA limitVCE - IC path with and without snubber

The following table may serve as a guide to the value ofdVCE/dt for some switching frequencies

f (kHz) 25 50 100

dVCE/dt 1 2 4(kV/µs)

Thesnubber resistor should be chosen so that the capacitorwill be discharged in the shortest occurring on-time of theswitch.

In some cases the losses in the snubber may beconsiderable. Clever designs exist to feed the energystored in the capacitor back into the supply capacitor, butthis is beyond the scope of this report.

5

10

15

20

200 400 600 800 1000

BUW13A

Ic

Vce

Without Snubber

With Snubber

Vs

Fig. 6 Transistor with maximum protection networks in SMPS circuit

R5C5 C4

D4

D5

D6

R4TR1

L6R6

D3 D1

D2

Lo

Co Vo

Vi

93


d) Other protection networks

In Fig. 6 a "maximum protection" diagram is shown withvarious networks connected. R4, C4, and D4 form thesnubber to limit the rate of rise of VCE. The network withD5, R5 and C5 forms a "peak detector" to limit the peakVCE.

The inductor L6 serves to limit the rate of rise of IC whichmay be very high for some transformer designs. The slowerdIC/dt leads to considerably lower turn-on losses. Addedto L6 is a diode D6 and resistor R6, with values chosen sothat L6 loses its energy during the off-time of the powerswitch.

While the snubber is present in almost all SMPS circuitswhere transistors are used above VCEOmax, the dIC/dt limiteris only needed when the transformer leakage inductanceis extremely low. The peak detector is applied in circuitswhich have bad coupling between primary and secondarywindings.

Application InformationImportant design factors of SMPS circuits are the maximumpower losses, heatsink requirements and base driveconditions of the switching transistor. The power lossesare very dependent on the operating frequency, the

maximum collector current amplitude and shape.

The operating frequency is usually between 15 and 50 kHz.The collector current shape varies from rectangular in aforward converter to sawtooth in a flyback converter.

Examples of base drive and losses are given in Appendix 1for the BUT11, BUW12 and BUW13. In these figures ICM

represents the maximum repetitive peak collector current,which occurs during overload. The information is derivedfrom limit-case transistors at a mounting base temperatureof 100 ˚C under the following conditions (see also Fig. 7):

- collector current shape IC1 / ICM = 0.9- duty factor (tp / T) = 0.45- rate of rise of IC during turn-on = 4 A/µs- rate of rise VCE during turn-off = 1 kV/µs- reverse drive voltage during turn-off = 5 V- base current shape IB1 / IBe = 1.5

The required thermal resistance of the heatsink can becalculated from

To ensure thermal stability a maximum value of the ambienttemperature, Tamb, is assumed: Tamb ≤ 40˚C.

Rth(mb− amb) <100− Tamb

Ptot

K/W

Fig. 7 Relevant waveforms of the switching transistor in a forward SMPS.

Ic

Ic1

Icm

Vce

Ib

Vbe

Ib1Ib(end)

-Vdrive

T

tp

dIc/dt

0.9 Icm

0.1 Icm

t1 = 0.5 us

Vce(t1)

ts

tf

Turn-on Turn-off

94


As a base coil is normally advised and a negative drivevoltage of -5V is rather common, the value for the base coil,LB, is given for these conditions. For other values of -Vdrive

(-3 to -7 volt) the base coil follows from:

Where LBnom is the value given in Appendix 1.

It should be noted, that this advice yields acceptable powerlosses for the whole spread in the product. It is not just fortypical products as is sometimes thought ! This isdemonstrated in Fig. 8, where limit and typical devices arecompared (worst-case saturation and worst-caseswitching).

It appears that the worst-case fall time devices have lossesP0 for IBend = (Ib adv) + 20%, while the saturationworst-casedevices have the same lossesat (Ib adv) - 20%.A typical device now has losses P1 at Ib adv, while theoptimum IBend for the typical case might yield losses P2 atan approximately 15% lower IBend (NB: this is not a rule, itis an example).

Fig. 8 Losses as a function of IBend

ConclusionTo avoid exceeding the RBSOA of an HVT, snubbers area requirement for most circuits. To minimise both switchingand on-state losses, particular attention should be given tothe design of the base drive circuit. It is generally advisedthat a high initial base current is applied for a short time tominimise turn-on loss. As a guide-line for turn-off, a basecoil should be chosen such that the peak value of thenegative base current equals half the value of the collectorcurrent.

-20% Ib adv +20% Ibe

w.c. (tf) typ. w.c. (sat)

P0

P1

P2

Ploss

LB = LBnom⋅(−Vdrive + 1)

6

95


Appendix 1 Base Drive Design Graphs

BUT11 Base Drive Design Information

BUW12 Base Drive Design Information

BUW13 Base Drive Design Information

96


1.3.4 Understanding The Data Sheet: High Voltage Transistors

Introduction

Being one of the most important switching devices inpresent day switched mode power supplies and other fastswitching applications, the high voltage transistor is acomponent with many aspects that designersdo not alwaysfully understand. In spite of its "age" and the variety ofpapersand publications by manufacturers andusers of highvoltage transistors, data sheets are somewhat limited in theinformation they give. This section deals with the datasheets of high voltage transistors and the background totheir properties. A more detailed look at the background totransistor specifications can be found in chapter 2.1.2.

Fig. 1 shows the cross section of a high voltage transistor.The active part of the transistor is highlighted (the areaunderneath the emitter) and it is this part of the silicon thatdetermines the primary properties of the device:breakdown voltages, hFE, switching times. All the addedparts can only make these properties worse: a badpassivation scheme can yield a much lower collector-basebreakdown voltage, too thin wires may seriously decreasethe current capability, a bad die bond (solder layer) leadsto a high thermal resistance leading to poor thermal fatiguebehaviour.

Fig. 1 Simplified cross section of an HVT

The Data Sheet

The data sheet of a high voltage transistor can specify -

* Limiting Values / Ratings: the maximum allowablecurrents through and voltages across terminals, as well astemperatures that must not be exceeded.

* Characteristics: describing properties in the on and offstate (static) as well as dynamic, both in words and infigures.

* SOA: Safe Operating Area both in forward and reversebiased conditions.

Data sheets are intended to be a means of presenting theessentials of a device and, at the same time, to give anoverview of the guaranteed specification points. This datais checked as a final measurement of the device andcustomers may wish to use it for their incoming inspection.For this reason the data is such that it can be inspectedrather easily in relatively simple test circuits. Thissomewhat application unfriendly way of presenting data isunavoidable if cheap devices are a must, and they are !

Each of the above mentioned items will now be discussedin more detail, in some instances parts of the data for aBUT11 will be used as an example. The BUT11 is intendedfor 3A applications and has a maximum VCES of 850V.

Limiting Values / Maximum RatingsThere is a significant difference between current andvoltage ratings. Exceeding voltage ratings can lead tobreakdown phenomena which are possibly destructivewithin fractions of a second. The avalanche effectsnormally take place within a very small volume and,therefore, only a little energy can be absorbed. Surgevoltages, that are sometimes allowed for othercomponents, are out of the question for high voltagetransistors.

There is, however, no reason to have a derating onvoltages: using the device up to its full voltage ratings - inworst case situations - is allowed. The life tests, carried outin Philips quality laboratories, clearly show that no voltagedegradation takes place and excellent reliability ismaintained.

From the above, it should be clear that the habit of deratingis not a good one. If, in a particular application, thecollector-emitter voltage never exceeds, say 800V, therequired device should be an 850V device not a 1500Vdevice. Higher voltage devices not only have lower hFE, butalso slower switching speeds and higher dissipation.

The rating for the emitter-base voltage is a special case:to allow a base coil to be used, the base-emitter diode maybe brought into breakdown; in some cases a -IBav is givento prevent excessive base-emitter dissipation. The onlyeffect of long term repetitive base-emitter avalanchebreakdown that has been observed is a slight decrease inhFE at very low values of collector current (approximately10% at ≤ 5mA); at higher currents the effects can beneglected completely.

N

P

N

mounting base = collector

bonding wire

glass passivation

active area solder

97


The maximum value for VCEO is important if no snubber isapplied; it sets a firm boundary in applications with a veryfast rising collector voltage and a normal base drive (seealso section on SOA).

Currents above a certain value may be destructive if theylast long enough: bonding wires fuse due to excessiveheating. Therefore, short peak currents are allowed wellabove the rated ICsat with values up to five times this valuebeing published for ICM. Exceeding the published maximumtemperatures is not immediately destructive, but mayseriously affect the useful life of the device. It is well known,that the useful life of a semiconductor device doubles foreach 10K decrease in working junction temperature.Another factor that should be kept in mind is the thermalfatigue behaviour, which strongly depends on thedie-bonding technology used. Philips high voltage devicesare capable of 10,000 cycles with a temperature rise of 90Kwithout any degradation in performance.

This kind of consideration leads to the following advice:under worst case conditions the maximumcase-temperature should not exceed 115 ˚C for reliableoperation. This advice is valid regardless of the maximumtemperature being specified. Of course, for storage thepublished values remain valid.

The maximum total power dissipation Ptot is an industrystandard, but not very useful, parameter. It is the quotientof Tjmax - Tmb and Rth(j-mb) (Rth(j-mb) is the thermal resistancefrom junction to mounting base and Tmb is assumed to be25˚C). This implies a rather impractical infinite heatsink,kept at 25˚C !

Electrical CharacteristicsStatic parameters characterise leakage currents, hFE,saturation voltages; dynamic parameters and switchingtimes, but also include transition frequency and collectorcapacitance.

To start: ICsat, the collector saturation current, is that valueof the collector current where both saturation and switchingproperties of the devices are specified. ICsat is not acharacteristic that can be measured, but it is used as anindicationof the of the peak workingcurrent allowedthrougha device.

In the off-state various leakage currents are specified,however, these are of little use as they indicate the low levelof dissipation in the off state. Also a VCEOsust is specified,usually being equal to the max. VCEO. For switchingpurposes it is the RBSOA that is important (see nextsection).

In the on state the saturation voltages VCEsat and, to a lesserextent, VBEsat are important. VCEsat is an indication of thesaturation losses and VBEsat normally influences base drive.Sometimes worst case VCEsat is given as a function of bothIC and IB. It is not possible to precisely relate these curves

to a real circuit; in practice, currents and voltages will varyover the switching cycle. The dynamic performance isdifferent to the static performance. However, a reasonableindication can be obtained from these curves.

Both the transition frequency (fT) and the collectorcapacitance (Cc or Cob) are minor parameters relating to thedesign and processing technology used.

Switching times may be given in circuits with an inductiveor a resistive collector load. See Figs. 2a-b for simplifiedtest circuits and Figs. 3a-b for waveforms.

Fig. 2a Test circuit for resistive load

Fig. 2b Test circuit for inductive load

When comparing similar devices from differentmanufacturers one is confrontedwith a great variety of basedrive conditions. The positive base current (+IB) may bethe same as the one used in the VCEsat spec. but also lowervalues (up to 40% lower) or desaturation networks may beused, yielding better ts and tf values. The negative basedrive, -IB, may equal +IB or it may be twice this value, yieldinga shorter ts, and sometimes it is determined by switchingthe base to a negative voltage, possibly via a base coil.Altogether it is quite confusing and when comparingswitching times one should be well aware of all thedifferences!

tp

T

VCC

RL

RBT.U.T.0

VIM

LBIBon

-VBB

LC

T.U.T.

VCC

98


Fig. 3a Waveforms for Resistive Switching.

Fig. 3b Waveforms for Inductive Switching.

As an example a BUT11 has been measured at IC = 3A ina resistive test circuit varying both +IB and -IB. The resultsin Table 1 show that it is possible to turn a normal transistorinto a super device by simple specmanship!

IC = 3 A ts (µs) tf (ns)

+IB = 0.6 A; -IB = 0.6 A 2.5 260(normal case)

+IB = 0.36 A; -IB = 0.72 A 1.6 210(underdriven)

+IB = 0.36 A; -VBE = -5 V 0.8 50(underdriven, hard turn-off)

Table 1 Switching times and base drive for the BUT11

The effect of base drive variations on storage and fall timesis given in Table 2. The reference is the condition that both+IB as well as -IB equals the value for IB given for the VCEsat

specification in the data sheet.

ts tf comments

+IB = ref. normal normal reference

+IB = 40% less ↓ ↓

Desaturated ↓ ↓

-IB = ref. normal normal reference

-IB = 2 x +IB ↓ ↓

Directly to -5 V ↓ ↑ with normalbase drive!

Directly to -5 V ↓ ↓ if underdriven

Via L to -5 V ↓ ↓

Table 2 Switching times and base drive variations.

The turn-on time is a parameter which only partiallycorrelates with dissipation as it is usually the behaviourdirectly after the turn-on time which appears to be mostsignificant. Both inductive and resistive load test circuitsare only partially useful, as resistive loads are seldom usedand very often some form of slow-rise network is used withinductive loads. Both circuits provide easy lab.measurements and the results can be guaranteed. Thealternative of testing the devices in a real switched modepower supply would be too costly!

Safe Operating AreaThe difference between forward bias safe operating area(FBSOA) and reverse bias safe operating area (RBSOA)is in the device VBE: if VBE > 0V it is FBSOA and if VBE < 0Vit is RBSOA. Chapter 2.1.3 deals with both subjects in moredetail, a few of the main points are covered below.

FBSOA gives boundaries for dc or pulsed operation. Inswitching applications, where the transistor is "on" or "off",normally the excursion in the IC-VCE plane is fast enough toallow the designer to use the whole plane, with theboundaries ICmax and VCEO, as given in the ratings. This isuseful for snubberless applications and for overload, faultconditions or at switch-on of the power supply

Fig. 4 gives the FBSOA of the BUT11 with the boundariesof ICmax, ICMmax and VCEO, all as given in the ratings. Thereis a Ptotmax (1) and ISB boundary (2), that both shift at higherlevels of IC when shorter pulses are used. Note that in theupper right hand corner pulse times of 20µs are permittedleading to a square switching SOA. For overload, faultcondition or power supply switch-on an extra area is added(area III). All these conditions are for VBE ≥ 0V.

IC

IB

10 %

10 %

90 %90 %

tontoff

tstf

IBon

-IBoff

ICon

IC

IB

ICon

IBon

-IBoff

t

tts tf

toff

10 %

90 %

99


(1) Ptotmax and Ptotpeak max. lines(2) Second breakdown limits (independent oftemperature).I Region of permissible dc operation.II Permissible extension for repetitive pulseoperationIII Area of permissible operation during turn-onin single transistor converters, providedRBE ≤ 100 Ω and tp ≤ 0.6 µs.IV Repetitive pulse operation in this region ispermissible provided VBE ≤ 0 V and tp ≤ 5 ms.Fig. 4 Safe Operating Area of BUT11.

Area IV is only valid for VBE ≤ 0V, so this is an RBSOAextension to the SOA curve. This is not the full picture forRBSOA, area IV is only for continuous pulsed operation.For single cycle and short burst fault conditions see theseparate RBSOA curve.

The RBSOA curve is valid when a negative voltage isapplied to the base-emiiter terminals during turn-off. Thiscurve should be used for fault condition analysis only;continuous operation close to the limit will result in 100’s Wof dissipation ! Due to localised current contraction within

the chip at turn-off, damage will occur if the limit isexceeded. In nearly all cases, the damage will result in theimmediate failure of the device to short circuit.

Emitter switching applications force different mechanismsfor carrier recombination in the device which allow a‘square’ RBSOA. A typical example is shown in Fig. 5,where for both base and emitter drive the RBSOA of theBUT11 is given.

Fig. 5 RBSOA of BUT11 for Base and Emitter Drive.

It is striking that for emitter drive the whole IC-VCES planemay be used so no snubber is necessary, however, a smallsnubber may prevent overshoot. The base drive RBSOAnormally depends on base drive conditions, butunfortunately there is no uniform trend in this behaviour.Therefore, the RBSOA curve in the data gives the worstcase behaviour of the worst case devices. Other datasheets may give RBSOA curves that at first sight look betterthan the Philips equivalent, but beware, these curves mighthold for only a limited base drive range.

SummaryVoltage limiting values / ratings as given in the data mustnever be exceeded, as they may lead to immediate devicefailure. Surge voltages, as sometimes given for othercomponents, are not allowed for high voltage transistors.Current limiting values / ratings are less strict as they aretime-dependent and should be used in conjunction with theFBSOA.

Static characteristics are useful for comparisons but offerlittle in describing the performance in an application. Thedynamic characteristics may be defined for a simple testcircuit but the values give a good indication of the switchingperformance in an application.

RBSOA is, for all switching applications, of primeimportance. Philips give in their data sheets a curve forworst case devices under worst case conditions. Forsnubber design a value of 1 nF per 100W of throughput

200 400 600 800 1000

Ic (A)

Vce (V)

0

1

2

3

4

5

6

7

8

base drive

emitter drive

Vcesm

100


power is advised as a starter value; afterwards, the IC-VCE

locus must be checked to see if it stays within the publishedRBSOA curve.

For characteristics both saturation and switching propertiesare given at ICsat. Most figures are of limited use as theygive static conditions, where in a practical situationproperties are time-dependent. Switching times are given

in relatively simple circuits that may be replicated rathereasily e.g. for incoming inspection.

Switching times depend strongly on drive conditions. Byaltering them a normal device can be turned into a superdevice. Beware of specmanship, this may disguise poortolerance to variations in base drive.

101

S.M.P.S. Power Semiconductor ApplicationsPhilips Semiconductors

CHAPTER 2

Switched Mode Power Supplies

2.1 Using Power Semiconductors in Switched Mode Topologies(including transistor selection guides)

2.2 Output Rectification

2.3 Design Examples

2.4 Magnetics Design

2.5 Resonant Power Supplies

103


Using Power Semiconductors in Switched Mode Topologies

105


2.1.1 An Introduction to Switched Mode Power SupplyTopologies

For many years the world of power supply design has seena gradual movement away from the use of linear powersupplies to the more practical switched mode power supply(S.M.P.S.). The linear power supply contains a mainstransformer and a dissipative series regulator. This meansthe supply has extremely large and heavy 50/60 Hztransformers, and also very poor power conversionefficiencies, both serious drawbacks. Typical efficiencies of30% are standard for a linear. This compares withefficiencies of between 70 and 80%, currently availableusing S.M.P.S. designs.

Furthermore, by employing high switching frequencies, thesizes of the power transformer and associated filteringcomponents in the S.M.P.S. are dramatically reduced incomparison to the linear. For example, an S.M.P.S.operating at 20kHz produces a 4 times reduction incomponent size, and this increases to about 8 times at100kHz and above. This means an S.M.P.S. design canproduce very compact and lightweight supplies. This is nowan essential requirement for the majority of electronicsystems. The supply must slot into an ever shrinking spaceleft for it by electronic system designers.

OutlineAt the heart of the converter is the high frequency invertersection, where the input supply is chopped at very highfrequencies (20 to200kHz using present technologies) thenfiltered and smoothed to produce dc outputs. The circuitconfiguration which determines how the power is

transferred is called the TOPOLOGY of the S.M.P.S., andis an extremely important part of the design process. Thetopology consists of an arrangement of transformer,inductors, capacitors and power semiconductors (bipolaror MOSFET power transistors and power rectifiers).

Presently, there is a very wide choice of topologiesavailable, each one having its own particular advantagesand disadvantages, making it suitable for specific powersupply applications. Basic operation, advantages,drawbacks and most common areas of use for the mostcommon topologies are discussed in the following sections.A selection guide to the Philips range of powersemiconductors (including bipolars, MOSFETs andrectifiers) suitable for use in S.M.P.S. applications is givenat the end of each section.

(1) Basic switched mode supply circuit.

An S.M.P.S. can be a fairly complicated circuit, as can beseen from the block diagram shown in Fig. 1. (Thisconfiguration assumes a 50/60Hz mains input supply isused.) The ac supply is first rectified, and then filtered bythe input reservoir capacitor to produce a rough dc inputsupply. This level can fluctuate widely due to variations inthe mains. In addition the capacitance on the input has tobe fairly large to hold up the supply in case of a severedroop in the mains. (The S.M.P.S. can also be configuredto operate from any suitable dc input, in this case the supplyis called a dc to dc converter.)

Fig. 1. Basic switched mode power supply block diagram.

PowerTransformer

HighFrequency

switch

Output rectificationand filteringand filtering

dc output

voltage

Vref

PWM

OSCcontrolcircuitry

T

ac input

supply

duty cyclecontrol

mosfet orbipolar

Input rectification

107


The unregulated dc is fed directly to the central block of thesupply, the high frequency power switching section. Fastswitching powersemiconductor devices such as MOSFETsand Bipolars are driven on and off, and switch the inputvoltage across the primary of the power transformer. Thedrive pulses are normally fixed frequency (20 to 200kHz)and variable duty cycle. Hence, a voltage pulse train ofsuitable magnitude and duty ratio appears on thetransformer secondaries. This voltage pulse train isappropriately rectified, and then smoothed by the outputfilter, which is either a capacitor or capacitor / inductorarrangement, depending upon the topology used. Thistransfer ofpower has to be carried out with the lowest lossespossible, to maintain efficiency. Thus, optimum design ofthe passive and magnetic components, and selection of thecorrect power semiconductors is critical.

Regulation of the output to provide a stabilised dc supplyis carried out by the control / feedback block. Generally,most S.M.P.S. systems operate on a fixed frequency pulsewidth modulation basis, where the duration of the on timeof the drive to the power switch is varied on a cycle by cyclebasis. This compensates for changes in the input supplyand output load. The output voltage is compared to anaccurate reference supply, and the error voltage producedby the comparator is used by dedicated control logic toterminate the drive pulse to the main power switch/switchesat the correct instance. Correctly designed, this will providea very stable dc output supply.

It is essential that delays in the control loop are kept to aminimum,otherwise stability problems would occur. Hence,very high speed components must be selected for the loop.In transformer-coupled supplies, in order to keep theisolation barrier intact, some type of electronic isolation isrequired in the feedback. This is usually achieved by usinga small pulse transformer or an opto-isolator, hence addingto the component count.

In most applications, the S.M.P.S. topology contains apower transformer. This provides isolation, voltage scalingthrough the turns ratio, and the ability to provide multipleoutputs. However, there are non-isolated topologies(without transformers) such as the buck and the boostconverters, where the power processing is achieved byinductive energy transfer alone. All of the more complexarrangements are based on these non-isolated types.

(2) Non-Isolated converters.The majority of the topologies used in today’s convertersare all derived from the following three non-isolatedversions called the buck, the boost and the buck-boost.These are the simplest configurations possible, and havethe lowest component count, requiring only one inductor,capacitor, transistor and diode to generate their singleoutput. If isolation between the input and output is required,a transformer must be included before the converter.

(a) The Buck converter.

The forward converter family which includes the push-pulland bridge types, are all based on the buck converter,shown in Fig. 2. Its operation is straightforward. Whenswitch TR1 is turned on, the input voltage is applied toinductor L1 and power is delivered to the output. Inductorcurrent also builds up according to Faraday’s law shownbelow:-

When the switch is turned off, the voltage across theinductor reverses and freewheel diode D1 becomesforwardbiased. Thisallows the energy stored in the inductorto be delivered to the output. This continuous current is thensmoothed by output capacitor Co. Typical buck waveformsare also shown in Fig. 2.

Fig. 2 Buck Regulator (step-down).

The LC filter has an averaging effect on the appliedpulsating input, producing a smooth dc output voltage andcurrent, with very small ripple components superimposed.The average voltage/sec across the inductor over acomplete switching cycle must equal zero in the steadystate. (The same applies to all of the regulators that will bediscussed.)

V = LdIdt

Vin Vo

CONTROL

CIRCUIT

Vo

L1

D1 Co

TR1

T = ton + toff

ton

toff

Appliedvoltage v

A

Vin

Vin - Vo

Io

Vo

Vo

Inductorcurrent

IL

Inductorvoltage V

L

TR1current Iin I D

ton toffT

0

0

0

0

t

t

t

tContinuous mode

108


Neglecting circuit losses, the average voltage at the inputside of the inductor is VinD, while Vo is the output sidevoltage. Thus, in the steady state, for the average voltageacross the inductor to be zero, the basic dc equation of thebuck is simply:-

D is the transistor switch duty cycle, defined as theconduction time divided by one switching period, usuallyexpressed in the form shown below:-

Thus, the buck is a stepdown type, where the output voltageis always lower than the input. (Since D never reaches one.)Output voltage regulation is provided by varying the dutycycle of the switch. The LC arrangement provides veryeffective filtering of the inductor current. Hence, the buckand its derivatives all have very low output ripplecharacteristics. The buck is normally always operated incontinuous mode ( inductor current never falls to zero)where peak currents are lower, and the smoothingcapacitor requirements are smaller. There are no majorcontrol problems with the continuous mode buck.

(b) The Boost Converter.Operation of another fundamental regulator, the boost,shown in Fig. 3 is more complex than the buck. When theswitch is on, diode D1 is reverse biased, and Vin is appliedacross inductor, L1. Current builds up in the inductor to apeak value, either from zero current in a discontinuousmode, or an initial value in the continuous mode. When theswitch turns off, the voltage across L1 reverses, causingthe voltage at the diode to rise above the input voltage. Thediode then conducts the energy stored in the inductor, plusenergy direct from the supply to the smoothing capacitorand load. Hence, Vo is always greater than Vin, making thisa stepup converter. For continuous mode operation, theboost dc equation is obtained by a similar process as forthe buck, and is given below:-

Again, the output only depends upon the input and dutycycle. Thus, by controlling the duty cycle, output regulationis achieved.

From the boost waveforms shown in Fig. 3, it is clear thatthe current supplied to the output smoothing capacitor fromthe converter is the diode current, which will always bediscontinuous. This means that the output capacitor mustbe large, with a low equivalent series resistance (e.s.r) to

produce a relatively acceptable output ripple. This is incontrast to the buck output capacitor requirementsdescribedearlier. On the other hand, the boost input currentis the continuous inductor current, and this provides lowinput ripple characteristics. The boost is very popular forcapacitive load applications such as photo-flashers andbattery chargers. Furthermore, the continuous input currentmakes the boost apopular choice as apre-regulator, placedbefore the main converter. The main functions being toregulate the input supply, and to greatly improve the linepower factor. This requirement has become very importantin recent years, in a concerted effort to improve the powerfactor of the mains supplies.

Fig. 3 Boost Regulator (step-up).

If the boost is used in discontinuous mode, the peaktransistor and diode currents will be higher, and the outputcapacitor will need to be doubled in size to achieve thesame output ripple as in continuous mode. Furthermore, indiscontinuous operation, the output voltage also becomesdependent on the load, resulting in poorer load regulation.

Unfortunately, there are major control and regulationproblems with the boost when operated in continuousmode. The pseudo LC filter effectively causes a complexsecond order characteristic in the small signal (control)response. In the discontinuous mode, the energy in theinductor at the start of each cycle is zero. This removes theinductance from the small signal response, leaving only theoutput capacitance effect. This produces a much simplerresponse, which is far easier to compensate and control.

Vo

Vi

= D

D =ton

T; where T= ton + toff

Vin Vo

CONTROLCIRCUIT

Vo

L1

CoTR1

D1

Inductorcurrent

IL

TR1current

ton toff

T

0

0

0

0

t

t

t

t

Vo

I in

TR1

voltage

Vce

Diode

current

ID Io

CONTINUOUS MODE

Vo

Vi

=1

1− D

109


(c) The Buck-Boost Regulator(Non-isolated Flyback).

The very popular flyback converter (see section 5(a)) is notactually derived solely from the boost. The flyback onlydelivers stored inductor energy during the switch off-time.The boost, however, also delivers energy from the input.The flyback is actually based on a combined topology ofthe previous two, called the buck-boost or non isolatedflyback regulator. This topology is shown in Fig. 4.

Fig. 4 Buck-Boost (Flyback) Regulator.

When the switch is on, the diode is reverse biased and theinput is connected across the inductor, which stores energyas previously explained. At turn-off, the inductor voltagereverses and the stored energy is then passed to thecapacitor and load through the forward biased rectifierdiode.

The waveforms are similar to the boost except that thetransistor switch now has to support the sum of Vin and Voacross it. Clearly, both the input and output currents mustbe discontinuous. There is also a polarity inversion, theoutput voltage generated is negative with respect to theinput. Close inspection reveals that the continuous modedc transfer function is as shown below:-

Observation shows that the value of the switch duty ratio,D can be selected such that the output voltage can eitherbe higher or lower than the input voltage. This gives theconverter the flexibility to either step up or step down thesupply.

This regulator also suffers from the same continuous modecontrol problems as the boost, and discontinuous mode isusually favoured.

Since both input and output currents are pulsating, lowripple levels are very difficult to achieve using thebuck-boost. Very large output filter capacitors are needed,typically up to 8 times that of a buck regulator.The transistor switch also needs to be able to conduct thehigh peak current, as well as supporting the higher summedvoltage. The flyback regulator (buck-boost) topology placesthe most stress on the transistor. The rectifier diode alsohas to carry high peak currents and so the r.m.s conductionlosses will be higher than those of the buck.

Vo

Vi

=D

1− D

Vin

CONTROL

CIRCUIT

Vo L1

D1

Co

TR1-Vo

Step up / down Polarity inversion

110


(3) Transformers in S.M.P.S. converters.The non-isolated versions have very limited use, such asdc-dc regulators only capable of producing a single output.The output range is also limited by the input and duty cycle.The addition of a transformer removes most of theseconstraints and provides a converter with the followingadvantages:-1) Input to output isolation is provided. This is normallyalways necessary for 220 / 110 V mains applications, wherea degree of safety is provided for the outputs.2) The transformer turns ratio can be selected to provideoutputs widely different from the input; non-isolatedversions are limited to a range of approximately 5 times.By selecting the correct turns ratio, the duty cycle of theconverter can also be optimised and the peak currentsflowing minimised. The polarity of each output is alsoselectable, dependent upon the polarity of the secondaryw.r.t the primary.3) Multiple outputs are very easily obtained, simply byadding more secondary windings to the transformer.There are some disadvantages with transformers, such astheir additional size, weight and power loss. The generationof voltage spikes due to leakage inductance may also be aproblem.

The isolated converters to be covered are split into two maincategories, called asymmetrical and symmetricalconverters, depending upon how the transformer isoperated.

Fig. 5 Comparative core usage of asymmetrical andsymmetrical converters.

In asymmetrical converters the magnetic operating point ofthe transformer is always in one quadrant i.e the flux andthe magnetic field never changes sign. The core has to bereset each cycle to avoid saturation, meaning that only halfof the usable flux is ever exploited. This can be seen inFig. 5, which shows the operating mode of each converter.The flyback and forward converter are both asymmetricaltypes. The diagram also indicates that the flyback converteris operated at a lower permeability (B/H) and lowerinductance than the others. This is because the flybacktransformeractually stores all of the energy before dumpinginto the load, hence an air gap is required to store thisenergy and avoid core saturation. The air gap has the effectof reducing the overall permeability of the core. All of theother converters have true transformer action and ideallystore no energy, hence, no air gap is needed.

In the symmetrical converters which always require an evennumber of transistor switches, the full available flux swingin both quadrants of the B / H loop is used, thus utilisingthe core much more effectively. Symmetrical converterscan therefore produce more power than their asymmetricalcousins. The 3 major symmetrical topologies used inpractice are the push-pull, the half-bridge and the full bridgetypes.

Table 1 outlines the typical maximum output poweravailable from each topology using present daytechnologies:-

Converter Topology Typical max output power

Flyback 200W

Forward 300W

Two transistor forward / 400Wflyback

Push-pull 500W

Half-Bridge 1000W

Full-Bridge >1000W

Table 1. Converter output power range.

Many other topologies exist, but the types outlined in Table1 are by far the most commonly used in present S.M.P.S.designs. Each is now looked at in more detail, with aselection guide for the most suitable Philips powersemiconductors included.

B

H

Bs

2Bs

flybackconverter

forwardconverter

symmetricalconverters

asymmetricalconverters

symmetricalconverters

availableflux swing

111


(4) Selection of the powersemiconductors.The Power Transistor.

The two most common power semiconductors used in theS.M.P.S.are the Bipolar transistor and the power MOSFET.The Bipolar transistor is normally limited to use atfrequencies up to 30kHz, due to switching loss. However,it has very low on-state losses and is a relatively cheapdevice, making it the most suitable for lower frequencyapplications. The MOSFET is selected for higher frequencyoperation because of its very fast switching speeds,resulting in low (frequency dependent) switching losses.The driving of the MOSFET is also far simpler and lessexpensive than that required for the Bipolar. However, theon-state losses of the MOSFET are far higher than theBipolar, and they are also usually more expensive. Theselection of which particular device to use is normally acompromise between the cost, and the performancerequired.

(i) Voltage limiting value:-

After deciding upon whether to use a Bipolar or MOSFET,the next step in deciding upon a suitable type is by thecorrect selection of the transistor voltage. For transformercoupled topologies, the maximum voltage developedacross the device is normally at turn-off. This will be eitherhalf, full ordouble the magnitude of the input supply voltage,dependent upon the topology used. There may also be asignificant voltage spike due to transformer leakageinductance that must be included. The transistor mustsafely withstand these worst case values without breakingdown. Hence, for a bipolar device, a suitably high Vces(max)

must be selected, and for a MOSFET, a suitably highVBR(DSS). At present 1750V is the maximum blocking voltageavailable for power Bipolars, and a maximum of 1000V forpower MOSFETs.

The selection guides assume that a rectified 220V or 110Vmains input is used. The maximum dc link voltages that willbe produced for these conditions are 385V and 190Vrespectively. These values are the input voltage levels usedto select the correct device voltage rating.

(ii) Current limiting value:-

The Bipolar device has a very low voltage drop across itduring conduction, which is relatively constant within therated current range. Hence, for maximum utilisation of abipolar transistor, it should be run close to its ICsat value.This gives a good compromise between cost, driverequirements and switching. The maximum current for aparticular throughput power is calculated for each topology

using simple equations. These equations are listed in theappropriate sections, and the levels obtained used to selecta suitable Bipolar device.

The MOSFET device operates differently from the bipolarin that the voltage developed across it (hence, transistordissipation) is dependent upon the current flowing and thedevice "on-resistance" which is variable with temperature.Hence, the optimum MOSFET for a given converter canonly be chosen on the basis that the device must not exceeda certain percentage of throughput (output) power. (In thisselection a 5% loss in the MOSFET was assumed). A setof equations used to estimate the correct MOSFET RDS(on)

value for a particular power level has been derived for eachtopology. These equations are included in Appendix A atthe end of the paper. The value of RDS(on) obtained wasthen used to select a suitable MOSFET device for eachrequirement.

NOTE! This method assumes negligible switching lossesin the MOSFET. However for frequencies above 50kHz,switching losses become increasingly significant.

Rectifiers

Two types of output rectifier are specified from the Philipsrange. For very low output voltages below 10V it isnecessary to have anextremely lowrectifier forward voltagedrop, VF, in order to keep converter efficiency high. Schottkytypes are specified here, since they have very low VF values(typically 0.5V). The Schottky also has negligible switchinglosses and can be used at very high frequencies.Unfortunately, the very low VFof the Schottky is lostat higherreverse blocking voltages (typically above 100V ) and otherdiode types become more suitable. This means that theSchottky is normally reserved for use on outputs up to 20Vor so.

Note. A suitable guideline in selecting the correct rectifierreverse voltage is to ensure the device will block 4 to 6 timesthe output voltage it is used to provide (depends on topologyand whether rugged devices are being used).

For higher voltage outputs the most suitable rectifier is thefast recovery epitaxial diode (FRED). This device has beenoptimised for use in high frequency rectification. Itscharacteristics include low VF (approx. 1V) with very fastand efficient switching characteristics. The FRED hasreverse voltage blocking capabilities up to 800V. They aretherefore suitable for use in outputs from 10 to 200V.

The rectifier devices specified in each selection guide werechosen as having the correct voltage limiting value and highenough current handling capability for the particular outputpower specified. (A single output is assumed).

112


(5) Standard isolated topologies.

(a) The Flyback converter.Operation

Of all the isolated converters, by far the simplest is thesingle-ended flyback converter shown in Fig. 6. The use ofa single transistor switch means that the transformer canonly be driven unipolar (asymmetrical). This results in alarge core size. The flyback, which is an isolated version ofthe buck-boost, does not in truth contain a transformer buta coupled inductor arrangement. When the transistor isturned on, current builds up in the primary and energy isstored in the core, this energy is then released to the outputcircuit through the secondary when the switch is turned off.(A normal transformer such as the types used in the buckderived topologies couples the energy directly duringtransistor on-time, ideally storing no energy).

Fig. 6 Flyback converter circuit and waveforms.

The polarity of the windings is such that the output diodeblocks during the transistor on time. When the transistorturns off, the secondary voltage reverses, maintaining aconstant flux in the core and forcing secondary current toflow through the diode to the output load. The magnitude

of the peak secondary current is the peak primary currentreached at transistor turn-off reflected through the turnsratio, thus maintaining a constant Ampere-turn balance.

The fact that all of the output power of the flyback has tobe stored in the core as 1/2LI2 energy means that the coresize and cost will be much greater than in the othertopologies, where only the core excitation (magnetisation)energy, which is normally small, is stored. This, in additionto the initial poor unipolar core utilisation, means that thetransformer bulk is one of the major drawbacks of theflyback converter.

In order to obtain sufficiently high stored energy, the flybackprimary inductance has to be significantly lower thanrequired for a true transformer, since high peak currentsare needed. This is normally achieved by gapping the core.The gap reduces the inductance, and most of the high peakenergy is then stored in the gap, thus avoiding transformersaturation.

When the transistor turns off, the output voltage is backreflected through the transformer to the primary and in manycases this can be nearly as high as the supply voltage.There is also a voltage spike at turn-off due to the storedenergy in the transformer leakage inductance. This meansthat the transistor must be capable of blockingapproximately twice the supply voltage plus the leakagespike. Hence, for a 220V ac application where the dc linkcan be up to 385V, the transistor voltage limiting value mustlie between 800 and 1000V.

Using a 1000V Bipolar transistor such as the BUT11A orBUW13A allows a switching frequency of 30kHz to be usedat output powers up to 200Watts.

MOSFETs with 800V and 1000V limiting values can alsobeused, suchas the BUK456-800A which cansupply 100Wat switching frequencies anywhere up to 300kHz. Althoughthe MOSFET can be switched much faster and has lowerswitching losses , it does suffer from significant on-statelosses, especially in the higher voltage devices whencompared to the bipolars. An outline of suitable transistorsand output rectifiers for different input and power levelsusing the flyback is given in Table 2.

One way of removing the transformer leakage voltage spikeis to add a clamp winding as shown in Fig. 8. This allowsthe leakage energy to be returned to the input instead ofstressing the transistor. The diode is always placed at thehigh voltage end so that the clamp winding capacitancedoes not interfere with the transistor turn-on current spike,which would happen if the diode was connected to ground.This clamp is optional and depends on the designer’sparticular requirements.

T1

n:1

Vo

Co

D1

Vin

TR1

IP

Isw

Primarycurrent

seccurrent

I

ID

S

Ip = Vin.ton/Lp

Isec = Idiode

Switchvoltage

Vceor

Vds

ton toff

Vin

leakageinductance

spike

T

t

t

t0

0

0

(discontinuous)

Discontinuous

Vin + Vo n1

n2

113


Advantages.

The action of the flyback means that the secondaryinductance is in series with the output diode when currentis delivered to the load; i.e driven from a current source.This means that no filter inductor is needed in the outputcircuit. Hence, each output requires only one diode andoutput filter capacitor. This means the flyback is the idealchoice for generating low cost,multiple output supplies.Thecross regulation obtained using multiple outputs is also verygood (load changes on one output have little effect on theothers) because of the absence of the output choke, whichdegrades this dynamic performance.

The flyback is also ideally suited for generating high voltageoutputs. If a buck type LC filter was used to generate a highvoltage, a very large inductance value would be needed toreduce the ripple current levels sufficiently to achieve thecontinuous mode operation required. This restriction doesnot apply to the flyback, since it does not require an outputinductance for successful operation.

Disadvantages.

From the flyback waveforms in Fig. 6 it is clear that theoutput capacitor is only supplied during the transistor offtime. This means that the capacitor has to smooth apulsating output current which has higher peak values thanthe continuous output current that would be produced in aforward converter, for example. In order to achieve lowoutput ripple, very large output capacitors are needed, withvery low equivalent series resistance (e.s.r). It can beshown that at the same frequency, an LC filter isapproximately 8 times more effective at ripple reductionthan a capacitor alone. Hence, flybacks have inherentlymuch higher output ripples than other topologies. This,together with the higher peak currents, large capacitors andtransformers, limits the flyback to lower output powerapplications in the 20 to 200W range. (It should be notedthat at higher voltages, the required output voltage ripplemagnitudes are not normally as stringent, and this meansthat the e.s.r requirement and hence capacitor size will notbe as large as expected.)

Two transistor flyback.

One possible solution to the 1000V transistor requirementis the two transistor flyback version shown in Fig. 7. Bothtransistors are switched simultaneously, and all waveformsare exactly the same, except that the voltage across eachtransistor never exceeds the input voltage. The clampwinding is now redundant, since the two clamp diodes actto return leakage energy to the input. Two 400 or 500Vdevices can now be selected, which will have fasterswitching and lower conduction losses. The output powerand switching frequencies can thus be significantlyincreased. The drawbacks of the two transistor version arethe extra cost and more complex isolated base driveneeded for the top floating transistor.

Fig. 7 Two transistor Flyback.

Continuous Vs Discontinuous operation.

As with the buck-boost, the flyback can operate in bothcontinuous and discontinuous modes. The waveforms inFig. 6 show discontinuous mode operation. Indiscontinuous mode, the secondary current falls to zero ineach switching period, and all of the energy is removedfrom the transformer. In continuous mode there is currentflowing in the coupled inductor at all times, resulting intrapezoidal current waveforms.The main plus of continuous mode is that the peak currentsflowing are only half that of the discontinuous for the sameoutput power, hence, lower output ripple is possible.However, the core size is about 2 to 4 times larger incontinuous mode to achieve the increased inductanceneeded to reduce the peak currents to achieve continuity.

A further disadvantage of continuous mode is that theclosed loop is far more difficult to control than thediscontinuous mode flyback. (Continuous mode contains aright hand plane zero in its open loop frequency response,the discontinuous flyback does not. See Ref[2] for furtherexplanation.) This means that much more time and effortis required for continuous mode to design the much morecomplicated compensation components needed to achievestability.

There is negligible turn-on dissipation in the transistor indiscontinuous mode, whereas this dissipation can be fairlyhigh in continuous mode, especially when the additionaleffects of the output diode reverse recovery current, whichonly occurs in the continuous case, is included. Thisnormally means that a snubber must be added to protectthe transistor against switch-on stresses.

One advantage of the continuous mode is that its open loopgain is independent of the output load i.e Vo only dependsupon D and Vin as shown in the dc gain equation at the endof the section. Continuous mode has excellent open loopload regulation, i.e varying the output load will not affect Vo.Discontinuous mode, on the other-hand, does have adependency on the output, expressed as RL in the dc gainequation. Hence, discontinuous mode has a much poorer

Vo

Vin

T1

Co

n : 1

TR1

D1TR2

isolatedbasedrive

114


open loop load regulation, i.e changing the output will affectVo. This problem disappears, however, when the controlloop is closed, and the load regulation problem is usuallycompletely overcome.

The use of current mode control with discontinuous flyback(where both the primary current and output voltage aresensed and combined to control the duty cycle) produces

a much improved overall loop regulation, requiring lessclosed loop gain.

Although the discontinuous mode has the majordisadvantage of very high peak currents and a large outputcapacitor requirement, it is much easier to implement, andis by far the more common of the two methods used inpresent day designs.

Output power 50W 100W 200W

Line voltage, Vin 110V ac 220V ac 110V ac 220V ac 110V ac 220V ac

Transistor requirementsMax current 2.25A 1.2A 4A 2.5A 8A 4.4AMax voltage 400V 800V 400V 800V 400V 800V

Bipolar transistors.TO-220 BUT11 BUX85 BUT12 BUT11A --- BUT12A

Isolated SOT-186 BUT11F BUX85F BUT12F BUT11AF --- BUT12AFSOT-93 --- --- --- --- BUW13 ---

Isolated SOT-199 --- --- --- --- BUW13F ---

Power MOSFETTO-220 BUK454-400B BUK454-800A BUK455-400B BUK456-800A --- ---

Isolated SOT-186 BUK444-400B BUK444-800A BUK445-400B BUK446-800A --- ---SOT-93 --- --- --- --- BUK437-400B BUK438-800A

Output RectifiersO/P voltage

5V PBYR1635 PBYR2535CT ---10V PBYR10100 PBYR20100CT PBYR30100PT

BYW29E-100/150/200 BYV79E-100/150/200 BYV42E-100/150/200BYV72E-100/150/200

20V PBYR10100 PBYR10100 PBYR20100CTBYW29E-100/150/200 BYW29E-100/150/200 BYV32E-100/150/200

50V BYV29-300 BYV29-300 BYV29-300100V BYV29-500 BYV29-500 BYV29-500

Table 2. Recommended Power Semiconductors for single-ended flyback.

Note! The above values are for discontinuous mode. In continuous mode the peak transistor currents are approximatelyhalved and the output power available is thus increased.

FlybackConverter efficiency, η = 80%; Max duty cycle, Dmax = 0.45

Max transistor voltage, Vce or Vds = 2Vin(max) + leakage spike

dc voltage gain:- (a) continuous (b) Discontinuous

Applications:- Lowest cost, multiple output supplies in the 20 to 200W range. E.g. mains input T.V. supplies, smallcomputer supplies, E.H.T. supplies.

Maxtransistorcurrent, IC ; ID = 2Pout

η Dmax Vmin

VoVin

= nD

1− DVoVin

= D√RL T

2 LP

115


(b) The Forward converter.Operation.

The forward converter is also a single switch isolatedtopology, and is shown in Fig. 8. This is based on the buckconverter described earlier, with the addition of atransformer and another diode in the output circuit. Thecharacteristic LC output filter is clearly present.

In contrast to the flyback, the forward converter has a truetransformer action, where energy is transferred directly tothe output through the inductor during the transistoron-time. It can be seen that the polarity of the secondarywinding is opposite to that of the flyback, hence allowingdirect current flow through blocking diode D1. During theon-time, the current flowing causes energy to be built up inthe output inductor L1. When the transistor turns off, thesecondary voltage reverses, D1 goes from conducting toblocking mode and the freewheel diode D2 then becomesforward biased and provides a path for the inductor currentto continue to flow. This allows the energy stored in L1 tobe released into the load during the transistor off time.

The forward converter is always operated in continuousmode (in this case the output inductor current), since thisproduces very low peak input and output currents and smallripple components. Going into discontinuous mode wouldgreatly increase these values, as well as increasing theamount of switching noise generated. No destabilising righthand plane zero occurs in the frequency response of theforward in continuous mode (as with the buck). See Ref[2].This means that the control problems that existed with thecontinuous flyback are not present here. So there are noreal advantages to be gained by using discontinuous modeoperation for the forward converter.

Advantages.

As can be seen from the waveforms in Fig. 8, the inductorcurrent IL, which is also the output current, is alwayscontinuous. The magnitude of the ripple component, andhence the peak secondary current, depends upon the sizeof the output inductor. Therefore, the ripple can be maderelatively small compared to the output current, with thepeak current minimised. This low ripple, continuous outputcurrent is very easy to smooth, and so the requirements forthe output capacitor size, e.s.r and peak current handlingare far smaller than they are for the flyback.

Since the transformer in this topology transfers energydirectly there is negligible stored energy in the corecompared to the flyback. However, there is a smallmagnetisation energy required to excite the core, allowingit to become an energy transfer medium. This energy isvery small and only a very small primary magnetisationcurrent is needed. This means that a high primary

inductance is usually suitable, with no need for the core airgap required in the flyback. Standard un-gapped ferritecores with high permeabilities (2000-3000) are ideal forproviding the high inductance required. Negligible energystorage means that the forward converter transformer isconsiderably smaller than the flyback, and core loss is alsomuch smaller for the same throughput power. However, thetransformer is still operated asymmetrically, which meansthat power is only transferred during the switch on-time,and this poor utilisation means the transformer is still farbigger than in the symmetrical types.

The transistors have the same voltage rating as thediscontinuous flyback (see disadvantages), but the peakcurrent required for the same output power is halved, andthis can be seen in the equations given for the forwardconverter. This, coupled with the smaller transformer andoutput filter capacitor requirements means that the forwardconverter is suitable for use at higher output powers thanthe flyback can attain, and is normally designed to operatein the 100 to 400W range. Suitable bipolars and MOSFETsfor the forward converter are listed in Table 3.

Fig. 8 The Forward converter and waveforms.

CONTROL

CIRCUIT

Vo

Vo

Vin

T1 D1

Co

n : 1

TR1

D2

L1

D3

Clamp

winding

necessary

IoInductorcurrent

IL

TR1current

ton toff

T

0

0

0

t

t

t

t

Diodecurrents Id1 Id2

Ip

output

TR1voltage

Vce Vin 2Vin

tImag

0

0

Id3

Is

116


Disadvantages.

Because of the unipolar switching action of the forwardconverter, there is a major problem in how to remove thecore magnetisation energy by the end of each switchingcycle. If this did not happen, there would be a net dc fluxbuild-up, leading to core saturation, and possible transistordestruction. This magnetisation energy is removedautomatically by the push-pull action of the symmetricaltypes. In the flyback this energy is dumped into the load attransistor turn-off. However, there is no such path in theforward circuit.

This path is provided by adding an additional reset windingof opposite polarity to the primary. A clamp diode is added,such that the magnetisation energy is returned to the inputsupply during the transistor off time. The reset winding iswound bifilar with the primary to ensure good coupling, andis normally made to have the same number of turns as theprimary. (The reset winding wire gauge can be very small,since it only has to conduct the small magnetisationcurrent.) The time for the magnetisation energy to fall tozero is thus the same duration as the transistor on-time.This means that the maximum theoretical duty ratio of theforward converter is 0.5 and after taking into accountswitching delays, this falls to 0.45. This limited control rangeis one of the drawbacks of using the forward converter. Thewaveform of the magnetisation current is also shown inFig. 8. The clamp winding in the flyback is optional, but isalways needed in the forward for correct operation.

Due to the presence of the reset winding, in order tomaintain volt-sec balance within the transformer, the inputvoltage is back reflected to the primary from the clampwinding at transistor turn-off for the duration of the flow ofthe magnetisation reset current through D3. (There is alsoa voltage reversal across the secondary winding, and thisis why diode D1 is added to block this voltage from theoutput circuit.) This means that the transistor must blocktwo times Vin during switch-off. The voltage returns to Vinafter reset has finished, which means transistor turn-onlosses will be smaller. The transistors must have the sameadded burden of the voltage rating of the flyback, i.e 400Vfor 110V mains and 800V for 220V mains applications.

Output diode selection.

The diodes in the output circuit both have to conduct thefull magnitude of the output current. They are also subjectto abrupt changes in current, causing a reverse recoveryspike, particularly in the freewheel diode, D2. This spikecan cause additional turn-on switching loss in the transistor,possibly causing device failure in the absence of snubbing.Thus, very high efficiency, fast trr diodes are required tominimise conduction losses and to reduce the reverserecovery spike. These requirements are met with Schottkydiodes for outputs up to 20V, and fast recovery epitaxialdiodes for higher voltage outputs. It is not normal for forwardconverter outputs to exceed 100V because of the need for

a very large output choke, and flybacks are normally used.Usually, both rectifiers are included in a single package i.ea dual centre-tap arrangement. The Philips range ofSchottkies and FREDs which meet these requirements arealso included in Table 3.

Two transistor forward.

In order to avoid the use of higher voltage transistors, thetwo transistor version of the forward can be used. Thiscircuit, shown in Fig. 9, is very similar to the two transistorflyback and has the same advantages. The voltage acrossthe transistor is again clamped to Vin, allowing the use offaster more efficient 400 or 500V devices for 220V mainsapplications. The magnetisation reset is achieved throughthe two clamp diodes, permitting the removal of the clampwinding.

Fig. 9 Two transistor Forward.

The two transistor version is popular for off-lineapplications. It provides higher output powers and fasterswitching frequencies. The disadvantages are again theextra cost of the higher component count, and the need foran isolated drive for the top transistor.

Although this converter has some drawbacks, and utilisesthe transformer poorly, it is a very popular selection for thepower range mentioned above, and offers simple drive forthe single switch and cheap component costs. Multipleoutput types are very common. The output inductors arenormally wound on a single core, which has the effect ofimproving dynamic cross regulation, and if designedcorrectly also reduces the output ripple magnitudes evenfurther. The major advantage of the forward converter isthe very low output ripple that can be achieved for relativelysmall sized LC components. This means that forwardconverters are normally used to generate lower voltage,high current multiple outputs such as 5, 12, 15, 28V frommains off-line applications, where lower ripplespecifications are normally specified for the outputs. Thehigh peak currents that would occur if a flyback was usedwould place an impossible burden on the smoothingcapacitor.

Vo

Vin

T1

Co

n : 1

TR1

D1TR2

isolatedbasedrive

D2

L1

117




Transistor requirementsMax current 2.25A 1.2A 4A 2.5A 6A 3.3AMax voltage 400V 800V 400V 800V 400V 800V






Output Rectifiers (dual)O/P voltage

5V PBYR2535CT --- ---10V PBYR20100CT PBYR30100PT PBYR30100PT

BYV32E-100/150/200 BYV42E-100/150/200 BYV72E-100/150/200BYV72E100/150/200

20V PBYR20100CT PBYR20100CT PBYR20100CTBYQ28E-100/150/200 BYV32E-100/150/200 BYV32E-100/150/200

50V BYT28-300 BYT28-300 BYT28-300

Table 3. Recommended Power Semiconductors for single-ended forward.

ForwardConverter efficiency, η = 80%; Max duty cycle, Dmax = 0.45

Max transistor voltage, Vce or Vds = 2Vin(max)

dc voltage gain:-

Applications:- Low cost, low output ripple, multiple output supplies in the 50 to 400W range. E.g. small computersupplies, DC/DC converters.

Maxtransistorcurrent, IC ; ID =Pout

η Dmax Vmin

VoVin

= n D

118


(c) The Push-pull converter.Operation.

To utilise the transformer flux swing fully, it is necessary tooperate the core symmetrically as described earlier. Thispermits much smaller transformer sizes and provideshigher output powers than possible with the single endedtypes. The symmetrical types always require an evennumber of transistor switches. One of the best known of thesymmetrical types is the push-pull converter shown inFig. 10.

The primary is a centre-tapped arrangement and eachtransistor switch is driven alternately, driving thetransformer in both directions. The push-pull transformer istypically half the size of that for the single ended types,resulting in a more compact design. This push-pull actionproduces natural core resetting during each half cycle,hence no clamp winding is required. Power is transferredto the buck type output circuit during each transistorconduction period. The duty ratio of each switch is usuallyless than 0.45. This provides enough dead time to avoidtransistor cross conduction. The power can now betransferred to the output for up to 90% of the switchingperiod, hence allowing greater throughput power than withthe single-ended types. The push-pull configuration isnormally used for output powers in the 100 to 500W range.

Fig. 10 Push-pull converter.

The bipolar switching action also means that the outputcircuit is actually operated at twice the switching frequencyof the power transistors, as can be seen fromthe waveformsin Fig. 11. Therefore, the output inductor and capacitor canbe even smaller for similar output ripple levels. Push-pullconverters are thus excellent for high power density, lowripple outputs.

Advantages.

As stated, the push-pull offers very compact design of thetransformer and output filter, while producing very lowoutput ripple. So if space is a premium issue, the push-pullcould be suitable. The control of the push-pull is similar tothe forward, in that it is again based on the continuous mode

buck. When closing the feedback control loop,compensation is relatively easy. For multiple outputs, thesame recommendations given for the forward converterapply.

Clamp diodes are fitted across the transistors, as shown.This allows leakage and magnetisation energy to be simplychannelled back to the supply, reducing stress on theswitches and slightly improving efficiency.

The emitter or source of the power transistors are both atthe same potential in the push-pull configuration, and arenormally referenced to ground. This means that simplebase drive can be used for both, and no costly isolatingdrive transformer is required. (This is not so for the bridgetypes which are discussed latter.)

Disadvantages.

One of the main drawbacks of the push-pull converter isthe fact that each transistor must block twice the inputvoltage due to the doubling effect of the centre-tappedprimary, even though two transistors are used. This occurswhen one transistor is off and the other is conducting. Whenboth are off, each then blocks the supply voltage, this isshown in the waveforms in Fig. 11. This means that TWOexpensive, less efficient 800 to 1000V transistors would berequired for a 220V off-line application. A selection oftransistors and rectifiers suitable for the push-pull used inoff-line applications is given in Table 4.

A further major problem with the push-pull is that it is proneto flux symmetry imbalance. If the flux swing in each halfcycle is not exactly symmetrical, the volt-sec will notbalance and this will result in transformer saturation,particularly for high input voltages. Symmetry imbalancecan be caused by different characteristics in the twotransistors such as storage time in a bipolar and differenton-state losses.

The centre-tap arrangement also means that extra copperis needed for the primary, and very good coupling betweenthe two halves is necessary to minimise possible leakagespikes. It should also be noted that if snubbers are used toprotect the transistors, the design must be very precisesince each tends to interact with the other. This is true forall symmetrically driven converters.

These disadvantages usually dictate that the push-pull isnormally operated at lower voltage inputs such as 12, 28or 48V. DC-DC converters found in the automotive andtelecommunication industries are often push-pull designs.At these voltage levels, transformer saturation is easier toavoid.

Since the push-pull is commonly operated with low dcvoltages, a selection guide for suitable power MOSFETs isalso included for 48 and 96V applications, seen in Table 5.

VoT1 D1

Co

n : 1

TR1

D2

L1

TR2

Vin

119


Current mode control.

The introduction of current mode control circuits has alsobenefited the push-pull type. In this type of control, theprimary current is monitored, and any imbalance whichoccurs is corrected on a cycle by cycle basis by varying theduty cycle immediately. Current mode control completely

removes the symmetry imbalance problem, and thepossibilities of saturation are minimised. This has meantthat push-pull designs have become more popular in recentyears, with some designers even using them in off-lineapplications.

Fig. 11 Push Pull waveforms.

Transistor

ITR1 I

TR2

TR1voltage

TR2voltage

D1current

D2current

outputinductorcurrent I

L

0

0

0

0

0

0

t

t

t

t

t

t

ton ton1 2

T

Vin 2Vin

2Vin Vin

currents

120




Transistor requirementsMax current 1.2A 0.6A 4.8A 3.0A 5.8A 3.1AMax voltage 400V 800V 400V 800V 400V 800V







5V PBYR2535CT --- ---10V PBYR20100CT PBYR30100PT ---

BYV32E-100/150/200 BYV72E-100/150/200 BYT230PI-20020V PBYR20100CT PBYR20100CT PBYR30100PT

BYQ28E-100/150/200 BYV32E-100/150/200 BYV42E-100/150/200BYV72E-100/150/200

50V BYT28-300 BYT28-300 BYV34-300

Table 4. Recommended Power Semiconductors for off-line Push-pull converter.


Line voltage, Vin 96V dc 48V dc 96V dc 48V dc 96V dc 48V dc

Power MOSFETTO-220 BUK455-400B BUK454-200A BUK457-400B BUK456-200B --- ---

Isolated SOT-186 BUK445-400B BUK444-200A BUK437-400B BUK436-200B --- ---SOT-93 --- --- --- --- BUK437-400B ---

Table 5. Recommended power MOSFETs for lower input voltage push-pull.

Push-Pull converter.Converter efficiency, η = 80%; Max duty cycle, Dmax = 0.9

Max transistor voltage, Vce or Vds = 2Vin(max) + leakage spike.

dc voltage gain:-

Applications:- Compact design, very low output ripple supplies in the 100 to 500W range. More suited to low inputapplications. E.g. battery, 28, 40V inputs, high current outputs. Telecommunication supplies.


η Dmax Vmin

VoVin

= 2 n D

121


(d) The Half-Bridge.Of all the symmetrical high power converters, thehalf-bridge converter shown in Fig. 12 is the most popular.It is also referred to as the single ended push-pull, and inprinciple is a balanced version of the forward converter.Again it is a derivative of the buck. The Half-Bridge hassome key advantages over the push-pull, which usuallymakes it first choice for higher power applications in the500 to 1000W range.

Operation.

The two mains bulk capacitors C1 and C2 are connectedin series, and an artificial input voltage mid-point isprovided, shown as point A in the diagram. The twotransistor switches are driven alternately, and this connectseach capacitor across the single primary winding each halfcycle. Vin/2 is superimposed symmetrically across theprimary in a push-pull manner. Power is transferred directlyto the output on each transistor conduction time and amaximum duty cycle of 90% is available (Some dead timeis required to prevent transistor cross-conduction.) Sincethe primary is driven in both directions, (natural reset) a fullwave buck output filter (operating at twice the switchingfrequency) rather than a half wave filter is implemented.This again results in very efficient core utilisation. As canbe seen in Fig. 13, the waveforms are identical to thepush-pull, except that the voltage across the transistors ishalved. (The device current would be higher for the sameoutput power.)

Fig. 12 Half-Bridge converter.

Advantages.

Since both transistors are effectively in series, they neversee greater than the supply voltage, Vin. When both are off,their voltages reach an equilibrium point of Vin/2. This is halfthe voltage rating of the push-pull (although double the

current). This means that the half-bridge is particularlysuited to high voltage inputs, such as off-line applications.For example, a 220V mains application can use two higherspeed, higher efficiency 450V transistors instead of the800V types needed for a push-pull. This allows higherfrequency operation.

Another major advantage over the push-pull is that thetransformer saturation problems due to flux symmetryimbalance are not a problem. By using a small capacitor(less than 10µF) any dc build-up of flux in the transformeris blocked, and only symmetrical ac is drawn from the input.

The configuration of the half-bridge allows clamp diodes tobe added across the transistors, shown as D3 and D4 inFig. 12. The leakage inductance and magnetisationenergies are dumped straight back into the two inputcapacitors, protecting the transistors from dangeroustransients and improving overall efficiency.

A less obvious exclusive advantage of the half-bridge isthat the two series reservoir capacitors already exist, andthis makes it ideal for implementing a voltage doublingcircuit. This permits the use of either 110V /220V mains asselectable inputs to the supply.

The bridge circuits also have the same advantages overthe single-ended types that the push-pull possesses,including excellent transformer utilisation, very low outputripple,andhigh outputpower capabilities. The limiting factorin the maximum output power available from the half-bridgeis the peak current handling capabilities of present daytransistors. 1000W is typically the upper power limit. Forhigher output powers the four switch full bridge is normallyused.

Disadvantages.

The need for two 50/60 Hz input capacitors is a drawbackbecause of their large size. The top transistor must alsohave isolated drive, since the gate / base is at a floatingpotential. Furthermore, if snubbers are used across thepower transistors, great care must be taken in their design,since the symmetrical action means that they will interactwith one another. The circuit cost and complexity haveclearly increased, and this must be weighed up against theadvantages gained. In many cases, this normally excludesthe use of the half-bridge at output power levels below500W.

Suitable transistors and rectifiers for the half-bridge aregiven in Table 6.

Vo

T1

D1

Co

n : 1

TR1

D2

L1

TR2

Vin

isolateddriveneeded

D3

D4

C1

C2

C3

A

122


Fig. 13 Half-Bridge waveforms.

Transistor

ITR1 I

TR2

TR1voltage

TR2voltage

D1current

D2current

outputinductorcurrent I

L

0

0

0

0

0

0

t

t

t

t

t

t

ton ton1 2

T

currents

Vin2

Vin2

Vin

Vin

123





Bipolar transistors.TO-220 BUT12 BUT11 --- --- --- ---

Isolated SOT-186 BUT12F BUT11F --- --- --- ---SOT-93 --- --- BUW13 BUW13 --- BUW13

Isolated SOT-199 --- --- BUW13F BUW13F --- BUW13F

Power MOSFETSOT-93 --- BUK437-500B --- --- --- ---


5V --- --- ---10V PBYR30100PT --- ---

BYV72E-100/150/20020V PBYR20100CT PBYR30100PT ---

BYV32E-100/150/200 BYV42E-100/150/200BYV72E-100/150/200

50V BYT28-300 BYV34-300 BYV34-300

Table 6. Recommended Power Semiconductors for off-line Half-Bridge converter.

Half-Bridge converter.Converter efficiency, η = 80%; Max duty cycle, Dmax = 0.9

Max transistor voltage, Vce or Vds = Vin(max) + leakage spike.

dc voltage gain:-

Applications:- High power, up to 1000W. High current, very low output ripple outputs. Well suited for high inputvoltage applications. E.g. 110, 220, 440V mains. E.g. Large computer supplies, Lab equipment supplies.

Maxtransistorcurrent, IC ; ID = 2Pout

η Dmax Vmin

VoVin

= n D

124


(e) The Full-Bridge.Outline.

The Full-Bridge converter shown in Fig. 14 is a higherpower version of the Half-Bridge, and provides the highestoutput power level of any of the converters discussed. Themaximum current ratings of the power transistors willeventually determine the upper limit of the output power ofthe half-bridge. These levels can be doubled by using theFull-Bridge, which is obtained by adding another twotransistors and clamp diodes to the Half-Bridgearrangement. The transistors are driven alternately in pairs,T1 and T3, then T2 and T4. The transformer primary is nowsubjected to the full input voltage. The current levels flowingare halved compared to the half-bridge for a given powerlevel. Hence, the Full-Bridge will double the output powerof the Half-Bridge using the same transistor types.

The secondary circuit operates in exactly the same manneras the push-pull and half-bridge, also producing very lowripple outputs at very high current levels. Therefore, thewaveforms for the Full-Bridge are identical to theHalf-Bridge waveforms shown in Fig. 13, except for thevoltage across the primary, which is effectively doubled(and switch currents halved). This is expressed in the dcgain and peak current equations, where the factor of twocomes in, compared with the Half-Bridge.

Advantages.

As stated, the Full-Bridge is ideal for the generation of veryhigh output power levels. The increased circuit complexitynormally means that the Full-Bridge is reserved forapplications with power output levels of 1kW and above.For such high power requirements, designers often selectpower Darlingtons, since their superior current ratings andswitching characteristics provide additional performanceand in many cases a more cost effective design.

The Full-Bridge also has the advantage of only requiringone mains smoothing capacitor compared to two for theHalf-Bridge, hence, saving space. Its other majoradvantages are the same as for the Half-Bridge.

Disadvantages.

Four transistors and clamp diodes are needed instead oftwo for the other symmetrical types. Isolated drive for twofloating potential transistors is now required. TheFull-Bridge has the most complex and costly design of anyof the converters discussed,and should only be used whereother types do not meet the requirements. Again, the fourtransistor snubbers (if required) must be implementedcarefully to prevent interactions occurring between them.

Table 7 gives an outline of the Philips powersemiconductors suitable for use with the Full-Bridge.

Fig. 14 The Full-Bridge converter.

Vo

T1

D1

Co

TR1

D2

L1

TR2

Vin

D3

D4

C1

* *

* Isolated drive required.

C2

TR3

TR4

D5

D6

125





Bipolar transistors.TO-220 BUT12 BUT18 --- --- --- ---

Isolated SOT-186 BUT12F BUT18F --- --- --- ---SOT-93 --- --- BUW13 BUW13 --- BUW13

Isolated SOT-199 --- --- BUW13F BUW13F --- BUW13F

Power MOSFETSOT-93 --- BUK438-500B --- --- --- ---


5V --- --- ---10V --- --- ---20V PBYR30100PT --- ---

BYV42E-100/150/200BYV72E-100/150/200

50V BYV34-300 BYV44-300 ---

Table 7. Recommended Power Semiconductors for the Full-Bridge converter.

Full-Bridge converter.Converter efficiency, η = 80%; Max duty cycle, Dmax = 0.9

Max transistor voltage, Vce or Vds = Vin(max) + leakage spike.

dc voltage gain:-

Applications:- Very high power, normally above 1000W. Very high current, very low ripple outputs. Well suited forhigh input voltage applications. E.g. 110, 220, 440V mains. E.g. Computer Mainframe supplies, Large lab equipment

supplies, Telecomm systems.


η Dmax Vmin

VoVin

= 2 n D

126


Conclusion.The 5 most common S.M.P.S. converter topologies, theflyback, forward, push-pull, half-bridge and full-bridge typeshave been outlined. Each has its own particular operatingcharacteristics and advantages, which makes it suited toparticular applications.

The converter topology also defines the voltage and currentrequirements of the power transistors (either MOSFET orBipolar). Simple equations and calculations used to outlinethe requirements of the transistors for each topology havebeen presented.

The selection guide for transistors and rectifiers at the endof each topology section shows some of the Philips deviceswhich are ideal for use in S.M.P.S. applications.

References.

(1) Philips MOSFET Selection Guide For S.M.P.S. byM.J.Humphreys. Philips Power SemiconductorApplications group, Hazel Grove.

(2) Switch Mode Power Conversion - Basic theory anddesign by K.Kit.Sum. (Published by Marcel Dekkerinc.1984)

127


Appendix A.

MOSFET throughput power calculations.Assumptions made:-

The power loss (Watts) in the transistor due to on-statelosses is 5% of the total throughput (output) power.

Switching losses in the transistor are negligible. N.B. Atfrequencies significantly higher than 50kHz the switchinglosses may become important.

The device junction temperature, Tj is taken to be 125˚C.The ratio Rds(125C˚)/Rds(25˚C) is dependent on the voltage of theMOSFET device. Table A1 gives the ratio for the relevantvoltage limiting values.

The value of Vs(min) for each input value is given in TableA2.

Device voltage limiting Rds(125C)

value. --------Rds(25C)

100 1.74

200 1.91

400 1.98

500 2.01

800 2.11

1000 2.15

Table A1. On resistance ratio.

Main input Maximum dc link Minimum dcvoltage voltage link

voltage

220 / 240V ac 385V 200V

110 / 120V ac 190V 110V

Table A2. Max and Min dc link voltages for mains inputs.

Using the following equations, for a given device with aknown Rds(125˚C), the maximum throughput power in eachtopology can be calculated.

Where:-

Pth(max) = Maximum throughput power.Dmax = maximum duty cycle.

τ = required transistor efficiency (0.05 ± 0.005)Rds(125˚C) = Rds(25˚C) x ratio.

Vs(min) = minimum dc link voltage.

Forward converter.

Dmax = 0.45

Flyback Converter.

Dmax = 0.45

Push Pull Converter.

Dmax = 0.9

Half Bridge Converter.

Dmax = 0.9

Full Bridge Converter.

Dmax = 0.9

Pth(max) =τ × Vs(min)

2 × Dmax

Rds(125c)

Pth(max) =3× τ × Vs(min)

2 × Dmax

4× Rds(125c)


2 × Dmax

Rds(125c)


2 × Dmax

4× Rds(125c)


2 × Dmax

2× Rds(125c)

128


2.1.2 The Power Supply Designer’s Guide to High VoltageTransistors

One of the most critical components in power switchingconverters is the high voltage transistor. Despite its wideusage, feedback from power supply designers suggeststhat there are several features of high voltage transistorswhich are generally not well understood.

This section begins with a straightforward explanation ofthe key properties of high voltage transistors. This is doneby showing how the basic technology of the transistor leadsto its voltage, current, power and second breakdown limits.It is also made clear how deviations from conditionsspecified in the data book will affect the performance of thetransistor. The final section of the paper gives practicaladvice for designers on how circuits might be optimised andtransistor failures avoided.

Introduction

A large amount of useful information about thecharacteristics of a given component is provided in therelevant data book. By using this information, a designercan usually be sure of choosing the optimum componentfor a particular application.

However, if a problem arises with the completed circuit, anda more detailed analysis of the most critical componentsbecomes necessary, the data book can become a sourceof frustration rather than practical assistance. In the databook, a component is often measured under a very specificsetof conditions. Very little is said abouthow the componentperformance is affected if these conditions are notreproduced exactly when the component is used in a circuit.

There are as many different sets of requirements for highvoltage transistors as there are circuits which make use ofthem. Covering every possible drive and load condition inthe device specification is an impossible task. There istherefore a real need for any designer using high voltagetransistors to have an understanding of how deviations fromthe conditions specified in the transistor data book will affectthe electrical performance of the device, in particular itslimiting values.

Feedback from designers implies that this information is notreadily available. The intention of this report is therefore toprovide designers with the information they need in orderto optimise the reliability of their circuits. The characteristicsof high voltage transistors stem from their basic technologyand so it is important to begin with an overview of this.

HVT technologyStripping away the encapsulation of the transistor revealshow the electrical connections are made (see Fig. 1). Thecollector is contacted through the back surface of thetransistor chip,which is soldered to the nickel-plated copperlead frame. For Philips power transistors the lead frameand the centre leg are formed from a single piece of copper,and so the collector can be accessed through either thecentre leg or any exposed part of the lead frame (eg themounting base for TO-220 and SOT-93).

Fig. 1 High voltage transistor without the plastic case.

The emitter area of the transistor is contacted from the topsurface of the chip. A thin layer of aluminium joins all of theemitterarea toa large bond pad. This bondpad is aluminiumwire bonded to the emitter leg of the transistor when thetransistor is assembled. The same method is used tocontact the base area of the chip. Fig. 2 shows the top viewof a high voltage transistor chip in more detail.

Viewing the top surface of the transistor chip, the base andemitter fingers are clearly visible. Around the periphery ofthe chip is the high voltage glass passivation. The purposeof this is explained later.

Taking a cross section through the transistor chip revealsits npn structure. A cross section which cuts one of theemitter fingers and two of the base fingers is shown in Fig. 3.

nickel-platedcopper leadframe

passivatedchip

aluminiumwires

tinned copperleads

ultrasonicwire bonds

Base Collector Emitter

129


Fig. 2 High voltage transistor chip.

On the top surface of the transistor are the aluminium trackswhich contact the base andemitter areas. Theemitter fingeris shown connected to an n+ region. This is the emitter area.The n+ denotes that this is very highly doped n type silicon.Surrounding the n+ emitter is the base, and as shown inFig. 3 this is contacted by the base fingers, one on eitherside of the emitter. The p denotes that this is highly dopedp type silicon.

On the other side of the base is the thick collector n- region.The n- denotes that this is lightly doped n type silicon. Thecollector region supports the transistor blocking voltage,and its thickness and resistivity must increase with thevoltage rating of the device.

Fig. 3 Cross section of HVT.

Following the collector region is the n+ back diffusion. Then+ back diffusion ensures a good electrical contact is madebetween the collector region and the lead frame/collectorleg, whilst also allowing the crystal to be thick enough toprevent it from cracking during processing and assembly.The bottom surface of the chip is soldered to the lead frame.

Voltage limiting valuesPart 1: Base shorted to emitter.

When the transistor is in its off state with a high voltageapplied to the collector, the base collector junction isreverse biased by a very high voltage. The voltagesupporting depletion region extends deep into the collector,right up to the back diffusion, as shown in Fig. 4.

Fig. 4 Depletion region extends deep into the collectorduring the off state.

With the base of the transistor short circuited to the emitter,or at a lower potential than the emitter, the voltage ratingis governed by the voltage supporting capability of thereverse biased base collector junction. This is the transistorVCESMmax. The breakdownvoltage of the reverse biased basecollector junction is determined mainly by the collector widthand resistivity as follows:

Figure 5 shows the doping profile of the transistor. Note thevery high doping of the emitter and the back diffusion, thehigh doping of the base and the low doping of the collector.Also shown in Fig. 5 is the electric field concentrationthroughout the depletion region for the case where thetransistor is supporting its off state voltage. The electricfield, E, is given by the equation, E = -dV/dx, where -dV isthe voltage drop in a distance dx. Rewriting this equationgives the voltage supported by the depletion region:

emitter fingersbase fingers

emitterbond pad

basebond pad

high

voltagepassivation

n+

p

n-

n+

base finger emitter finger base finger

emitterbase

collector

back diffusion

Depletion Region

n+

p

n-

n+

base finger emitter finger base finger

emitterbase

collector

back diffusion

solder

lead frame

V = −⌠⌡Edx

130


Fig. 5 Doping profile and E field distribution.

This is the area under the dotted line in Fig.5.

During the off state, the peak electric field occurs at thebase collector junction as shown in Fig. 5. If the electric fieldanywhere in the transistor exceeds 200 kVolts per cm thenavalanche breakdown occurs and the current which flowsin the transistor is limited only by the surrounding circuitry.If the avalanche current is not limited to a very low valuethen the power rating of the transistor can easily beexceededand the transistor destroyed as a result of thermalbreakdown. Thus the maximum allowable value of electricfield is 200 kV/cm.

The gradient of the electric field, dE/dx, is proportional tocharge density which is in turn proportional to the level ofdoping. In the base, the gradient of the electric field is highbecause of the high level of doping, and positive becausethe base is p type silicon. In the collector, the gradient ofthe electric field is low because of the low level of doping,and negative because the collector is n type silicon. In theback diffused region, the gradient of the electric field is veryhighly negative because this is very highly doped n typesilicon.

Increasing the voltage capability of the transistor cantherefore be done by either increasing the resistivity(lowering the level of doping) of the collector region in orderto maintain a high electric field for the entire collector width,or increasing the collector width itself. Both of thesemeasures can be seen to work in principle because theyincrease the area under the dotted line in Fig. 5.

The breakdown voltage of the transistor, VCESMmax, is limitedby the need to keep the peak electric field, E, below 200kV/cm. Without special measures, the electric field wouldcrowd at the edges of the transistor chip because of thesurface irregularities. This would limit breakdown voltagesto considerably less than the full capability of the silicon.Crowding of the equipotential lines at the chip edges is

avoided by the use of a glass passivation (see Fig. 6). Theglass passivation therefore allows the full voltage capabilityof the transistor to be realised.

Fig. 6 High voltage passivation.

The glass used is negatively charged to induce a p- channelunderneath it. This ensures that the applied voltage issupported evenly over the width of the glass and does notcrowd at any one point. High voltage breakdown thereforeoccurs in the bulk of the transistor, at the base collectorjunction, and not at the edges of the crystal.

Exceeding the voltage rating of the transistor, even for afraction of a second, must be avoided. High voltagebreakdown effects can be concentrated in a very small areaof the transistor, and only a small amount of energy maydamage the device. However, there is no danger in usingthe full voltage capability of the transistor as the limit underworst case conditions because the high voltage passivationis extremely stable.

Part 2: Open circuit base.

With the base of the transistor open circuit the voltagecapability is much lower. This is the VCEOmax of the deviceand it is typically just less than half of the VCESMmax rating.The reason for the lower voltage capability under opencircuit base conditions is as follows:

As the collector emitter voltage of the transistor rises, thepeak electric field located at the base collector junction risestoo. Above a peak E field value of 100 kV/cm there is anappreciable leakage current being generated.

In the previous case, with the base contact short circuitedto the emitter, or held at a lower potential than the emitter,any holes which are generated drift from the edge of thedepletion region towards the base contact where they areextracted. However, with the base contact open circuit, theholes generated diffuse from the edge of the depletionregion towards the emitter where they effectively act asbase current. This causes the emitter to inject electrons intothe base, which diffuse towards the collector. Thus there isa flow of electrons from the emitter to the collector.

Doping

Distance

n+ p

n-

n+

E B C

E field

base emitter

250V

600V

850V

1150V

n-

n+

n+ p n+

n-

special glass

131


The high electric field in the collector accelerates theelectrons to the level where some have sufficient energy toproduce more hole electron pairs through their collisionswith the lattice. The current generated in this way adds tothe leakage current. Thus with the base contact open circuitthe emitter becomes active and provides the system withgain, multiplying the leakage current and consequentlyreducing the breakdown voltage.

For a given transistor the gain of the system is dependanton two things. Firstly it is dependant on the probability thata hole leaving the depletion region will reach the emitter. Ifthe base is open circuit and no recombination occurs thenthis probability is 1. If the base is not open circuit, andinstead a potential below VBEon is applied, then there is achance that a hole leaving the depletion region will beextracted at the base contact. As the voltage on the basecontact is made less positive the probability of holesreaching the emitter is reduced.

Secondly, the gain is dependant on the probability ofelectrons leaving the emitter, diffusing across the base andbeing accelerated by the high field in the collector to thelevel where they are able to produce a hole electron pair inone of their collisions with the lattice. This depends on theelectric field strength which is in turn dependant on thecollector voltage.

Thus fora givenvoltage at the base there is acorrespondingmaximum collector voltage before breakdown will occur.With the base contact shorted to the emitter, or at a lowerpotential than the emitter, the full breakdown voltage of thetransistor is achieved (VCESMmax). With the base contactopencircuit, or at a higher potential than the emitter, thebreakdown voltage is lower (VCEOmax) because in this casethe emitter is active and it provides the breakdownmechanism with gain.

With the base connected to the emitter by a non zeroimpedance, the breakdown voltage will be somewherebetween the VCESMmax and the VCEOmax. A low impedanceapproximates to the shorted base, ’zero gain’, case and ahigh impedance approximates to the open base, ’high gain’,case. With a base emitter impedance of 47 Ω and noexternally applied base voltage, the breakdown voltage istypically 10% higher than the VCEOmax.

Current limiting valuesThe maximum allowed DC current is limited by the size ofthe bond wires to the base and emitter. Exceeding the DClimiting values ICmax and IBmax, for any significant length oftime, may blow these bond wires. If the current pulses areshort and of a low duty cycle then values greatly in excessof the DC values are allowed. The ICMmax and IBMmax ratingsare recommendations for peak current values. For a dutycycle of 0.01 and a pulse width of 10ms these values willtypically be double the DC values.

If the pulses are shorter than 10ms then even therecommended peak values can be exceeded under worstcase conditions. However, it should be noted thatcombinations of high collector current and high collectorvoltagecan lead to failure by second breakdown (discussedlater). As the collector current is increased, the collectorvoltage required to trigger second breakdown drops, andso allowing large collector current spikes increases the riskof failure by second breakdown. It is therefore advised thatthe peak values given in the data book are used as designlimits in order to maximise the component reliability.

In emitter drive circuits, the peak reverse base current isequal to the peak collector current. The pulse widths andduty cycles involved are small, and this mode of operationis within the capability of all Philips high voltage transistors.

Power limiting value

The Ptotmax given in device data is not generally anachievable parameter because in practice it is obtainableonly if the mounting base temperature can be held to 25 ˚C.In practice, the maximum power dissipation capability of agiven device is limited by the heatsink size and the ambienttemperature. The maximumpower dissipation capability fora particular circuit can be calculated as follows;

Tjmax is the maximum junction temperature given in the datasheet. The value normally quoted is 150 ˚C. Tamb is theambient temperature around the device heatsink. A typicalvalue in practice could be 65 ˚C. Rthj-mb is the device thermalresistance given in the data sheet, but to obtain a value ofjunction to ambient thermal resistance, Rthj-a, the thermalresistance of the mica spacer (if used), heatsink andheatsink compound should be added to this.

Themaximum power which can be dissipated under a givenset of circuit conditions is calculated using;

Pmax = (Tjmax-Tamb)/Rthj-a

For a BUT11AF, in an ambient temperature of 65 ˚C,mounted on a 10 K/W heatsink with heatsink compound,this gives;

Rthj-a = 3.95 K/W + 10 K/W = 13.95 K/W

and hence the maximum power capable of being dissipatedunder these conditions is;

Pmax = (150-65)/13.95 = 6 W

Exceeding the maximum junction temperature, Tjmax, is notrecommended. All of the quality and reliability work carriedout on the device is based on the maximum junctiontemperature quoted in data. If Tjmax is exceeded in the circuitthen the reliability of the device is no longer guaranteed.

132


Secondary breakdownPure silicon, also known as ’intrinsic’ silicon, contains fewmobile charge carriers at room temperature and so itsconductivity is low. By doping the silicon (ie introducingatoms of elements other than silicon) the number of mobilecharge carriers, and hence the conductivity, can beincreased. Silicon doped in such a way as to increase thenumber of mobile electrons (negative charge) is called ntype silicon. Silicon doped in such a way as to increase thenumber of mobile holes (positive charge) is called p typesilicon. Thus the base region of an npn transistor containsan excess of mobile holes and the collector and emitterregions contain an excess of mobile electrons.

When a high voltage is applied to the transistor, and thecollector base junction is reverse biased, a depletion regionis developed. This was shown in Fig. 4. The depletionregion supports the applied voltage. The electric fielddistribution within the depletion region was shown in Fig. 5.

The term depletion region refers to a region depleted ofmobile charge carriers. Therefore, within the depletionregion, the base will have lost some holes and hence it isleft with a net negative charge. Similarly the collector willhave lost some electrons and hence it is left with a netpositive charge. The collector is said to have a ’positivespace charge’ (and the base a ’negative space charge’.)

Consider the case where a transistor is in its off statesupporting a high voltage which is within its voltagecapability. The resulting electric field distribution is shownin Fig. 7.

Fig. 7 VCE high, IC = 0.

If the collector voltage is held constant, and the collectorcurrent increased so that there is now some collectorcurrent flowing, this current will modify the chargedistribution within the depletion region. The effect this hason the base is negligible because the base is very highlydoped. The effect this has on the collector is significantbecause the collector is only lightly doped.

The collector current is due to the flow of electrons from theemitter to the collector. As the collector current increases,the collector current density increases. This increase incollector current density is reflected in Fig. 8 by an increasein the electron concentration in the collector.

At a certain collector current density, the negative chargeof the electrons neutralises the positive space charge of thecollector. The gradient of the electric field, dE/dx, isproportional to charge density. If the space charge isneutralised then the gradient of the electric field becomeszero. This is the situation illustrated in Fig. 8. Note that theshaded area remains constant because the applied voltageremains constant. Therefore the peak value of electric fielddrops slightly.

Fig. 8 VCE high, IC>0.

Keeping the collector-emittervoltage constant,and pushingup the collector current density another step, increases theconcentration of electrons in the collector still further. Thusthe collector charge density is now negative, the gradientof electric field in the collector is now positive, and the peakelectric field has shifted from the collector-base junction tothe collector-back diffusion interface. This is shown inFig. 9.

Increasing the collector current density another step willfurther increase the positive gradient of electric field. Thecollectorvoltage isunchanged and so the shaded areamustremain unchanged. Therefore the peak electric field isforced upwards. This is shown in Fig. 10.

Efield

Electron Concentration

CollectorBase

Efield

CollectorBase

133


Fig. 9 VCE high, IC increased further.

Fig. 10 VCE high, IC increased further.

At a certain critical value of peak electric field, Ecrit, aregenerative breakdown mechanism takes place whichcauses the electron concentration in the collector toincrease uncontrollably by a process known as avalanchemultiplication. As the electron concentration increases, thegradient of electric field increases (because the gradient ofelectric field is proportional to charge density). The peakelectric field is clamped by the breakdown and so thecollector voltage drops. In most circuits the collapsingcollector voltage will result in a further rise in collectorcurrent density, causing a further rise in electronconcentration (ie positive feedback). This is shown inFig. 11.

At approximately 30 V, the holes produced by theavalanche multiplication build up sufficiently to temporarilystabilize the system. However, with 30 V across the deviceand a high collector current flowing through it, aconsiderable amount of heat will be generated. Within lessthan one microsecond thermal breakdown will take place,followed by device destruction.

Fig.11 VCE falling, IC increasing

Safe Operating AreaIt has been shown that the electric field profile, and hencethe peak electric field, is dependent on the combination ofcollector current density and applied collector voltage. Thepeak electric field increases with increasing collectorvoltage (increase in shaded area in Figs. 7 to 11). It alsoincreases with increasing collector current density(increase in gradient of electric field). At all times the peakelectric field must remain below the critical value. If thecollector voltage is lowered then a higher collector currentdensity is permitted. If the collector current density islowered then a higher collector voltage is permitted.

Potentially destructive combinations of collector currentdensity and collector voltage are most likely to occur duringswitching andduring fault conditions in the circuit (eg ashortcircuited load). The safe operating areas give informationabout the capability of a given device under theseconditions.

The collector current density is dependent on the collectorcurrent and the degree of current crowding in certain areasof the collector. The degree of current crowding is differentfor turn-on (positive base voltage) and turn-off (negativebase voltage). Therefore the allowed combinations ofcollector current and collector voltage, collectively knownas the safe operating area (SOA) of the transistor, will bedifferent for turn-on of the transistor and turn-off.

Forward SOAWith a positive voltage applied to the base, the shape ofthe safe operating area for DC operation is that shown inFig. 12. Operation outside the safe operating area is notallowed.

For pulsed operation the forward SOA increases, and forsmall, low duty cyclepulses itbecomes square. The forwardSOA provides useful information about the capabilities ofthe transistor under fault conditions in the circuit (eg. a shortcircuited load).

Efield


CollectorBase

Efield


Ecrit

Electron Density Increasing

Voltage Collapsing

Base Collector

Efield


CollectorBase

134


Fig. 12 Forward SOA.

The safe operating area is designed to protect the current,power, voltage and second breakdown limits of thetransistor. The current, power and voltage limits of thetransistor have already been discussed. Note that the peakvoltage rating is the VCEOmax rating and not the VCESMmax

rating. The VCESMmax rating only applies if the base emittervoltage is not greater than zero volts.

Sometimes shown on forward SOA curves is an extensionallowing higher voltages than VCEOmax to be tolerated forshort periods (of the order of 0.5 µs). This allows turn-on ofthe transistor from a higher voltage than VCEOmax. However,the pulses allowed are very short, and unless it can beguaranteed that the rated maximum pulse time will neverbe exceeded, transistor failures will occur. If the circuitconditions can be guaranteed then there is no danger inmaking use of this capability.

As mentioned in the previous section, second breakdownis triggered by combinations of high collector voltage andhigh collector current density. With a positive voltageapplied to the base, the region of highest current density isat the edges of the emitter as shown in Fig. 13.

Fig. 13 Forward biased second breakdown.

The base region under the emitter constitutes a resistance(known as the sub emitter resistance). With a positivevoltage applied to the base, the sub emitter resistance willmean that the areas of the emitter which are nearest to thebase have a higher forward bias voltage than the areasfurthest from the base. Therefore the edges of the emitterhave a higher forward bias voltage than the centre and sothey receive a higher base current.

As a result of this the edges of the emitter conduct asubstantial proportion of the collector currentwhen the baseis forward biased. If the collector current is high then thecurrentdensity at the edgesof the emitter is also high. Therewill be some spreading out of this current as it traversesthe base. When the edge of the depletion region is reached,the current is sucked across by the electric field.

If the transistor is conducting a high current and alsosupporting a high voltage, then the current density will behigh when the current reaches the edge of the depletionregion. If the current density is beyond that allowed at theapplied voltage, then the second breakdown mechanism istriggered (as explained in the previous section) and thedevice will be destroyed.

With a positive base current flowing, the region of highestcurrent density is at the edges of the emitter. A forward SOAfailure will therefore produce burns which originate from theedge of one of the emitter fingers.

Forward SOA failure becomes more likely as pulse widthand/or duty cycle is increased. Because the edges of theemitter are conducting more current than the centre, theywill get hotter. The temperature of the emitter edges at theend of each current pulse is a function of the pulse widthand the emitter current. Longer pulse widths will increasethe temperature of the emitter edges at the end of eachcurrent pulse. Higher duty cycles will leave insufficient timefor this heat to spread. In this manner, combinations of longpulse width and high duty cycle can give rise to cumulativeheating effects. Current will crowd towards the hottest partof the emitter. There is therefore a tendency for current tobecome concentrated in very narrow regions at the edgesof the emitter fingers, and as pulse width and/or duty cycleis increased the degree of current crowding increases. Thisis the reason why the forward SOA for DC operation is asshown in Fig. 12, but for pulsed operation it is enlarged andfor small, low duty cycle pulses it becomes square.

Reverse SOA

During turn-on of the transistor, the high resistance of thecollector region is reducedby the introduction of holes (fromthe base) and electrons (from the emitter). This process,known as conductivity modulation, is the reason why bipolartransistors are able to achieve such a low collector voltageduring the on state, typically 0.2 V. However, during turn-off

Maximum CollectorCurrent rating

Maximum Powerrating (Ptotmax)

Second breakdownlimit

Maximum CollectorVoltage rating(VCEOmax)

VCE

IC

ICmax

n+

p

n-

n+

emitter

base

collector

back diffusion

Depletion Region

e- e-

IB IB

1V1V0.8V 0.8V

135


of the transistor, these extra holes and electrons constitutea stored charge which must be removed from the collectorbefore the voltage supporting depletion region can develop.

To turn off the transistor, a negative voltage is applied tothe base and a reverse base current flows. During turn-offof the transistor, it is essential that the device stays withinits reverse bias safe operating area (RBSOA). The shapeof a typical RBSOA curve is as shown in Fig. 14.

With no negative voltage applied to the base, the RBSOAis very much reduced, as shown in Fig. 14. This isparticularly important to note at power up and power downof power supplies, when rail voltages are not well defined(see section on improving reliability).

Fig. 14 Reverse SOA.

On applying a negative voltage to the base, the chargestored in the collector areas nearest to the base contactswill be extracted, followed by the charge stored in theremaining collector area. Holes not extracted through thebase contact are free to diffuse into the emitter where theyconstitute a base current which keeps the emitter active.During the transistor storage time, the collector charge isbeing extracted through the base, but the emitter is stillactive and so the collector current continues to flow.

During the transistor fall time, the voltage supportingdepletion region is being developed and therefore thecollector voltage is rising. In addition to this, the negativevoltage on the base is causing holes to drift towards thebase contact where they are neutralised, thus preventingholes from diffusing towards the emitter.

This has two effects on the collector current. Firstly, therising collector voltage results in a reduction in the voltageacross the collector load, and so the collector current startsto drop. Secondly, the extraction of holes through the basewill be most efficient nearest to the base contacts (due tothe sub emitter resistance), and so the collector currentbecomes concentrated into narrow regions under thecentre of the emitter fingers (furthest from the base). This

is shown in Fig. 15. This current crowding effect leads toan increase in the collector current density during turn off,even though the collector current itself is falling.

Thus for a portion of the fall time, the collector voltage isrising and the collector current density is also rising. Thisis a critical period in the turn-off phase. If the turn-off is notcarefully controlled, the transistor may be destroyed duringthis period due to the onset of the second breakdownmechanism described earlier.

During this critical period, the collector current isconcentrated into a narrow region under the centre of theemitter. RBSOA failure will therefore produce burns whichoriginate from the centre of one of the emitter fingers.

Fig. 15 Reverse biased second breakdown.

Useful tips as an aid to circuit design

In recent years, the Philips Components PowerSemiconductor Applications Laboratory (P.S.A.L.) hasworked closely with a number of HVT users. It has becomeapparent that there are some important circuit designfeatures which, if overlooked, invariably give rise to circuitreliability problems. This section addresses each of theseareas and offers guidelines which, if followed, will enhancethe overall performance and reliability of any power supply.

Improving turn-on

There is more to turning on a high voltage transistor thansimply applying a positive base drive. The positive basedrive must be at least sufficient to keep the transistorsaturated at the current it is required to conduct. However,transistor gain as specified in data sheets tends to beassessed under static conditions and therefore assumesthe device is already on.

Maximum CollectorCurrent rating

Second breakdownlimit

Maximum CollectorVoltage rating(VCESMmax)

VCE

IC

VCEOmax

VBEoff = 5VVBEoff = 0V

ICmax n+

p

n-

n+

emitter

base

collector

back diffusion

Depletion Region

e-

IB IB

0V 0V

1V

136


Fig. 16 Transistor switching waveforms in a typicalpower supply.

Note 1. The base current requirements at turn-on of thetransistor are higher than the static gain would suggest.

The conductivity modulation process, described at thebeginning of the previous section, occurs every time thetransistor is turned on. The faster the charges areintroduced into the collector, the faster the collectorresistance will drop, allowing the collector voltage to dropto its saturation level. The rate at which the collector chargeis built up is dependent on the applied base current and theapplied collector current. In order to turn the transistor onquickly, and hence minimise the turn-on dissipation, thetransistor needs to be overdriven until the collector voltagehas dropped to its saturation level. This is achieved byhaving a period of overshoot at the start of the base currentpulse. The turn-on waveforms are shown in Fig. 17.

Fig. 17 Turn on waveforms.

Note 2. A fast rising base current pulse with an initial periodof overshoot is a desirable design feature in order to keepthe turn-on dissipation low.

The base current overshoot is achieved by having acapacitor in parallelwith the forward base drive resistor (seeFig. 18). The RC time constant determines the overshootperiod and as a first approximation it should be comparableto the transistor storage time. The capacitor value is thenadjusted until the overshoot period is almost over by thetime the transistor is saturated. This is the optimum drivecondition. A resistor in series with the capacitor (typicallyR/2) can be used to limit the peak base current overshootand remove any undesirable oscillations.

The initial period of overshoot is especially necessary incircuits where the collector current rises quickly (ie squarewave switching circuits and circuits with a high snubberdischarge current). In these circuits the transistor wouldotherwise be conducting a high collector current during theearly stages of the turn-on period where the collectorvoltagecan still be high. This would lead to an unacceptablelevel of turn-on dissipation.

Fig. 18 Forward base drive circuit.

Note 3. Square wave switching circuits, and circuits with ahighsnubber dischargecurrent, are very susceptible tohighturn-on dissipation. Using an RC network in series with theforward base current path increases the turn-on speed andtherefore overcomes this problem.

It should also be noted that during power up of power supplyunits, when all the output capacitors of the supply aredischarged, the collector current waveform is often verydifferent to that seen under normal running conditions. Therising edge of the collector current waveform is often faster,the collector current pulse width is often wider and the peakcollector current value is often higher.

VCE

IC

TURN ON TURN OFF

+VBB

RC

TR

R/2

IC

IB

VCE

5 V

137


In order to prevent excessive collector current levels (andtransformer saturation) a ’soft start’ could be used to limitthe collector current pulse width during power up.Alternatively, since many power supply designs are nowusing current mode control, excessive collector current canbe avoided simply by setting the overcurrent threshold atan acceptable level.

Note 4. Using the ’soft start’ and/or the overcurrentprotection capability of the SMPS control IC preventsexcessive collector current levels at power up.

Improving turn-offAs far as the collector current is concerned, optimumturn-off for a particular device is determined by how quicklythe structure of the device will allow the stored charge tobe extracted. If the device is turned off too quickly, chargegets trapped in the collector when the collector basejunction recovers. Trapped charge takes time to recombineleading to a long collector current tail at turn-off and hencehigh turn-off losses. On the other hand, if the device isturned off too slowly, the collector voltage starts to riseprematurely (ie while the collector current is at its peak).This would also lead to high turn-off losses.

Note 1. Turning the transistor off either too quickly or tooslowly leads to high turn-off losses.

Optimum turn-off is achieved by using the correctcombination of reverse base drive and storage time control.Reverse base drive is necessary to prevent storage timesfrombeing too long (andalso togive the maximumRBSOA).Storage time control is necessary to prevent storage timesfrom being too short.

Storage time control is achieved by the use of a smallinductor in series with the reverse base current path (seeFig. 19). This controls the slope of the reverse base current(as shown in Fig. 20) and hence the rate at which chargeis extracted from the collector. The inductor, or ’base coil’,is typically between 1 and 6 µH, depending on the reversebase voltage and the required storage time.

Fig. 19 Reverse base drive circuit.

Note 2. Applying a base coil in series with the reverse basecurrent path increases the transistor storage time butreduces both the fall time and the turn-off losses.

Applying this small base inductor will usually mean that thebase emitter junction of the transistor is brought intobreakdown during part of the turn-off cycle. This is not aproblem for the device because the current is controlled bythe coil and the duty cycle is low.

If the transistor being used is replaced by a transistor of thesame technology but having either a higher current ratingor a higher voltage rating, then the volume of the collectorincreases. If the collector volume increases then the volumeof charge in the collector, measured at the same saturationvoltage, also increases. Therefore the required storagetime for optimum turn-off increases and also the requirednegative drive energy increases.

Overdriving the transistor (ie. driving it well into saturation)also increases the volume of stored charge and hence therequired storage time for optimum turn-off. Conversely, therequired storage time for a particular device can be reducedby using a desaturation network such as a Baker clamp.The Baker clamp reduces the volume of stored charge byholding the transistor out of heavy saturation.

Note 3. The required storage time for optimum turn-off andthe required negative drive energy will both increase as thevolume of stored charge in the collector is increased.

The reverse base current reaches its peak value at aboutthe same time as the collector current reaches its peakvalue. The turn-off waveforms are shown in Fig. 20.

Fig. 20 Turn off waveforms.

Note 4. For optimum turn-off of any transistor, the peakreverse base current should be half of the peak collectorcurrent and the negative drive voltage should be between2 and 5 volts.

IC

IB

ts tf

VCE

ICpeak

-IBpeak(= -ICpeak/2)TR

-VBBOV

LB

138


As far as the collector voltage is concerned, the slower thedV/dt the lower the turn-off dissipation. Control of thecollector dV/dt is achieved by the use of a snubber network(see Fig. 21). The snubber capacitor also controls thecollector voltage overshoot and thus prevents overvoltageof the transistor.

Fig. 21 RCD snubber.

High collector dV/dt at turn-off can bring an additionalproblem for the transistor. A charging current flows throughthe collector-base (Miller) capacitance of the device, andaccording to the law, I = C x dV/dt, this charging currentincreases in magnitude with increasing dV/dt. If this currententers the base then the transistor can begin to turn backon. Control of the collector dV/dt is usually enough toprevent this from happening. If this is insufficient then thebase-emitter impedance must be reduced by applying aresistor and/or capacitor between base and emitter to shuntsome of this current.

Note 5. High collector dV/dt at turn-off leads to parasiticturn-on if the charging current of the transistor Millercapacitance is not shunted away from the base.

High collector dI/dt at turn-off can also bring problems if theinductance between the emitter and the base groundreference is too high. The falling collector current will inducea voltage across this inductance which takes the emittermore negative. If the voltage on the emitter falls below thevoltage on the base then the transistor can begin to turnback on. This problem is more rare but if it does arise thenadding a resistor and/or capacitor between base andemitter helps to keep the base and emitter more closelycoupled. At all times it is important to keep the length of thesnubber wiring to an absolute minimum.

Note 6. High collector dI/dt at turn-off leads to parasiticturn-on if the inductance between the emitter and the baseground reference is too high.

Fig. 22 HVT environment.

Improving reliabilityIn the majority of cases, the most stressful circuit conditionsoccur during power up of the SMPS, when the base driveis least well defined and the collector current is often at itshighest value. However, the electrical environment atpower up is very often hardly considered, and potentiallydestructive operating conditions go unnoticed.

A very common circuit reliability problem is RBSOA failureoccurring on the very first switching cycle, because thereverse drive to the base needs several cycles to becomeestablished. With no negative drive voltage on the base ofthe transistor, the RBSOA is reduced (as discussed earlier).To avoid RBSOA failure, the collector voltage must be keptbelow VCEOmax until there is sufficient reverse drive energyavailable to hold the base voltage negative during theturn-off phase.

Even with the full RBSOA available, control of the rate ofrising collector voltage through the use of a snubber is oftenessential in order to keep the device within the specifiedoperating limits.

Note 1. The conditions at power up often come close to thesafe operating limits. Until the negative drive voltage supplyis fully established, the transistor must be kept below itsVCEOmax.

Another factor which increases the stress on manycomponents is increased ambient temperature. It isessential that the transistor performance is assessed at thefull operating temperature of the circuit. As the temperatureof the transistor chip is increased, both turn-on and turn-offlosses may also increase. In addition to this, the quantityof stored charge in the device rises with temperature,leading to higher reverse base drive energy requirements.

TR

-VBB

LB

+VBB

R

C

D R

C

0V

R/2

TR

D R

C

0V

139


Note 2. Transistor performance should be assessed underall operating conditions of the circuit, in particular themaximum ambient temperature.

A significant proportion of power supply reliability problemscould be avoided by applying these two guidelines alone.By making use of the information on how to improve turn-on

and turn-off, small design changes can be made to thecircuit which will enhance the electrical performance andreliability of the transistor, leading to a considerableimprovement in the performance and reliability of the powersupply as a whole.

140


2.1.3 Base Circuit Design for High Voltage Bipolar Transistorsin Power Converters

Fast, high voltage switching transistors such as theBUT211, BUT11, BUT12, BUT18, BUW13, BU1508,BU2508, BU1706 and BU1708 have all helped to simplifythe design of converter circuits for power supplyapplications. Because the breakdown voltage of thesetransistors is high (from 850 to 1750V), they are suitablefor operation direct from the rectified 110V or 230V mainssupply. Furthermore, their fast switching properties allowthe use of converter operating frequencies up to 30kHz(with emitter switching techniques pushing this figure past100kHz).

The design of converter circuits using high-voltageswitching transistors requires a careful approach. This isbecause the construction of these transistors and theirbehaviour in practical circuits is different from those of theirlow-voltage counterparts. In this article, solutions to basecircuit design for transistor converters and comparablecircuits are developed from a consideration of theconstruction and the inherent circuit behaviour of highvoltage switching transistors.

Switching behaviourFigure 1 shows a complete period of typical collectorvoltage and current waveforms for a power transistor in aswitching converter. The turn-on and turn-off intervals areindicated. The switching behaviour of the transistor duringthese two intervals, and the way it is influenced by thetransistor base drive, will now be examined.

Fig. 1 VCE and IC waveforms during the conductionperiod for a power transistor in an S.M.P.S.

Turn-on behaviourA particular set of voltage and current waveforms at thecollector and base of a converter transistor during theturn-on interval is shown in Fig. 2(a). Such waveforms arefound in a power converter circuit in which a (parasitic)capacitance is discharged by a collector current pulse attransistor turn-on. The current pulse due to this dischargecan be considered to be superimposed on the trapezoidalcurrent waveform found in basic converter operation.

Fig. 2(a) Turn-on waveforms of a practical convertercircuit.

A positive base current pulse IB turns on the transistor. Thecollector-emitter voltage VCE starts to decrease rapidly andthe collector current IC starts to increase. After some time,the rate of decrease of VCE reduces considerably and VCE

remains relatively high because of the large collectorcurrent due to the discharge of the capacitance. Thus, theturn-on transient dissipation (shown by a broken line)reaches a high value.

141


Fig. 2(b) Turn-on waveforms: fast-rising base currentpulse.

The collector current then decreases to a trough beforeassuming the normal trapezoidal waveform. This is againfollowed by a rapid decrease in VCE, which reaches thesaturation value defined by the collector current and basecurrent of the particular transistor.

Figure 2(b) depicts a similar situation but for a greater rateof rise of the base current. The initial rapid decrease in VCE

is maintained until a lower value is reached, and it can beseen that the peak and average values of turn-ondissipation are smaller than they are in Fig. 2(a).

Figure 2(c) shows the effect on the transistor turn-onbehaviour of a very fast rising base current pulse whichinitially overshoots the final value. The collector-emittervoltage decreases rapidly to very nearly the transistorsaturation voltage. The turn-on dissipation pulse is nowlower and much narrower than those of Figs. 2(a) and 2(b).

From the situations depicted in Figs. 2(a), 2(b) and 2(c), itfollows that for the power transistor of a converter circuitthe turn-on conditions are most favourable when the drivingbase current pulse has a fast leading edge and overshootsthe final value of IB.

Fig. 2(c) Turn-on waveforms: very fast-rising basecurrent pulse with overshoot.

Turn-off behaviourThe waveforms which occur during the turn-off intervalindicated in Fig. 1 are shown on an expanded timescaleandwith four differentbase drive arrangements in Figs. 3(a)to 3(d). These waveforms can be provided by base drivecircuits as shown in Figs. 4(a) to 4(c). The circuit of Fig. 4(a)provides the waveforms of Fig. 3(a); the circuit of Fig. 4(b)those of Fig. 3(b) and, with an increased reverse drivevoltage, Fig. 3(c). The circuit of Fig. 4(c) provides thewaveforms of Fig. 3(d). The waveforms shown are typicalof those found in the power switching stages of S.M.P.S.and television horizontal deflection circuits, usinghigh-voltage transistors.

In practical circuits, the waveform of the collector-emittervoltage is mainly determined by the arrangement of thecollector circuit. The damping effect of the transistor on thebase circuit is negligible except during the initial part of theturn-off period, when it only causes some delay in the riseof the VCE pulse.

142


Fig. 3(a) Turn-off waveforms; circuit with speed-upcapacitor.

The IC × VCE (turn-off dissipation) pulse is dependent onboth the transistor turn-off time and the collector currentwaveshape during turn-off. Turn-off dissipation pulses areindicated in Figs. 3(a) to 3(d) by the dashed lines.

The circuit of Fig. 4(a) incorporates a speed-up capacitor,an arrangement often used with low-voltage transistors.The effect of this is as shown in Fig. 3(a), a very rapiddecrease in the base current IB, which passes through anegative peak value, and becomes zero at t3. The collectorcurrent IC remains virtually constant until the end of thestorage time, at t1, and then decreases, reaching zero at t3.The waveform of the emitter current, IE, is determined by ICand IB, until it reaches zero at t2, when the polarity of thebase-emitter voltage VBE is reversed.

After time t2, whenVBE is negative and IE is zero, the collectorbase currents are equal and opposite, and the emitter is nolonger effective. Thus, the further decrease of collectorcurrent is governed by the reverse recovery process of thetransistor collector-base diode. The reverse recovery ’tail’of IC (from t2 to t3) is relatively long, and it is clear the turn-offdissipation is high.

In the circuit of Fig. 4(b) the capacitor is omitted. Fig. 3(b)shows that the negative base current is limited to aconsiderably lower value than in the previous case. All thecurrents IB, IC and IE reach zero at time t3. The transistoremitter base junction becomes reverse biased at t2, so thatduring the short interval from t2 to t3 a small negative emittercurrent flows.

Fig. 4 Base circuits for turn-off base drive. The drivertransistor is assumed to be bottomed to turn off the

power transistor.(a) With speed-up capacitor.

(b) Without speed up capacitor.(c) With series inductor.

The emitter current, determined by the collector current andby the (driven) base current, therefore maintains controlover the collector until it reaches zero. Furthermore, thecollector current has a less pronounced tail and so the falltime is considerably shorter than that of Fig. 3(a). Theturn-off dissipation is also lower than in the previous case.

Increasing the reverse base drive voltage in the circuit ofFig. 4(b), with the base series resistance adjusted so thatthe same maximum reverse base current flows, gives riseto the waveforms shown in Fig. 3(c). The collector currenttail is even less pronounced, and the fall time shorter thanin Fig. 3(b).

143


Fig. 3(b) Turn-off waveforms: circuit without speed-upcapacitor.

A further improvement in turn-off behaviour can be seen inthe waveforms of Fig. 3(d), which are obtained by includingan inductor in the base circuit as in Fig. 4(c). The rate ofchange of the negative base current is smaller than in thepreceding cases, and the negative peak value of the basecurrent is smaller than in Fig. 3(a). The collector current ICreaches zero at t3, and from t3 to t4 the emitter and basecurrents are equal. At time t2 the polarity of VBE is reversedand the base-emitter junction breaks down. At time t4 thenegative base-emitter voltage decreases from thebreakdown value V(BR)EBO to the voltage VR produced by thedrive circuit.

The collector current fall time in Fig. 3(d) is shorter than inany of the previous cases. The emitter current maintainscontrol of the collector current throughout its decay. Thelarge negative value of VBE during the final part of thecollector current decay drives the base-emitter junction intobreakdown, and the junction breakdown voltagedetermines the largest possible reverse voltage. Theturn-off of the transistor is considerably accelerated by theapplication (correctly timed) of this large baseemitter-voltage, and the circuit gives the lowest turn-offdissipation of those considered.

Fig. 3(c) Turn-off waveforms: circuit without speed-upcapacitor, with increased reverse drive voltage.

The operation of the base-emitter junction in breakdownduring transistor turn-off, as shown in Fig. 3(d), has nodetrimental effect on the behaviour of transistors such asthe BUT11 or BU2508 types. Published data on thesetransistors allow operation in breakdown as a method ofachieving reliable turn-off, provided that the -IB(AV) and -IBM

ratings are not exceeded.

It is evident from Figs. 3(a) to 3(d) that the respectiveturn-off dissipation values are related by:-

Poff(a) > Poff(b) > Poff(c) >Poff(d)

The fall times (related in each case to the interval from t1to t3) are given by:-

tf(a) > tf(b) > tf(c) > tf(d)

The storage times (equal to the interval from t0 to t1) are:-

ts(a) < ts(b) < ts(d)

144


where the subscripts (a), (b), (c) and (d) refer to thewaveforms of Figs. 3(a), 3(b), 3(c) and 3(d) respectively. Itfollows that the circuit of Fig. 4(c), which provides thewaveforms of Fig. 3(d), gives the most favourable turn-offpowerdissipation. It has,however, the longest storage time.

Fig. 3(d) Turn-off waveforms: circuit with seriesinductor.

From consideration of the waveforms in Figs. 3(a) to 3(d),it can be concluded that optimum turn-off of a high voltagetransistor requires a sufficiently long storage timedetermined by the turn-off base current and a sufficientlylarge negative base-emitter voltage correctly timed withrespect to the collector current waveform.

The phenomena which have been described in this sectionbecome more pronounced when the temperature of theoperating junction of the transistor is increased: inparticular, the fall times and storage times are increased.The design of a base drive circuit should therefore bechecked by observing the waveforms obtained at elevatedtemperatures.

Optimum base drive circuitryFrom the foregoing study of the required base current andbase-emitter voltage waveforms, a fundamental basecircuit arrangement to give optimum turn-on and turn-off ofhigh voltage switching transistors will now be determined.It will be assumed that the driver stage istransformer-coupled to the base, as in Fig. 5(a), and thatthe driver transformer primary circuit is such that a lowimpedance is seen, looking into the secondary, during boththe forward and reverse drive pulses. The complete drivercircuit can then be represented as an equivalent voltagesource of +V1 volts during the forward drive period and -V2

volts during the reverse drive/bias period. This is shown inFig. 5(b).

Fig. 5 (a) Schematic drive circuit arrangement.(b) Equivalent drive circuit arrangement.

(c) Equivalent circuit for current source forward drive.

Forward base drive can also be obtained from a circuitwhich acts as a current source rather than a voltage source.This situation, where the reverse drive is still obtained froma voltage source, is represented in Fig. 5(c). The basiccircuit arrangements of Figs. 5(b) and 5(c) differ only withrespect to forward drive, and will where necessary beconsidered separately.

Comparable base drive waveforms can, of course, beobtained from circuits differing from those shown inFigs. 5(b) and 5(c). For such alternative circuitconfigurations the following discussion is equally valid.

145


Base series resistor

Most drive circuits incorporate a resistor RB in series withthe base. The influence of the value of this resistor on thedrive characteristic will be briefly discussed.

Voltage source forward drive.

In circuits with a voltage source for forward drive, shown ina simplified form in Fig. 6(a), the following parametersdetermine the base current:-

The transistor base characteristic ;

The value of the base resistor RB;

The forward drive voltage V1.

Fig. 6(a) Drive circuit with base resistor RB and voltagesource forward drive.

Figure 6(b) shows how the tolerances in these parametersaffect the base current. It is clear that to avoid largevariations in IB, the tolerances in RB and V1 should beminimised. The voltage drop across RB reduces thedependence of IB on the spreads and variations of thetransistor VBE(on). For good results the voltage drop acrossRB must not be less than VBE(on).

Current source forward drive

In circuits where a current source is used for forward drive,the forward base current is independent of spreads andvariations of VBE(on). The base current level and tolerancesare governed entirely by the level and tolerances of thedrive. A separate base series resistor is thereforeunnecessary, but is nevertheless included in manypracticalcurrent-source-driven circuits, to simplify the drive circuitdesign. The following discussions will assume that a seriesbase resistor RB always forms part of the base drivenetwork.

Fig. 6(b) Effects on the value of IB on circuit tolerances.(i) Variation of transistor base characteristic.

(ii) Variation of value of resistor RB.(iii) Variation of drive voltage V1.

Turn-off arrangementTo initiate collector current turn-off, the drive voltage isswitched at time t0 from the forward value +V1 to the reversevalue -V2.

146


Fig. 7(a) Turn-off waveforms of the circuit of Fig. 7(b).

The desired turn-off voltage and current waveforms areobtained by adding various circuit elements to the basicresistive circuit of Fig. 6(a). A convenient method ofachieving the desired slowly-decreasing base current is touse a series inductor LB as shown in Fig. 7(b). The turn-offwaveforms obtained by this method are shown in Fig. 7(a).

Fig. 7(b) Base drive circuit with series inductor.

Base series inductorAt time t0 the base current starts to decrease from theforward drive value IB1 with a slope equal to:-

For a considerable time after t0, the (decreasing) inputcapacitance of the transistor maintains a charge such thatthere is no perceptible change in VBE. At time t2 the amountof charge removed by the negative base current (-IB) isinsufficient to maintain this current, and its slopedecreases.

At time t3, when:-

−V2 − (+VBE(on))LB

d IBdt

= 0 where IB = IB2

VBE = −V2 −RBIB2

147


Immediately after t3, the stored energy in LB gives rise to avoltage peak tending to increase the reverse bias of thetransistor. The voltage is clamped by the base-emitterbreakdown voltage, so that:-

At time t4 the negative base current starts to decrease withan initial slope equal to:-

At t5 the base current reaches zero. The base-emittervoltage then changes from -V(BR)EBO to the value -V2, thelevel of the drive voltage. As has been demonstrated, thecollector storage time, ts, is an important parameter of thedrive circuit turn-off behaviour. Fig. 7(a) shows that thevalue of ts can be calculated approximately from:-

and this expression is sufficiently accurate in practice. Inmost cases the base current values are related by:-

In the case where (-IB2 / IB1) = 2, the collector storage timeis given by:-

In practical circuits, design considerations frequentlyindicate a relatively small value for V2. The required valueof ts is then obtained with a small value of LB, andconsequently the energy stored in the inductor (1/2 LBIB2

2)is insufficient to maintain the base-emitter junction in thebreakdown condition. Figure 7(a) shows that breakdownshould continue at least until the collector current iscompletely turned off. The higher the transistor junctiontemperature, the more stored energy is necessary tomaintain breakdown throughout the increased turn-off time.

These phenomena are more serious in applications wherethe storage time must be short, as is the case for the BUT12or BUW13 transistors, for example. For horizontaldeflection output transistors such as the BU508 andBU2508, which require a much longer storage time, thebase inductance usually stores sufficient energy for correctturn-off behaviour.

Diode assisted base inductorIt is possible to ensure the storage of sufficient turn-offenergy by choosing a relatively large value for V2. Wherea driver transformer is employed, there is then acorresponding increase in V1. To obtain the desired value

of forward base current, the base resistance RB must alsobe large. A large value of RB, however, diminishes the effectof LB on the transistor turn-off behaviour, unless RB isbypassed by a diode as in Fig. 8.

Fig. 8 Base drive circuit with diode-assisted seriesinductor.

Fig. 9 Base drive circuit extended for improved turn-offbehaviour.

Turn-off RC networkImproved turn-off behaviour can be obtained withoutincreasing V2, if additional circuit elements are used. Anarrangement used in practice is shown in Fig. 9, andconsists of network R3C3 which is connected in series withRB and LB.

A voltage V3 is developed across C3 because of the forwardbase current. (This voltage drop must be compensated bya higher value of V1). When reverse current flows at turn-off,the polarity of V3 is such that it assists the turn-off drivevoltage V2. Using the same approximation as before, thestorage time is given by:-

The same value of ts now requires a larger value of LB. Theenergy stored in LB is therefore greater and the transistorcan more reliably be driven into breakdown for the timerequired.

The waveforms of Fig. 7(a) are equally applicable to thecircuit of Fig. 9, if V2 is replaced by (V2 + V3). In practice V3

will not remain constant throughout the storage time, andreplacing V3 by its instantaneous value will make a slightdifference to the waveforms.

VBE = −V(BR)EBO

− V2 + V(BR)EBO

LB

− V2 + V(BR)EBO

LB

. ts = IB1 − IB2

IB2

IB1

≈ 1 to 3

ts =3 IB1 LB

−V2 − (+VBE(on))

ts =3 IB1 LB

− (V2 + V3) − (+VBE(on))

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Turn-on arrangementsIt has been shown that for optimum turn-on of a high voltageswitching transistor, the turn-on base current pulse musthave a large amplitude and a fast leading edge withovershoot. However, the inductance LB included in thecircuits derived for optimum turn-off (Figs. 7 to 9) makes itdifficult to produce such a turn-on pulse. The additionalcomponents (R1, C1, D1) in the circuit of Fig. 10(a) help tosolve this problem as shown by the waveforms of Fig. 10(b).

Fig. 10(a) Base drive circuit extended for improvedturn-on behaviour with voltage source drive.

At the instant of turn-on, network R1C1 in series with D1

provides a steep forward base current pulse. The turn-offnetwork is effectively by-passed during the turn-on periodby C1 and D1. The time-constant R1C1 of the turn-on networkshould be chosen so that the forward current pulseamplitude is reduced virtually to zero by the time thetransistor is turned on.

The turn-on network of Fig. 10(a) can also be added to thediode-assisted turn-off circuit of Fig. 8. In circuits which areforward driven by a current source, the overshoot requiredon the turn-on base current pulse must be achieved byappropriate current source design.

Fig. 10(b) Turn-on waveforms of the circuit of Fig.10(a).

Practical circuit design

The base drive circuit of Fig. 10(a) combines the drivevoltage sources +V1 and -V2 with circuit elements RB, LB,R3C3 and R1C1D1 which, if correctly dimensioned, allowoptimum transient behaviour of the switching transistor. Notall these elements, however, will be necessary in everycase for good results.

In circuits where the collector current rate of rise is limitedby collector circuit inductance, the turn-on network R1C1D1

can be omitted without danger of excessive collectordissipation at turn-on. In circuits where the base seriesinductance LB is sufficiently large to give complete turn-off,network R3C3 can be omitted. Networks R1C1D1 and R3C3

are superfluous in horizontal deflection circuits which useBU508, BU2508 transistors or similar types.

A discrete component for inductance LB need not alwaysbe included, because the leakage inductance of the drivertransformer is sometimes sufficient.

The omission of RB from circuits which are forward drivenby a voltage source should generally be considered baddesign practice. It is, however, possible to selectcomponent values such that the functions of R1C1 and R3C3

are combined in a single network.

In some cases, the circuits of Figs. 7 to 10 may generateparasitic oscillations (ringing). These can usually beeliminated by connecting a damping resistor R4 betweenthe transistor base and emitter, as shown in broken linesin Fig. 10(a).

Physical behaviour of high-voltageswitching transistors

Base circuit design for high-voltage switching transistorswill now be considered with respect to the physicalconstruction of the devices. To achieve a high breakdownvoltage, the collector includes a thick region of highresistivity material. This is the major difference in theconstruction of high and low voltage transistors.

The construction of a triple-diffused high voltage transistoris represented schematically in Fig. 11(a). The collectorregion of an n-p-n transistor comprises a high resistivity n-region and a low resistivity n+ region. Most of the collectorvoltage is dropped across the n- region. For semiconductormaterial of achosen resistivity, the thickness of the n- regionis determined by the desired collector breakdown voltage.The thickness of the n+ region is determined bytechnological considerations, in particular the mechanicalconstruction of the device. Fig. 11(b) shows the impurityconcentration profile of the transistor of Fig. 11(a).

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Fig. 11 High voltage switching transistor.

For good switching performance, the high voltage blockingcharacteristic of the transistor structure must be modifiedat transistor turn-on, so that a low forward voltage conditionis exhibited. One method of achieving this is to inject a largenumber of carriers through the base to the collector region.The high resistivity of the n- region is then "swamped" byexcess carriers. This effect is often referred to as acollector-width modulation.

The following discussion of the physical changes whichoccur at transistor turn-on and turn-off is based on a muchsimplified transistor model; that is, the one dimensionalcharge control model. Fig. 12 shows such a model of alow-voltage transistor, and assumes a large freecarrier-to-doping concentration ratio in the base due to thecarriers injected from the emitter. Line a represents the freecarrier concentration in the base for transistor operation inthe active region (VCB>0), and line c that for the saturatedcondition (VCB<0). Line b represents the concentration atthe onset of saturation, where VCB=0. The slope of the freecarrier concentration line at the collector junction isproportional to the collector current density, and therefore,to the collector current.

Turn-on behaviourThe carrier concentration profile of a high-voltage transistorduring turn-on is shown in Fig. 13(a). Line 1 represents acondition where relatively few carriers are injected into thebase from the emitter. Let line 1 be defined as representingthe onset of saturation for the metallurgic collector junction;that is, point 1(C’). In this case, VCB=0, whereas theexternally measured collector voltage is very high becauseof the voltage drop across the high-resistivity collectorregion.

Fig. 12 Charge-control representation of a low-voltagetransistor:

Line a in the active regionLine b nearing the onset of saturation

Line c heavily saturated condition

Line2 in Fig. 13(a) represents ahigh level ofcarrier injectioninto the base from the emitter. Carriers have alsopenetrated the high-resistivity collector region as far aspoint 2(C’), and so the base region is now, in effect,extended to this point and the effective width of the collectorregion is reduced. The voltage drop across the collectorregion, caused by the collector current which is proportionalto the concentration gradient at point 2(C’), is therefore lessthan the voltage drop which occurred with the level of carrierinjection on line 1.

Lines 3, 4 and 5 represent still higher carrier injection levels,and hence decreasing effective collector widths. Thevoltage drop across the effective collector also decreases.

In the situation represented by line 6, the entire highresistivity collector region has been flooded with excesscarriers. The collector-base voltage is therefore so low thatthe transistor is effectively saturated. The low saturationvoltage has been obtained at the expense of a large basecurrent, and this explains why a high-voltage transistor hasa low current gain, especially at large collector currents.

Figure 13(b) shows simplified collector current/voltagecharacteristics for a typical high voltage transistor. Betweenlines OQ and OP, voltage VCE progressively decreases asexcess carriers swamp the high-resistivity collector region.Line OP can be regarded as the ’saturation’ line.

When the transistor is turned on, the carrier injection levelincreases from the very small cut-off level (not shown inFig. 13(a)) to the level represented by line 6 in Fig. 13(a).The transistor operating point therefore moves from thecut-off position along the locus shown in Fig. 13(b) toposition 6, which corresponds to line 6 in Fig. 13(a). Theeffect of this process on IC and VCE is shown in Fig. 13(c),where the time axis is labelled 0 to 6 to correspond to the

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Fig. 13 Turn-on behaviour of high voltage switchingtransistor.

numbered positions on the operating point locus ofFig. 13(b) and the numbered lines on the carrierconcentration diagram of Fig. 13(a).

The time taken to reach the emitter injection level 6 isdirectly proportional to the turn-on time of the transistor.The rate of build-up of emitter injection depends on the peakamplitude and rise time of the turn-on base current pulse.Theshortest turn-on time is obtained from a large amplitude

base current pulse with a fast leading edge. Thus, physicalconsiderations support the conclusion already drawn froma study of the circuit behaviour of the transistor.

Turn-off behaviour

The carrier concentration in the saturated transistor at thebeginning of the turn-off period is represented by line 0 inFig. 14(a), corresponding to line 6 in Fig. 13(a). As shownin Fig. 14(b), the base current IB gradually decreases, butIC remains almost constant for some time, and -IE thereforedecreases to match IB. The resulting carrier concentrationpatterns are shown as lines 1 and 2 in Fig. 14(a). Thisprocess is plotted against time in Fig. 14(b) where, again,the graduation of the horizontal axis corresponds to that ofthe lines in Fig. 14(a).

At time point 3 the emitter current has reduced to zero, andis slightly negative until point 6. Thus the carrierconcentration lines 4 and 5 have negative slope. Completecollector current cut-off is reached before point 6. (Thissituation is not represented in Fig. 14).

Excess carriers present in the collector region are graduallyremoved from point 0 onwards. This results in increasingcollector voltage because of the increasing effective widthof the high-resistivity collector region.

Figures 14(a) and 14(b) depict a typical turn-off processgiving good results with high voltage transistors; thewaveforms of Fig. 14(b) should be compared with those ofFigs. 3(d) and 7(a). A different process is shown inFigs. 15(a) and 15(b). The initial situation is similar (line 0,Fig. 15(a)) but the base current has a steep negative slope.At time point 1 of Fig. 15(b), the emitter current -IE hasreached zero, and so the carrier concentration line 1 haszero slope at the emitter junction. The emitter-base junctionis effectively cut off and only the relatively small leakagecurrent (not shown in Fig. 15(b)) is flowing. From point 1onwards, therefore, the emitter has no influence on thebehaviour of the transistor. The switching process is nolonger ’transistor action’, but the reverse recovery processof a diode. The carrier concentration pattern during thisprocess is shown in Fig. 15(a) in broken lines, with zeroslope at the emitter junction because the emitter isinoperative.

The reverse recovery process is slow because of the highresistivity of the collector region and the consequent slowdecrease of collector current. (Collector and base currentsare, of course, equal and opposite when the emitter is cutoff). The turn-off dissipation increases progressively as thetransition time from collector saturation to cut-off increases.Furthermore, at higher junction temperatures the reverserecovery charge, and hence the duration of the recoveryprocess, is greater.

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Fig. 14 Turn-off behaviour.

The longer the turn-off time, the greater the turn-offdissipation and, hence, the higher the device temperaturewhich itself causes a further increase in turn-off time anddissipation. To avoid the risk of thermal runaway andsubsequent transistor destruction which arises under theseconditions, the turn-off drive must be such that no part ofthe turn-off is governed by the reverse recovery process ofthe collector base diode. Actual transistor action should bemaintained throughout the time when an appreciableamount of charge is present in the transistor collector andbase regions, and therefore the emitter should continue tooperate to remove the excess charge.

There are many conditions of transistor turn-off which liebetween the extreme cases of Figs. 14(a) and 15(a).Circuits in which the operating conditions tend towardsthose shown in Fig. 15(a) must be regarded as a potentialsource of unreliability, and so the performance of suchcircuits at elevated temperatures should be carefullyassessed.

Fig. 15 Further turn-off waveforms.

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2.1.4 Isolated Power Semiconductors for High FrequencyPower Supply Applications

This section describes a 100 W off-line switcher using thelatest component and application technology forcost-effective miniaturisation (see Ref.1). Thepowersupplyhas a switching frequency of 500kHz with 1MHz outputripple. The section focuses on new power semiconductorcomponents and, in particular, the need for good thermalmanagement and electrical isolation. The isolated F-pack- SOT-186, SOT-199 and the new SOT-186A - areintroduced. Philips has developed these packages forapplications in S.M.P.S. The importance of screening tominimise conducted R.F.I. is covered and supported withexperimental results.

IntroductionThere is an ever-growing interest in high frequency powersupplies and examples are now appearing in the marketplace. The strong motivation for miniaturisation is wellfounded and a comprehensive range of high frequencycomponents is evolving to meet this important newapplication area, including:-

The output filter capacitor, which was traditionally anelectrolytic type, can be replaced by the lower impedancemulti-layer ceramic type.

The output filter choke may be reduced in size andcomplexity to a simple U-core with only a few turns.

The benefits of reduced transformer size can be realisedat high frequency by using core materials such as 3F3.However, transformer size is ultimately limited by creepageand clearance distances defined by international safetystandards.

Power MOSFETs provide the almost ideal switch, sincethey are majority carrier devices with very low switchinglosses. Similarly, Schottky diodes are the best choice forthe output rectifiers.

This paper concentrates on the semiconductors andintroduces three isolated encapsulations:- the ’F-packs’ -SOT-186, SOT-186A and SOT-199 - and applies them tohigh frequency S.M.P.S.

Power MOSFETs in isolated packages

Making power supplies smaller requires devices such asMOSFETs to be used as the power switch at highfrequency. At this high frequency the size and efficiency ofthe output filter can be dramatically improved. Presentabstract perception of acceptable inefficiency in powersemiconductors remains constant i.e. 5 to 10% overallsemiconductor loss at 500kHz is just as acceptable as at50kHz. So throughout the trend to higher frequencies, theheatsink size has remained constant.

Fig. 1 Mounting of SOT-186 and TO-220 compared.

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At 50kHz it is possible to use the earthed open frame of thepower supply as the heatsink. Then all semiconductors arelaid out around the periphery of the p.c.b. and mounted withisolation onto the heatsink. To gain the minimum overallsize from high frequency operation, this technique mustbecome standard practice to avoid having to leaveclearance distances between primary and secondary sideheatsinks. The component manufacturers are respondingto the need for transistors with isolation by making themwith a fully isolated package - the F-pack.

F-pack, SOT-186, is an encapsulation with a functionallyisolating epoxy layer moulded onto its header; see Fig. 1.This allows a common heatsink to be used with no furtherisolation components. With just a spring clip, an insulatedmounting (up to 1000V) of virtually all existing TO-220components is possible without degrading performance.Screw mounted, the SOT-186 is still simplicity itself; thereis no need for metal spacers, insulation bushes and micainsulators. Mounted either way, the F-pack reducesmounting hardware compared with that required for astandard TO-220.

The insulating layer of a SOT-186 can withstand more than1000V, but the maximum voltage between adjacent leadsis limited to 1000V. This is slightly less than the breakdownvoltage between TO-220 legs due to the distance betweenthe legs being reduced from 1.6mm to 1.05mm. However,the 375 µm thick epoxy gives more creepage and clearancebetween transistor legs and heatsink than a traditional micawasher of 50 µm. The capacitive coupling to an earthedheatsink is therefore reduced from 40pF to 13pF. This canbe of significant help with the control of R.F.I.

Fig. 2 Typical transient thermal response of SOT-186and TO-220 packages (experimental).

The latest isolated package introduced by Philips is theSOT-186A. This is a fully encapsulated TO-220replacementwhich provides true isolation from the heatsinkof 2500V RMS. It is fully pin-compatible with the TO-220package since it possesses the same distance between theleads and the back of the tab where thermal contact is madewith the heatsink.

The transient thermal response of the SOT-186 andTO-220encapsulations is shown in Fig. 2. A BUX84F (SOT-186)and a BUX84 (TO-220) were used for the test. Eachtransistor was mounted on a heatsink at 25˚C. The BUX84was mounted on a mica washer. The test conditions weregiven by: Mounting force = 30N; IE = 1A; VCB = 10V.

The thermal resistance of the F-pack is better than thestandard package in free air because it is all black andslightly larger. The difference is quite small, 55K/W for theSOT-186 and 70K/W for the TO-220. Mounted on aheatsink, the typical thermal resistance of the SOT-186 isslightly better than the standard TO-220, see Fig. 2.However, the exact value of Rth(mb-hs) depends on thefollowing:

- Whether heatsink compound is used.

- The screw’s torque or pressure on the encapsulation.

- The flatness of the heatsink.

The flatness of the TO-220 metal heatsink is morecontrollable than the moulded epoxy on the back of theSOT-186. Therefore, the use of a heatsink compound withSOT-186 is of great importance. Once this is done thethermal characteristics of the two approaches are similar.

Schottky diodes in isolated packagesTo be consistent with the small, single heatsink approach,the output rectifying diodes must be isolated from theheatsink too. Schottky diodes in SOT-186 are available,andencapsulations accommodating larger crystal sizes areavailable for higherpowers.The F-packversion of the largerSOT-93 package is the SOT-199. Two Schottky diodes canbe mounted in SOT-199 for power outputs up to a maximumof IF(AV) equal to 30 A. The SOT-199 package is similar to,but larger than, the SOT-186 shown in Fig. 1, and can bemounted similarly.

The epoxy isolation is thicker at 475µm. This furtherreduces the capacitive coupling to heatsink whencompared to a Schottky diode isolated with either 50µmmica or 250µm alumina. Equally important is the increasein the breakdown voltage, from a guaranteed 1000V to1500V. As with SOT-186, the use of heatsink compound isadvised to give good thermal contact.

In conclusion, the combination of isolated packages allowsan S.M.P.S. to be designed with many devices thermallyconnected to, but electrically isolated from, a singlecommon heatsink.

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Transistor characteristics affecting choiceof high frequency converter

In this exercise only MOSFETs were considered practicalfor the target operating frequency of 500kHz. The range ofconverters to choose from is enormous if all the resonantcircuits are included. The choice in this case is reduced byconsidering only the square wave types because:-• The p.w.m technique is well understood.• The main output is easily controlled over a wide range of

input voltages and output loads.• A resonant tank circuit, which may increase size, is not

needed.

It is recognised that there are many situations andcomponents which equally affect the choice of converter.The transformer component has been studied in Ref. 1. Formaximum power through the transformer in a mains input,500kHz, 100W power supply, a half-bridge converterconfiguration was chosen. The influence of the transistoris now examined.

The relationship of on-resistance RDS(on), with drain-sourcebreakdown voltage, V(BR)DSS, has been examined in Ref. 2.It was shown that RDS(on) is proportional to V(BR)DSS raised tothe power 2. This implies equal losses for equal total siliconarea. The advantage is therefore with the forward / flybackcircuits because they have easier drive arrangements andoften only require one encapsulation. Particular attentionis paid to the frequency dependent losses, which are nowconsidered.

COSS and the loss during turn-on

No matter how fast the transistor is switched in an attemptto avoid switching losses, there are always capacitancesassociated with the structure of the transistor which willdissipate energy each time the transistor is turned on andoff. For a BUK456-800A, 800V MOSFET of 20mm2 chiparea, the turn-off waveform is shown in Fig. 3.

All loads have been reduced to nearly zero to highlight theturn-on current spike due to the capacitance of the circuit.The discharge of the output capacitance of the device willbe similar but is unseen by the oscilloscope because it iscompletely internal to the device. The discharge of theenergy is done in two different stages:-

Stage 1 - From the flyback voltage to the D.C link voltage.

This energy is mainly either returned to the supply orclamped in the inductance of the transformer by thesecondary diodes, which release it to supply the load whenthe primary switch turns on. This energy is not dissipatedin the power supply.

Stage 2 - From the link voltage to the on-state voltage.

This energy is dissipated in the transistor when it turns on.The calculation of the effective output capacitance at thisvoltage involves integration to take into account the varyingnature of the capacitance with the applied drain voltage.The general expression for energy stored in the outputcapacitance of a MOSFET is:-

For a BUK456-800A switching on with VDS = 325V, theenergy is 1.6 µJ. Gate to drain capacitance is not taken intoaccount but would probably add about 20% extradissipation to take it to 1.9µJ. This is for a transistoroperating in a fixed frequency flyback, forward, or push-pullconverter. A transistor in the half bridge circuit switches onfromhalf the linevoltage and so the losses in each transistorwould be approximately a quarter of those in the previousconverters. In self-oscillating power supplies the transistorswitcheson from 750 V. This would dissipateall of the stage(1) energy as well and so that could make approximatelyfour times the loss in the transistor in this configuration. Thisexample of a BUK456-800A operating at 500kHz, in a fixedfrequency forward, flyback, or push pull system woulddissipate 0.95 W internal to the device.

Stray capacitance around the circuit includes mountingbase to heatsink capacitance, which for a ceramic isolatoris 18pF. The energy for this is simply calculated by using0.5 CV2, and is 1µJ when charged to 325 V. F-pack reducesthis by about a factor of two.

Fig. 3 MOSFET voltage and current waveforms in aforward converter.

In conclusion, the fixed frequency half-bridge systembenefits from discharging from only half the d.c. link voltageand is the best choice to minimise these effects. There aretwo switches, so the overall benefit is only half, but thethermal resistance is also half, so the temperature rise of

E = 3.3 Coss(25V) Vd1.5

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each transistor is actually four times less than in a forwardconverter. This makes this internal loss at 500kHz, 0.25 Win each transistor.

CISS and drive circuit lossesIt is common to drive MOSFETs from a voltage source,through a series gate resistor. This gate resistor is seenusually to dampen stray inductance ringing with the gatecapacitance during turn-on and turn-off of the transistor.This effectively prevents spurious turn-on. The resistor hasanother function when operating at a frequency of 500kHz,and that is to remove the dissipation of the energy of thegate capacitance from inside to outside the transistor. Thisis important because at frequencies in the MHz region thedissipation becomes the order of 1 W. A graph of chargingthe gate with a constant 1mA current source is shown inFig. 4. The area under the curve was measured as 220µVs.

Therefore, at 10kHz, the power dissipation is 2mW and at10MHz, 2W.

BUK455-500AFig. 4 Change of gate voltage with time for a power

MOSFET with a 1mA constant charge current.

If the system chosen has two transistors, as in thehalf-bridge, then the dissipation will be doubled. Therefore,a single transistor solution is the most efficient to minimisethese losses.

Concluding this section on the significant transistorcharacteristics, the power loss due to discharging internalMOSFET capacitances is seen to become significantaround 500kHz to 1MHz, affecting the efficiency of a 100Wconverter. The predominant loss is output capacitance,which is discharged by, anddissipated in RDS(on). Converterswhich reduce this loss are those which switch from a lowerVDS, i.e.:-

• Resonant converters which switch at zero voltage.

• Converters designed for rectified 110V a.c. mains ratherthan 230V a.c. mains.

• Square-wave converters which use a half-bridgeconfiguration rather than forward, flyback, or push-pullcircuits.

Self oscillating power supplies give higher losses becausethey discharge from the flyback voltage of 750V at turn-on.

SMPS design considerationsThere are two major areas which influence the choice ofconverter to be considered here:-

- multiple outputs

- R.F.I.

The influence of multiple outputs on thechoice of converter.If only one output is required then the half-bridge would beselected to minimise the loss due to output capacitance, asdescribed above.

If multiple outputs are specified, and some of these requirerectifying diodes other than Schottky diodes, then theswitching loss of power epitaxial diodes has to beconsidered. Before the arrival of 100V Schottky diodes,epitaxial diodes would have been a natural first choice foroutputs higher than 5V. However, a 12V auxiliary outputoften has less current than a 5V output, so MOSFETs cancompete better on forward volt drop. Then there is switchingloss: a MOSFET can have less loss than an epitaxial diode,but the actual frequency at which it becomes effective isdebatable.

Synchronous MOSFET rectifiers were first seen as a threattoSchottkydiodes for use in low voltageoutputs.They couldrectify with less forward volt drop, albeit sometimes at acost.MOSFETrectifiers are nowmore of a threat toepitaxialdiodes in higher voltage outputs above 15 to 20V. Applyingthese transistors is not as straightforward as it may firstappear. Looking at flyback, forward and bridge outputs inturn:-

Flyback converter

A diode rectified output is replaced by a MOSFET, with noextra components added, (Fig. 5). Putting the transistor inthe negative line and orientating it with the cathode of theparasitic diode connected to the transformer allows it to bedriven well and does not threaten the gate oxide isolation.If the drive is slowed down by the addition of a gate resistor,the voltage across RDS during transient switching can belarge enough such that, when added to the output voltage,gives VGS greater than that recommended in data. Fastturn-on is therefore essential for the good health of thetransistor.

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Fig. 5 Flyback and Forward converters with Synchronous Rectification.

Forward converter

Normal diode rectifiers are replaced by MOSFETs in aforward output, as shown in Fig. 5, with no extracomponents added. However, there is a problem atmaximum input voltage. At minimum volts, the transformerwinding supplies Vout + Vchoke, where:-

Vout = Vchoke = 12V (for a 12V output)at 50% mark/space ratio.

Vtrans = 24V

At maximum input volts, the choke may have 2 or 3 timesthe voltage across it, which makes the total 36V or 48V.With the gate rated at 20V, the choke is necessary for theforward transistor, as shown in Fig. 5, to supply the correctvoltage. It may also be necessary for the freewheel diode,but this may be marginal depending on the input voltagerange specified. This costs even more money, but may beconsidered good value if the loss in an epitaxial diode coststoo much in efficiency.

Bridge converters

The circuit shown in Fig. 6 at first glance looks attractive.Parasitic diodes are arranged never to come on, and thusdo not cause switching losses themselves. Also, the chokevoltage drop is less than in the forward case, which mayindicate that the MOSFETs can be used without extraoverwinds to protect the gate voltage.

However, the simple drive waveforms used here, which arenaturally synchronised to the primary switches, do not biasthe rectifying transistors on when both the switches are off.During this time the transformer magnetising currents needa path to freewheel around. Normally this path is providedby the diodes. When the drive has been removed in thecircuit example of Fig. 6, this path no longer exists. To turn

the transistor around so that their body diode can conductduring this freewheel time would only give diode turn-offloss, which is what the technique is intended to avoid. Anybypass diode has the same drawback. The correct drivewaveforms are not even available from the choke. They canbe generated most easily in conjunction with the primaryswitch waveforms, but involves expensive isolating drivetoroids.

The conclusions on which converters are most suitable,andhow to connect the MOSFETs in the most cost-effectivemanner for a 12V output are:-

• A flyback MOSFET rectifier can be connected with noextra components.

• A forward MOSFET needs one overwind, maybe two.

• A bridge output requires drive toroids whose signal is noteasily derivable from the secondary side waveforms.

Fig. 6 Half-Bridge converter with SynchronousRectification.

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Even though MOSFETs may have less switching loss thanepitaxial diodes, they do have capacitancedischarged eachcycle. The only consolation is that it has a built-in’anti-snap-off’ feature. If the rectifiers are switching at lowVDS then this loss is indeed very low.

Influence of R.F.I. on the choice ofconverterThis section deals with R.F.I. considerations of primaryswitches and secondary rectifying diodes only. Thetechniques will be applied to a power supply operating at500kHz that has been developed to deliver a single 5Voutput at 15A, from 250V a.c. mains input. The converterchoice is a half bridge circuit to minimise the loss in thecircuit due to COSS.

A single heatsink arrangement is required to minimise size,so primary and secondary semiconductors need to bethermally cooled on the same heatsink.R.F.I. currentsneedtobe prevented from coupling primary to secondary throughthe heatsink. Connection of R.F.I. screens underneath allcomponents attached to the metal is not necessary whenthe structure of the semiconductors is understood.

Taking the rectifiers first:-

The arrangement of the output bridge is shown in Fig. 7.The cathodes of the diodes are connected to the substratewithin their encapsulation. Thus, as long as the cathodesare connected as close as possible to the ceramiccapacitor, C3, of the output filter, the commoncathode/capacitor junction is a solid a.c. earth point.Therefore, no R.F.I. currents are connected into thecommon heatsink. An isolated encapsulation for anelectrical arrangement such as this is all that is needed tominimise R.F.I. from diodes to heatsink.

Considering next the primary power transistors:-

The arrangement of power transistors is also shown inFig. 7. The drains of the transistors are connected to thesubstrates of their encapsulations. Thus, as long as TR1 isconnected as close as possible to the film-foil bridgecapacitors, C1 and C2, the common drain/capacitorjunction is a solid a.c. earth point. A SOT-186, SOT-186A,SOT-199 or TO-220 with mica washers may be suitable forTR1, the final selection being dependent on the isolationrequirements. For TR2, the drain and therefore thesubstrate is modulated by the action of the circuit. Thus,without preventive action, R.F.I. currents will be coupled tothe heatsink.

Fig. 7 Half-Bridge converter power stage.

The transistor TR2 is in a similar situation to one in a flybackor forward configuration. A simple solution is to use aSOT-186 (F-pack), plus copper screen connected to thetransistor source lead and the film-foil capacitor, C2, pluswhatever degree of isolation is required to the heatsink.This assembly was tested, and the result was that thescreen reduced the line R.F.I. peaks by an average of 10dBover the range 500kHz to 10MHz. A small percentage ofthis can be attributed to the distance that the copper screenmoves the substrate away from the heatsink. Nevertheless,the majority is due to the inclusion of the 0.1mm thick copperscreen.

The conclusion is that a variety of encapsulations isnecessary to allow R.F.I. to be minimised when the powersupply is constructed.

Conclusions

This paper shows how to calculate some of the limitingparameters in the application of semiconductors to highfrequency SMPS. It also highlights new encapsulationsdeveloped for high frequency power conversionapplications. Some of the range of encapsulations weredemonstrated in a 500kHz half-bridge off-line switcher.

References

1. Improved ferrite materials and core outlines for highfrequency power supplies. Chapter 2.4.1

2. PowerMOS introduction. Chapter 1.2.1

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Output Rectification

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2.2.1 Fast Recovery Epitaxial Diodes for use in High FrequencyRectification

In the world of switched-mode power supply (S.M.P.S.)design, one of the most pronounced advances in recentyears has been the implementation of ever increasingswitching frequencies. The advantages include improvedefficiency and an overall reduction in size, obtained by theshrinking volume of the magnetics and filtering componentswhen operated at higher frequencies.

Developments in switching speeds and efficiency of theactive switching power devices such as bipolars,Darlingtons and especially power MOSFETs, have meantthatswitching frequencies of 100kHz are now typical. Somemanufacturers are presently designing p.w.m. versions atup to 500kHz, with resonant mode topologies (currently anarea of intensive academic research) allowing frequenciesof 1MHz and above to be achievable.

These changes have further increased demands on theother fundamental power semiconductor device within theS.M.P.S. - the power rectification diode.

Key Rectifier Characteristics.

In the requirements for efficient high frequency S.M.P.S.rectification, the diode has to meet the following criticalrequirements:-

- Short reverse recovery time, trr ,for compatibility with highfrequency use.

- Low forward voltage drop, VF , to maximise overallconverter efficiency.

- Low loss switching characteristics, which reduce themajor frequency dependent loss in the diode.

- A soft reverse recovery waveform, with a low dIR/dt rate,reduces the generation of unwanted R.F.I. within thesupply.

The Philips range of fast recovery epitaxial diodes (FREDs)has been developed to meet the requirements of highfrequency, high power rectification. With many years’experience in the development of epitaxial devicetechnology, Philips offers a comprehensive range ofFREDs. Some of their standard characteristics include:-

- A reverse blocking voltage range from 100V to 800V, andforward current handling capability from 1A to 30A. Thus,they are compatible for use in a wide range of S.M.P.S.applications, from low voltage dc/dc converters rightthrough to off-line ac/dc supplies. Philips epitaxial diodesare compatible with a range of output voltages from 10Vto 200V, with the capability of supplying a large range ofoutput powers. Several different package outlines arealso available, offering the engineer flexibility in design.

- Very fast reverse recovery time, trr , as low as 20ns,coupled with inherent low switching losses permits thediode to be switched at frequencies up to 1MHz.

- Low VF values, typically 0.8V, produce smaller on-statediode loss and increased S.M.P.S. efficiency. This isparticularly important for low output voltagerequirements.

- Soft recovery is assured with the whole range of FREDs,resulting in minimal R.F.I. generation.

Structure of the power diodeAll silicon power diodes consist of some type of P-I-Nstructure, made up of a highly doped P type region on oneside, and a highly doped N+ type on the other, bothseparated by a near intrinsic middle region called the base.The properties of this base region such as width, dopinglevels and recombination lifetime determine the mostimportant diode characteristics, such as reverse blockingvoltage capability, on-state voltage drop VF, and switchingspeed, all critical for efficient high frequency rectification.

(a) (b) (c) (d)

Fig. 1 Main steps in epitaxial diode process.

n

Epitaxial layer

Wafer

n+

n

n+

p p-diffusion

n

n+

p Full mesa passivation

n

n+

p metalglass

metal

161


A high blocking voltage requires a wide lightly doped base,whereas a low VF needs a narrow base. Using a short baserecombination lifetime produces faster recovery times, butthis also increases VF. Furthermore, in any P-N junctionrectifier operating at high currents, carrier injection into thebase takes place from both the P and N+ regions, helpingto maintain a low VF.

TechnologyHigh voltage power diodes are usually manufactured usingeither double-diffused or an epitaxial technology. Highinjection efficiency into the base coupled with a narrow basewidth are essential for achieving a low VF. High injectionefficiency requires the slope of the diffusion profile at theP+N and N+N junctions to be very steep. Achieving aminimum base width requires very tight control of the lightlydoped base layer. Both these criteria can be met usingepitaxial technology.

Epitaxial processThe epitaxial method involves growing a very lightly dopedlayer of silicon onto a highly doped N+ type wafer; seeFig. 1(a). A very shallow P type diffusion into the epi layeris then made to produce the required P-I-N structure(Fig. 1(b)).This gives accuratecontrol of the base thicknesssuch that very narrow widths may be produced. Abruptjunction transitions are also obtained, thus providing for therequired high carrier injection efficiency. The tighter controlof width and junction profile also provides a tighter controlof Qs, hence, the switching recovery times are typically tentimes faster than double diffused types.

Fig. 2 Comparison of diffusion profiles.(a) fast recovery epitaxial diode

(b) standard double diffused type

Double-diffused processDouble diffusion requires deep diffusions of the P+ and N+regions into a slice of lightly doped silicon, to produce therequired base width. This method is fraught with toleranceproblems, resulting in poor control of the base region. Thejunction transitions are also very gentle, producing a poorcarrier injection efficiency. The combination of the two

produces ahigher VFvalue, and also a poor control of storedcharge Qs in the base, leading to a relatively slow switchingspeed.

Figure 2 gives a comparison of the diffusion profiles for thetwo methods.

Lifetime controlTo achieve the very fast recovery time and low storedcharge, Qs, required for high frequency rectification, it isnecessary to introduce lifetime killing (gold doping) into thebase of the diode. This produces a lower Qs and fasterreverse recovery time, trr. Unfortunately, doping also hasthe effect of increasing VF. Fig. 3 shows a graph ofnormalised VF versus the minority carrier lifetime for a 200Vand 500V device. It can be seen that there is an optimumlifetime for each voltage grade, below which the VF

increases dramatically.

Philips has been using gold-killing techniques for well overtwenty years, and combining this with epitaxial technologyresults in the excellent low VF, trr and Qs combinations foundin the FRED range.

Fig. 3 Normalised VF versus minority carrier lifetime.

PassivationTo ensure that the maximum reverse blocking potential ofthe diode is achieved, it is necessary to ensure that highfields do not occur around the edges of the chip. This isachieved by etching a trough in the epitaxial layer anddepositing a special glass into it (Fig. 1(c)). Known as fullmesa glass passivation, it achieves stable reverse blockingcharacteristics at high voltages by reducing chargebuild-up, and produces a strong chip edge, reducing therisk of assembly damage. This means that the diodes arerugged and reliable, and also allows all devices to be fullytested on-slice.

200V

500V

*

*

10010minority carrier lifetime (nsec)

1.0

norm

alis

ed V

fin

crea

sing

Depth

Doping density

p

n

n+

Epitaxialdevice

(a)

Depth

Doping density

p

n

n+

Double

diffusedtype

(b)

162


Finally, Fig. 1(d) shows the chip after it has been diced andmetallised. The rectifier is then assembled into a wideselectionof differentpower packages, the standard TO-220outline being one example.

Characteristics

Forward conduction lossForward conduction loss is normally the major componentof power loss in the output rectification diodes of anS.M.P.S. For all buck derived output stages, for examplethe forward converter shown in Fig. 4, the choke currentalways flows in one or other of the output diodes (D1 andD2).

Fig. 4 Forward converter schematic.

The output voltage is always lowered by the diode forwardvoltage drop VF such that:-

Where D is the transistor duty cycle. Thus, the resultingpower loss due to VF of the output rectifiers is:-

where Io is the output load current of the converter. The lossas a percentage of the output power is thus:-

This loss in efficiency for a range of standard S.M.P.S.outputs is shown in Fig. 5. It is clear that Vf needs to be keptto an absolute minimum particularly for low output voltagesif reasonable efficiency is to be achieved.

To accommodate variations in the input voltage, the outputrectifiers are usually chosensuch that their blocking voltagecapability is between 4 and 8 times the output voltage. Forthe lowest output voltages, Schottky diodes should be thefirst choice. Unfortunately, the characteristically low Vf ofthe Schottky cannot be maintained at voltages much higherthan 100V. For outputs above 24V, fast recovery epitaxialdiodes are the most suitable rectifiers.

Fig. 5 Percentage S.M.P.S. loss versus VF for somestandard output voltages.

Figure 6 shows an example of VF versus forward current IFfor the Philips BYV32 series, rated from 50V to 200V andwith a maximum output current of 20A. This reveals the lowVF values typical of the epitaxial technique.

From Fig. 6 and equation 2, it is possible to estimate theloss due to the output rectifiers in an S.M.P.S. For example,for a 12V, 20A output, a conduction loss of 17W typical and20W maximum is obtained. This corresponds to a worstcase loss of 8% of total output power, normally anacceptable figure.

Philips devices offer some of the lowest VF values on themarket. Maximum as well as typical values are alwaysquoted at full rated currents in the datasheets. However thisis not the case with all manufacturers, and care should betaken when comparing Philips devices with those of othermanufacturers.

Vf Io

Vo Io

=Vf

Vo

(3)

C1

TR1

D1

D2

D3L1

C2

primsecVi

VoVp Vs

Ip

Is

drive

Simple forward converter circuit

0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

100

10

1

Diode forward voltage Vf (volts)

Per

cent

age(

%)

loss

5 V

O/P

10 V12 V

20 V

24 V

48 V

Vs

time

I

ID1

D2

time

time

Secondary voltage and diode current waveforms

reverse recoveryspike

at Vin max

at Vin min

Typ5 x Vo

T

Vo + Vf = Vs D (1)

Ponloss= Vf Io (2)

163


- - - - 150˚C, 25˚CFig. 6 VF vs IF for the Philips BYV32 series.

Reverse recovery

a) QS, trr and I rrm

Following VF, the most important feature of a high frequencyrectifier is the reverse recovery characteristic. This affectsS.M.P.S. performance in several ways. These includeincreased diode switching loss, higher peak turn-on currentand dissipation in the power transistors, and increasedgeneration of electro-magnetic interference (e.m.i.) andvoltage transient oscillations in the outputs. Clearly, therectifier must have optimum reverse recoverycharacteristics to keep this catalogue of effects to aminimum.

When the P-N diode is conducting forward current, a chargeis built up in the base region, consisting of both electronsand holes. It is the presence of this charge which is the keyto achieving low Vf. The higher the forward current, thegreater is this stored charge. In order to commutate thediode (i.e switch the device from forward conduction intoreverse blocking mode) this charge has to be removed fromthe diode before the base can sustain any reverse blockingvoltage. The removal of this charge manifests itself as asubstantial transient reverse current spike, which can alsogenerate a reverse voltage overshoot oscillation across thediode.

The waveforms of the reverse recovery for a fast rectifierare shown in Fig. 7. The rectifier is switched from its forwardconduction at a particular rate, called dIF/dt. Stored chargebegins to be extracted after the current passes throughzero, and an excess reverse current flows. At this point thecharge is being removed by both the forcing action of thecircuit, and recombination within the device (dependentupon the base characteristics and doping levels).

At some point the charge has fallen to a low enough levelfor a depletion region to be supported across the base, thusallowing the diode to support reverse voltage. The peak ofreverse current, Irrm occurs just after this point. The time forthe current to pass through zero to its peak reverse valueis called ta. From then on, the rectifier is in blocking mode,and the reverse current then falls back to zero, as theremainder of the stored charge is removed mostly byrecombination. The time for the peak reverse current to fallfrom its maximum to 10% of this value is called tb.

Fig. 7 Rectifier diode reverse recovery waveforms.

The stored charge, Qs, is the area under the current-timecurve and is normally quoted in nano-Coulombs. The sumof ta and tb is called the rectifier reverse recovery time, trrand gives a measure of the switching speed of the rectifier.

Factors influencing reverse recovery

In practice, the three major parameters trr, Qs and Irrm areall dependent upon the operating condition of the rectifier.This is summarised as follows:-

• Increasing the forward current, IF, increases trr, Qs andIrrm.

• Increasing the dIF/dt rate by using a faster transistor andreducing stray inductance, significantly decreases trr, butincreases Qs and Irrm. High dIF/dt rates occur in the highfrequency square wave switching found in S.M.P.S.applications. (MOSFETs can produce very small falltimes, resulting in very fast dIF/dt).

• Increasing diode junction temperature, Tj increases allthree.

• Reducing the reverse voltage across the diode, Vr , alsoslightly increases all three.

IfIf

dIfdt

Qs

t

trr

10%

dIrdt

Vf

V RM

IRRM

current

voltage

V R

0

IR

ta tb

164


Specifying reverse recovery

Presently, all manufacturers universally quote the trr figureas a guide. This figure is obtained using fixed testprocedures. There are two standard test methods normallyused:-Method 1Referring to the waveform of Fig. 7:IF = 1A; dIF/dt =50A/µsec; Vr > 30V; Tj= 25˚C.trr is measured to 10% of Irrm.

Fig. 8 E.I.A. trr test procedure.

Method 2IF = 0.5A, the reverse current is clamped to 1A and trr ismeasured to 0.25A.This is the Electronics Industries Association (E.I.A.) testprocedure, and is outlined in Fig. 8.

The first and more stringent test is the one used by Philips.The second method, used by the majority of competitorswill give a trr figure typically 30% lower than the first, i.e. willmake the devices look faster. Even so, Philips have thebest trr / Qs devices available on the market. For example,

the Philips BYW29 200V, 8A device has a trr of 25ns, thecompetitordevicesquote 35ns using the easiersecond test.This figure would be even higher using test method 1.

Reverse recovery is specified in data by Philips in terms ofall three parameters trr, Qs and Irrm. Each of theseparameters however is dependent on exact circuitconditions. A set of characteristics is therefore providedshowing how each varies as a function of dIf/dt, forwardcurrent and temperature, Fig. 9. These curves enableengineers to realise what the precise reverse recoveryperformance will be under circuit operating conditions. Thisperformance will normally be worse than indicated by thequoted figures, which generally speaking do not reflectcircuit conditions. For example, a BYW29 is quoted ashaving a trr of 25 ns but from the curves it may be as highas 90 ns when operated at full current and high dIF/dt.Similarly aquoted Qs of 11 nC compares with the full currentworst case of 170 nC.

In the higher voltage devices (500V and 800V types) trr andQs are much higher, and will probably be the most criticalparameters in the rectification process. Care must be takento ensure that actual operating conditions are used whenestimating more realistic values.

Frequency range

Figure 10 compares the recovery of a Philips 200V FREDwith a double diffused type. The FRED may be switchedapproximately10 times faster than the double diffused type.This allows frequencies of up to 1MHz to be achieved withthe 200V range.

If

0.5A

1.0AIR

00.25A

t RR

clamped IR

time

Fig. 9 Reverse recovery curves for BYW29.

1 10 102

1

10

102

103

Tj = 25 C Tj = 100 C

trr(ns)

(a) Maximum trr

If=10A5A 1A

1A5A10A

dIf/dt (A/us)1 10 10

21

10

102

103

Qs(nC)

If=10A

5A2A

10A5A

2A1A

Tj = 25 C Tj = 100 C

dIf/dt (A/us)

(b) Maximum Qs1 10 10

2

Tj = 25 C Tj = 100 C10

1

0.1

0.01

IRRM

(A)

(c) Maximumm I RRM

If=10A5A

2A1A

1A2A

5A10A

dIf/dt (A/us)

165


In the higher voltage devices where the base width isincreased to sustain the reverse voltage, the amount ofstored charge increases, as does the trr. For a 500V device,500kHzoperation is possible,and for 800Vtypically 200kHzis realistic.

Fig. 10 Comparison of reverse recovery of FRED vsdouble diffused.

(a) Philips 200V FRED.(b) Double-diffused diode.

Effects on S.M.P.S operation

In order to analyse the effects of reverse recovery on thepower supply, a simple non-isolated buck converter shownin Fig. 11 is considered. The rectifier D1 in this applicationis used in freewheel mode, and conducts forward currentduring the transistor off-time.

Fig. 11 Buck converter.

The waveforms for the diode and transistor switch duringthe reverse recovery of the diode when the transistor turnson again are given in Fig. 12.

As the transistor turns on, the current ramps up in thetransistor as it decays and reverses in the diode. The dIF/dtis mainly dependent on the transistor fall time and, to someextent, the circuit parasitic inductances. During the periodta the diode has no blocking capability and therefore thetransistor must support the supply voltage. The transistorthus simultaneously supports a high voltage and conducts

both the load current and the reverse recovery current,implying a high internal power dissipation. After time ta thediode blocking capability is restored and the voltage acrossthe transistor begins to fall. It is clear that a diode with anIrrm half the value of IF will effectively double the peak powerdissipation in the transistor at turn-on. In severe caseswhere a high Irrm / trr rectifier is used, transistor failure couldoccur by exceeding the peak current or power dissipationrating of the device.

Fig. 12 Reverse recovery diode and transistorwaveforms.

There is also an additional loss in the diode to beconsidered. This is a product of the peak Irrm and the diodereverse voltage, Vr. The duration of current recovery to zerowill affect the magnitude of the diode loss. However, in mostcases the additional transistor loss is much greater than thediode loss.

Diode loss calculationAs an example of the typical loss in the diode, consider theBYW29, 8A, 200V device as the buck freewheel diode, forthe following conditions:-

IF = 8A; Vr =100V; dIF/dt = 50A/µs;Tj = 25˚C; duty ratio D = 0.5; f = 100KHz.

The diode reverse recovery loss is given by:-

From the curves of Fig. 7, trr=35ns, Irrm = 1.5A. Assuming tb= trr/2 gives:

(A)

(B)

1A/div

50ns/div

0A

0A

Irrm

t

t

t

t

Transistor

switch

waveforms

Transistor

loss

Diode

waveforms

Diode

loss

Vsw

Isw

Psw

Id

Vd

Pd

0

0

0

0

additionalturn-onloss

diodereverse recovery

loss

ta tb

trr

Vin VoL1

D1 Co

TR1

Prr =12

⋅ Vr ⋅ Irrm ⋅ tb ⋅ f

Prr =12

⋅ 100⋅ 1.5⋅ 17.5⋅ 100k= 132mW

166


This is still small compared to the diode VF conduction lossof approximately 3.6 W. However, at Tj=100˚C,dIF/dt=100A/µs and f=200kHz, the loss becomes 1.05W,which is fairly significant. In the higher voltage deviceswhere trr and Irrm are significantly worse, then the frequencydependent switching loss will tend to dominate, and can behigher than the conduction loss. This will limit the upperfrequency of operation of the diode.

The turn-on current spike generated in the primary circuitsdue to diode reverse recovery can also seriously affect thecontrol of the S.M.P.S. when current mode control is used(where the peak current is sensed). An RC snubber isusually required to remove the spike from the sense inputs.Good reverse recovery removes the need for theseadditional components.

b) Softness and dI R/dtWhen considering the reverse recovery characteristics, itis not just the magnitude (trr and Irrm) which is important, butalso the shape of the recovery waveform. The rate at whichthe peak reverse current Irrm falls to zero during time tb isalso important. The maximum rate of this slope is calleddIR/dt and is especially significant. If this slope is very fast,it will generate significant radiated and conducted electricalnoise in the supply, causing R.F.I. problems. It will alsogenerate high transient voltages across circuit inductancesin series with the diode, which in severe cases may causedamage to the diode or the transistor switch by exceedingbreakdown limits.

Fig. 13 "Soft" and "snappy" reverse recovery.

A diode which exhibits an extremely fast dIR/dt is said tohave a "snap-off" or "abrupt" recovery, and one whichreturns at a relatively smooth, gentle rate to zero is said tohave a soft recovery. These two cases are shown in thewaveforms in Fig. 13. The softness is dependent uponwhether there is enough charge left in the base, after thefull spread of the depletion region in blocking mode, to allowthe current to return to zero smoothly. It is mainly by therecombination mechanism that this remaining charge isremoved during tb.

Maintaining tb at a minimum would obviously give somereduction to the diode internal loss. However, a snappyrectifier will produce far more R.F.I. and transient voltages.The power saving must therefore be weighed against the

additional cost of the snubbers and filtering which wouldotherwise be required if the rectifier had a snappycharacteristic.

The frequency range of R.F.I. generated by dIR/dt typicallylies in the range of 1MHz to 30MHz, the magnitude beingdependent upon how abrupt the device is. One secondaryeffect that is rarely mentioned is the additional transformerlosses that will occur due to the extremely high frequenciesgenerated inside it by the diode recovery waveform. Forexample, core loss at 10MHz for a material designed tooperate at 100kHz can be significant. There will also beadditional high frequency loss in the windings due to theskin effect. In this case the use of a soft device whichgenerates a lower frequency noise range will reduce theselosses.

Characterising softness

A method currently used by some manufacturers tocharacterise the softness of a device is called the softnessfactor, S. This is defined as the ratio of tb over ta.

An abrupt device would have S much less than 1, and asoft device would have S greater than 1. A compromisebetween R.F.I. and diode loss is usually required, and asoftness factor equal to 1 would be the most suitable valuefor a fast epitaxial diode.

Fig. 14 Different diode dIR/dt rates for same softnessfactor.

Although the softness factor does give a rough guide to thetype of recovery and helps in the calculation of the diodeswitching loss, it does not give the designer any real ideaof the dIR/dt that the rectifier will produce. Hence, levels ofR.F.I. and overvoltages could be different for devices withthe same softness factor. This is shown in Fig. 14, wherethe three characteristics have the same softness factor butcompletely different dIR/dt rates.

In practice, a suitable level for dIR/dt would be to have itvery similar in magnitude to dIF/dt. This would keep thenoise generated to a minimum.

softness factor, S =tbta

t t

IrrmIrrm

Snap-offrecovery

softrecovery

(a) (b)

I I

ta tb ta tb ta tb

(a) (b) (c)

167


At present there is no universal procedure used bymanufacturers to characterise softness, and so any figuresquoted must be viewed closely to check the conditions ofthe test.

Comparison with competitor devices

Figure 15 compares a BYV32 with an equivalent competitordevice. This test was carried out using an L.E.M. Qs testunit.

The conditions for each diode were identical. The resultswere as follows:-

Fig. 15 Comparison of softness of reverse recovery.(a) Philips BYV32 200V 8A device(b) Equivalent competitor device

BYV32:- S = 1.2, dIR/dt = 40A/µs,Voltage overshoot = 5V

Competitor:- S = 0.34, dIR/dt = 200A/µs,Voltage overshoot = 22V

For the Philips device, apart from the very low Qs and Irrm

values obtained, the S factor was near 1 and the dIR/dt ratewas less than the original dIF/dt of 50A/µs. These excellentparameters produce minimal noise and the very smallovershoot voltage shown. The competitor device was muchsnappier, the dIR/dt was 4 times the original dIF/dt, andcaused a much more severe overshoot voltage with theassociated greater R.F.I. The diode loss is also higher inthe competitor device even though it is more abrupt, sinceQs and Irrm are larger.

The low Qs of the Philips FRED range thus maintains diodeloss to a minimum while providing very soft recovery. Thismeans using a Philips type will significantly reduce R.F.I.and dangerous voltage transients, and in many casesreduce the power supply component count by removing theneed for diode snubbers.

Forward recovery

A further diode characteristic which can affect S.M.P.S.operation is the forward recovery voltage Vfr. Although thisis not normally as important as the reverse recovery effectsin rectification, it can be particularly critical in some specialapplications.

Fig. 16 Forward recovery characteristics.

I

V

20ns/div

(a)

If =8A

Tj = 25 C

Vr = 30V

1A/div

10V/div

dIf/dt = 50A/usec

V

I

1A/div

10V/div

20ns/div

(b)

If = 8A

Tj = 25 CVr = 30V

dIf/dt = 50A/usec

10%

90%

If

tr

100% 110%

t fr

Vf

t

t

0

0

Vfrm

168


Forward recovery is caused by the lack of minority carriersin the rectifier p-n junction during diode turn-on. At theinstant a forward bias is applied, there are no carrierspresent at the junction. This means that at the start ofconduction, the diode impedance is high, and an initialforward voltage overshoot will occur. As the current flowsand charge builds up, conductivity modulation (minoritycarrier injection) takes place. The impedance of the rectifierfalls and hence, the forward voltage drop falls rapidly backto the steady state value.

The peak value of the forward voltage is known as theforward recovery voltage, Vfrm. The time from the forwardcurrent reaching 10% of the steady state value to the timethe forward voltage falls to within 10% of the final steadystate value is known as the forward recovery time (Fig. 16).

The magnitude and duration of the forward recovery isnormally dependent upon the device and the way it iscommutated in the circuit. High voltagedevices will producelarger Vfrm values, since the base width and resistivity(impedance) is greater.

The main operating conditions which affect Vfr are:-• If; high forward current, which produces higher Vfr.• Current rise time, tr; a fast rise time produces higher Vfr.

Effects on s.m.p.s.

The rate of rise in forward current in the diode is normallycontrolled by the switching speed of the power transistor.When the transistor is turned off, the voltage across it rises,and the reverse voltage bias across the associated rectifierfalls. Once the diode becomes forward biased there is adelay before conduction is observed. During this time, thetransistor voltage overshoots the d.c supply voltage whileit is still conducting a high current. This can result in thefailure of the transistor in extreme cases if the voltagelimiting value is exceeded. If not, it will simply add to thetransistor and diode dissipation. Waveforms showing thiseffect are given in Fig. 17.

Fig. 17 Forward recovery effect on transistor voltage.

Table 1 outlines typical Vfrm values specified for rectifiers ofdifferent voltage rating. This shows the relatively low valuesobtained. No comparable data for any of the competitordevices could be found in their datasheets. It should benoted that in most S.M.P.S. rectifier applications, forwardrecovery can be considered the least important factor in theselection of the rectifier.

Device VBR If dIf/dt typ Vfrm

type (Volts) (Amps) (A/µs) (Volts)

BYW29 200 1.0 10 0.9

BYV29 500 10 10 2.5

BYR29 800 10 10 5.0

Table 1. Vfrm values for different Philips devices.

Reverse leakage currentWhen a P-N junction is reverse biased, there is always aninherent reverse leakage current that flows. In any piece ofundoped semiconductor material there is a thermallygenerated background level of electron and hole pairs.These pairs also naturally recombine, such that anequilibrium is established. In a p-n junction under reversevoltage conditions, the electric field generated will sweepsome of the free carriers generated out of the device beforethey can recombine, hence causing a leakage current. Thisphenomenon is shown in Fig. 18.

Fig. 18 Clarification of reverse leakage current.

When the rectifier base is gold doped to decrease Qs andtrr, a new energy level is introduced very close to the centreof the semiconductor energy band gap. This provides lowerenergy transition paths as shown, and thermal generation

P N

Vr

e_

h+

Ir

distance

Eapplied electric field

intensity

Econduction

Evalence

Eitransition

transition

recombination centre added

1.1eV

lower energy

lower energy

p-n junction

due to dopingVswitch

Vswitch

Iswitch

0 time

Idiode

switch off

diodeconducts

diodeforward biased

169


(and recombination)of hole-electron pairs is more frequent.Thus, the reverse leakage current is greater still in the killed,fast rectifier.

Since the pairs are generated thermally, it is obvious thatraising the junction temperature will increase the leakagesignificantly. For example, the leakage current of a FREDcan increase by up to 20 times by raising the junctiontemperature, Tj from 25˚C to 100˚C. This increase can befar greater in other diode technologies.

Many S.M.P.S. designers have a misconception aboutleakage current, and believe that it renders the rectifier poorquality, giving high losses, and is unreliable. This is not so.Leakage is a naturally occurring effect, and is present in allrectifiers. The leakage in an S.M.P.S. diode is normallyextremely small and stable, with very little effect on therectification process. Some manufacturers haveover-emphasised the benefits of very low leakage devices,claiming that they have great advantages. However, thiswill be shown to be groundless, since any reduction in theoverall diode power loss will be minimal.

In practice, the reverse leakage current only becomessignificant athigh operating temperatures (above 75˚C) andfor high reverse blocking voltages (above 500V), where theproduct of reverse voltage and leakage current (hence,power loss) is higher. Even then, the leakage current is stillusually lower than 1mA.

Table 2 lists the maximum leakage currents for some of thedevices from the Philips range (gold killed), revealing lowlevels,even in the higher voltage devices, achieved throughoptimised doping.

Device VBR(max) max Ir (mA) max Ir (µA)type (Volts) Tj =100˚C Tj=25˚C

full Vrrm full Vrrm

BYW29 200 0.6 10

BYV29 500 0.35 10

BYR29 800 0.2 10

Table 2. Maximum reverse leakage currents for Philipsdevices.

The power dissipation due to leakage is a static loss anddepends on the product of the reverse voltage and theleakage current over a switching cycle. A worst caseexample is given below where the data sheet leakagecurrent maximum is used at maximum reverse blockingvoltage of the diode.

S.M.P.S example:-Flyback converterConsider first the BYV29-500 as the output rectifier in thediscontinuous flyback converter (Note: the reverse blockingoccurs during the transistor on time, and a minimum dutyof 0.25 has been assumed.) The BYV29-500 couldgenerate a possible maximum output voltage of 125V. Themaximum leakage power loss is:-

Alternatively, for the BYR29-800, maximum rectified outputis approximately 200V, and by similar calculations, itsmaximum loss is 40mW. Lower output voltages would giveleakage losses lower than this figure.

These types of calculation can be carried out for othertopologies, when similar low values are obtained.

ConclusionPhilips produces a comprehensive range of Fast RecoveryEpitaxial Diodes. The devices have been designed toexhibit the lowest possible Vf while minimising the majorreverse recovery parameters, Qs, trr and Irrm. Because of thelow Qs, switching losses within the circuit are minimised,allowing use up to very high frequencies. The soft recoverycharacteristic engineered into all devices makes themsuitable for use in today’s applications where low R.F.I. isan important consideration. Soft recovery also providesadditional benefits such as reduced high frequency lossesin the transformer core and, in some cases, the removal ofsnubbing components.

PL = 500V⋅ 0.35mA⋅ 0.25= 43.75mW

170


FRED Selection Guide

Single Diodes

Type Number Outline IF(AV) max Voltage Grades

Amps 100 150 200 300 400 500 600 700 800

BYW29E TO-220AC 8 * * *

BYV29 TO-220AC 9 * * *

BYR29 TO-220AC 8 * * * *

BYV79E TO-220AC 14 * * *

BYT79 TO-220AC 14 * * *

Dual Diodes (Common cathode)

Type Number Outline IO max Voltage Grades

Amps 100 150 200 300 400 500 600 700 800

BYV40 SOT-223 1.5 * * *

BYQ27 SOT-82 10 * * *

BYQ28E TO-220AB 10 * * *

BYT28 TO-220AB 10 * * *

BYV32E TO-220AB 20 * * *

BYV34 TO-220AB 20 * * *

BYV42E TO-220AB 30 * * *

BYV72E SOT-93 30 * * *

BYV44 TO-220AB 30 * * *

BYV74 SOT-93 30 * * *

’E’ denotes rugged device.

171


Single Diodes (Electrically isolated Package)

Type Number Outline IF(AV) max Voltage Grades

Amps 100 150 200 300 400 500 600 700 800

BYW29F SOT-186 8 * * *

BYV29F SOT-186 9 * * *

BYR29F SOT-186 8 * * *

Dual Diodes (Electrically Isolated Package)

Type Number Outline IO max Voltage Grades

100 150 200 300 400 500 600 700 800

BYQ28F SOT-186 10 * * *

BYV32F SOT-186 12 * * *

BYV72F SOT-199 20 * * *

BYV74F SOT-199 20 * * *

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2.2.2 Schottky Diodes from Philips Semiconductors

The Schottky diodes from Philips have always had goodforward characteristics and excellent switchingperformance. With this new, more extensive range ofSchottky diodes come the additional benefits of stable, lowleakage reverse characteristics and unsurpassed levels ofguaranteed ruggedness.

The performance improvements have been achieved bychanging both the design and the processing of Schottkydiode wafers. The changes are the products of thecontinuing programme of research in the field of Schottkybarrier technology being carried out at Stockport.

This report will look at the new range, the improvementsthat have been made and the changes that have producedthem.

New processThe manufacturing process for all the devices in the newrange includes several changes which have significantlyimproved the quality and performance of the product.

Perhaps the most significant change is moving theproduction of the Schottky wafers from the bipolarprocessing facility into the PowerMOS clean room. TheSchottky diode is a ’surface’ device - its active region is rightat the conductor / semiconductor interface, not deep withinthe silicon crystal lattice. This means that it can usefullyexploit the high precision equipments and extremely cleanconditions needed to produce MOS transistors. In somerespects Schottkies have more in common with MOStransistors than they do with traditional bipolar products. Inone respect they are identical - their quality can bedramatically improved by:-

- growing purer oxide layers,

- depositing metal onto cleaner silicon,

- more precise control of ion implantation.

Another change has been in the method of producing theSchottky barrier. The original method was to ’evaporate’molybdenum onto the surface of the silicon. In the newprocess a Pt/Ni layer is ’sputtered’ onto the surface andthen a heat treatment is used to produce a Pt/Ni silicide.This has the effect of moving the actual conductor /semiconductor interface a small distance away from thesurface and into the silicon.

The advantage of this change is that it puts the barrier inan environment where the conditions are morehomogeneous, resulting in a more consistent barrier. Thisconsistency produces devices in which every part of theactive area has the same reverse characteristic.

Ruggedness

The RUGGEDNESS of a Schottky diode is a measure ofits ability to withstand the surge of power generated by thereverse current which flows through it when the appliedreverse voltage exceeds its breakdown voltage. Operationin this mode is, of course, outside the boundaries of normaloperation - it always exceeds the VRRM rating of the device.However, situations can arise where the voltages presentin the circuit far exceed the expectations of the designer. Ifdevices are damaged by these conditions then theequipment they are in may fail. Such failures often result inequipments being condemned as unreliable. In recognitionof this, Philips will now supply devices which operatereliably during both normal and abnormal operation.

All the Schottky diodes supplied by Philips now have twoguaranteed reverse surge current ratings:-

IRRM - guarantees that devices can withstand repetitivereverse currentpulses (tp =2µs; ∆ = 0.001)of greaterthan the quoted value,

IRSM - guarantees that single, 100µs pulses of the ratedvalue can be applied without damage.

At the moment these ratings are quoted as either 1A or 2A,depending on device size. It should be understood thatthese figures do not represent the limit of device capability.They do, however, represent the limit of what, experiencesuggests, might be needed in most abnormal operationalsituations.

In an attempt to determine the actual ruggedness of thenew devices, a series of destructive tests was carried out.The results shown in Fig. 1 give the measured reverseruggedness of different sizes of device. It clearly shows thateven small devices easily survive the 1A IRRM / IRSM limit andthat the larger devices can withstand reverse currentsgreater than the 85A that the test gear was designed todeliver.

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Fig. 1 Typical reverse ruggedness

Reverse leakage

The reverse characteristic of any diode depends upon twofactors - ’bulk’ and ’edge’ leakage. The first is the currentwhich leaks through the reverse biased junction in the mainactive areaof the device.The second is the leakage throughthe junction around its periphery - where the junction meetsthe outside world. Attention must be paid to both of thesefactors if ahighperformance diode is to beproduced. Duringthe development of the new range of Philips Schottkydiodes both of these factors received particular attention.

Bulk leakage

To achieve low forward voltage drop and very fastswitching, Schottky diodes use the rectifying properties ofa conductor / semiconductor interface. The ’height’ of thepotential barrier has a significant effect upon both theforward voltage drop and the reverse leakage. High barriersraise the VF and lower the general reverse leakage level.Conversely low barrier devices have a lower VF but higherleakage. So the choice of barrier height must result in thebest compromise between leakage and VF to producedevices with the best allround performance.

The height of a Schottky barrier depends, to a large extent,upon the composition of the materials at the interface. Sothe selection of the barrier metal and the process used forits deposition is very important. The final decision was madewith the help of the extensive research and devicemodelling facilities available within the Philips organisation.The materials and processes that were selected havesignificantly reduced the bulk leakage of the new range ofSchottky diodes. It is believed that this present design givesthe optimum balance between leakage and Vf that iscurrently achievable.

Edge leakageThe other component influencing the reverse characteristicis edge leakage. In a diffused diode the mechanisms whichoperate at the edge of the active area - where the junctionmeets the outside world - are different from those whichoperate in the centre. The Schottky barrier is the same asa diffused junction in this respect. The field at the edge ofa simple (untreated in any way) Schottky barrier is very highand as a consequence the leakage through the junction atthe periphery can also be very high.

In diffused diodes the edge of the junction is treated by’passivating’ it. In a Schottky diode the edge of the barrieris treated by implanting a shallow, very low dose, p regionaround the periphery of the active area. This region, calleda ’guard ring’, effectively replaces the high field peripheryof the barrier. It is now the characteristics of the guard ringwhich determine the edge leakage and not those of theSchottky barrier.

In this way the mechanisms controlling the two elementsof leakage are now independent and can be adjustedseparately, eliminating the need for compromises. Thisfreedom, and a combination of good design and the closetolerance control - achievable with ion implantation -ensures that the characteristics are excellent, having bothgood stability and very low leakage.

Fig. 2 Cross Section of Schottky Diode

Overall leakageAs mentioned earlier, good reverse characteristics relyupon both the edge and bulk leakages being good. Byeliminating the interactions between the mechanisms andby concentrating on optimising each, it has been possibleto improve both edge and bulk leakage characteristics. Thishas allowed Philips to produce Schottky diodes with typicalroom temperature reverse currents as low as 20µA, or100µA max (PBYR645CT) - considerably lower than wasever achieved with molybdenum barrier devices.

Max

imum

Rev

erse

Rec

over

y C

urre

nt (

amps

)

100

90

80

70

60

50

40

30

20

10

0 2 3 4 5 6 7 8 9 10 20 30

Data Limit

Test Gear Limit

Active Area of Crystal (mm 2 )

PtNi

Silicide

Guard RingOxide

TiAl

174


RangeThe Schottky diode was originally designed to be used asthe rectifier and freewheel diode in the 5V output of highfrequency SMPS. The arrival of the new 100V Schottkieshas now extended this up to 24V outputs. These suppliesare fitted into equipments whose power requirements varywidely. Satisfying these needs efficiently means that anequally wide range of supplies has to be produced. Inrecognition of this, Philips has produced a range of diodepackages with current ratings from 6A to 30A. With thisrange it is possible to produce power supplies of 20W to500W output - higher powers are achievable withparallelling.

The full range of Philips Schottky diodes is shown inTable 1. At the heart of the range are the ’PBYR’ devices.The numbers and letters following the PBYR prefix arecompatible with industry standards. These figures give anindication of a device’s structure (single or dual) and itscurrent and voltage rating. An explanation of the numbersis given in Table 2. Care has been taken to ensurecompatibility between Philips devices and those from othersuppliers, which share number/letter suffices. It is hopedthat this will ease the process of equivalent type selection.

Included in the range is a group of devices with ’BYV1xx’numbers. These devices are a selection of the most populartypes from the previous Philips Schottky range. They haveproved to be conveniently sized devices which have a mixof ratings and characteristics not matched by other

manufacturers. Although these are ’old’ numbers, delivereddevices will have been manufactured by the new processand will therefore be better. However, changing theproduction process of established types can often causeconcern amongst customers. Philips has recognised thisand, during the development, took particular care to ensurethat all the new devices would be as closely comparableas possible with previously delivered product. Clarificationis given in the cross reference guide given in Table 3.

Summary

This range ofSchottky diodes enhances the ability ofPhilipsComponents to meet all the requirements and needs of theSMPS designer. The well established range of epitaxialdiodes,bipolar andPowerMOStransistors, ICs and passivecomponents is now complemented by a range of Schottkydiodes with:-

- very low forward voltage drop,

- extremely fast reverse recovery,

- low leakage reverse characteristics, achieved WITHOUTcompromising overall system efficiency

- stable characteristics at both high and low temperatures

- guaranteed ruggedness, giving reliability under bothnormal and abnormal operating conditions.

175


Table 1 Range of Schottky Diodes

Single DiodeType Number Outline IF(AV) (A) IO (A) Voltage Grades (V)

per diode per device 35 40 45 60 80 100

PBYR7** TO-220AC 7.5 7.5 * * *

PBYR10** TO-220AC 10 10 * * * * * *

PBYR16** TO-220AC 16 16 * * *

Dual Diodes - Common CathodeType Number Outline IF(AV) (A) IO (A) Voltage Grades (V)


PBYR2**CT SOT-223 1 2 * * *

PBYR6**CT SOT-82 3 6 * * *

BYV118** TO-220AB 5 10 * * *

PBYR15**CT TO-220AB 7.5 15 * * *

BYV133** TO-220AB 10 20 * * *

PBYR20**CT TO-220AB 10 20 * * * * * *

BYV143** TO-220AB 15 30 * * *

PBYR25**CT TO-220AB 15 30 * * *

PBYR30**PT SOT-93 15 30 * * * * * *

Dual Diodes - Common Cathode (Electrically Isolated Package)Type Number Outline IF(AV) (A) IO (A) Voltage Grades (V)


BYV118F** SOT-186 (3 leg) 5 10 * * *

PBYR15**CTF SOT-186 (3 leg) 7.5 15 * * *

BYV133F** SOT-186 (3 leg) 10 20 * * *

PBYR20**CTF SOT-186 (3 leg) 10 20 * * *

BYV143F** SOT-186 (3 leg) 15 30 * * *

PBYR25**CTF SOT-186 (3 leg) 15 30 * * *

PBYR30**PTF SOT-199 15 30 * * *

Single Diodes (Electrically Isolated Package)Type Number Outline IF(AV) (A) IO (A) Voltage Grades (V)


PBYR7**F SOT-186 (2 leg) 7.5 7.5 * * *

PBYR10**F SOT-186 (2 leg) 10 10 * * *

PBYR16**F SOT-186 (2 leg) 16 16 * * *

176


Table 2 ’PBYR’ Types - explanation of the numbering system.

The numerical part of the type number gives information about the current and voltage rating of the devices. The finaltwo digits are the voltage grade. The number(s) preceding these give an indication of the current rating. This figure mustbe used with care. Single and dual devices derive this number in different ways so the data sheet should be consultedbefore final selection is made.Letters after the type number indicate that the device is NOT a single diode package. The codes used by Philips canbe interpreted as follows:-CT - means that the device is dual and the cathodes of the two diodes are connected together.PT - means the device is a dual with common cathode but for compatibility reasons ’CT’ cannot be used.For examplePBYR1645 a device consisting of a single diode with an average current rating (IF(AV)) of 16 A and a reverse voltage

capability of 45 V.

Table 3 Cross Reference Guide

Single DiodesOld Type Intermediate Type New Type

BYV19-** none PBYR7**

none none PBYR10**

BYV39-** none PBYR16**

BYV20-** BYV120-** none


BYV22-** withdrawn none

BYV23-** withdrawn none

Dual Diodes - Common CathodeOld Type Intermediate Type New Type

none none PBYR6**CT


BYV33-** BYV133-** PBYR15**CT

none none PBYR20**CT

BYV43-** BYV143-** PBYR25**CT

BYV73-** none PBYR30**PT

FULL PACK Dual Diodes - Common CathodeOld Type Intermediate Type New Type

none BYV118F-** none

BYV33F-** BYV133F-** PBYR15**CTF

none none PBYR20**CTF

BYV43F-** BYV143F-** PBYR25**CTF

177


2.2.3 An Introduction to Synchronous Rectifier Circuits usingPowerMOS Transistors

Replacing diodes with very low RDS(on) POWERMOStransistors as the output rectifiers in Switch Mode PowerSupplies operating at high operating frequencies can leadto significant increases in overall efficiency. However, thisis at the expense of the extra circuitry required for transistordrive and protection. In applications where efficiency is ofoverriding importance (such as high current outputs below5V) then synchronous rectification becomes viable.

This paper investigates two methods of drivingsynchronous rectifiers:-

(i) Using extra transformer windings.

(ii) Self-driven without extra windings.

Multi-output power supplies do not easily lend themselvesto extra transformer windings (although there is usually onlyone very low output voltage required in each supply).Therefore, the self-driven approach is of more interest. Ifthe additional circuitry and power devices were integrated,an easy to use, highly efficient rectifier could result.

Introduction.The voltage drop across the output diode rectifiers duringforward conduction in an SMPS absorbs a high percentageof the watts lost in the power supply. This is a major problemfor low output voltage applications below 5V (See section2.2.1). The conduction loss of this component can bereduced and hence, overall supply efficiency increased byusing very low RDS(on) POWERMOS transistors assynchronous rectifiers (for example, the BUK456-60A).

The cost penalties involved with the additional circuitryrequired are usually only justified in the area of highfrequency, low volume supplies with very low outputvoltages. The methods used to provide these drivewaveforms have been investigated for various circuitconfigurations, in order to assess the suitability of thePOWERMOS as a rectifier.

The main part of the paper describes these circuitconfigurations which include flyback, forward and push-pulltopologies. To control the synchronous rectifiers they eitheruse extra windings taken from the power transformer orself-driven techniques.

The PowerMOS as a synchronous rectifier.POWERMOS transistors have become more suitable forlow voltage synchronisation for the following reasons:-

(1) The cost of the POWERMOS transistor has fallensharply in recent years.

(2) Very low RDS(on) versions which yield very low conductionlosses have been developed.

(3) The excellent POWERMOS switching characteristicsand low gate drive requirements make them ideal for highfrequency applications.

(4) Parallelling the POWERMOS devices (which is normallystraightforward) will significantly reduce the RDS(on), thusproviding further increases in efficiency. This process is notpossible with rectifier diodes since they have inherentforward voltage offset levels.

Fig. 1 POWERMOS transistor showing body diode.

Design constraints.

When the POWERMOS transistor shown in Fig. 1 is usedas a synchronous rectifier, the device is configured suchthat the current flow is opposite to that for normal operationi.e. from source to drain. This is to ensure reverse voltageblocking capability when the transistor is turned off, sincethere will be no current path through the parasitic bodydiode. This orientation also gives a degree of safety. If thegate drive is lost, the body diode will then perform therectification, albeit at a much reduced efficiency.

Unfortunately, this configuration has limitations in the wayin which it can be driven. The device gate voltage mustalways be kept below ± 30V. The on-resistance (RDS(on)) ofthe device must be low enough to ensure that the on-statevoltagedrop is always lower than the Vf of the POWERMOSintrinsic body diode. The gate drive waveforms have to bederived from the circuit in such a way as to ensure that thebody diode remains off over the full switching period. Forsome configurations this will be costly since it can involvediscrete driver I.C.s and isolation techniques.

G

S

D

Intrinsicbodydiode

179


If the body diode were to turn on at any point, it would resultin a significant increase in the POWERMOS conductionloss. It would also introduce the reverse recoverycharacteristic of the body diode, which could seriouslydegrade switching performance and limit the maximumallowable frequency of operation.

It is well known that the RDS(on) of the POWERMOS istemperature dependent and will rise as the device junctiontemperature increases during operation. This means thatthe transistor conduction loss will also increase, hence,lowering the rectification efficiency. Therefore, to achieveoptimum efficiency with the synchronous rectifier it isimportant that careful design considerations are taken (forexample good heat-sinking) to ensure that the devices willoperate at as low a junction temperature as possible.

Fig. 2 Conventional output rectifier circuits.

Transformer Driven SynchronousRectifiers.

The conventional output rectifier circuits for the flyback,forward and push-pull converters are shown in Fig. 2.These diodes can be replaced by POWERMOS transistorswhich are driven off the transformer as shown in Fig. 3.These configurations can be summarised as follows:-

(a) Flyback converter - this is very straightforward; the gatevoltage can be maintained at below 30V and the body diodewill not come on.

(b) Forward converter - the gate drives for the twotransistors can be maintained below 30V. However, due tothe shape of the transformer waveforms, the freewheelrectifier will not have a square wave signal and the bodydiode could come on.

(c) Push-pull converter - deriving the gate drives for the twosynchronous rectifiers from the transformer means thatduring the dead time which occurs in each switching cycle,both transistors are off. There is nowhere for the circulatingcurrent to go and body diodes will come on to conduct thiscurrent. This is not permissible because of the slowcharacteristics of the less than ideal body diode. Therefore,the push-pull configuration cannot be used for synchronousrectification without the costly derivation of complex drivewaveforms.

Fig. 3 Synchronous rectifier circuits with windings.

One significant advantage of using this topology is that ther.m.s. currentof the rectifiers and, hence,overall conductionloss is significantly lower in the push-pull than it is in theforward or flyback versions.

180


Self-Driven Synchronous Rectifiers.The disadvantage of the transformer driven POWERMOSis the requirement for extra windings and extra pins on thepower transformer. This may cause problems, especiallyfor multi-output supplies. A method of driving the transistorswithout the extra transformer windings would probably bemore practical. For this reason basic self-drivensynchronous rectifier circuits were investigated.

It should be noted that the following circuits were basedupon an output of 5V at 10A. In practice, applicationsrequiring lower voltages such as 3 or 3.3 volts at outputcurrents above 20A will benefit to a far greater extent byusing synchronous rectification. For these conditions theefficiency gains will be far more significant. However, the5V output was considered useful as a starting point for anintroductory investigation.

(a) The Flyback converter.An experimental circuit featuring the flyback converterself-oscillating power supply was developed. This wasdesigned to operate at a switching frequency of 40kHz anddelivered 50W (5V at 10A).

Directly substituting the single rectifier diode with thePOWERMOS transistor as is shown in Fig. 4(a) does notwork because the gate will always be held on. The gate isVo above the source so the device will not switch.

Therefore, some additional circuitry is required to performthe switching, and the circuitry used is shown in Fig. 4(b).The BUK456-60A POWERMOS transistor which featuresa typical RDS(on) of 24mΩ (at 25˚C) was used as thesynchronous rectifier for these basic configurations.

The drive circuit operates as follows: the pnp transistorswitches on the POWERMOS and the npn switches it off.Good control of the POWERMOS transistor is possible andthe body diode does not come on. The waveforms obtainedare also shown in Fig. 4.

If the small bipolar transistors were replaced by smallPOWERMOS devices, then this drive circuit would be agood candidate for miniaturisation in a Power IntegratedCircuit.This couldprovide good control with low drive powerrequirements.

Unfortunately, the single rectifier in a flybackconverter mustconduct a much higher r.m.s. current than the two outputdiodes of the buck derived versions (for the same outputpower levels). Since the conduction loss in a POWERMOSis given by ID(RMS)

2.RDS(on), it is clear that the flyback, althoughsimple, does not lend itself as well to achieving largeincreases in efficiency when compared to other topologiesthat utilise POWERMOS synchronous rectifiers.

Fig. 4 Flyback self-driven synchronous rectifier circuits.

(b) The Forward converter.An experimental self-driven circuit based on the forwardconverter was then investigated. In this version thefrequency ofoperation was raised to300kHz with the supplyagain delivering 5V at 10A.

The direct replacement of the output diodes withPOWERMOS transistors is shown in Fig. 5. In thisarrangement, the gate sees the full voltage across thetransformer winding. Therefore, the supply input voltagerange must be restricted to ensure the gate of thePOWERMOS is not driven by excessively high voltages.This would occur during low primary transistor duty cycle

181


conditions. The waveforms obtained for the forwardsynchronous rectifier in this configuration are also shownin Fig. 5.

(Forward rectifier) Timebase: 1µs/divTop trace: VGS - 20V/div

Middle: VDS - 20V/divBottom: ID - 10A/div

Fig. 5 Forward converter with synchronous rectification - direct replacement with POWERMOS.

In this case the method of control is such that the gate isreferenced to the source via the drain-source body diode.This clamps the gate, enabling it to rise to a voltage whichwill turn the POWERMOS on. If the body diode was notpresent, the gate would always remain negative withrespect to the source and an additional diode would haveto be added to provide the same function.

Additional circuitry is required to turn off the freewheelsynchronous rectifier. This is due to the fact that when thefreewheel POWERMOS conducts, the body diode will takethe current first before the gate drive turns the device on.An additional transistor can be used to turn off thePOWERMOS in order to keep conduction out of the bodydiode. This additional transistor will short the gate to groundand ensures the proper turn-off of the POWERMOS. Thecircuit with this additional circuitry and the resultingfreewheel rectifier waveforms are given in Fig. 6.

(Freewheel rectifier) Timebase: 1µs/divTop waveform: VGS - 20V/div


Fig. 6 Forward converter with synchronous rectification- additional circuitry to turn-off body diode.

A very simple circuit configuration can be used in whichbody diode conduction in the freewheel synchronousrectifier does not occur. By driving the freewheel rectifierfromthe output choke via a closely coupled winding, a muchfaster turn-on can be achieved because the body diodedoes not come on. This circuit configuration and associatedwaveforms are shown in Fig. 7.

To avoid gate over-voltage problems a toroid can beenadded which will provide the safe drive levels. This toroideffectively simulates extra transformer windings withoutcomplicating the main power transformer design. Thelimitations of this approach are that there will be extraleakage inductance and that an additional woundcomponent is required. The applicable circuit andwaveforms for this arrangement are given in Fig. 8.

ConclusionsThe main advantage of POWERMOS synchronousrectifiers over existing epitaxial and Schottky dioderectifiers is the increase in efficiency. This is especially truefor applications below 5V, since the development of verylow RDS(on) POWERMOS transistors allows very significant

182


efficiency increases. It is also very easy to parallel thePOWERMOS transistors in order to achieve even greaterefficiency levels.

The difficulties involved with generating suitable drives forthe POWERMOS synchronous rectifiers tend to restrict thenumber of circuits for which they are suitable. It will alsosignificantly increase the cost of the supply compared withstandard rectifier technology.

The circuit examples outlined in this paper were very basic.However, they did show what can be achieved. The flybackconfiguration was the simplest, and there were variouspossibilities for the forward converters.



Fig. 7 Forward converter with synchronous rectification- avoiding body diode conduction.

Recent work has shown that there are topologies moresuited to using MOSFET synchronous rectifiers (featuringlow rectifier r.m.s. current levels) such as the push-pull.These can achieve overall power supply efficiency levelsof up to 90% for outputs of 5V and below. However, thediscrete control circuitry required is quite complex andrequires optical/magnetic isolation, since the waveformsmust be derived from the primary-side control.

The true advantage of synchronous rectifiers may only bereached when the drive circuit and POWERMOS devicesare hybridised into Power Integrated Circuits. However, inapplications where the efficiency performance is of moreimportance than the additional costs incurred, thenPOWERMOS synchronous rectification is presently themost suitable technique to use.



Fig. 8 Forward converter with synchronous rectifiers -method of protecting the gate inputs.

183


Design Examples

185


2.3.1 Mains Input 100 W Forward Converter SMPS: MOSFETand Bipolar Transistor Solutions featuring ETD Cores

The following two switched-mode powersupplies describedare low cost easy to assemble units, intended primarily forthe large number of equipment manufacturers who wish tobuild power supplies in-house.

The designs are based upon recent technologies and bothfeature ETD (Economic Transformer Design) ferrite cores.The first design features a high voltage Bipolar transistor,the BUT11 at a switching frequency of 50kHz. The seconddesign is based around a power MOSFET transistor, theBUK456-800A whose superior switching characteristicsallow higher switching frequencies to be implemented. Inthis case 100kHz was selected for the MOSFET versionallowing the use of smaller and cheaper magneticcomponents compared with the lower frequency version.

Both supplies operate from either 110/120 or 220/240 Vmains input, and supply 100W of regulated output powerup to 20A at 5V, with low power auxiliary outputs at ±12V.The PowerMOS solution provides an increase in efficiencyof 5% compared with the Bipolar version, and both havebeen designed to meet stringent R.F.I. specifications.

ETD ferrite cores have round centre poles and constantcross-sectional area, making them ideally suited for thewindings required in high-frequency S.M.P.S. converters.The cores are available with clips for rapid assembly, andthe coil formers are suitable for direct mounting onto printedcircuit boards.

The ETD cores, power transistors and power rectifiersfeatured are part of a comprehensive range of up-to-datecomponentsavailable from Philips fromwhich cost effectiveand efficient S.M.P.S. designs can be produced.

50kHz Bipolar version

Circuit descriptionThe circuit design which utilises the Bipolar transistor isshown in Fig. 1. This is based upon the forward convertertopology, which has the advantage that only one powerswitching transistor is required.

An operating frequency of 50kHz was implemented usingaBUT11transistor (available in TO-220 packageor isolatedSOT-186 version). This was achieved by optimising theswitching performance of the BUT11 Bipolar powertransistor TR5, by careful design of the base drive circuitryand by the use of a Baker clamp. The 50kHz operating

frequency allows the size and the cost of the transformerandchoke tobe reducedcompared with older Bipolar basedsystems which worked around 20kHz.

The base drive waveform generated by IC1 is bufferedthrough TR3 and TR4 to the switching transistor TR5.Although operating from a single auxiliary supply line, thedrive circuit provides optimum waveforms. At turn-off,inductor L3 controls the rate of change of reverse biascurrent (-dIB/dt). The reverse base-emitter voltage isprovided by capacitor C16 (charged during the on-time).The resulting collector current and voltage waveforms areprofiled by a snubber network to ensure that the transistorSOA limits are not exceeded.

Voltage regulation of the 5V output is effected by means ofan error signal which is fed back, via the CNX82Aopto-coulper, to IC1 which adjusts the transistor duty cycle.Over-current protection of this output is provided bymonitoring the voltage developed across the 1Ω resistor,R28 and comparing this with an internal reference in IC1.Voltage regulation and overcurrent protection for the 12Voutputs are provided by the linear regulating integratedcircuits IC4 and IC5.

Specification and performance(Bipolar version)Input

220/240 V a.c. nominal (range 187 to 264 V a.c.)110/120 V a.c. nominal (range 94 to 132 V a.c.)

Output

Total output power = 100 W.

Fig. 2 Output voltage versus input voltage - (Iout = 20A).

187


Fig. 1 100W SMPS circuit diagram (50kHz Bipolar transistor version).

188


Main output

5V at 20A max output power - Adjustment range ±5%.

Line regulation

The change in output voltage over the full input voltagerange of 187 to 264 V is typically 0.2%; see Fig. 2.

Load regulation

The change in output voltage over the full load range ofzero to 100 W is typically 0.4%; see Fig. 3.

Fig. 3 Output voltage as a function of output current(input voltage = 220Vac).

Auxiliary outputs

±12V at 0.1A.Regulation (worst-case condition of max change in inputvoltage and output load) < 0.4%.

Ripple and Noise

0.2% r.m.s. 1.0% pk-pk (d.c. to 100MHz).

Fig. 4 Output hold-up during mains drop-out at input.

Output hold-up

Both the main and auxiliary outputs will remain withinspecification for a missing half-cycle (18ms) at full load andminimum input voltage; see Fig. 4.

Isolation

Input to output ground 2kV r.m.s.Output to ground 500V r.m.s.

Efficiency

The ratio of the d.c output power to the a.c input power istypically 71% at full load; See Fig. 5.

Fig. 5 Efficiency as a function of output current.

Radio frequency interference

R.F.I. fed back to the mains meets VDE0875N and BS800.

Transient response

The response to a 50% change in load is less than 200mVand the output returns to the regulation band within 400µs:See Fig. 6.

Fig. 6 Response to 50% change in load with nominal220Vmains input.

Vertical scale: 200nV/divHorizontal scale: 1ms/div

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Optimum drive of high voltage Bipolartransistor (H.V.T.)A feature of the high voltage Bipolar transistor is the verylow conduction loss that can be obtained. This is madepossible by the "conductivity modulation" process thattakes place due to the influence of minority carriers in thecollector region of the device. However, the presence ofthese carriers means that a stored charge will exist withinthe collector region (especially in high voltage types) whichhas the effect of producing relatively slow switching speeds.This leads to significant switching losses, limiting themaximum frequency of operation to around 50kHz.

To effectively utilise the power switching H.V.T. the basedrive must be optimised to produce the lowest switchinglosses possible. This is achieved by accurate control of theinjection and more importantly the removal of the storedcharge during the switching periods. This is fulfilled bycontrolling the transistor base drive current. (The Bipolartransistor is a current-controlled device). The simple stepstaken to achieve this are summarised as follows:-

(1) A fast turn-on "kick-up" pulse in the base current shouldbe provided to minimise the turn-on time and associatedswitching loss.

(2) Provide the correct level of forward base current duringconduction, based upon the high current gain of thetransistor. This ensures the device is neither over-driven(which will cause a long turn-off current tail ) norunder-driven (coming out of saturation causing higherconduction loss). The Baker clamp arrangement used (seeFig. 1) prevents transistor over-drive (hard saturation).

(3) The correct level of negative base drive current must beproduced to remove the stored charge from the transistorat turn-off. The majority of this charge is removed duringthe transistor storage time ts. This cannot be swept out tooquickly, otherwise a "crowding effect" will taken placecausing a turn-off current tail with very high switching loss.This accurate control of the charge is provided by a seriesinductorplaced in the path of the negative base drive circuit.(For further information see sections 1.3.2. and 2.1.3).

BUT11 waveforms

These techniques have been applied in the BUT11 drivecircuit shown in Fig. 1, and the resulting base drivewaveforms are given in Fig. 7.

Optimised base drive minimises both turn-on and turn-offswitching loss, limiting the power dissipation in both thetransistor and snubber resistor allowing acceptable

operation at 50kHz. This is outlined in Fig. 8 which givesthe BUT11 collector current (IC) and collector-emittervoltage (VCE) waveforms.

The transistor VCE(sat) would normally be as low as 0.3V.However, the use of the Baker clamp limits it to about 1V.Even so this still yields a transistor conduction loss of only0.76W for the full output load condition.

Fig. 7 Base voltage VB and base current IB of BUT11with nominal 220V input and full 5V, 20A output.

Upper trace VB: 5V/divLower trace IB: 0.2A/divHorizontal scale: 5µs/div

Fig. 8 Collector-emitter voltage VCE

and collector current IC for the BUT11with nominal 220V mains input and full 5V, 20A output.

Upper trace VCE: 200V/divLower trace IC: 1A/div

Horizontal scale: 5µs/div

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50kHz Magnetics designOutput Transformer

For 50kHz operation the transformer was designed usingan ETD39 core. The winding details are given in Fig. 9 andlisted as follows:-

Winding

1. 1/2 demag 42 turns 0.315mm dia. enamelledcopper wire (e.c.w.) (single layer).

2, 3 1/2 primary 42 turns 0.315mm e.c.w.(2 layers inparallel).

4, 5 r.f.i. screens each 1 turn 0.05 x 16.5mm copperstrip.

6. 5V sec 6 turns 0.2 x 16.5mm copper strip.

7. ±12V sec 18 turns 0.355mm e.c.w. bifilarwound (1 wire each output).

8, 9 r.f.i. screens each 1 turn 0.05 x 16.55mm copperstrip.

10, 1/2 prim 42 turns 0.315mm e.c.w. (2 layers in11 parallel).

12. 1/2 demag 42 turns 0.315 e.c.w (single layer).

13. primary drive 7 turns 0.2mm e.c.w.

- interleaving 0.04mm film insulation.

Airgap 0.1mm total in centre pole.

Fig. 9 50kHz Output transformer winding details. The 5V secondary and r.f.i. screens are connected together byflying leads. Pin numbering is consistent with the ETD39 coil former.

(The insulation has been added to meet isolation and safety requirements for a mains input SMPS.)

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Fig. 10 50kHz output choke L1, winding details.Inductance of 5V winding = 43µH.

Coupled Inductor technique.

50kHz output chokes

All of the output chokes have been wound on a single core;i.e. using the coupled inductor approach. This reducesoverall volume of the supply and provides better dynamiccross-regulation between the outputs. The design of thischoke, L1, is based upon 43µH for the main 5V output,using an ETD44 core which was suitable for 100W, 50kHzoperation.

The winding details are shown in Fig. 10 and are specifiedas follows :-

Windings

1. 19 turns 0.25 x 25mm copper strip.

2. 57 turns 0.4mm e.c.w. bifilar wound.

Airgap 2.5mm total in centre pole.

Note. Choke L3 was wound with 1 turn 0.4mm e.c.w.

100kHz MOSFET versionThe circuit version of the 100W forward converter basedaround the high voltage power MOSFET is shown inFig. 11. The operating frequency in this case has beendoubled to 100kHz.

Feedback is again via opto-coupler IC1, the CNX83A whichcontrols the output by changing the duty cycle of the drivewaveform to the power MOSFET transistor, TR3 which isthe BUK456-800A (available in TO-220 package or the fullyisolated SOT-186 version). The transistor is driven by IC4via R16 and operates within its SOA without a snubber: seethe waveforms of Fig. 15. There is low auxiliary supplyvoltage protection and primary cycle by cycle currentlimiting which inhibit output drive pulses and protect thesupply.

The power supply control and transistor drive circuitry(enclosed within the broken lines in Fig. 11) have lowcurrent requirements (5mA). This allows dropper resistorsR2 and R3 to provide the supply for these circuits directlyfrom the d.c. link thereby removing the supply windingrequirement from the transformer.

Specification and performance(MOSFET version)The specification and performance of the 100kHz MOSFETversion is the same as the earlier 50kHz Bipolar versionwith the exception of the following parameters:-

Output ripple and noise

< 10 mV r.m.s.< 40mV pk-pk (100MHz bandwidth) See Fig. 12.

Fig. 12 Output voltage and noise at full load for 100kHzversion.

Vertical scale: 50mV/div.Horizontal scale: 2µs/div.

Transient response

The transient response has been improved to a 100mV linedeviation returning to normal regulation limits within 100µsfor a 10A change in load current.

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Radio frequency interference

The 100kHz version meets BS800 and CISPRArecommendations; see Fig. 13.

Fig. 13 Measured r.f.i. at supply terminals.

Efficiency

The overall efficiency has been improved by up to 5%compared to the Bipolar version, achieving 76% at fulloutput load. This is mainly due to the more efficientswitching characteristics of the MOSFET allowing theremoval of the lossy snubber, reduced transistor drivepower requirements and lower control circuit powerrequirements. Fig. 14 shows the overall efficiency of thepower supply against load current.

Fig. 14 Efficiency vs load current (VIN = 220V a.c.).

It should be noted that for the high current and low voltage(5V) main output, a large portion of the efficiency loss willbe due solely to the output rectifiers’ forward voltage dropVF. Therefore, these two output rectifiers are required to below loss, very low VF power Schottky diodes in order to keepoverall converter efficiency as high as possible. In this casethe Dual PBYR2535CT device was selected for the 5Voutput. This is available in the TO-220 package and will

comfortably rectify an average output current well abovethe 20A required, providing a suitably sized heat-sink isadded.

Mains isolation

The mains isolation conforms to IEC435.

The power MOSFET as a high frequencyswitchPower MOSFET transistors are well known for their easeof drive and very fast switching characteristics. Since theseare majority carrier devices, they are free from the chargestorage effects which lessen the switching performance ofthe Bipolar products. Driving the MOSFET is far simplerand requires much less drive power than the equivalentBipolar version.

The speed at which a MOSFET can be switched isdetermined by the rate at which its internal capacitancescan be charged and discharged by the drive circuit. Inpractice these capacitances are very small (e.g the inputcapacitanceCiss for the BUK456-800A isquoted as 1000pF)allowing MOSFET rise and fall times in the tens ofnano-seconds region. The MOSFET can conduct fullcurrent when the gate-source voltage VGS, is typically 4V to6V. However, further increases in VGS are usually employedto reduce the device on-resistance and 8V to 10V isnormally the final level applied to ensure a lower conductionloss.

With such fast switching times, the associated switchinglosses will be very low, giving the MOSFET the ability tooperate as an extremely high frequency switch. Powerswitching in the MHz region can be obtained by using aMOSFET.

One major disadvantage of the MOSFET is that it has arelatively high conduction loss in comparison with bipolartypes. This is due to the absence of the minority carriersmeaning no "conductivity modulation" takes place.

MOSFET on-resistance

The conduction loss is normally calculated by using theMOSFET "on-resistance", RDS(on), expressed in Ohms. Thevoltage developed across the device during conduction isan Ohmic drop and will rise as the drain current increases.Therefore, the conduction loss is strongly dependent uponthe operating current. Furthermore, the value of theMOSFET RDS(on) is strongly dependent upon temperature,and increases as the junction temperature of the devicerises during operation. Clearly, the MOSFET does notcompare well to the Bipolar which has a stable lowsaturation voltagedrop VCE(sat), and is relatively independentof operating current or temperature.

It should be noted that the RDS(on) of the MOSFET alsoincreases as the breakdown voltage capability of the deviceis increased.

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How fast should the MOSFET be switched?

Although very fast switching times are achievable with thepower MOSFET, it is not always suitable or necessary touse the highest frequency possible. A major limiting factorinS.M.P.S.design is the magnetics. Presenthigh frequencycore loss for high grade ferrite core materials such as 3C85limits the maximum operating frequency to about 200kHz,although new types such as 3F3 are now suitable for useat 500kHz.

There has always been a drive to use ever higher operatingfrequencies with the aim of reducing magnetics and filtercomponent sizes. However, most S.M.P.S. designs stilloperate below 300kHz, since these frequencies are quiteadequate for most applications. There is no reason to goto higher frequencies unneccessarily, since very highfrequency design is fraught with extra technical difficulties.

Furthermore, although the very fast MOSFET switchingtimes reduce switching loss, the increased dI/dt and dV/dtrates will generate far worse oscillations in the circuitparasitics requiring lossy snubbers. The R.F.I. levelsgenerated will also be far more severe, requiring additionalfiltering to bring the supply within specification. The goldenrule in S.M.P.S. square wave switching design is to use thelowest operating frequency and switching times that theapplication will tolerate.

Estimating required switching times

In the 100kHz example presented here, the typicalconduction time of the transistor will be approximately 3µs.A rule of thumb is to keep the sum of the turn-on and turn-offtimes below 10% of the conduction time. This ensures awide duty cycle control range with acceptable levels ofswitching loss. Hence, the target here was to produceswitching times of the order of 100ns to 150ns.

Gate drive requirements

The capacitances of the power MOSFET are related to theoverall chip size with the gate-source capacitance typicallyin the range 1nF to 2nF. However, these capacitances arevery voltage dependent and are not suitable for estimatingthe amount of drive current required to obtain the desiredswitching times. A more accurate method is to use theinformation contained in the turn-on gate charge (QG)characteristic given in the data-sheets. The graph of QG forthe BUK456-800A for a maximum d.c. rated drain currentof 4A is shown in Fig. 15.

Theshape of this characteristic needs explaining. The initialslope shows the rise of VGS to the device 4A thresholdvoltage Vth. This requires very little charge, and at the toppoint of this slope the MOSFET can then conduct fullcurrent. However, further gate charge is required while VDS

falls from its off-state high voltage to its low on-state level.This is the flat part of the characteristic and at the end ofthis region the MOSFET is fully switched on. (This is shown

for a range of initial off state voltages). The second slopecharacterises any further increase in QG and VGS that maybe employed to minimise the device on-resistance.

Note. Since the turn-off mechanism involving the removalof gate charge is almost identical to the turn-on mechanism,the required turn-off gate chargecan also be estimated fromthe turn-on gate charge plot.

Fig. 15 Typical turn-on gate charge versus VGS forBUK456-800A

Conditions: ID = 4A; plotted for a range of VDS.

In this topology the typical d.c. link voltage is 280V, hencethe MOSFET VDS prior to turn-on will be 280V, doubling to560V at turn-off. From Fig. 14, for these two VDS levels itcan be estimated that the BUK456-800A will require 23nCto fully turn on and 27nC to turn off. It should be noted thatthis estimation of gate charge is for the 4A condition. In thispresent application the peak current is under 2A and inpractice the actual QG required will be slightly less.

To a first approximation the gate current required can beestimated as follows:-

where tsw is the applicable switching time. If an initial valueof the turn-on and turn-off time is taken to be 125ns thenthe required gate current is given by:-

In the majority of MOSFET drive circuits the peak currentsand resulting switching times are controlled by using aseries gate resistor RG. An initial estimation of the value ofthis resistor can be found as follows:-

0 20 40QG / nC

VGS / V12

10

8

6

4

2

0

VDS / V =160

640

BUK4y6-800

QG = IG tsw

IG(on) =23nC125ns

= 0.184A; IG(off) =27nC125ns

= 0.216A

RG =Vdrive − Vth

IG(ave)

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where IG(ave) is the average value of the turn-on and turn-offpeak gate current. In this example the gate driver I.C.4.consists of 5 parallel T.T.L. gates in order to provide highenough current sink and source capability. The driversupply voltage was approximately 10V, the MOSFETthreshold voltage was 5V and the average peak gatecurrent was 0.2A.

This gives a value for RG of 25Ω. A value of 22Ω wasselected, and the resulting gate drive waveforms for TR3under these conditions at the full 100W output power aregiven in Fig. 16.

Fig. 16 PowerMOS TR3 gate drive waveforms.Upper VGS=5V/div; Lower IG=0.2A/div

Horizontal 2µs/div.

This shows a peak IG of 0.17A at turn-on and 0.28A atturn-off. The magnitudes of the turn-on and turn-off peakgate currents in operation are slightly different to thecalculated values. This is due to the effect of the internalimpedanceof the driver, where the impedance while sinkingcurrent is much lower than while sourcing, hence thediscrepancy.

These drive conditions correspond to a turn-on time of143ns and turn-off time of 97ns, which are reasonably closeto the initial target values.

In this application, and for the majority of simple gate drivearrangements which contain a series gate resistor (seesection 1.1.3) the total power dissipation of the gate drivecircuit can be expressed by:-

where QG is the peak gate charge and VGS is the operatinggate-source voltage. From Fig. 15, taking QG to be 43nCfor a VGS of 10V gives a maximum gate drive powerdissipation of only 43mW, which is very small and can beneglected.

MOSFET losses

Switching losses

The waveforms for the drain current and drain-sourcevoltage at full output load for the drive conditions specifiedare given in Fig. 17. In this case no transistor snubbing wasrequired.

Fig. 17 PowerMOS drain-source voltage and draincurrent at full load.

Upper VDS=200V/div; Lower ID=1A/divHorizontal scale 2µs/div

The waveforms of ID and VDS were found to cross atapproximately half their maximum values for both turn onand turn-off. The switching loss can therefore beapproximated to two triangular cross-conduction pulsesshown in Fig. 18.

Fig. 18 Graphical approximation of MOSFET switchingloss.

Hence, the total switching loss can be expressed by thefollowing simplified equation:-

Inserting the correct values for this example gives:-

Id

Vds

turn-on energy loss turn-off energy lossper cycle

Vlink x Ion x ton2 x 2 x 2

2Vlink x Ioff x toff

2 x 2 x 2

(Vlink)

(2Vlink)

Ion

Ioff

per cycle

ton toff

Power = Energy x freq

PG = QG.VGS.f

Psw =18

f (IDon Vlink ton + IDoff 2Vlink toff)

Psw = 0.125× 100k(1.3× 280× 147n+ 1.95× 560× 97n)

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The MOSFET switching loss in this application is a veryrespectable 1.73W. It should be noted that a directcomparison with the switching loss of the earlier Bipolarversion is not practical. It was necessary to use a snubberwith the Bipolar in order to remove a large amount of theexcessive switching loss generated by the device.Furthermore, the MOSFET switching frequencyimplemented was double that of the Bipolar version.

If a direct comparison were to be made under the samecircuit conditions, the Bipolar switching loss would alwaysbe far in excess of the low values achievable with theMOSFET.

Conduction loss

The conduction loss for a power MOSFET is calculated byestimating (ID(rms))

2RDS(on). The drain current at full outputload is as shown in Fig. 17 and the r.m.s. value of thetrapezoidal current waveforms found in the forwardconverter is given by:-

At full load, these values can be seen to be Imin=1.25A;Imax=1.95A; D= 0.346. Substituting these values into theabove equation gives an ID(rms) = 0.95A.

The typical RDS(on) value for the BUK456-800A is quoted as2.7Ω. However, this is for a junction temperature of 25˚C.The value at higher operating junction temperatures can becalculated from the normalisation curve given in thedata-sheets. If a more realistic operating temperature of100˚C is assumed, the weighting factor is 1.75. Hence, thecorrect RDS(on) to use is 4.725Ω. Therefore, the conductionloss is given by:-

The conduction loss of 4.26W is over double the switchingloss. However, this is typical for a high voltage MOSFEToperated around this frequency. The MOSFET conductionloss is much higher than was previously obtained using theBipolar transistor at 50kHz, as expected.

The total loss for the MOSFET device thus comes to 6Wi.e. 6% of the total output power.

It should be remembered that this figure has beencalculated for the full output load condition which will be atransient worst case condition. A more realistic typicaldissipation of approximately 4W has been estimated for thehalf load condition, where the conduction loss isapproximately halved. This 4W figure should be used when

estimating the heatsink requirement. In this case a relativelysmall heatsink with a thermal co-efficient of around 10˚C/Wwould be adequate.

For more information on MOSFET switching refer tochapters 1.2.2. and 1.2.3. of this handbook.

100kHz magnetics designOutput transformer

Doubling the switching frequency to 100kHz has allowedthe use of the smaller sized ETD34 core for the transformer.This transformer has been designed with a 0.1mm centrepole air gap. The winding details are shown in Fig. 19 andlisted as follows:-

Winding

2 to 1 Reglnsupply

5 to 4 +12V sec 3 x 12 turns 0.4mm e.c.w. in 1 layer.

6 to 7 -12V sec 3 x 12 turns 0.4mm e.c.w. in 1 layer.

8 r.f.i. 1 turn 0.1 x 13mm copper strip.screen

10 to 1/2 prim 28 turns 0.355mm e.c.w. bifilar in two12 layers.

11 to 1/2 28 turns 0.355mm e.c.w. in 1 layer.13 demagn

12 to 1/2 prim 28 turns 0.355mm e.c.w. bifilar in 214 layers.

13 to 8 1/2 28 turns 0.355mm e.c.w. in 1 layer.demagn

Interleaving:- 1turn 0.04mm insulation between each layerexcept 3 turns between r.f.i. screens.

Output choke

Again the implementation of the higher frequency hasallowed the use of the smaller sized ETD39 core for thecoupled output inductor. A centre pole air-gap of 2mm wasutilised. The winding details are shown in Fig. 20 and arelisted as follows:-

Winding

Copper strip +5V 15 turns 0.3 x 21mm copper strip.

2 to 15 -12V 45 turns 0.4mm e.c.w. in 1 layer.

1 to 16 +12V 45 turns 0.4mm e.c.w. in 1 layer.

Interleave:- 1 layer 0.04mm insulation between each stripand winding.

= 0.67W+ 1.06W= 1.73W

Irms =√D

Imin2 + Imin Imax+ Imax

2

3

D =tON

T

Pcond = (0.95)2 4.723 = 4.26W

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Fig. 19 100kHz transformer construction. Fig. 20 100kHz inductor construction.

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2.3.2 Flexible, Low Cost, Self-Oscillating Power Supply usingan ETD34 Two-Part Coil Former and 3C85 Ferrite

This sectiondescribes a low-cost, flexible, full performance,Self Oscillating Power Supply (SOPS) using the flybackprinciple.

The circuit is based around an ETD34 transformer using atwo-part coil former and3C85 ferrite material. The feedbackregulation is controlled from the secondary side by meansof a small U10 transformer.

The circuit is described and the details of the magneticdesign using the two-part coil former is given. Theadvantages of the two-part coil former are highlightedtogether with 3C85 material properties. Power supplyperformance of a 50W SMPS design example is given.

Introduction.A recently developed low-cost full-performanceswitched-mode power supply design is presented,highlighting a new transformer concept using a novelETD34 two-part coil former and 3C85 low-loss material.The SMPS is of the Self Oscillating Power Supply (SOPS)type and uses the flyback principle for minimum componentcount and ultra-low cost/watt.

Compliance with safety and isolation specifications hasalways been a headache for magnetics designers. Now,the introduction of the ETD34 two-part coil former solvesthe problem of the 4+4mm creepage and clearancedistances by increasing the available winding area andconsequently decreasing copper losses. It also offers theadvantage of a more flexible approach with the possibilityof using a standard ’plug-in’ primary and a customisedsecondary to meet any set of output requirements.

3C85 is a recently developed material superseding 3C8and offers lower core loss, better quality control and higherfrequency operation at no extra cost.

These products are illustrated in the following 50W SMPSdesign example, which is suitable for microcomputerapplications.

SOPSThe principle of the Self-Oscillating Power Supply is shownin Fig. 1 and is based on the flyback converter principle.Stabilisation of the output voltage against mains and loadvariation is achieved by varying the duty cycle of thepowerMOS switching transistor. The on-time varies mainlywith input voltage, whereas the off-time varies only with theload. This means that both the duty cycle and the frequencyvary due to the control circuit. The switching frequency is

therefore at a maximum for maximum input voltage andminimum load. Regulation is achieved by varying the pointat which the POWERMOS transistor is switched off. A.C.magnetic coupling is used in preference to opto-couplersfor long-term life stability and guaranteed creepage andclearance. This circuit has the inherent property of selflimiting energy transfer, since the maximum energy 1/2LI2,is defined by the bipolar transistor VBE threshold and thesource resistance value.

Fig. 1 Principle of S.O.P.S. with magnetic feedback forisolation.

The Transformer

The transformer uses the versatile ETD system. This is therange of four IEC standardised cores based on an E-coreshape with a round centre pole. This permits easy windingespecially for copper foil and standard wire. The ETDsystem includes coil formers into which the cores are clipassembled. The coil formers are designed for automaticwinding and comply with all the standard safetyspecifications.

The two-part coil former was especially designed for theETD34, and is shown in Fig. 2. There is 25% more windingarea compared to the standard coil former yet full safetyisolation is provided so that the creepage and clearancespecifications are fully met. The inner part is a "click" fit intothe outer part, such that the former is mechanically stableeven with the cores removed. This two-part constructionleads to a very versatile winding approach where standardprimaries can be wound and assembled, yet still retainingthe flexibility for various secondaries to be added fordifferent requirements.

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Fig. 2 ETD34 Two Part Coil Former.

Leakage inductance is always a problem with flybacktransformers, but using this special construction theincrease in leakage can be almost offset by the greaterwinding area of the two-part coil former when compared tothe standardproduct with 4+4mm creepageand clearance.Fig. 3 shows standard and two part transformercross-sections, where the leakage inductance is not morethan 20% greater for the two-part coil former for this 50Wdesign.

The transformer details for the 50W microcomputer powersupply design example are shown in Fig. 4. The primaryside consists of three windings:- a feedback winding of 5turns, the main primary winding and a bifilar voltage clamp

winding of 92 turns. This is achieved with 4 layers to fill theinner coil space area. The secondaries consist of a 5Vwinding of 3 turns and the +12V windings of 7 turns each.As there are so few turns, the winding area is mosteffectively filled with stranded wire, copper strip or parallelwindings, and these are therefore all possible choices.

In addition to the improved windings possibilities with thetwo-part coil former, the ETD core material has beenenhanced. The quality of the 3C85 material is muchimproved compared to the older 3C8 type. Fig. 5 comparescurves of core loss versus frequency for 3C85 against 3C8.The 30% improvement in 3C85 has been due to refiningthe material composition and tighter process quality control.

200


Fig. 3 The two types of transformer construction compared.

Fig. 4 Transformer winding details using two part coilformer.

Fig. 5 Core loss versus frequency for 3C8 and 3C85.

Application and Operation of SOPS

The SOPS circuit is ideally suited for microcomputersystems, where full performance at low cost is required.The 50W output power is split between a regulated 5Voutput at 5A for the logic, a +12V output at 1.8A and a -12Voutput at 0.2A for the peripherals. The circuit diagram ofthe power supply is shown in Fig. 6. The operatingfrequency varies from 250kHz at open circuit to 35kHz atfull load. The circuit works as follows:-

The mains input is filtered (L1), rectified (D1-D4) andsmoothed (C7) to provide a d.c. rail. This supply rail utilisesa single electrolytic capacitor which is a low profile , lowcost, snap-fit 055 type.

The main switching transistor, Q1, is a TO-220 powerMOSdevice, the BUK456-800A. Starting current is provided viaR1 to Q1 to start the self-oscillating operation. Feedbackcurrent is provided by a small winding on the transformer(T1), via C8 to maintain bias. Duty cycle control is via R5and T2, with final control being achieved with R5, T2 andQ2. The triangular transformer magnetising current is seenacross R5 as a voltage ramp, (see Fig. 7). This is fed to thebase of Q2, via a small U10 transformer, T2. When thevoltage becomes greater than the VBE of the transistor, Q2is turned on, causing the gate of Q1 to be taken to thenegative rail, so terminating the magnetisation of thetransformer T1. The output voltage is controlled by feedingback a turn-off pulse by means of T2, thus causing Q2 toturn on earlier.

A voltage clamp winding is bifilar wound with the primaryto limit voltage overshoots on the drain of Q1 at turn-off,thus ensuring that the transistor operates within its voltagerating.

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Fig. 6 Circuit diagram of 50W S.M.P.S.

Maximum throughput power is determined by the value ofR5: the higher its resistance value, the lower the maximumpower. The same drive and control circuit can be used fordifferent throughput powers, ETD core sizes andpowerMOS transistors.

The 5V secondary uses a single plastic TO-220 Schottkydiode, the PBYR1635 shown as D8. The output filter is api type giving acceptable output ripple voltage together withgood transient response. Two electrolytic capacitors areused in parallel, C11a/C11b (to accommodate the ripplecurrent inherent in flyback systems), together with a smallinductor wound on a mushroom core, L4, and a secondcapacitor, C14.

The turn-off pulse is created, cycle-by-cycle, by charging acapacitor from the output and comparing it with a reference,D10 and by using the transition signal to feed back a turn-offpulse via transformer T2. A potential divider is present

across the output 5V rail, consisting of R10, R11 and R12,via Q3. The potential divider controls the base voltage ofthe transistor Q4, which charges capacitor C16 via R13.The voltage on C16 ramps up to a voltage equal to that onthe base of the transistor less the VBE, causing Q4 to switchoff. The capacitor continues to charge more slowly viaresistor R14, i.e. a ramp and pedestal (see Fig. 8), until thevoltage on the emitter of Q5 is equal to the voltagedetermined by the band-gap reference D10 (2.45V) plusthe VBE drop of Q5. When this voltage is reached, Q5switches on, causing Q6 to switch on, pulling Q5 on harder.The edge produced is transmitted across T2 and adds tothe voltage on the base of Q2. Transistor Q3 is there tomaintain the voltage level at the end of the ’on’ period ofthe waveform to prevent premature switching. CapacitorC16 is reset by diode D9 on the edge of the switchingwaveform of the schottky diode, D8.

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Fig. 7 BUK456-800A powerMOS transistor switchingwaveforms.

Top trace - Drain voltage VDS 200V/divBottom trace - Source current IS 1A peak (across R5)

Timebase - 5µs/div

Fig. 8 Ramp and pedestal control waveforms acrossC16 = 1V/div, 5µs/div.

PerformanceThe performance of the supply is as follows:- the 5V outputhas load regulation of 1.2% from 0.5A to 5A load current.The line regulation is 0.5% for 187V to 264V a.c. mainsinput voltage.

The 12V secondaries are unregulated, and therefore havean inferior regulation compared to the 5V output. Each railhas a load regulation of 6% from open-circuit to full load.This is adequate for typical microcomputer peripheralrequirements.

The efficiency of the power supply is typically 80%. Theripple and noise on all outputs is less than 75mV peak topeak. The radio frequency interference is less than 50dB(above 1µV) from 150kHz to 30MHz and complies withVDEO875 and BS800, based on a 150Ω V network. SeeFig. 9. The transient response of the 5V output due to a 2Ato 5A step load change gives a deviation of 100mV.

Fig. 9 Conducted R.F.I. on the supply terminalscomplying with VDE0875 and BS800.

Conclusion

A novel Self Oscillating Power Supply has been introducedfeaturing two recently developed products, increasing thecost effectiveness and efficiency of low-power SMPS:-

The new ETD34 two-part coil transformer featuring:

* solving of isolation problems

* standard ’plug-in’ primaries

* suitable for automatic winding

* ETD system compatible.

The 3C85 ferrite material offers:

* 30% lower loss than 3C8

* comparable price with 3C8

* high frequency operation, up to 150kHz

* improved quality

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Magnetics Design

205


2.4.1 Improved Ferrite Materials and Core Outlines for HighFrequency Power Supplies

Increasing switching frequency reduces the size ofmagnetic components. The current trend is to promoteSMPS miniaturisation by using this method. The maximumswitching frequency used to be limited by the performanceof available semiconductors. Nowadays however, PowerMOSFETs are capable of square-wave switching at 1MHzand beyond. The ESL of the output capacitor had untilrecently limited any major size reduction in output filterabove 100kHz. The advent of multi-layer ceramic capacitorstacks of up to 100µF removed this obstacle. This allowedthe operating frequency to be raised significantly, providinga dramatic reduction in the size of the output filter (by anorder of magnitude). The transformer has now become thelargest single component in the power stage, and reducingits size is very important. The transformer frequencydependent core losses are now found to be a majorcontributing factor in limiting the operating frequency of thesupply.

Part 1 of this section highlights the improvements in ferritematerial properties for higher frequency operation. Thestandard 3C8 with its much improved version the 3C85 arediscussed. However, the section concentrates on the newhigh frequency power ferrite, 3F3. This material featuresvery low switching losses at higher frequencies, allowingthe process of miniaturisation to be advanced yet further.

The popular ETD system shown in Fig. 1 is also outlined,and used as an example to compare the losses obtainedwith the above three materials.

In Part 2, the new EFD (Efficient Flat Design) core shapeis introduced. These cores have been specifically designedfor applications where a very low build height is important,such as the on-card d.c. - d.c. converters used in distributedpower systems.

Circuit topologies suitable for high frequency applicationsare considered in the final part. Optimum winding designsfor the high frequency transformer, which maximise thethroughput power of the material are described.

PART 1: Improved magnetic materials

The ETD core system

The very widely used ETD core shape is shown in Fig. 1,which also outlines the method of coil-former assembly.The ETD range meets IEC standardisation, and is basedon an E-core shape with a round centre pole. This permitseasy winding especially for copper foil and stranded wire.The ETD system includes coil-formers into which the coresare clipped for quick, simple and reliable assembly. The

coil-formers are designed for automatic winding and enableconformance with all standard safety specificationsincluding UL.

ETD cores are suitable for a wide range of transformer andinductordesigns, and are very commonly featured inoff-linepower supply transformers because the ease of windingallows insulation and creepage specifications to be met.

Fig. 1 The ETD core and assembly system.

Core materials

Three types of ferrite core material are compared. Thestandard3C8 which is applicable for 50kHzuse, the popular3C85 which is usable at up to 200kHz, and the new highfrequency core material 3F3, which has been optimised foruse from 200kHz upwards.

The throughput power of a ferrite transformer is, neglectingcore losses, directly proportional to (amongst other things)the operating frequency and the cross-sectional area of thecore. Hence for a given core, an increase in the operatingfrequency raises the throughput power, or for a given powerrequirement, raising the frequency allowssmaller coresandhigher power densities. This is expressed by the followingequation:-

where Wd is the winding parameter, Cd is the core designparameter, f is the switching frequency and B is theinduction (flux density) in Tesla.

Unfortunately, the core losses are also frequencydependent, and increasing frequency can substantiallyincrease the core losses. Thus an increase in the corevolume is required to maintain the desired powerthroughput without overheating the core. This means thetransformer bulk in a higher frequency supply could limitthe size reduction target.

Pth = Wd × Cd × f × B

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The new 3F3 material with low-loss characteristics at highfrequencies will reduce this problem, allowing new levelsof miniaturisation to be obtained. An example of thepractical size (and weight) reduction possible by moving tohigher operating frequencies is given in Fig. 2. Incomparison with the 50kHz examples, there is a significantreduction in transformersize when switched at500kHz, andan even more impressive shrinking of the output inductorwhen operated at 1MHz.

Fig. 2 Size reduction possible using 3F3 ferrite.

Note. The size of the output capacitor and inductor requiredto filter the high frequency output ripple components isgreatly reduced - up to 90% smaller, resulting in excellentvolume savings and very low ripple outputs.

Fig. 3 Performance factor (f.Bmax) as a function offrequency for material grades 3C8, 3C85 and 3F3.

The performance factor (f.Bmax) is a measure of the powerthroughput that a ferrite core can handle at a loss of200mW/cm3. This level is considered acceptable for a welldesigned medium size transformer. The performancefactors for the three different material grades 3C8, 3C85and 3F3 are shown in Fig. 3. For frequencies below 100kHz(the approximate transition frequency, ft) the powerthroughput is limited by core saturation and there is notmuch difference between the grades. However forfrequencies above 100kHz, core loss is the limitation, whichreduces the allowable throughput power level byoverheating the core. Therefore, in order to utilise higherfrequencies to increase throughput power or reduce coresize, it is important that the core losses must first beminimised.

Reducing the lossesThere are three main identifiable types of ferrite materiallosses: namely, hysteresis, eddy current and residual.

Hysteresis loss

This occurs because the induced flux, B, lags the drivingfield H. The B/H graph is a closed loop and hysteresis lossper cycle is proportional to the area of the loop. This lossis expressed as:-

where Ca is a constant, Bpk is the peak flux density, f is thefrequency with x and y experimentally derived values.

Eddy current loss

This loss is caused by energy from the magnetic flux, B,setting up small currents in the ferrite which causes heatdissipation. The energy lost is represented by:-

Cb is a constant, Ae is the effective cross-sectional core areaand σ is the material resistivity.

Residual/Resonant loss

Residual losses are due to the reversal of the orientationof magnetic domains in the material at high frequencies.When the driving frequency is in resonance with the naturalfrequency at which the magnetic domains flip, there is alarge peak in the power absorption. This gives:-

where

Physt = Ca × f x×Bpky

Pec =Cb × f 2×Bpk

2 × Ae

σ

Pres = Cc × f × Bpk2 ×

tanδδ

tanδ = loss angle =µ"µ’

µ = µ ’ + j µ"

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Comparison of different materials

Fig. 4 Core losses in 3C85,3C8 and 3F3 for varioustemperatures at 100kHz and 100mT.

These losses (in mW/cm3) are now presented for the threematerial grades in a partitioned form. These are given forvarious operating temperatures under two differentoperating conditions. Fig. 4 shows performance at 100kHzand a peak flux density of 100mT, which is typical for the3C8 and 3C85 materials. The hysteresis loss is clearlydominantat this frequency. Inspection revealsa reasonableloss reduction when comparing 3C85 to the cheaper 3C8grade. More significantly however, even at this lowerfrequency the new 3F3 grade can be seen to offersubstantial loss reduction compared to 3C85 (especially atlower operating temperatures).

Fig. 5 Core losses in 3F3 and 3C85 for varioustemperatures at 400kHz and 50mT.

At higher operating frequencies well above 100kHz, eddycurrents and residual losses are far more dominant. Fig. 5gives the values for 400kHz and 50mT high frequencyoperation. This shows the superiority of the 3F3 material,offering significant reductions (60% vs 3C85) in allmagnitudes, particularly in the eddy currents and residuallosses.

Figure 6 gives a comparison of the peak operating fluxdensity versus frequency at a core loss of 200mW/cm3 foreach grade. This shows that the maximum allowableoperating frequency for 3F3 is always higher than for theother two types, hence, making it much more suitable forminiaturisation purposes. For example, at 100mT, 3F3 canoperate at 280kHz, compared to 170kHz for 3C85 and100kHz for 3C8.

Fig. 6 Peak flux density versus frequency for 3F3,3C85 and 3C8 at constant 200mW/cm3 core loss.

Figure 7 compares the three types of core material in termsof complex permeabilities µ’ and µ" over the frequencyrange 1 to 10 MHz, at very low flux density levels of < 0.1mT. It can be seen that the resonant loss peaks at a higherfrequency for 3F3, producing much lower high frequencyresidual losses right up to 1MHz.

Fig. 7 Complex permeability versus operatingfrequency for 3F3 and 3C85/3C8.

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Material 3C8 3C85 3F3

Bsat (mT) at f = 25kHz ≥ 320 ≥ 320 ≥ 320H = 250A/m

AL PV AL PV PV AL PV PV

Core type ± 25% Watts ± 25% Watts Watts ± 25% Watts WattsnH/N2 nH/N2 nH/N2

f 10kHz 25kHz 10kHz 25kHz 100kHz 10kHz 100kHz 400kHz

B 0.1mT 200mT 0.1mT 200mT 100mT 0.1mT 100mT 50mT

ETD29 - - 2100 ≤ 0.8 ≤ 1.0 1900 ≤ 0.6 ≤ 1.0ETD34 2500 ≤ 1.6 2500 ≤ 1.1 ≤ 1.3 2300 ≤ 0.85 ≤ 1.5ETD39 2800 ≤ 2.2 2800 ≤ 1.6 ≤ 1.9 2600 ≤ 1.3 ≤ 2.3ETD44 3500 ≤ 3.6 3500 ≤ 2.5 ≤ 3.0 3200 ≤ 2.0 ≤ 3.7ETD49 4000 ≤ 4.6 4000 ≤ 3.4 ≤ 4.0 3600 ≤ 2.6 ≤ 5.2

Table 1. Comparison of material properties for the ETD range

Comparison of material grade propertiesfor the ETD range

The values shown in Table 1 are for a core set under powerconditions at an operating temperature of 100˚C.

3F3 offers a major improvement over existing ferrites forSMPS transformers. With reduced losses across the entirefrequency range (but most markedly at 400kHz and higher)3F3 enables significant reductions in core volume while stillmaintaining the desired power throughput.

As well as the ETD range, 3F3 is also available in thefollowing shapes:-

• RM core

• P core

• EP core

• EF core

• E core

• ring core

• new EFD core

The new EFD core system which also offers size reductioncapabilities shall now be described.

PART 2: The EFD core(Economic flat design)The newly developed EFD power transformer core systemshown in Fig. 8 offers a further significant advance in circuit

miniaturisation. Their low build height and high throughputpower density make them ideally suited to applicationswhere space is at a premium.

One such application is with distributed power systems,which is becoming an increasingly popular method of powerconversion, especially in the telecommunication and EDPmarket. Such power-systems convert a mains voltage intoan unregulated voltage of about 44 to 80V d.c. This is thenfed to individual sub-units, where d.c. - d.c. convertersproduce the required stabilised voltages. These convertersare usually mounted on PCBs which in modern systems,are stacked close together to save space. The d.c. - d.c.converter, therefore, has to be designed with a very lowbuild height.

Fig. 8 The EFD core assembly and accessories.

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The low-profile designThe EFD core offers a significant reduction in transformercore height. The ETD core combines extreme flatness witha very high throughput power-density. The range consistsof four coreassemblies complemented by acomplete rangeof accessories. It is planned that the EFD outline willbecome a new European standard in d.c. - d.c. powertransformer design.

The four core assemblies have a maximum finished heightof 8mm, 10mm or 12.5mm. The type numbers are:-

• 8mm height - EFD 15/8/5

• 10mm height - EFD 20/10/7

• 12.5mm height - EFD 25/13/9 and EFD 30/15/9

Figure 9 shows that the EFD range has a lower build heightthan any other existing low profile design with the samemagnetic volume.

Integrated product design

Because there is no room in a closely packed PCB forheavily built coil formers, they must be as small and lightas possible. For this reason high quality thermo-settingplastics are used. This ensures that the connecting pins inthe base remain positioned correctly.

To ensure suitability for winding equipment the connectingpins have been designed with a square base, saving timein wire terminating. To allow thick wire or copper foilwindings to be easily led out, both core and coil former havea cut-out at the top (see Fig. 8).

To increase efficiency and reduce size, the ferrite core hasbeen designed with the centre pole symmetricallypositioned within the wound coil former. This is clearlyshown in the cross-sectional view in Fig. 10.

Because of this, the full winding area can be used, resultingin an extremely flat design which is ideally suited forsurface-mounting technology (SMT). SMT designs arealready under consideration.

Maximising throughput power-density

Besides their extreme flatness, the most important featureof the EFD transformer is the very high throughput powerdensity. This is especially true when the core ismanufactured from the high-frequency low loss 3F3material, which was described in the previous section.Combining EFD with 3F3 can provide throughput powerdensities (in terms of transformer volume) between 10 and20 W/cm3. Furthermore, with ausable frequency range from100kHz to 1MHz, the EFD transformer will cover mostapplications.

Fig. 9 EFD build height compared to existing designs.

Fig. 10 Cross-section of EFD based transformers.

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Fig. 11 Temp rise versus Pth for ETD based transformers Fig. 12 Pth for forward mode transformers based onwith 3F3 material. EFD core with 3F3 material.

As described earlier, high frequency transformer design(above 100kHz) is mainly limited by the temperature rise,caused by heat dissipation from the high frequency corelosses as well as the power dissipation in the windingsthemselves. So the extent of transformer miniaturisation athigh frequencies is limited by this rise in temperature (Thecurie temperature of a typical power ferrite material isaround 200˚C). As a general rule, maximum transformerefficiency is reached when about 40% of the loss is in theferrite core, and 60% in the windings. The temperature risefor a range of throughput powers for transformers basedon the EFD range in 3F3 material is shown in Fig. 11.

In order to optimise the core dimensions and winding area,a sophisticated computer aided design (CAD) model of ad.c. - d.c. forward mode converter was used. This predictedthe temperature rise of the transformer as a function ofthroughput power. The following parameters wereassumed:-

Ferrite core - 3F3.

Vin = 44V to 80V; Vout = 5V, +12V and -12V.

Tamb = 60˚C; Trise = 40˚C.

Primary - Cu wire; Secondary - Cu foil.

(Split sandwiched winding with 2 screens).

The CAD program was used to find an optimised designfor the EFD transformer at well chosen frequency bands.The dotted line in Fig. 12 indicates the theoretical resultderived from the CAD model. This shows in practice howwell the EFD range approximates to the ideal model. Theopen circle for EFD 15/8/5 in Fig. 12 indicates the maximumoptimal switching frequency.

Fromthese results the range was grouped, dependinguponcore size into their optimal frequency bands.

• 100 to 300kHz - EFD 30/15/9 and EFD 25/13/9.

• 300 to 500kHz - EFD 20/10/7.

• 500kHz to 1MHz - EFD 15/8/5.

These are the recommended frequency ranges for eachEFD type. The transformers can operate outside theseranges, but at a reduced efficiency, since the ratio of theircore to winding areas would be less than ideal. Table 2 liststhe power throughput at certain frequencies for each EFDcore.

Core type 100 kHz 300kHz 500kHz 1MHz

EFD 30/15/9 90 - 100 W 110-140W -- --EFD 25/13/9 70 - 85 W 90 - 120 W -- --EFD 20/10/7 -- 50 - 65 W 55 - 70 W --EFD 15/8/5 -- -- 20 - 30 W 25 - 35 W

Table 2. Power handling capacity for EFD range.

Valid for single-ended forward d.c. - d.c. converter(Vin = 60V; Vout = 5V)

TypicalEFD throughput power curves given in Fig. 13 showthe performance of the low loss 3F3 material as well as3C85. These results were confirmed from measurementstaken during tests on EFD cores in a transformer testingset up. As expected these show that, especially above300kHz, the 3F3 (compared to 3C85) significantly improvesthroughput power.

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Fig. 13 ETD performance for 3F3 and 3C85 material.

PART 3: Applications

Circuit (transformer) configurationsForward, flyback and push-pull circuit configurations havebeen used successfully for many different SMPSapplications. This includes mains-isolated square-waveswitching over the frequency range 20-100kHz, and withoutput powers up to 200W. Recent transformer designshave been developed to minimise the effects of leakageinductance and stray capacitance upon these circuits. Theinfluences of the transformer characteristics on the choiceof circuit configuration for higher switching frequencyapplications are now discussed.

The flyback converter

The flyback converter shown in Fig. 14 has leakageinductance between the primary and secondary windingswhich delays the transfer of power when the primary powertransistor turns off. For the example waveforms shown inFig. 14, the delay lasts for 600ns. During this time, poweris returned to the d.c. supply. The circulating powerincreases with the switching frequency, and in this casewould produce 50W at 1MHz. This tends to limit themaximum operating frequency for flyback converters.

The forward converter

The power transistor in the forward converter shown inFig. 15 normally has a snubber network (and stray circuitcapacitance) which protects the transistor at turn-off. Thisis necessary because the energy stored in the leakageinductance between the primary and secondary windingswould produce a large voltage spike at transistor turn-off.

At transistor turn-on the energy stored in the capacitanceis discharged and dissipated. For the example waveformsgiven in Fig. 15, this would be7.5W at aswitching frequencyof 1MHz. Furthermore, as in the flyback converter, thecirculating magnetising power can also be as high as 50W

at 1MHz, hence reducing the efficiency of the transformer.Thesecharacteristics limit the maximumfrequency atwhichforward converters can be usefully applied.

Fig. 14 Flyback converter and leakage inductanceeffect.

Centre-tapped push-pull converter

The centre-tapped push-pull circuit configuration given inFig. 16 uses magnetic B/H loop symmetry when driving thetransformer. Therefore, when either transistor is turned off,the magnetising current is circulated around the secondarydiodes, thereby reducing energy recovery problems or theneed for voltage clamping.

However, the transformer must be correctly "flux balanced"by monitoring the current in the transistors to preventtransformer saturation and subsequent transistor failure.

The drain current and voltage waveforms resulting from twoexamplesof push-pull transformer winding construction arealso shown in Fig. 16. In Fig. 16(a) (most serious case) theleakage inductance has distorted the waveforms. InFig. 16(b) it is the circuit capacitance which produces thedistortion.Thesedistortions mean that the transistor current

Flyback

L

L - leakage inductance

500ns

500mV

2V

5mV

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sense waveforms must be adequately filtered, so that thecontrol circuit can vary mark/space correctly and preventtransformer saturation.

Fig. 15 Forward converter and effects of parasitics.

As the switching frequency is increased, the accuracy ofthe current balancing information is reduced by the actionof the filtering and there might be a point at which thisbecomes unacceptable. The filter itself is also dissipativeand will also produce a high frequency loss.

The half-bridge converter

The half-bridge push-pull transformer shown in Fig. 17 isinherently self-balancing. Standard winding methods fortransformer construction using this configuration arepossible at frequencies up to around 1MHz. Fig. 17 alsogives waveform examples for the half-bridge transformer.This design allows the most flexibility when choosing aparticular switching frequency.

(a) Oscillation due to leakage inductance.

(b) Oscillation due to winding capacitance.Fig. 16 Push-pull transformer configuration.

L

C

W1 W2

TR1 TR2

Centre-tapped push-pull

W1 - Primary Limb 1W2 - Primary Limb 2

L

L - leakage inductance

CTR

Lprim

C - snubber capacitorLprim - primary inductance

TR - transistor

Forward

50mV 1us

1V

50mV

2V 50mV 1us

200mV 500ns

5V

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Switching frequencyWhendesigning a transformerandcalculating the core loss,the exponent for frequency in the hysteresis loss equationis assumed to be constant at all frequencies. Only thefundamental is considered significant compared to all otherharmonics of the square wave. This is a reasonableapproximation to make from 20kHz to 100kHz because thecontribution of eddy losses and resonant losses to theoverall core loss is negligible (see Fig. 4).

As the frequency increases to 1MHz and beyond, theresonant and eddy current losses contribute proportionallymore to the overall core loss.This means that the harmonicsof a 1MHz square wave have more significance indetermining the core loss than those at 100kHz. When themark/space is reduced, the harmonics increase, and theloss will increase proportionally. This effectively limits theupper frequency of a fixed frequency square-wave,mark/space controlled power supply. However, as outlined,new materials such as 3F3 have been specially developedto keep these high frequency transformer losses as low aspossible.

Transformer constructionIn the half-bridge push-pull configuration of Fig. 17, duringthe period that the two primary transistors are off, there iszero volts across the secondary winding. Therefore, thesecondary diodes are both conducting and share the chokecurrent.The primaryside should also have zero voltsacrossit, but it rings because of the stray capacitance and leakageinductance between the primary and the secondarywindings (see waveform of Fig. 17). At 500kHz, using anETD29 or an EFD20 core, for example, a 1+1 copper stripsecondary winding is suitable for providing an output of 5V.This is preferable to using more turns for the secondarywinding because the leakage inductance and the amplitudeof the ringing during the period that the MOSFETs are offis minimised. Reducing the ringing is of vital importance forthe following reasons:-

1. It prevents the anti-parallel diode inherent in the upperMOSFET switch from conducting when the lower transistoris turned on. This will increase the MOSFET dV/dt ratingtypically by a factor 10, allowing the switching speed to bemaximised and the switching losses to be reduced.

2. For low voltage outputs, the ringing will only be slightlyreduced by the 1+1 construction. However, the core lossesincrease significantly at the actual frequency of the ringing(5-10MHz). Hence, any reduction in the ringing amplitudewill be beneficial to core loss.

To further optimise the operation of the transformer, andreduce the ringing, the output clamping diodes should beoperated with the minimum of secondary leakageinductance and mounted physically close to thetransformer.

Fig. 17 Half-Bridge transformer configuration withtypical waveforms.

Conclusions

To advance the trend towards SMPS miniaturisation,low-loss ferrites for high frequency have been speciallydeveloped. A new ferrite material has been presented, the3F3, which offers excellent high-frequency, low losscharacteristics.

A wide range of power ferrite materials is now availablewhich offers performance/cost optimisation for eachapplication. The particular SMPS application slots for thethree ferrites discussed in this paper are summarised asfollows:-

• 3C8 for low-cost 20-100kHz frequency range.

• 3C85 for high performance 20-150kHz.

• 3F3 for miniaturised high performance power supplies inthe frequency range above 150kHz.

L

TR1

TR2

L

Half-bridge push-pull

prim

200mV 500ns

2V

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A new type of power core shape, the EFD was alsointroduced. The use of the EFD core also allows furtherSMPS miniaturisation by providing extremely low buildheights in conjunction with very high throughput powerdensities. Optimum use of the EFD design can be made ifthe 3F3 material grade is selected. The EFD system isintended for applications with very low height restrictions,and is ideal for use in the d.c. - d.c. converter designs foundin modern distributed power systems.

Different transformer winding configurations were also

described (particularly for mains isolated SMPS.) It wasfound that to obtain the greatest size reduction using thenew 3F3 material at very high frequencies, the followingapplication ideas are useful:-

• Use the half-bridge push-pull circuit configuration.

• Minimize the transformer leakage inductance by carefulwinding construction.

• Minimise the lead-lengths from the transformer to rectifierdiodes.

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Resonant Power Supplies

217


2.5.1. An Introduction To Resonant Power Supplies

Whilst many application requirements can be satisfied bythe use of conventional switching topologies, theirshortcomings, particularly the switching losses in highpower / high frequency circuits, are becoming a seriouslimitation. Some of the problems can be overcome by theuse of resonant, or quasi-resonant, converters.

A resonant converter is a switching converter in which thenatural resonance between inductors and capacitors isused to shape the current and voltage waveforms.

There are many ways in which inductors, capacitors andswitches can be combined to form resonant circuits. Eachof the configurations will have advantages anddisadvantages in terms of stress placed on the circuitcomponents.

Toreduce switching loss, a resonantconverter which allowsthe switching to be performed at zero current and low dI/dtis needed. A range of such circuits can be produced bytaking any of the standard converter topologies andreplacing the conventional switch with a resonant switch.

Fig.1 Basic resonant switch circuits

Resonant switchA resonant switch consists of an active element (the switch)plus an additional inductor, L, and capacitor, C. The valuesof L and C are chosen so that, during the on time of theswitch, the resonant action between them dominates. Thisensures that the current through the switch, instead of justincreasing linearly and having to be turned off, forms asinusoid which rises to a peak and falls to zero again.

Two basic resonant switch configurations are shown inFig.1. Before the switch is closed, C is in a state where ithas a small negative charge. With the switch closed, C isdischarged into L and then recharged positively. During therecharging extra energy is drawn from the supply to replacethat delivered to the load during the previous cylce. With Ccharged positively, the switch is opened. The energy in Cis now transfered to the load, either directly or via the maininductor of the converter. In the process of this transfer, Cbecomes negatively charged.

Figure 2 shows the three basic SMPS topologies - buck,boost and buck / boost - with both conventional (a) andresonant (b) switches. It should be noted that parasiticinductance and capacitance could form part, or even all, ofthe components of the resonant network.

Fig.2 Standard SMPS circuits using(a) conventional switch(b) resonant switch

Flyback converterTo show how the resonant switch circuit reduces switchingloss we will now consider the operation of the flybackconverter, firstly with a conventional switch and then witha resonant switch.

219


Conventional switchThe basic flyback converter circuit is shown in Fig.3(a). Ifthe transformer is assumed to have negligible leakageinductance it can be replaced by a single equivalentinductor Lm and the circuit becomes as shown in Fig.3(b),which is the same as a buck-boost converter shown in Fig.2.

Before the switch S is closed, a current Io will be flowing inthe loop formed by Lm, diode D and the output smoothingcapacitor Co. When S closes, voltage Es reverse biasesthe diode, which switches off and blocks the flow of Io. Acurrent Is then flows via S and Lm. The only limitations onthe initial rate of change of current are the stray inductancein the circuit and the switching speed of S. This means thatswitching current Is rises very quickly, leading to largeturn-on losses in S and D.

Fig.3 Conventional switch flyback converter(a) circuit(b) equivalent circuit

The current Is rises linearly from Io until the switch is forcedto reopen. The diode is then no longer reverse biased andthe current switches back from Is to Io via D, with Co thenacting as a voltage source. The losses in this switching willalso be very high due to the high level of Is and the rapidapplication of the off-state voltage. Io now falls linearly,delivering a charging current to Co, until the switch closesagain.

Figure 4 shows the current waveforms for Io and Is and thecurrent in inductor Lm.

Fig.4 Waveforms for conventional switch flybackconverter

Resonant switchThe resonant switch flyback converter circuit is shown inFig.5(a). The equivalent circuit (Fig.5 (b)) is the same asthat for the conventional switch except for the addition ofthe inductor La and capacitor Ca whose values are verymuch less than those of Lm and Co respectively.

Fig.5 Resonant switch flyback converter(a) circuit(b) equivalent circuit

220


Fig.6 Resonant switch flyback converteroperating modes(a) Mode 1: S close , D on(b) Mode 2: S closed, D off(c) Mode 3: S open, D off(d) Mode 4: S open, D on

If it is assumed that the switch is closed before the currentin Lm has fallen to zero, then the initial equivalent circuitwill be as shown in Fig.6(a). The rate of rise of current in Sis determined by the value of La which, although small, ismuch larger than the stray inductance that limits currentrise in a conventional switch. Turn-on losses are thussignificantly reduced. Co, being much larger than Ca, actsas a voltage source (Vo) preventing current from flowinginto Ca and maintaining a constant rate of change of currentin Lm. Ia will increase linearly until it equals Im at whichtime Io is zero and diode D turns off.

With D turned off, the equivalent circuit becomes as shownin Fig.6(b). The resonant circuit, La, Ca and Lm, causes Iato increase sinusoidally to a peak and then fall back to zero.S can then be opened again with very low losses.

With the switch open, the circuit is as shown in Fig.6(c).The resonant action between Ca and Lm causes energy tobe transferred from the capacitor to the inductor. Vc will fall,passing through zero as Im reaches a peak, and then willincrease in the opposite direction until it exceeds Vo. Atwhich point D becomes forward biased, so it will turn on.

As D turns on (Fig.6(d)) the voltage across Ca becomesclamped and Im now flows into Co. Im falls linearly until theswitch is closed again and the cycle repeats.

Voltage and current waveforms for a complete cycle ofoperation are shown in Fig.7.

From the description of operation it can be seen that thereduced switching losses result from:

- La acting as a di/dt limiter at switch on

- The resonant circuit La, Lm and Ca ensuring that thecurrent is zero at turn-off

These factors combine to allow the switching devices to beoperated at higher frequencies and power levels than waspreviously possible.

Circuit designCorrect operation of a resonant switch converter dependson the choice of suitable values for the inductors andcapacitors. It is not possible to determine these valuesdirectly but they can be selected using simple computermodels. An example of a model for a resonant switchflyback converter is given below to demonstrate the basictechnique that can be used to analyse many different typesof resonant circuits. Writing the final computer program willbe a simple task for anyone with proramming experienceand the model will run relatively quickly on even smallpersonnel computers.

Circuit analysisHere we analyse the operation of a resonant flybackconverter circuit in mathemtical terms, assuming idealcircuit components.

In the equivalent circuit of the flyback converter, Fig.5(b),there are two switching elements S and D and the circuithas four possible modes of operation:

Mode 1 S closed D on

Mode 2 S closed D off

Mode 3 S open D off

Mode 4 S open D on

221


Fig.7 Waveforms for resonant switch flyback converter

Using Laplace analysis of the equivalent circuit for eachoperating mode, equations can be written for Ia, Ic, Im, Ioand Vc.

J and U are the values of, Im and Vc respectively at thestart of each operating mode i.e. when t = 0.

Mode 1

Figure 6(a) shows the equivalent circuit when S is closedand D is on. The large output capacitor Co as shown actsas voltage source (Vo).

The equations are:

Mode 2Figure 6(b) shows the equivalent circuit when S is closedand D is off.

The equations are:

where,

Ia = J + A1.t +A2 − A1

ω1.sin(ω1.t)

Im = J + A1.t +A3 − A1

ω1.sin(ω1.t)

Ic = Ia − Im

Vc = U +

Lm.(Es− U) − La.ULa + Lm

.(1− cos(ω1.t))

Io = 0

Ia =Es− U

La.t

A1 =Es

La + LmIm =ULm

.t + J

A2 =Es− U

LaIc = 0

Vc = UA3 =

ULmIo = Im − Ia

222


Mode 3Figure 6(c) shows the equivalent circuit when S is open andD is off.

The equations are:

where,

Mode 4Figure 6(d) shows the equivalent circuit when S is open andD is on.

The equations are

Computer simulationUsing the previous equations, it is possible to write acomputer program which will simulate the operation of thecircuit.

If S is closed before Im falls to zero, then during a completecycle each of the operating modes occurs only once, in thesequence mode 1 to mode 4.

The first function of the program is to determine the durationof each mode.

Mode 1The time between the switch turning on and the current Iareach Im is given by:

J1, the initialvalue of Im chosenby the designer, determinesthe average output current. U1 is the initial value of Vc. IfIm is greater than zero, D will still be on so Vc and thereforeU1 will equal Vo.

Mode 2The duration, T2, of the second mode cannot be founddirectly and must be determined by numerical methods. T2ends when Ia falls back to zero, so by successiveapproximation of t in the mode 2 equation for Ia, it is possibleto find T2.

J and U at the start of mode 2, i.e., J2 and U2, are foundby solving the mode 1 equations for Im and Vc respectivleyat t = T1.

For any given set of circuit values there is a value of J1above which Ia will not reach zero. This condition has to bedetected by the program. Decreasing the value of La orincreasing the value of Lm or Ca will allow Ia to reach zero.

Mode 3Mode 3 operation ends when Vc = Vo. The duration, T3, isgiven by:

where,

and J3 and U3 are the values of Im and Vc respectively atthe start of mode 3.

Mode 4If the circuit operation is stable then the value of Im, whenS is again closed, will equal J1 and the duration of the modewill be

Where J4 and U4 are the values of Im and Vc at the startof mode 4.

Calculation of Io and VsHaving found the durations of the four modes, the averageoutput current in D can be calculated, from:

Peak, RMS and average values of the current in S (Ia) canbe determined by numerical analysis during modes 1 and2. The voltage across S is given by

ω1 = √

La + LmLm.Ca.La

Ia = 0

Im = J.cos(ω2.t) +U

Lm.ω2.sin(ω2.t)

Ic = −Im

Vc = U .cos(ω2.t) +J

Ca.ω2.sin(ω2.t)

Io = 0

ω2 = √

1Lm.Ca

T3 =1ω

2.cos−1

Vo

√U32 + A42

− tan−1

A4U3

Ia = 0A4 =

J3Ca.ω2

Im = J +ULm

.t

Ic = 0

Vc = U

Io = Im

T4 =Lm.(J4 − J1)

U4

Io(av) =T4.(J4 + J1) + T1.J12.(T1 + T2 + T3 + T4)

T1 =J1.Lm.La

Lm.(Es− Vo) − U1.La

223


These values will be needed when the components S andD are chosen.

Conclusions

Resonant combinations of inductors and capacitors can beused to shape the current and voltage waveforms inswitching converters. This shaping can be used to:

- reduce RFI and EMI,

- eliminate the effects of parasitic inductance andcapacitance,

- introduce a degree of self limiting under faultconditions,

- reduce switching losses.

The resonant switch configuration is one way of reducingswitching losses in the main active device. It can be adaptedfor use in all the standard square wave circuit topologiesand with all device types.

Although the analysis of resonant circuits is more complexthan the analysis of square wave circuits, it is stillstraightforward if the operation of the circuit is broken downinto its different modes. Such an analysis will yield a set ofequationswhich can be combined into acomputer program,toproduce a modelof the systemwhich can be run relativelyquickly on even small computers.

Vs = Es− Vc

224


2.5.2. Resonant Power Supply Converters - The Solution ForMains Pollution Problems

Many switch mode power supplies which operate directlyfrom the mains supply, use an electrolytic buffer capacitor,after the bridge rectifier, to smooth the 100/120 Hz rippleon the DC supply to the switching circuit. This capacitiveinput filter causes mains pollution by introducing harmoniccurrents and therefore cannot be used in supplies withoutput powers above 165W. (TV, IEC norm 555-2, part 2:Harmonics, sub clause 4.2).

The smoothing capacitor can be charged only when themains voltage is greater than the DC voltage. Therefore theinput current will take the form of high amplitude, shortduration pulses. For comparison, the load current for a220W resistive load (an RMS current of 1A for 220Vmains/line) and the load current for a 220W rectifier withcapacitive input buffer are shown in Fig. 1.

The peak value of the current with the capacitor load is 5times higher than for the resistive load, while the RMScurrent is doubled. It is understandable that the electricitysupply authorities do not like this kind of load, because itresults in high levels of harmonic current and a power factorbelow 0.5. It is, therefore, necessary to find alternativemethods of generating a smooth DC voltage from themains.

The PRE-CONVERTER switched mode supply is onepossible solution. Such a converter can operate from theunsmoothed rectified mains/line voltage and can producea DC voltage with only a small 100/120 Hz ripple. By addinga HF transformer it is possible to produce any value of DCvoltage and provide isolation if necessary.

By proper frequency modulation of the pre-converter, theinput current can be made sinusoidal and in-phase with thevoltage. The mains/line now ’sees’ a resistive load, theharmonic distortion will be reduced to very low levels andthe power factor will be close to 1.

A pre-converter has to be able to operate from inputvoltages between zero (at the zero crossings) and the peakvalue of mains/line voltage and still give a constant outputvoltage. The SMPS converter that can fulfil theseconditions is the ’flyback’ or ’ringing’ choke converter. ThisSMPS converter has the boost and buck properties neededby a pre-converter. However, the possibility of stabilityproblems under ’no load’ operation and its moderateconversion efficiency, means that this converter is not themost attractive solution for this application.

a) Resistive Load

b) Capacitor Filter

Fig. 1 Current taken from mains

The RESONANT POWER SUPPLY (RPS) has the rightproperties for pre-converter systems. The boost and buckproperties of a resonant L-C circuit around its resonantfrequency are well known. In principle any current can beboosted up to any voltage for a PARALLEL RESONANTL-C circuit. Furthermore, the current and voltage waveforms in a resonant converter are more or less sinusoidal,resulting in a good conversion efficiency and there are nostability problems at no load operating conditions.

Resonant pre-converter circuitsThere are two basic resonant power supply (RPS)principles that can be considered, namely:

- The SERIES RESONANT POWER SUPPLY (SRPS),where a series resonant L-C circuit determines the no loadoperation cycle time. The output power increases withincreasing operation cycle time (thus with decreasingoperation frequency).

Iin1A/div

Iin1A/div

225


- The PARALLEL RESONANT POWER SUPPLY (PRPS),where a parallel resonant L-C circuit determines the noload operation cycle time. The output power increaseswith decreasing operation cycle time (thus with increasingoperation frequency).

The basic SRPS converter circuit

A basic SRPS converter topology is shown in Fig. 2. Forsimplicity in the following description, the input voltage Epis taken to be constant - 310 VDC for the 220VACmains/line. If the circuit is to appear as a ’resistive’ load tothe mains, then the output power of the pre-converter hasto be proportional to the square of the instantaneous valueof Ep. This means that the peak output power of the circuitmust be equal to twice the average output power. So a250W pre-converter has to be delivering 500W when Ep isat its peak.

Fig. 2 Basic SRPS Pre-converter Circuit

In Fig. 2, the semiconductor switch S1 has an anti-paralleldiode D1 to avoid a negative voltages across S1.Principally, a diode in series with S1 also gives a suitableSRPS pre-converter, but it slightly increases the positivepeak voltage on S1 without giving an advantage over thecircuit with anti-parallel diode. The lower value of the RMScurrent in S1 and thus the reduction in its on-state lossesis completely cancelled by increased turn-on losses in thisdevice.

Furthermore, stability problems can occur under no loadconditions for the circuit with series diode (infinitely smallcurrent pulses in S1). The circuit with anti-parallel diode hasno infinitely short current pulses under no load conditions,because the positive current in S1 will be preceded by thenegative current in D1. As a result, no nett DC current issupplied to the circuit at finite pulse widths.

The input inductance Lo forms the connection between theinput voltage and the switch voltage Vsw. A ’SERIES’resonant L-C circuit, consisting of the capacitor Cp (whenbothS1 and D1 are OFF), the inductance Ls, the DC voltageblocking capacitor Cb and the capacitor Cs (when B1 isOFF), determines the no load operation frequency. Theinfluence of the input inductance Lo can be neglected if itsvalue is several times that of Ls.

A practical SRPS pre-converter for 250W nett output power(500W peak power conversion) can have componentvalues shown in Table 1.

Fig. 3 Waveforms of Basic SRPS Circuit(Tcycle = 1.01 x Tref, no load, Ep = 310V)

Capacitor Cp changes the voltage waveform across switchS1/D1 from the rectangular shape associated with SMPSconverters, to the sinusoidal shape of an SRPS converter.

Vsw500V/div.

Isw5A/div

S1 D1

Lo Ls

Isw

Io

Vsw

Cb

Cs

IsVb

VsCout

+Eo

0

Cp

Cin

+Ep

0

B1

Vs500V/div.

Is5A/div

226


Lo 4 mH 8 x LsCp 16 nF Cs / 1.5Ls 500 µHCs 24 nFCb 360 nF 15 x CsTref 13.3 µs minimum cycle time

Table 1 Component Values for SRPS circuit

The output rectifier bridge B1 has been connected inparallel with the output capacitor Cs. The whole converteralso can be viewed as a parametric amplifier, where theswitchS1 or the diode D1 modulate the value of Cp betweenCp and infinity, while the output bridge B1 has similarinfluence on the value of the capacitor Cs. Heavier loadmeans longer conduction of S1/D1 and of B1, so that someautomatic frequency adaptation of the SRPS circuit takesplace at operation frequencies below the no load resonantfrequency. The output power of the SRPS increases withdecreasing operation frequency.

Fig. 3 shows time plots of some of the voltages and currentsof the basic SRPS circuit for the minimum ON time of S1/D1.

Under no load operation, the voltage Vsw is a pure sinewave superimposed on the input voltage with an amplitudeequal to this voltage. The operation cycle time isapproximately equal to the series resonant circuit cycletime, Tref, for no load conditions. The voltage Vsw and Vsand the current Is are sine waves with a low harmonicdistortion. The input current Io is a low amplitude sine waveand it has no DC component for zero load.

In order to give an impression of the boosting properties ofthe SRPS converter, the no load voltages and currents foran operation cycle time of 1.25 x Tref are plotted in Fig. 4.

Fig. 3 gives the minimum ’ON’ time condition for the S1/D1switch and thus the minimum output voltage amplitude fora given input voltage. The minimum ratio of the amplitudeof Vs and the input voltage Ep, with the component valuesgiven earlier, has been found to be:

It will be obvious, that the value of the output voltage Eohas to be in excess of the minimum amplitude of Vs. Thus:

A practical value of Eo has to be about 10% in excess ofthis minimum value in order to deal with tolerances incomponent values, thus:

Fig. 4 Waveforms of Basic SRPS Circuit(Tcycle = 1.25 x Tref, no load, Ep = 310V)

To realise the situation shown in Fig. 4, the output voltageEo has to be increased considerably for no load operationfor the same Ep or Ep can be decreased considerably forthe same Eo. In fact, the relation between Eo and Ep in thisfigure is found to be:

Vsw500V/div.

Isw5A/div

Vs500V/div

Is5A/div

VsEp

= 0.7

Eo > 0.7× Ep

Eo > 0.8× Ep Eo> 2.7× Ep

227


Fig. 5 Waveforms of Basic SRPS Circuit(Tcycle = 1.462 x Tref, 500W output, Ep = 310V)

Finally, Fig. 5 shows the voltages and currents for full load(Pout = 500W) at Ep = 310V and Eo = 300V. The inputcurrent Io is not shown but is a DC current of 1.6A with asmall ripple current. The cycle time has been increased to1.45 x Tref to get the 500W output power, giving anoperating frequency of about 50 kHz.

It should be noted that S1 has to switch ’OFF’ a high currentat a relatively high dV/dt, resulting in significant turn-offlosses. These losses are the main reason to prefer PRPSover SRPS for pre-converter applications.

The basic PRPS converter circuit

A basic PRPS converter topology is shown in Fig. 6. Justas for the basic SRPS pre-converter, we will assume a DCsupply voltage Ep of 310 Vdc and a peak output power of500W, i.e. a nett output power of 250W average.

The topology of Fig. 6 (PRPS) is almost identical to thetopology of Fig. 2 (SRPS), except for the following points:

- Diode D1 is now in series with the switch S1 instead of inanti-parallel.

- Capacitor Cp has been omitted.

Fig. 6 Basic PRPS Pre-converter Circuit

The value of the two inductors Lo and Ls remain the sameas they were in the SRPS, but the values of Cb and Cs arechanged to obtain proper PRPS circuit operation. HavingD1 in series with S1 does not lead to ’no-load’ stabilityproblems because, in the PRPS circuit, both the amplitudeand the duration of the S1 current pulse are reduced as theoutput power decreases.

The input inductance Lo again forms the connectionbetween the input voltage Ep and the switch voltage Vsw(across D1 and S1 in series). A ’PARALLEL’ resonant L-Ccircuit, consisting of the series connection of Lo and Ls, theDC voltage blocking capacitor Cb and the capacitor Cs(both the switch S1 and the diode bridge B1 OFF) nowdetermines the no load operation frequency. The value ofthe input capacitor Cin is chosen to be sufficiently large withrespect to Cs to be neglected with respect to the no loadoperation frequency.

A practical PRPS pre-converter for 250W nett output power(500W peak power) can have component values as shownin Table 2.

Vsw500V/div.

Isw5A/div

S1

D1

Lo Ls

Isw

Io

Vsw

Cb

Cs

IsVb

VsCout

+Eo

0

Cin

+Ep

0

B1

Vs500V/div.

Is5A/div

228


Lo 4 mH 8 x LsLs 500 µHCs 24 nFCb 48 nF 2 x Cs

Table 2 Component Values for PRPS circuit

To be able to put a full wave rectifier across capacitor Cs,the DC voltage blocking capacitor Cb cannot have a valueof several times Cs. Therefore, a value of only twice Cs hasbeen chosen for Cb. This ratio gives good practical resultsin combination with an output voltage, Eo, of 450V.

The parallel L-C circuit consists of series combinations ofLo and Ls and Cb and Cs. The output rectifier bridge nowmodulates the value of the capacitor between 2/3 Cs and2 Cs (Cb and Cs in series and Cb only). It should be notedthat the resonant frequencies of the two states differ by afactor of .

The switch S1 modulates the inductance value of theparallel L-C circuit between Lo + Ls and Ls. This iscombined with a change in input voltage from zero (S1 ON)and Ep (S1 OFF). Again, the PRPS can be seen as aparametric amplifier, but now with both inductance andcapacitance modulation.

In contrast with the SRPS circuit, the output power of aPRPS converter will increase with increasing operationfrequency, thus with decreasing operation cycle time.

Under no load conditions and maximum operation cycletime, the output voltage and current will be near sinusoidaland will have their minimum no load values. This minimumoutput voltage can be calculated from

Substituting the values for Lo, Ls, Cb and Cs in the formulagives

An output voltage choice of Eo = 450 V for Ep = 375 V will,therefore, be amply sufficient.

The voltage Vsw, the current Isw, the output voltage Vs andthe current Is for the maximum operation cycle time, i.e.about equal to Tref, are shown in Fig. 7.

To get an impression of the boosting properties of the PRPScircuit, the no load voltages and currents are shown, for anoperation cycle time Tcycle = 0.975 x Tref, in Fig. 8. It canbe seen that the output voltage has been increased by afactor 2.5 with only a very small decrease of operation cycletime.

Fig. 7 Waveforms of Basic PRPS Circuit(Tcycle = 0.995 x Tref, no load, Ep = 310V)

Finally, the full load voltages and currents are shown in Fig.9 (output power 500W at Eo = 450V and Ep = 310V). Itshould be noted that the operation cycle time has beendecreased to .5694 x Tref.

Vsw500V/div.

Isw5A/div

√3

Vs500V/div.

Vs > Ep.(Lo + Lp)

Lo.

Cb(Cb + Cs)

Is5A/div

Vs > 0.75× Ep

229


The significant feature of the PRPS circuit is that the currentin the main switching device S1 is brought down to zero bythe circuit and not by the device itself. Device S1 can nowbe turned off without loss. The negative voltage whichcauses the current to fall, is supported by diode D1, whichneeds to be a fast recovery type like the BYR79. Thereverse recovery loss in D1 is small because the resonantaction of the circuit make the rate of fall of current relativelyslow - up to two orders of magnitude slower than in astandard SMPS.

SRPS and PRPS compared

A pre-conditioner can be implemented using either anSRPSor PRPStopology. Thecapacitor and inductorvaluesare roughly the same, as are the peak values of voltageand current. The main difference between the circuits is inthe switching requirements of S1 and D1.

In the SRPS, the turn on loss of S1 is very low - the voltageacross S1 is zero and the current rises relatively slowly.However the turn off loss is large - S1 has to turn off a largecurrent and, although the dVsw/dt is moderated by Cp it isstill relatively fast. On the other hand, the turn off loss in D1is negligible - no voltage is applied to the diode until S1 isturned off giving plenty of time for reverse recovery - butthe turn on loss may be significant because the dIsw/dt isun-restrained.

In the PRPS circuit, however, the turn off loss in S1 is closeto zero but the recovery loss in D1 is not negligible - Iswfalls through zero and the negative voltage appears acrossthe diode. S1 is turned on from a high voltage so there willbe some loss in both S1 and D1 even though the rate ofrise of current is moderated by Ls.

It is generally true that reducing turn off loss produces abigger cost/performance benefit than reducing turn on loss.It is also true that losses in diodes are usually much lowerthan in their associated switching device. Since the PRPSconfiguration reduces turn off loss in S1 to zero it appearsthat PRPS is a better choice than SRPS as a resonantpre-converter.

Therefore, the remainder of this paper will concentrate onPRPS circuits.

PRPS transformer for >1kW

The practical PRPS circuits in this paper all use atransformer with a built-in leakage inductance to give mainsisolation and inductance Ls. The inexpensive U-64 core,used in large quantities in the line deflection and EHTcircuits in colour TV sets, can be used successfully as thetransformer core in PRPS converters with a nett outputpower in excess of 1000W.

Fig. 8 Waveforms of Basic PRPS Circuit(Tcycle = 0.975 x Tref, no load, Ep = 310V)

Fig. 10 illustrates a PRPS transformer constructed with apair of U-64 cores. Both the primary and secondarywindings are split into two halves. Each leg of the U-coreis fitted with a two-chamber coil former with a primary anda secondary winding. To achieve a reasonable ’leakage

Vsw500V/div.

Isw5A/div

Vs500V/div.

Is5A/div

230


inductance’ Ls, the primary and secondary coils arecrossed. Thus each U-core has one primary and onesecondary coil.

A pre-converter transformer with this arrangement offersseveral advantages over the ’standard’ SMPS transformerusing E-cores.

s

Fig. 9 Waveforms of Basic PRPS Circuit(Tcycle = 0.5694 x Tref, 500W output, Ep = 310V)

- It will be easier to meet the mains isolation requirements,particularly with respect to creepage distances.

- The thermal properties will be much better because thewinding is distributed over both core legs.

- The mean length of a turn is less than with a single coreleg, reducing copper loss.

- The two leg arrangement will need only 70% of the turnsof the one leg design. This is because of the active(magnetic) fluxing of both legs.

- It is a simpler and hence less expensive transformer towind.

One disadvantage of this arrangement is that the windingsare not layered. This means that ’skin effect’ will have to beovercome by using Litz wire for both the primary andsecondary windings.

a) Cross Section

b) Winding connection

Fig. 10 PRPS transformer using U-64 cores

Vsw500V/div.

Isw5A/div

U64 core 3C8

U64 core 3C8

P1

P2S1

S2

airgap

Vs500V/div.

S1

P1

In

In

P2

S2

Out

Out

Is5A/div

231


The equivalent electrical circuit diagram of the PRPStransformer is given in Fig. 11. It is the well known ’Tee’circuit with primary winding(s) leakage inductance Llp, amagnetisation inductance Lm and secondary winding(s)leakage inductance Lls, followed by an ’ideal’ transformerfor the output voltage transformation.

Fig. 11 PRPS transformer equivalent circuit

The primary and secondary leakage inductance isdetermined by the transformer construction and, inparticular, by the positioning of the windings. In thesymmetrical arrangement of Fig. 10, the values of Llp andLls will be equal. Llp and Lls are also proportional to thesquare of the number of primary turns as is Lm. However,Lm is also strongly dependent on the width of the ’airgap’between the two U-cores. The airgap can be adjusted togive a value of Lm between 2 and 100 times Llp+Lls.

The transformer can be characterised by two inductancemeasurements:

- Lx, the measured primary inductance with the secondarywinding(s) shorted.

- Ly, the measured primary inductance with the secondarywinding(s) open circuit

It can be seen from the equivalent circuit diagram that,

If the transformer is assumed to be symmetrical then,

rearranging gives,

If the airgap is <50µm then Lm will be at least 100 timesthe value of Llp or Lls. In this case,

and

Fig. 12 PRPS pre-converter for 250V output

A PRPS pre-converter transformer for 1250W nett outputhas been constructed to the arrangement shown in Fig. 10.It had a primary consisting of two 36 turn windingsconnected in series, wound using 600 x 0.07mm Litz wire.The number of turns on the secondary varied dependingon the required output voltage. Measurements of thistransformer gave the following values for Lx and Ly.

Lx = 200 µH

Ly = 1600 µH (Note that this value is strongly influenced bythe size of the airgap)

PRPS pre-converter for high outputvoltagesThe circuit shown in Fig. 12 is a PRPS pre-converter usingthe type of transformer mentioned earlier. This circuit isintended to deliver 1250W at a relatively high voltage - inthis case 250V. To achieve an final output voltage of 250Vwith an effective output voltage, Eo, of 450V means havinga transformer with a turns ratio of 8:5.

Cf1 2µF 2 x 1µFCin 2µF 2 x 1µFCb1 0.2µF 2 x 0.1µFCb2 1.36µF 2 x 0.68µFCs 0.3µF 2 x 0.15µFLf 1600µHLo 1600µHLx 200µHLy 1600µH

Table 3 Component Values for High Output VoltagePRPS circuit

The transformer has replaced the inductance Ls in the basiccircuit diagram of Fig. 6. The DC voltage blocking capacitorCb has been split up into a primary blocking capacitor Cb1and a secondary blocking capacitor Cb2. There will,therefore, be no DC current in Tr1 so in principle thetransformerdoes not need an air gap. However, experience

Lx ≈ Llp + Lls

Ly ≈ Lm

S1

D1

Lo

Isw

Io

Vsw

Cb1

Cs

Vb1

Cout

+Eo

0

Cin

Cb2

Vb2

Ipr

Cf1

Lf

Isec

B1

Llp Lls

Lm

ideal

In Out

Lx = Llp +Lm.Lls

Lm + Lls

Ly = Llp + Lm

Llp = Lls

Llp = Ly − √Ly2 − Lx.Ly

Lm = √Ly2 − Lx.Ly

232


Fig. 13 Waveforms of high voltage pre-converter(Tcycle=0.7446 x Tref, 2.5kW output, Ep=310V)

has shown that a limited value of magnetisation inductanceimproves the operation of the circuit, so an airgap has beenincluded which keeps the Ly value, of Tr1, equal to Lo.

The pre-converter circuit has been completed by theaddition of capacitor Cf1, rectifier bridge and filter inductorLf (an iron cored choke). The combination of Cf1, Lf, Cinand Lo prevents a significant switching frequency signalappearing at the mains terminals.

The component values shown in table 3 are used in thecircuit of Fig. 12. With these values the no load referencecycle time will be 49.7 µs. Therefore, the no load operatingfrequency is just over 20 kHz.

Figs. 13 and 14 show the waveforms associated with thecircuit when the input voltage is 310 V and the circuit isdelivering 2.5 kW

Ep Pout Pout % Deviation(PRPS) (R load)

310.0 2501 2501 0.0%308.3 2476 2474 0.1%303.2 2389 2392 -0.1%294.8 2249 2262 -0.6%283.2 2068 2087 -0.9%268.5 1857 1876 -1.0%250.8 1621 1637 -1.0%230.4 1375 1382 -0.5%207.4 1128 1119 0.8%182.2 890 864 3.0%155.0 668 625 6.8%126.1 472 414 14.1%95.8 305 239 27.7%64.5 171 108 57.9%32.4 70 27 156.2%

Table 4 Output power of PRPS pre-converter.

Of particular interest is Iobecause it canbe easily measuredwith a low value resistor. This current will be used to controlpower output of the PRPS pre-converter. Io will becompared with a reference, Ioref, which will be proportionalto input voltage Ep. The comparison of Io and Ioref shouldbe done at the right time, namely during the period whenIo has a negative slope. The switch S1 is turned ON assoon as the value of Io drops below Ioref.

The computed values of Pout for 15 values of Ep whichwould be achieved using this control strategy are given inTable 4. As a comparison the output power for a resistiveload is also shown in Table 4.

It can be seen from Table 4, that the PRPS output powerclosely matches the power of a purely resistive load exceptfor Ep values near the zero crossings of the mains/linevoltage.

Of course, an average output power control loop (with atime constant far in excess of the 10 (8.3) ms cycle time ofa half mains/line period) is required to determine the

Vsw500V/div.

Isw10A/div

Vs500V/div.

Isec15A/div

233


Fig. 14 Waveforms of high voltage pre-converter(Tcycle=0.7446 x Tref, 2.5kW output, Ep=310V)

proportionality constantbetween the mains/line voltageandIoref for the mains/line voltage variations and for the outputpower control.

It can also be concluded, from table 4, that the PRPS circuitcan indeed fulfil the pre-converter action successfully, i.e.a resistive load for the mains voltage can be easilyachieved, thus no mains distortion and a power factor >0.99is possible.

The circuit shown in Fig. 12 is only suitable for high outputvoltages. At low output voltages (below 100V for outputpowers in excess of 1000W), the secondary blockingcapacitor Cb2 has to have a high value and pass a largecurrent and is, therefore, an expensive component. If a lowoutput voltage pre-converter is required, then an alternativearrangement is needed.

PRPS pre-converter for low outputvoltagesThe high cost of Cb2, in a low output voltage PRPSpre-converter, could be avoided if it could be eliminatedfrom the circuit. The problem is that removing Cb2 allowsa DC current to flow in the transformer. The resulting fluxcan be handled by increasing the airgap between the coresof the transformer. This will have the additional effect ofreducing Ly from 1600 µH to 800 µH. This change has beenincorporated in the circuit shown in Fig. 15, which isintended to deliver 1200W at 60V.

Fig. 15 PRPS pre-converter for 60V output

To get 1200W nett from a transformer of the type shown inFig. 10 it is necessary to change the number of primaryturns Np and thus decrease the value of Lx. Suitable valueswould be:

Np (primary turns) 2 x 28 (600 x .07 mm Litz wire)

Ns (secondary turns) 2 x 4 (flat Litz wire 7 mm2)

The air gap in the transformer should be adjusted to givean Lx of 125 µH.

Suitable values for the other components are given in table5. The reference cycle time, Tref, with these values will be39 µs.

The inductance Lo can be made with either a pair of U-64cores - with the winding distributed over both legs- or witha pair of E-cores.

Vb1500V/div.

Ipr10A/div

Vb2500V/div.

S1

D1

Lo

Isw

Io

Vsw

Cb1

Cs

Vb1

Cout

+Eo

0

Cin

Ipr

Cf1

Lf

Isec

B1

Io10A/div

234


Cf1 2µF 2 x 1µFCin 2µF 2 x 1µFCb1 0.15µFCs 3.75µF 5 x 0.75µFLf 1600µHLo 1600µH

Table 5 Component Values for Low Output VoltagePRPS circuit

In practice, PRPS pre-converters produce about 150W foreach Amp(rms) flowing in the primary winding. So for a1200W converter:

Ipr = 8AIsec = 56A (at 60V and 20A)

The voltage and current wave forms for the circuit of Fig.15 are similar to those shown in Figs. 13 and 14, except forthe amplitudes in the secondary side.

This configuration of PRPS pre-converter is viable foroutput voltages as low as 40 V. Below this, however, thevalue and current rating of Cs becomes excessive and it islikely that alternative configurations would be more costeffective.

Control circuit for PRPS convertersFigure 16 shows a simple control circuit for PRPSconverters. In is constructed from MOS ICs and standardcomparators. The analogue control section for the outputpower stabilisation is not shown because it will, in principle,be no different than for an SMPS converter.

The PRPS control circuit comprises of a dual sawtoothoscillator whose frequency can be adjusted by applying avoltage to X1. The output of this oscillator is fed to the clockpulse input of a divide-by-8 counter. The highest oscillatorfrequency needs to be just over 8x the highest expectedoperating frequency of the PRPS power section.

The oscillator can be stopped by applying a hold up signal(low) to G1. This hold-up input is used to modulate the cycletime of the control circuit. As soon as this ’hold up’ signalis removed (high), a pulse will sent to the divide-by-8 circuitwhich then advances one position.

The counter has 8 outputs, Q0-Q7. Output Q0 will go higheither synchronously following Q7 or asynchronously witha high on pin15. Output Q0 sets a flip-flop consisting of a2and a 3 input NOR-gate. The output terminal X8 then goeshigh to indicate that the main switching device S1 shouldturn on.

Fig. 16 PRPS control circuit

-

+

-

+

-

+

-

+

-

+

-

+

+

+

+

++

+

+

+

+

+

+

+X2

X3

X4

X5

X6

X1

X8

X7

HEF4022B13

14

15

Q7 Q5Q0

G1

G2

G3

G4

G5

G6

G7

-

+

-

+

235


The Q7 output is used to enable both the ’hold-up’ signalfor the oscillator and the reset input for the divide-by-8, i.e.both the ’hold-up’ and the reset only can be active if thereis a ’1’ at Q7. The output flip-flop is reset either by thenegative voltage across S1-D1 - via comparator G3 - or bythe sixth position, Q5, of the counter. To prevent thepossibility of immediate reset of the flip-flop, the indicationof negative voltage across S1-D1 is blanked out while Q0is high.

The voltage across S1-D1 is connected to terminal X6 viaa high value resistor (220 kΩ). X4 is connected to thenegative supply line of the power circuit. Comparator G3then gives logical information about the polarity of thevoltage across S1-D1.

Information about the amplitude of this voltage is obtainedvia comparator G4. A reference voltage, proportional to themains voltage, is connected to X5. If the attenuated S1-D1voltage falls below this reference, and Q7 is high, thecounter will be reset and S1 will be turned ON. This is anemergency measure in case the normal current control loopvia the comparator G2 fails to disable the ’hold up’ signal.This could occur if there were a false current referencesignal at X2.

The best strategy for the control of a PRPS pre-converteris by comparing the current, Io, in the input inductor, Lo,with a mains proportional reference current. In Fig. 16 asignal, proportional to Io, is connected to X3 and thereference signal to X2. As soon as Io falls below thereference value the ’hold-up’ signal is removed, the counteris advanced from Q7 to Q0 and S1 is turned ON.

A ’1’ at input X7 allows the control circuit to run, whereas a’0’ will cause the PRPS to switch OFF in a controlledmanner. When X7 goes high, the output of NAND gate G7goes low. This signal is used to reset the counter whichtakes Q0 high, turns on S1 and starts the operating cycle.The output of G5, which was pulled high while the circuitwas stopped, is now driven low and is kept low by the RCnetwork as long as S1 continues to be switched. This ’low’keeps the output of G7 high and allows the correct signalto be fed from G4 to the counter reset. The high on X7 alsoenables G6 and lets the information from G2 - the ’current’comparator - through to the ’hold up’ circuit.

If X7 is taken low then G6 is disabled and the signal whichwould start the next switching cycle is not allowed to getthrough. The counter will continue to run until Q7 goes highat which time the circuit will be ’held up’ and the operatingcycle will be halted.

The cycle time will be adjusted by changing the referencevalue at X2. This signal will be a series of half sinewaveswhose peak value is proportional to the power that thepre-converter needs to deliver to the keep the output

voltage at the required level. This control strategy has beentested on various PRPS circuits and fulfils all therequirements properly.

Modelling PRPS pre-convertersThere are no equations which summarise the overallbehaviour of a PRPS pre-converter circuit. Determiningfactors like the throughput power of the circuit and the peakvoltages and currents, means developing a computermodel. In this model the operation of the circuit is brokendown into its separate modesand the appropriateequationsderived for each of them.

The circuit of Fig. 6 has, basically, two switches whichdetermine its mode of operation. The first is the combinationofS1 and D1- this is the controllableswitch - and the secondis the bridge rectifier B1.

Therefore the circuit has four different modes of operation.For all these modes, the time functions for the currents andvoltages can be derived by circuit analysis. The four modesare given below:

Mode S1-D1 Bridge

I ON ONII ON OFFIII OFF OFFIV OFF ON

Table 6 PRPS Operating Modes

Using Laplace transformation it is possible to derive thetime functions for currents Io and Is, for the circuit in eachof its 4 modes. This method allows the initial values of thecurrents and voltages to be easily introduced into theequations. The initial conditions of Io, Is, Vb1 and Vs willbe indicated by Jo, Js, Ub1 and Us respectively.

Mode IWe will start with the derivation of the time functions for theoperation of the PRPS circuit in mode I (S1-D1 ON and B1ON). The initial conditions are:

Calculation starts at t = 0 with the switching ON of S1-D1,while B1 is already conducting, i.e. . The followingLaplace equations are then valid:

Io = Jo

Is = Js = −Jo

Vb1 = Ub1

Vs = Us = Eo

Jo > 0

Eps

+ Lo.Jo = Io .s.Lo

236


Note: B1 is conducting, so , i.e. Cs is infinitelylarge and has no influence on Is.

If we define the following:

The Laplace equations for Io and Is can then be written as:

The inverse Laplace transformation of these two equationsgives the following time functions:

To calculate the input power and the voltage Vb1 and Vs,these time functions can be integrated to give Ioint and Isint,thus:

The input power during the validity of mode I (i.e. during atime interval of length T1) is equal to:

The voltages Vb1 and Vs are equal to:

In the computer program, these formulae will be stored ina subroutine called sub1.

Mode IIThe initial conditions for mode II operation (S1-D1 ON andB1 OFF) are:

(either +Eo or -Eo)

The Laplace equations for Io and Is are now:

Define:

The Laplace functions for Io and Is are now identical tothose for mode I, so the time functions are:.


Ub1 + Uss

+ Ls.Js = Is.s.Ls +

1s.Cb1

Vs = Us = Eo

Io = Jo

Is = Js

ω = √1Ls.Cb1

Vb1 = Ub1

Vs = UsF1 = Jo

F2 =EpLo Ep

s+ Lo.Jo = Io .s.Lo

G1 = Js

(Ub1 + Us).s + Ls.Js = Is.s.Ls +

Cb1+ Css.Cb1.Cs

G2 =

Ub1 + UsLs

ω = √Cb1+ CsLs.Cb1.CsIo =

F1s

+F2

s2

F1 = JoIs =

G1.ss2 + ω2

+G2

s2 + ω2

F2 =EpLo

G1 = Js

Io = F1 + F2.tG2 =

Ub1 + UsLs

Is = G1.cos(ω.t) +G2ω

.sin(ω.t)

Io = F1 + F2.t


.sin(ω.t)Ioint = F1.t +F22

.t2

Ioint = F1.t +F22

.t2Isint =

G1ω

.sin(ω.t) +G2

ω2.(1− cos(ω.t))

Isint =G1ω

.sin(ω.t) +G2

ω2.(1− cos(ω.t))

Pin(T1) =Ep.Ioint

T1 Pin(T2) =Ep.Ioint

T2

Vb1 = Ub1 −IsintCb1


Vs = Us −IsintCsVs = Us = Eo

237


Mode IIIThe initial conditions for mode III operation (S1-D1 OFFand B1 OFF) are:

The correct Laplace equation for Is ( ) can beexpressed by the relationship:

Define:

The time functions can then be expressed by:


Mode IVThe initial conditions for the mode IV operation (S1-D1 OFFand B1 ON) are given below:

The Laplace equation for current Is is now:

Define:

The time functions are given by,


Program structureThe modelling program can be written around the foursubroutines. The central part of the program will makesuccessive calls to the appropriate subroutine. Thecalculated values of current and voltage will be used todetermine when the circuit moves form one mode to thenext. The final values of Io, Is, Vb1 and Vs will be used asthe initial values, Jo, Js, Ub1 and Us, for the next mode.The actual sequence of the modes depends upon theoperating frequency and load condition. Under full loadcondition when Ep is not close to zero, the sequence ofmodes will be as shown in Table 7.

One cycle of operation ends when Io falls below Ioref. Thiswould result in S1 being turned ON, putting the circuit in tomode I and starting the cycle once more. At the end of eachcycle, the input power can be compared with a referencevalue (Pref) and Ioref can be adjusted until the powers areequal. It is then possible to read various important values

Vs = Us = Eo

Ub1 + Us − Eps

+ (Lo + Ls).Js = Is.s.(Lo + Ls) +

1(s.Cb1)

Io = Jo

Is = Js = −Jo

Vb1 = Ub1ω = √1(Lo + Ls).Cb1Vs = Us

G1 = JsIo = −Is

G2 =Ub1 + Us − Ep

Lo + LsUb1 + Us − Eps

+ (Lo + Ls).Js = Is.s.(Lo + Ls) +

Cb1+ Css.Cb1.Cs


.sin(ω.t)ω = √Cb1+ Cs

(Lo + Ls).Cb1.CsIo = −Is

G1 = JsIsint =

G1ω

.sin(ω.t) +G2

ω2.(1− cos(ω.t))

G2 =Ub1 + Us − Ep

Lo + LsIoint = Isint

Pin(T4) =Ep.Ioint

T4Is = G1.cos(ω.t) +G2ω

.sin(ω.t)


Io = −Is

Isint =G1ω

.sin(ω.t) +G2

ω2.(1− cos(ω.t)) Vs = Us

Ioint = Isint

Pin(T3) =Ep.Ioint

T3


Vs = Us −IsintCs

Io = Jo

Is = Js = −Jo

Vb1 = Ub1

238


S1-D1 B1 Mode End Condition

ON ON I Is>0ON OFF II Vs<-EoON ON I Is<0ON OFF II Isw=Io+Is<0OFF OFF III Vs>EoOFF ON IV Io<Ioref

Table 7 PRPS Operating Sequence

such as the initial conditions for Io, Is, Vb1, Vs, the cycletime, output power, RMS values of Io and Is, DC and ACfluxes in the ferrite cores, etc.

Writing a program like this is well within the capabilities ofanyone with some experience of programming. Thecalculations involved are so simple that there will be littledifficulty in using almost any programming language. Amodel produced in this way will be faster and more accuratethan could be produced with any of the standard modellingprograms.

ConclusionsThe PRPS configuration is well suited to the needs of thepre-converter application. It can boost the low mainsvoltages, near zero crossing, to high levels so that somepower is delivered to the load throughout all of the mainscycle. This helps the PRPS appear as a resistive load tothe mains.

A PRPS pre-converter can deliver a DC output voltage withlow levels of mains ripple using only moderately sized

output smoothing capacitors. The addition of a highfrequency transformer gives mains isolation and the abilityto have a wide range of output voltages.

The transformer need not be a major additional cost. Thehigh operating frequency means the transformer usesferrite core and is relatively small (5% of the size of copper/ iron transformer). A side by side arrangement of thewindings means the transformer is easy to wind, easy toinsulate and can have the right leakage inductance toreplace the resonant network inductor.

The resonant action of the PRPS circuit allows the mainsemiconductor switching device to be turned off at zerocurrent. This reduces, considerably, the switching loss ofthis device allowing a smaller device to be used in higherpower / frequency circuits than it could normally resultingin a significant cost saving.

Unfortunately an overall analysis of the performance of aPRPS pre-converter is difficult. However, by breaking thecycle of operation into its logical modes, it becomes easyto generate the time functions for all the currents andvoltages. It is simple to incorporate these equations into acomputer program to produce an accurate, detailed andfast running model of the system.

The use of pre-converters is become increasinglynecessary and the characteristics of PRPS circuits meanthat there are well suited to this function. It is easy toovercome the apparent complexity of resonant systems toproduce PRPS pre-converters which are elegant, efficientand cost effective.

239

Motor Control Power Semiconductor ApplicationsPhilips Semiconductors

CHAPTER 3

Motor Control

3.1 AC Motor Control

3.2 DC Motor Control

3.3 Stepper Motor Control

241


AC Motor Control

243


3.1.1 Noiseless A.C. Motor Control: Introduction to a 20 kHzSystem

Controlling an a.c. induction motor by the technique ofsinewave-weighted pulse-width modulation (PWM)switching gives the benefitsof smooth torqueat low speeds,andalso complete speedcontrol fromzero upto the nominalrated speed of the motor, with only small additional motorlosses.

Traditional power switches such as thyristors needswitching frequencies in the audible range, typicallybetween 400 and 1500Hz. In industrial environments, thesmall amount of acoustic noise produced by the motor withthis type of control can be regarded as insignificant. Bycontrast, however, the same amount of noise in a domesticor office application, such as speed control of a ventilationfan, might prove to be unacceptable.

Now, however, with the advent of power MOSFETs,three-phase PWM inverters operating at ultrasonicfrequencies can be designed. A three-phase motor usuallymakes even less noise when being driven from such asystem than when being run directly from the mainsbecause the PWM synthesis generates a purer sinewavethan is normally obtainable from the mains.

The carrier frequency is generally about 20kHz and so it isfar removed from the modulation frequency, which istypically less than 50Hz, making it economic to use alow-pass filter between the inverter and the motor. Byremoving the carrier frequency and its sidebands andharmonics, the waveform delivered via the motor leads canbe made almost perfectly sinusoidal. RFI radiated by themotor leads, or conducted by the winding-to-framecapacitance of the motor, is therefore almost entirelyeliminated. Furthermore, because of the high carrierfrequency, it is possible to drive motors which are designedfor frequencies higher than the mains, such as 400Hzaircraft motors.

This section describes a three-phase a.c. motor controlsystem which is powered from the single-phase a.c. mains.It is capable of controlling a motor with up to 1kW of shaftoutput power. Before details are given, the generalprinciples of PWM motor control are outlined.

Principles of Pulse-Width ModulationPulse-width modulation (PWM) is the technique of usingswitching devices to produce the effect of a continuouslyvarying analogue signal; this PWM conversion generallyhas very high electrical efficiency. In controlling either athree-phase synchronous motor or a three-phase inductionmotor it is desirable to create three perfectly sinusoidalcurrent waveforms in the motor windings, with relativephase displacements of 120˚. The production of sinewave

power via a linear amplifier system would have lowefficiency, at best 64%. If instead of the linear circuitry, fastelectronic switching devices are used, then the efficiencycan be greater than 95%, depending on the characteristicsof the semiconductor power switch.

Fig.1 Half-bridge switching circuit

Fig.2 Waveforms in PWM inverter(a) Unmodulated carrier

(b) Modulated carrier(c) Current in inductive load

The half-bridge switching circuit in Fig.1 is given as anexample: the switches can be any suitable switchingsemiconductors. If these two switches are turned onalternately for equal times, then the voltage waveformacross the load is as shown in Fig.2a. The mean value ofthis waveform, averaged over one switching cycle is 0. Thissquare wave with a constant 50% duty ratio is known asthe ’carrier’ frequency. The waveform in Fig.2b shows theeffect of a slow variation or ’modulation’ of the duty ratio;the mean voltage varies with the duty ratio. The waveformof the resultant load current depends on the impedance ofthe load Z. If Z is mainly resistive, then the waveform of thecurrent will closely follow that of the modulated squarewave. If, however, Z is largely inductive, as with a motorwinding or a filter choke, then the switching square wave

V/2

V/2

+

+

Z

-V/2

V/2

0

0

-V/2

V/2

0

I

(a)

(b)

(c)

245


will be integrated by the inductor. The result is a load currentwaveform that depends mainly on the modulation of theduty ratio.

If the duty ratio is varied sinusoidally in time, then the currentin an inductive load has the form of a sinewave at themodulation frequency, lagging in phase, and carrying rippleat the switching frequency as shown in Fig.2c. Theamplitude of the current can be adjusted by controlling thedepth of modulation, that is, the deviation of the duty ratiofrom 50%. For example, a sinewave PWM signal whichvaries from 5% to 95%, giving 90% modulation, will producea current nine times greater than that produced by a signalwhich varies only from 45% to 55%, giving only 10%modulation.

For three-phase a.c. motor control, three such waveformsare required,necessitating threepairs ofswitches like thoseshown in Fig. 1, connected in a three-phase bridge. Theinductance required to integrate the waveform can usuallybe provided by the inductance of the stator windings of themotor, although in some instances it might be provided bythe inductance of a separate low-pass filter. Themodulations in the three switching waveforms must bemaintained at a constant relative phase difference of 120˚,so as to maintain motor current sinewaves which arethemselves at a constant 120˚ phase difference. Themodulation depth must be varied with the modulationfrequency so as to keep the magnetic flux in the motor atapproximately the design level.

In practice, the frequency of the modulation is usuallybetween zero and 50Hz. The switching frequency dependson the type of power device that is to be used: until recently,the only devices available were power thyristors or therelatively slow bipolar transistors, and therefore theswitching frequency was limited to a maximum of about 1

kHz. With thyristors, this frequency limit was set by theneed to provide forced commutation of the thyristor by anexternal commutation circuit using an additional thyristor,adiode, a capacitor, and an inductor, in a process that takesat least 40µs. With transistors, the switching frequency waslimited by their switching frequency and their long storagetimes.

In this earlier type of control circuit, therefore, the ratio ofcarrier frequency to modulation frequency was only about20:1. Under these conditions the exact duty-ratios andcarrier frequencies had to be selected so as to avoid allsub-harmonic torques, that is, torque components atfrequencies lower than the modulation frequency. This wasdone by synchronising the carrier to a selected multiple ofthe fundamental frequency; the HEF4752V, an excellentIC purpose-designed for a.c. motor control, uses thisparticular approach. The 1kHz technique is still extremelyuseful for control of large motors because whenever shaftoutput powers of more than a few kW are required,three-phase mains input must be used, and there are, asyet, few available switching devices with combined highvoltage rating, current rating, and switching speed.

However, using MOSFETs with switching times of muchless than 1µs, the carrier frequency can be raised to theultrasonic region, that is, to 20kHz or more. There areobvious system benefits with this higher frequency, butthere are also several aspects of PWM waveformgeneration that become easier. It is possible to use a fixedcarrier frequency because the sub-harmonics that areproduced as a result of the non-synchronisation of thecarrier frequency with a multiple of the fundamental areinsignificant when the ratio of the carrier frequency to thefundamental frequency is typically about 400:1.

Fig.3 20kHz AC motor controller

246


To maintain good waveform balance, and thus avoid anyd.c. in the motor, and therefore also avoid parasitic torques,adigital waveform generation technique is appropriate. Thewaveform can be stored as a ’look-up’ table of numbersrepresenting the sinewave. To generate the three phases,this table can be read at three points that have the correct120˚ phase relationship. The numbers taken from the tablerepresent the duty ratios corresponding to 100%modulation: these numbers can then be scaled down bymultiplication or some equivalent technique to give thecorrect duty-ratio numbers for the modulation depthrequired.

The speed of the motor is controlled by the rate at whichthe reading pointers scan the look-up table and this can beas slow as desired. If the pointers are stationary, then thesystem will be ’frozen’ at a particular point on thethree-phase sinewave waveform, giving the possibility ofobtaining static torque from a synchronous motor at zerospeed. The rate at which the numbers are produced by thisread-out process from the look-up table is constant anddetermines the carrier frequency.

To convert these three simultaneous parallel digitalnumbers into time lengths for pulses, three digital countersare needed. The counters can be designed to givedouble-edged modulation, such that both the leading edgeand the trailing edge of each pulse move with respect tothe unmodulated carrier. The line-to-line voltage across theload will have most of its ripple at a frequency of twice theswitching frequency, and will have a spectrum with

minimum even harmonics and no significant componentbelow twice the switching frequency. Motor ripple currentis therefore low and motor losses are reduced.

There is a further advantage to be obtained from the highratio of carrier to modulation frequency: by adding a smallamount of modulation at the third harmonic frequency ofthe basic fundamental modulation frequency, the maximumline-to-line output voltage obtainable from the inverter canbe increased, for the following reason. The effect of the thirdharmonic on the output voltage of each phase is to flattenthe top of the waveform, thus allowing a higher amplitudeof fundamental while still reaching a peak modulation of100%. When the difference voltage between any twophases is measured, the third harmonic terms cancel,leavinga pure sinewave at the fundamental frequency. Thisallows the inverter output to deliver the same voltage as themains input without any significant distortion, and thus toreduce insertion losses to virtually zero.

Overview of a practical systemThe principles outlined above are applied to a typicalsystem shown in Fig.3. The incoming a.c. mains is rectifiedand smoothed to produce about 300V and this is fed to thethree-phase inverter via a current-sensing circuit. Theinverter chops the d.c. to give 300V peak-to-peak PWMwaves at 20kHz, each having low-frequency modulation ofits mark-space ratio. The output of the inverter is filtered toremove the 20kHz carrier frequency, and the resultantsinewaves are fed to the a.c. motor.

Fig.4 Waveform generator circuit

247


The six switches in the inverter are under the command ofa waveform-generation circuit which determines theconduction time of each switch. Because the controlterminals of the six switches are not at the same potential,the outputs of the waveform-generation circuits must beisolated and buffered. A low-voltage power supply feedsthe signal processing circuit, and a further low-voltagepower supply drives a switch-mode isolating stage toprovide floating power supplies to the gate drive circuits.

Signal processing

Fig.4 shows a block diagram of the circuit which generatesthe PWM control signals for the inverter. The input to thesystem is a speed-demand voltage and this is also usedfor setting the required direction of rotation: the analoguespeed signal is then separated from the digital directionsignal. The speed-demand voltage sets the frequency ofthe voltage-controlled oscillator (VCO). Information todetermine the modulation depth is derived from thespeed-control signal by a simple non-linear circuit and isthen converted by an analogue-to-digital converter into an8-bit parallel digital signal.

A dedicated IC, type MAB8051, receives the clock signalsfrom the VCO, the modulation-depth control number fromthe A/D converter, the direction-control logic signal, andlogic inputs from the ’RUN’ and ’STOP’ switches. Byapplying digital multiplication processes to internal look-uptable values, the microcomputer calculates the ’on-time’ foreach of the six power switches, and this process is repeatedat regular intervals of 50µs, giving a carrier frequency of20kHz. The pulses from the VCO are used for incrementingthe pointers of the look-up table in the microcomputer, andthus control the motor speed.

The output signals of the microcomputer are in the form ofthree 8-bit parallel numbers: each representing theduty-ratio for the next 50µs switching cycle for one pair ofinverter switches, on a scale which represents 0% to 100%on-time for the upper switch and therefore also 100% to 0%on-time for the complementary lower switch. A dedicatedlogic circuit applies these three numbers from themicrocomputer to digital counters and converts eachnumber to a pair of pulse-widths. The two signals producedfor each phase are complementary except for a small’underlap’ delay. This delay is necessary to ensure that theswitch being turned off recovers its blocking voltage beforeits partner is turned on, thus preventing ’shoot-through’.

Fig.5 DC link, low voltage and floating power supplies

248


Other inputs to the microcomputer are the on/off switches,the motor direction logic signal, and the current-sensingsignal. Each input triggers a processor interrupt, causingthe appropriate action to be taken. The STOP switch andthe overcurrent sense signals have the same effect, that ofcausing the microcomputer to instructall six power switchesin the inverter to turn off. The RUN switch causes themicrocomputer to start producing output pulses. Anychange in the direction signal first stops the microcomputerwhich then determines the new direction of rotation andadjusts its output phase rotation accordingly.

D.C. link and power supplies

The d.c. link and the low-voltage power supplies for thesystem are shown in Fig.5. The high voltage d.c. supply forthe inverter is derived from a mains-fed bridge rectifier witha smoothing capacitor; the capacitor conducts both the100Hz ripple fromthe rectified single-phasemains, andalsothe inverter switching ripple. A resistor, or alternatively athermistor, limits the peak current in the rectifier while thecapacitor is being charged initially. This resistor is shortedout by a relay after a time delay, so that the resistor doesnot dissipate power while the motor is running. As a safetymeasure, a second resistor discharges the d.c. linkcapacitor when the mains current is removed.

Oneof the d.c. link lines carriesa low-value resistor to sensethe d.c. link current. A simple opto-isolation circuit transmitsa d.c. link current overload signal back to the signalprocessing circuit.

The logic circuitry of the waveform generator is poweredconventionally by a 50Hz mains transformer, bridgerectifier, and smoothing capacitor. The transformer has twosecondary windings; the second one provides power to aswitched-mode power supply (SMPS), in which there is aswitching transistor driven at about 60kHz to switch powerthrough isolating transformers. Rectifying the a.c. outputsfrom the isolating transformers provides floating powersupplies for the inverter gate drive circuits. As will be seenbelow, one supply is needed for the three ’lower’ powerswitches (connected to a common d.c. link negative line),but three separate power supplies are needed for the three’upper’ switches (connected to the three inverter outputs).Thus four isolating transformers are required for the gatesupply circuits. For low power systems the gate suppliescan be derived directly from the d.c. link without excessiveloss.

To prevent spurious turn-on of any inverter switch duringthe start-up process, the floating power supply to the lowerthree gate-drive circuits is connected only after a delay. Thesame delay is used for this as is used for the d.c. linkcharging-resistor bypass switch.

Fig.6 Signal isolation, gate drive, inverter and filter (one phase of three)

15 V

HEF40097

2k22k2

10T 20T

47 pF18 k

1 k c18v

100R

FX3848

8 uF2n2

15 V

HEF40097

2k22k2

10T 20T

47 pF18 k

1 k c18v

100R

FX3848

8 uF2n2

249


Signal isolation, gate drive, and inverterThe most important part of the system is the power inverterand it is the use of MOSFETs, with their short switchingtimes, which makes it possible for the inverter to switch at20kHz. It is in the area of the drive circuits to the powerswitches that using MOSFETs gives a saving in the numberof components needed. Driving MOSFETs is relativelyeasy: the total power needed is very small because all thatmust be provided is the capability to charge and dischargethe gate-source capacitance (typically between 1 and 2nF)by a few volts in a short time (less than 100ns). This ensuresthat the quality of the waveform is not degraded, and thatswitching losses are minimised.

In this circuit the six pulse outputs from the dedicated logicpart of the waveform generator section are coupled to theMOSFET gate driver stages via pulse transformers. (seeFig.6). Each gate drive circuit is powered from one of thefour floating power supplies described above. The three’lower’ stages share a common power supply, as the sourceterminals of the three ’lower’ MOSFETs are all at the samepotential. Each of the three ’upper’ stages has its ownfloating power supply. The isolated signals are coupled tothe gate terminals of the six MOSFETs by small amplifierscapable of delivering a few amperes peak current for a shorttime. Alternative gate driver circuits may use level shiftingdevices or opto-couplers. (Refer to "Power MOSFET GateDrive Circuits" for further details.)

It will be seen from Fig.6 that each MOSFET has twoassociated diodes. These are necessary because theMOSFETs have built-in anti-parallel diodes with relativelylong reverse-recovery times. If these internal diodes wereallowed to conduct, then whenever load currentcommutated from a diode to the opposite MOSFET, a largecurrent would be drawn from the d.c. supply for the durationof the diode reverse-recovery time. This would greatlyincrease the dissipation in the inverter. To avoid this, anexternal fast epitaxial diode is connected in anti-parallelwith the MOSFET. Because the internal diode of theMOSFET has a very low forward voltage drop, a secondlow-voltageepitaxial diode must be connected inseries witheach MOSFET to prevent the internal diode fromconducting at all. Thus, whenever the MOSFET isreverse-biased, it is the external anti-parallel diode whichconducts, rather than the internal one. FREDFETs haveinternal diodes which are much faster than those ofMOSFETs, opening the way for a further cost-saving byomitting the twelve diodes from the 3-phase inverter.

Output low-pass filterFor conventional, lower frequency inverters the size, weightand cost of output filter stages has held back theirproliferation. An advantage of the constant high carrierfrequency is that a small, economical low-pass filter can bedesigned to remove the carrier from the inverter output

waveform. Compared with low frequency systems the filtercomponent has been reduced by an order of magnitude,and can often be eliminated completely. In unfilteredsystems cable screening becomes an important issuealthough on balance the increased cost of screening is lessthan the cost and weight of filter components.

A typical filter arrangement was shown in Fig.6. As anexample, for a 50Hz motor-drive the filter would bedesigned with a corner-frequency of 100Hz, so that theattenuation at 20kHz would be about 46dB. The carrierfrequency component superimposed on the outputsinewave would therefore be only a few mV in 200Vrms.Fig.7 shows the relative spectral characteristics of differenttypes of inverter switching strategies.

Fig.7 Spectral characteristics for different inverterswitching strategies

(a) Quasi-square(b) 1kHz, 15 pulse, Synchronous

(c) 20kHz, Non-synchronous

There are two main advantages in supplying the motor withpure sinewave power. First, the motor losses are small,because there is no rms motor current at the switchingfrequency, and second, there is less radio-frequencyinterference(RFI), because the switching frequency currentcomponents circulate entirely within the inverter and filterand do not reach the outside world.

Advantages of a 20 kHz systemThe principal advantages of the system described here are:

-Controller and motor are acoustically quiet.-PWM waveform is simple and thus easy togenerate.-Output filter for removal of carrier is economic.-RFI is low because of output filter.-No snubbers are required on power devices.-High efficiency is easily obtainable.-No insertion loss.

f(Hz)100 1k 10k 100k

Power (W)1kW

10W

100mW

f(Hz)100 1k 10k 100k

Power (W)1kW

10W

100mW

f(Hz)100 1k 10k 100k

Power (W)1kW

10W

100mW

(a)

(b)

(c)

250


3.1.2 The Effect of a MOSFET’s Peak to Average Current Rating on Inverter Efficiency

The control of induction motors using a synthesisedsinewave generated using pulse width modulation (PWM)control is becoming increasingly popular. The peak currentrequirement of switches used for the inverter bridge isbased on the maximum current when the output is shortcircuited. The overcurrent during a short circuit fault islimited by an inductor connected in series with the switches.There is therefore a trade off between the peak currentcarrying capability of the switch and the size of the inductor.It is demonstrated in this note that the efficiency of the circuitduring normal operation of the inverter is affected by thesize of this choke. The ratio of peak to average currentcarrying capability of Philips Powermos is typcially aboutfour. This compares favourably with the typical ratio ofInsulated Gate Bipolar Transistors (IGBTs) which is aboutthree.

A simplified diagram of the inverter and the windings of theinductionmotor is shown in Fig.1. TheMOSFETs are drivenwith a PWM signal as shown in Fig. 2. The voltages at theoutputs of each leg of the inverter are smoothed using alow pass filter and the inductance of the motor windings.The system has the following advantages; it uses aninduction motor which is relatively cheap and maintenancefree and it has the facility for 0 to 100% speed control. Thenear perfect sinewaves generated by the PWM techniqueproduce a smooth torque, audible noise is reduced andfiltering is made easier since MOSFETs make possible theuse of switching frequencies above 20 kHz.

Fig. 1 A simplified diagram of the inverter

Fig. 2 PWM drive signal for the inverter MOSFETs

If the output of the inverter is short circuited there will be arapid riseof current in the switches. To limit this peak currentan inductor, Ls, is often connected in each leg of the inverteras shown in Fig 3. The rate of rise of current under shortcircuit conditions, is then given in equation 1.

(1)

Fig. 3 Inverter bridge leg with dI/dt limiting inductor

Vdc

0

Vdc2

dITdt

=VD

Ls

VD

M1

M2

D1

D2

CS

R S

I motor

0V

I M1 LS

251


When the MOSFETs turn this fault current (ISC) off theenergy in the inductor is transferred to a snubber capacitor,CS. The overvoltage across the MOSFETs is given byequation 2.

(2)

The presence of inductor LS affects the normal operationof the inverter. When the MOSFET M1 in Fig. 3 turns offthe diode D2 does not turn on until the voltage across CS

is equal to the d.c. link voltage, VD. If the diode did turn onthen the rate of rise of current in LS would be given byequation 3.

(3)

This would be greater than the rate of rise of motor currentso IM1 > Imotor and the diode would have to conduct in thereverse direction, which is clearly not possible.

During the time when the capacitor CS is charging up to VD,the voltage across LS will always be such as to increase thecurrent in the bottom MOSFET, IM1. When VCS=VD thevoltage across LS will reverse and IM1 will fall. Diode D2 willnow turn on. The energy stored in LS will now be transferredto CS. This energy will subsequently be dissipated in RS andthe MOSFET.

If the ratio of peak to average current carrying capability ofthe switch is large then it follows from equation 1 that LS

can be made smaller. This reduces the energy that is

transferred to CS when the MOSFETs switch off duringnormal operation. Hence the efficiency of the inverter isimproved.

The short circuit fault current can be limited by connectingan inductor in the d.c. link as shown in Fig. 4. In this caseanalysis similar to that outlined above shows that theexcellent ratio of peak to average current carrying capabilityof Philips Powermos again reduces the losses in theinverter. It has been shown that components chosen toensure safe shutdown of inverters for motor drives can havedeleterious effects on the efficiency of the inverter. Inparticular the addition of an inductor to limit the peak currentthrough the semiconductor switches when the output isshort circuited can increase the switching losses. The highpeak to average current carrying capability of PhilipsPowermos reduces the size of this choke and the losses itcauses.

Fig. 4 Modified inverter circuit to limit short circuitcurrent

V = √ Ls

Cs

. ISC

dIM1

dt=

VD −VCS−Vdiode

Ls

252


3.1.3 MOSFETs and FREDFETs for Motor Drive Equipment

The paper discusses the properties of the FREDFET, atechnology which yields a MOSFET with a very fast built-inreverse diode with properties similar to a discrete fastepitaxial rectifier. It is shown that its characteristics makethe device an excellent choice for high frequency bridge legsystems such as 20 kHz AC motor control systems.

Investigations have been carried out in dedicated testcircuits as well as in a 20 kHz ACMC system which showthat the FREDFET exhibits very low diode losses. Itcompares favorably with adiscrete solution, using two extradiodes to overcome the slow speed of the standard built-indiode, and also with devices from the present standardranges.

Introduction

The Power MOSFET has inherent in its structure a largebuilt-in diode which is present between the source anddrainof the device. Under single switch applications such asforward and flyback converters, this diode isn’t forwardbiased and consequently its presence can be ignored. Inthe case of bridge legs, however, this diode is forced intoforward conduction and the properties of the diode becomeof prime importance. The reverse recovery of the built-indiode is relatively slow when compared with discrete fastrecovery epitaxial diodes (FRED’s). As a consequence, thecurrents flowing through the MOSFET and its diode can behigh and the losses considerable.

Fig.1. ACMC bridge leg.

These losses can be reduced through the application of twoextra diodes as discussed in section 2. A more elegantsolution is a MOSFET with a built-in diode which exhibitsproperties similar to discrete fast epitaxial rectifiers. TheFREDFET has been designed to satisfy this requirement.This paper presents the results of studies, carried out withnew FREDFETs, comparing them with both theconventional MOSFET and the discrete solution.

MOSFETS in half bridge circuitsMOSFETS have gained popularity in high frequency ACmotor controllers, since they enable frequencies above20kHz to be used. The short on-times required in ACMCsystems make the use of bipolar devices very difficult, dueto the storage times. Both the short switching times and theease of drive of the MOSFET are essential ingredients inthe design of a ultrasonic ACMC. Difficulties can arise,however, when trying to use the built in source to draindiode of the MOSFETs.

One bridge leg of an ACMC is shown in Fig.1. When currentis flowing out of the load, MOSFET T1 and freewheel diodeD2 conduct alternately. Conversely, when flowing into theload, the current alternates between TR2 and D1. Considerthe case when current is being delivered by the load, suchthat the pair TR1/D2 carries the current. When the MOSFETconducts current, the voltage at the drain is almost zeroand the diode blocks. When the MOSFET is turned off bythe drive circuit, the inductive load forces the voltage toincrease making diode D2 conductive. Associated withconduction of the diode is a volume of stored charge whichmust be removed as the MOSFET TR1 returns to itson-state.

Fig.2. Recovery waveformsTop: VDS, ID of TR1 turning on

Bottom: VD, ID of D2. (t=200ns/div)

The waveforms appropriate to this situation can be foundin Fig.2. One may observe that during the diode recoverytime, the voltage across the MOSFET remains high whilstat the same time its current increases rapidly. Temporarilythe drain current will increase to a level higher than the loadcurrent since the diode recovery current is added to it. Longrecovery times and excessive charge storage result in avery high power dissipation in the MOSFET.

253


Fig.3. Network with extra diodes.

Using the inherent source drain diode of a conventionalMOSFET as the freewheel diode results in considerablelosses, since it is not optimised for fast switching or lowstored charge. To avoid such losses the internal diode isusuallydeactivatedby means of aspecial circuit (see Fig.3).This circuit, using two diodes D2 and D3, ensures that allfreewheel current is flowing through the external diode D2and not through the internal diode D1. When the MOSFETis switched on, the current flows via D3. This circuit isrequired for each MOSFET in the bridge. The FREDFET,which has a fast built-in diode offers the prospect of a muchneater solution for these kind of circuits.

Technology of the FREDFET

Fig.4. FREDFET cross section.

The power MOSFET is a majority carrier device andfeatures fast turn-on and, in particular, fast turn-off. Thereare no charge storage effects such as in bipolar devices.In bridge leg applications the internal diode can becomeforward biased and the N- epitaxial region (see Fig.4) isflooded with holes, which must later be removed when thesource becomes negatively biased again with respect tothe drain.

The stored charge can be removed by holes diffusing fromthe N- epilayer into the P+ and P-body regions, and alsoby recombination of holes and electrons in the N- epitaxialregion. A significant reduction in the stored charge Qrr canbe achieved by doping the devices with heavy metal atomsto introduce recombination centres. A standard MOSFETwill normally have a low concentration of recombination

centres. In the FREDFET the heavy metal doping does nothave any significant effects on the threshold voltage or thetransconductance, however, the efficiency with which theextra recombination centres remove the stored charge isimproved substantially. This can be observed whencomparing Qrr and trr results for killed and non-killeddevices as described in the next section.

FREDFET measurementsA comparison of the reverse recovery characteristics of theinternal diode has been made for a BUK637-500BFREDFET and a similar competitor conventional MOSFET.The devices were tested using an ’LEM 20 A Qrr’ gear.

Fig.5. Reverse recovery waveforms, t=200ns/div;T=25˚C

Oscillograms are presented in fig.5. showing the testwaveforms for both the FREDFET and the conventionaldevice. The diode turn-off process commences at t=t0,where upon the forward current (set at 10A) is reduced ata preset 100A/usec. The current falls through zero and thediode passes into reverse conduction signifying theremoval of stored charge. At t=t2 sufficient charge has beenremoved for the formation of a depletion layer across thep-n junction. The dI/dt starts to fall and a voltage buildsacross an inductance in the source circuit such that thesource becomes negatively biased with respect to drain.

254


Beyond t2 the dI/dt reverses and the diode current beginsto fall as the drain-source voltage rises to the clamp setting.The moment t3 identifies the point at which the diode currenthas fallen to 10% of its peak value, Irrm.

The reverse recovery time, trr is defined as t3-t1 while thetotal stored charge Qrr is equal to the area of the shadedregion, fig.5. A direct comparison of the diode reverserecovery at 25˚C is shown in fig.6. The respective valuesfor trr, Qrr and Irrm are presented in Table 1.

Tj = 25˚C trr (ns) Qrr (uC) Irrm (A)

BUK637-500B 193 1.2 8

Conventional device 492 7.5 23

Table 1.

It can be seen that Qrr is 84 % lower for the FREDFET whileIrrm and trr approximately 60 % less. Fig.7 shows the samecomparison measured at a junction temperature of 150˚C.Corresponding values of trr, Qrr and Irrm are shown inTable 2.

Fig.6. Comparison of diode reverse recovery(t=100ns/div; Tj=25˚C)

Fig.7. Comparison of diode reverse recovery(t=100ns/div; Tj=150˚C)

Tj = 150˚C trr (ns) Qrr (uC) Irrm (A)

BUK637-500B 450 4.5 17

Conventional device 650 10.5 26

Table 2.

While higher temperatures are known to reduce theeffectiveness of recombination centres, it is clear thatsignificant improvements still existeven at the peak junctiontemperature with savings of 55 % in Qrr and over 30 % inIrrm and trr evident for the FREDFET

Performance in a bridge circuit

The circuit of Fig.8 is a simplified representation of a bridgecircuit, and was used to evaluate the performance of theBUK637-500B FREDFET against a conventional MOSFETand a conventional MOSFET configured with both seriesand parallel diodes.

Fig.8. Simplified bridge circuit.

In each case the MOSFET in the bottom leg was switchedon until the load current reached the desired value, at whichpoint it was switched off, forcing the load current to flywheelthrough the inverse diode of the upper leg. The lower devicewas then switched on again to obtain reverse recovery ofthe upper diode. The current levels were set to simulate theconditions found in a 20 kHz 1 kVA ACMC. The device inthe upper leg was mounted on a temperature controlledheatsink and the test was performed at very low duty cyclesuch that Tcase approximated to Tj.

Oscillograms of current and voltage in relation to the lowerleg are shown for the conventional device, conventionaldevice plus external diodes and the FREDFET in Fig.9. Thefreewheel current in the upper diode is related to current inthe MOSFET as shown in Fig.2. Also presented are thepower waveforms for both the upper and lower legs in eachcase.

255


Fig.9. Waveforms (100ns/div; Tj=110˚C)

The superior performance of the FREDFET whencompared to the conventional device is clear with thecurrent overshoot kept to below 8 A compared to over 18 Ausing the latter. The lower reverse recovery current andfaster trr are reflected in the power waveforms with nearlydouble the peak power being dissipated in the lower legusing a conventional device compared to that dissipatedusing the FREDFET. The power dissipated by the internaldiode of the FREDFET is also observed to be remarkablyreduced in comparison with the conventional MOSFET.

The performance of the three device implementations issummarised in table 3 which shows the total energydissipated during switching in both legs for each case.

It can be seen that using a conventional MOSFET withoutthe external diode circuitry involves a six fold increase inthe energy dissipated in the MOSFET. However if aFREDFET implementation is used the turn-on energy isonly a factor of two above the minimum achievable with theextradiodes.Energy loss in the diode itself is relativelysmallfor both the FREDFET and the externaldiode configuration,

Tj = 110˚C Energy Dissipated

Lower Leg Upper Leg(mJ) (mJ)

Conventional MOSFET 1.2 0.533

MOSFET plus external 0.2 0.035diodes

BUK637-500B FREDFET 0.4 0.095

Table 3.

being less than 25 % that dissipated in the lower leg. Forthe conventional device the diode loss is more significant,equal to 44 % of the power dissipated during turn-on in thelower leg. The energy value presented above representonly the losses during turn-on, in addition to these are theon-state losses which for the external diode configurationinclude the extra power dissipated by the series diode.

256


Fig.10. Simplified circuit output stage circuit diagram (One phase shown)

20 kHz ACMC with FREDFETSThe three device options discussed above have each beenimplemented in a 20 kHz AC Motor Control circuit. Theinverter provides a three phase 1 kVA output from a singlephase mains input. A simplified diagram of one of the outputstages is presented in Fig.10.

Figure 11 shows the current waveforms as the load currentcommutates from the upper leg (anti-parallel diode inconduction) to the lower leg (turn-on of the MOSFET) foreach device option. In each case the load current is 4.5 A.Fig.11a illustrates the large overshoot current obtained withaconventional device whileFig.11b showswhat is achievedwhen the two external diodes are incorporated. FinallyFig.11c shows the current waveform for the FREDFETimplementation where the current overshoot is kept below1.5 A by the built-in fast recovery diode of the device.

ConclusionsIt has been shown that the FREDFET compares favorablyin ACMC systems compared with the standard MOSFET.The normally employed extra diodes can be omitted thussaving considerable costs in the system. The fast internaldiode is seen to be comparable with the normally used fastepitaxial rectifiers and enables a simple ultrasonic ACMC.

Fig.11. Current waveforms in 20 kHz ACMC(t=200ns/div; ID=2A/div).

257


3.1.4 A Designers Guide to PowerMOS Devices for MotorControl

This section is intended to be used as a designers guide tothe use and selection of power MOSFETS and FREDFETSin a.c. motor control (ACMC) applications. It is particularlyconcerned with the variable speed operation of inductionmotors using pulse width modulation (PWM) techniques.One of the most important considerations in the design ofACMC inverters is the optimum choice of power switchingdevice and heatsinking arrangement. Other factors whichrelate to the losses in the power switch are switching speedand design of suitable gate drive circuits. This sectionaddresses each of these factors and presents a series ofdesign graphs relating system operating temperature todevice type and heatsink size for systems rated up to 2.2kWand operated from a single phase supply.

It should be noted that this article refers to some productswhich may not be available at this time.

IntroductionVariable speed control of induction motors is a widespreadrequirement in both industrial and domestic applications.The advantages of an induction motor drive over alternativesystems such as d.c. motor controllers include:

-high reliability and long life-low maintenance requirements-brushless operation-availability of standard machines.

With the advent of power switching devices able to providethe required ratings for ACMC applications and theavailability of fast PWM pattern generation circuits theseadvantages have lead to an increasing number ofapplications where the inverter-fed induction motor systemproduces a cost effective drive. Before considering in detailthe use of MOSFETs and FREDFETs in ACMC inverters itis worth briefly considering the principles and operation ofthe induction motor, the PWM method of voltage controland the characteristics of the switching devices.

The induction motorInduction motors are three phase machines where thespeed of rotation of the stator field (the synchronous speed,Ns) is determined by the number of poles, p, and thefrequency of the applied voltage waveforms, fs.

(1)

Torque production in an induction motor is due to theinteraction of the rotating stator field and currents in therotorconductors. Torque is developedwhen the rotor speed’slips’ behind the synchronous speed of the stator travellingfield. Fig.1 shows the torque-speed characteristic of aninduction motor where ωs is the speed of the stator field(ωs=2πfs) and ωr is the rotor speed. The difference betweenthe two is usually relatively small and is the slip speed. Thesolid portion of the characteristic is the main region ofinterest where the motor is operating at rated flux and atlow slip. In this region the rotor speed is approximatelyproportional to the stator supply frequency, except at verylow speeds. The operating point of the motor on itstorque-speed characteristic is at the intersection of the loadtorque line and the motor characteristic. For small amountsof slip and at constant airgap flux the motor torque isproportional to the slip speed.

Fig.1 AC induction motor, Torque-Speed characteristic.

Fig.2 Torque-Speed characteristics, Variable speedoperation.

Torque

Speed

Te

Rated flux

Loadtorque

Motortorque

Slip

w wr s

Torque

Speed

Te Load

torque

f 1 f 2 f 3

w w w w w wr1 s1 r2 s2 r3 s3

V/f = constant

Ns =120.fs

p(rpm)

259


In avariable speed system the motor is operatedon a seriesof torque-speed characteristics as the applied frequency isincreased. Fig.2 shows a set of characteristics for threeconditions, ωs1, ωs2 andωs3. The corresponding rotorspeedsare ωr1, ωr2 and ωr3. However in order that the airgap flux inthe motor is maintained at its rated value then the appliedvoltage must be reduced in proportion to the appliedfrequency of the travelling field. This condition for constantairgap flux gives the constant v/f requirement for variablespeed control of a.c. induction motors. At low speeds thisrequirement may be modified by voltage boosting thesupply to the motor in order to overcome the increasedproportion of ’iR’ voltage drop in the motor windings whichoccurs at low speeds.

The PWM Inverter

A variable voltage, variable frequency three phase supplyfor the a.c. induction motor can be generated by the use ofa pulse width modulated (PWM) inverter. A schematicdiagram of the system is shown in Fig.3. The systemconsists of a rectified single phase a.c. supply, which isusually smoothed to provide the d.c. supply rails for themain switching devices. Alternate devices in each inverterleg are switched at a high carrier frequency in order toprovide the applied voltage waveforms to the motor. Duringeach switching cycle the motor current remainsapproximately constant due to the inductive nature of theAC motor load.

Fig.3 PWM inverter, block diagram.

In the circuit of Fig.3 the main switching devices areMOSFETs and each MOSFET has a freewheeling diodeconnected in antiparallel. The motor load current isdetermined by the circuit conditions. When the load currentin a particular phase is flowing into the motor thenconduction alternates between the top MOSFET and thebottom freewheel diode in that inverter leg. When the loadcurrent is flowing from the motor then the bottom MOSFETand top diode conduct alternately. Fig.4 shows a typical

Fig.4 PWM phase voltage waveform.

sinusoidal PWM voltage waveform for one motor phase.The three phases are maintained at 120˚ relative to eachother.

Both the frequency and amplitude of the fundamentalcomponent of the output voltage waveform can be variedby controlling the timing of the switching signals to theinverter devices. A dedicated i.c. is usuallyused to generatethe switching signals in order to maintain the required v/fratio for a particular system.(1) The PWM algorithmintroduces a delay between the switching signal applied tothe MOSFETs in each inverter leg which allows for the finiteswitching times of the devices and thus protects the systemfrom shoot-through conditions.

Additional harmonic components of output voltage, such asthe third harmonic, can be added to the PWM switchingwaveform.(2,3) The effect of adding third harmonic to theoutput voltage waveform is to increase the amplitude of thefundamental component of output voltage from a fixed d.c.link voltage. This is shown in Fig.5. The third harmoniccomponent of output phase voltage does not appear in theoutput line voltage due to the voltage cancellation whichoccurs in a balanced three phase system. Using thistechnique it is possible to obtain an output line voltage atthe motor terminals which is nearly equal to the voltage ofthe single phase supply to the system.

For many applications the PWM ACMC system is operatedat switching speeds in the range 1kHz to 20kHz and above.Operation at ultrasonic frequencies has advantages thatthe audible noise and RFI interference are considerablyreduced. The advantages of PowerMOS devices overbipolar switching devices are most significant at theseswitching speeds due to the low switching times ofPowerMOS devices. Additional advantages include goodoverload capability and the fact that snubber circuits arenot usually required. It is usually straightforward to operatePowerMOS devices in parallel to achieve higher systemcurrents than can be achieved with single devices. This isbecause the devices have a positive temperaturecoefficient of resistance and so share the load current

Vdc

0

Vdc2

Mains input

Rectifier Filter Three phaseinverter

InductionmotorA

B

C

PWM patterngenerator

Gate drivers

260


Fig.5 Addition of third harmonic to output voltagewaveform.

equally. The simple gate drive requirements of PowerMOSdevices means that a single gate circuit can often be usedfor a range of devices without modification.

MOSFETs and FREDFETs in ACMC

One of the features associated with the transfer ofconduction between the switching devices and thefreewheel diodes in an inverter circuit is the reverserecovery of the freewheel diode as each conductingMOSFET returns to its on-state. Reverse recovery currentflows due to the removal of stored charge from a diodefollowing conduction. Fig.6 shows the device current pathsin an inverter leg when conduction is transferred from thetop diode to the bottom MOSFET.

The switching waveforms are shown in Fig.7 where thediode reverse recovery current is Irr and the time taken forthe reverse recovery currents to be cleared is trr. Theamount of stored charge removed from the body of thediode is represented by the area Qrr. The reverse recoverycurrent flows through the MOSFET which is being turnedon in addition to the load current and thus causes additionalturn-on losses. The amount of stored charge increases withincreasing temperature for a given diode. Both themagnitude of the reverse recovery current and its durationmust be reduced in order to reduce the switching losses ofthe system.

This effect is important because inherent in the structure ofa power MOSFET is a diode between the source and drainof the device which can act as a freewheeling diode in aninverter bridge circuit. The characteristics of this diode arenot particularly suited to its use as a freewheel diode dueto its excessive charge storage and long recovery time.These would lead to large losses and overcurrents duringthe MOSFET turn-on cycle.

Fig.6 Inverter bridge leg.

Fig.7 Diode reverse recovery waveforms.

Fig.8 Circuit to deactivate MOSFET intrinsic diode.

In inverter applications the internal diode of a MOSFET isusually deactivated by the circuit of Fig.8. Conduction bythe internal MOSFET diode is blocked by the seriesSchottky diode (D3). This series device must carry all theMOSFET current and so contributes to the total conductionlosses. The external diode, usually a fast recovery epitaxial

0 30 60 90 120 150 180

0

1

No 3rd harmonic Added 3rd harmonic

Fundamental component Fundamental + 3rd harmonic

Vdc

I LI rr

IL

IL

MOSFET current

Diodecurrent

Outputvoltage I rr

t rr

Time

Time

Time

IL+ I rr

Vdc

Q rr

D1

D2

D3

261


diode (FRED), carries the freewheel current. This device ischosensuch that its low values of Irr and trr reduce the overallswitching losses.The FREDFET is essentially a MOSFETwith a very fast built-in diode, and hence can replace thenetwork of Fig.8 with a single device giving a very compactACMC inverter design using only six power switches.(4)Thereverse recovery properties of a FREDFET diode aresimilar to those of a discrete FRED thus giving aconsiderably neater circuit without any loss in switchingperformance.

ACMC design considerations

Voltage ratingThe first selection criteria for a PowerMOS device in aninverter application is the voltage rating. For a 240V a.c.single phase supply the peak voltage is 340V. Assumingthat the rectifier filter removes the voltage ripplecomponents which occur at twice the mains frequency, anddependent on the values of the filter components andrectifier conduction voltage, then the dc link voltage will bearound 320V. Devices with a voltage rating of 500V willallow sufficient capability for transient overvoltages to bewell within the capability of the device. Thus the dc linkvoltage is given by:

Vdc = √2.Vac (2)

where Vac is the rms ac input line voltage.

The output phase voltage, shown in Fig.4, switchesbetween the positive and negative inverter rail voltages.The mean value of the output voltage is Vdc/2. Neglectingthe delays which occur due to the finite switching times ofthe devices then the maximum rms output phase voltageis given by:

(3)

and hence the rms output line voltage is:

(4)

Comparing equations (2) and (4) shows that:

Vline = 0.866.Vac (5)

This shows that the fundamental rms line output voltage is13% less than the rms ac input voltage. Adding thirdharmonic to the PWM output waveform can restore this rmsoutput voltage to the ac input voltage. In a practical systemthe effect of switching delays and device conductionvoltages can reduce the output voltage by upto 10-15%.

Current ratingThe nameplate rating of an induction motor is usuallyquoted in terms of its power (W) and power factor (cosϕ).The VA requirement of the inverter is found from the simpleequation:

Power(W) = η.cosϕ.VA (6)

where η is the efficiency. In terms of the rms motor linevoltage (Vline) and output current (IL):

VA = √3.Vline.IL (7)

The efficiency of small ac induction motors can be quitehigh but they usually run at quite poor power factors, evenat rated conditions. For small induction motors (<2.2kW)the efficiency-power factor product is typically in the range0.55 to 0.65. The exact value will vary from motor to motorand improves with increasing size. Thus from equations (6)and (7) it is possible to calculate the approximate rmscurrent requirement. The peak device current for sinusoidaloperation is given by equation (8). (NB. The devices willexperience currents in excess of this value at switchinginstants.)

Imax =√2.IL (8)

Device packageThe device package chosen for a particular application willdepend upon device rating, as discussed above, as well ascircuit layout and heatsinking considerations. PhilipsPowerMOS devices are available in a range of packagetypes to suit most applications.

Drive considerationsUnlike bipolar devices the MOSFET is a majority carrierdevice and so no minority carriers must be moved in andout of the device as it turns on and off. This gives the fastswitching performance of MOSFET devices. Duringswitching instants the only current which must be suppliedby the gate drive is that required to charge and dischargethe device capacitances. In order to switch the devicequickly the gate driver must be able to rapidly sink andsource currents of upto 1A. For high frequency systems theeffect of good gate drive design to control switching timesis important as the switching losses can be a significantproportion of the total system losses.

Fig.9 shows an equivalent circuit of the device with thesimplest gate drive arrangement. The drain-sourcecapacitance does not significantly affect the switchingperformance of the device. Temperature only has a smalleffecton the values of thesecapacitances and so the deviceswitching times are essentially independentof temperature.The device capacitances, especially CGD, vary with VDS andthis variation is plotted in data for all PowerMOS devices.

Vph =1

√2.Vdc

2

Vline = √3.Vph = √3.Vdc

2.√2

262


Fig.9 MOSFET capacitances and basic gate driver

Turn-on ( Fig.10)

A turn-on gate voltage pulse commences at t0. The gatevoltage vGS rises as current flows into the device via RGG.CGS starts to charge up until vGS reaches its threshold valuevGS(TO) at time t1. The device is now operating in its activeregion with a relatively high power loss. The MOSFETcurrent, rises as a function of vGS-vGS(TO) and causes acorresponding fall in the diode current. Thus the rate of fallof diode current, and hence the amount of diode reverserecovery current, is controllable by the rate of rise of vGS.At time t4 the diode has recovered and the MOSFET currentis equal to the load current, IL. VGS is clamped to vGS(IL) andso the gate current is given by:

(9)

This current flows through CGD, discharging it and so therate of fall of output voltage is given by:

(10)

The fall in vDS commencing at time t3 is not linear, principallybecause CGD increases with reducing vDS. At time t5 CGD isfully discharged and the device is on. The gate voltagecontinues to charge up to its final value, vGG. It is usual tohave a value of vGG significantly higher than vGS(IL) becauserDS(on) falls with increasing vGS. Additionally a high value ifvGG speeds up the turn-on time of the device and providessome noise immunity.

Switching losses occur during the period t1 to t5. Theminimum turn-on time is usually governed by the dv/dtcapability of the system. Reducing the turn-on timeincreases the amount of diode reverse recovery current andhence increases the peak power dissipation, however thetotal power dissipated tends to reduce.

Fig.10 MOSFET turn-on waveforms

Fig.11 MOSFET turn-off waveforms

Turn-off ( Fig.11)Unlike the conditions which occur at turn-on there is nointeraction between the switching devices at turn-off. Theswitching waveforms are, therefore, relativelystraightforward. The gate voltage is switched to ground or,if very fast turn-off is required, to a negative voltage. Duringthe delay time t0 to t1 the gate voltage falls to the valuerequired to maintain the output current, IO. From time t1 tot2 the gate supply is sinking current and CGD charges thedrain up to the positive rail voltage. VGS then continues tofall and so the device current falls between times t2 and t3,At t3 the gate voltage falls below its threshold value and thedevice turns off. The rate of rise of output voltage is:

CDS

CGD

CGS

D

S

GR GGV

GG

t0 t1 t2 t3 t4 t5 t6

vGG

vGS

i DIODE

i D

vDS

VGG

VGG

I L

vGG

vGS

i D

v DS

t0 t1 t2 t4

Vdc

t3

iG =vGG − vGS(IL )

RGG

dvDS

dt=

iGCGD

=(vGG−vGS(IL ))

RGG .CGD

263


(11)

Parasitic turn-onIn a high frequency system the device switching times arenecessarily short and so the rates of change of inverteroutput voltage are high. The high values of dv/dt whichoccur when one device turns on can cause a sufficientlyhigh voltage at the gate of the other device to also turn iton. The coupling occurs via CGD and CGS. If the rate ofchange of output voltage due to one device turning on isgiven by dvDS/dt then the voltage that would be seen at thegate of the other device if it were left open circuit is:

(12)

If CGS is shorted out by a zero impedance, then clearlydVGS/dt can be reduced to zero. In practice achieving a zeroimpedance in the gate-source circuit is extremely difficultand dVGS/dt will not be zero. In the worst case this risinggate voltage will turn the device fully on and a destructiveshoot-through condition occur. If the conditions are lesssevere then the MOSFET may only turn on for a short periodof time giving rise to an additional overcurrent in the turn-oncycle of the device being switched. Parasitic turn-on, as thiseffect is referred to, must be prevented by either limitingdvDS/dt or by ensuring that vGS is clamped off. In systemswhere the off-state gate-source voltage is negative then thepossibility of parasitic turn-on can be reduced.

Gate drive circuits for ACMC invertersThe previous section discussed device switchingwaveforms using a resistive gate drive circuit. In this sectionvariousalternativegate drive circuits for ACMC applicationsare presented and compared.The discussion assumes thateach MOSFET gate drive circuit is isolated and driven usingaCMOS buffer capable of sinking and sourcing the requiredgate current. In unbuffered gate drive circuits the leakageinductance of an isolating pulse transformer can increasethe gate impedance, thus reducing the maximum possibleswitching rate and making the MOSFET more susceptibleto parasitic turn-on. A zener diode clamp protects thegate-source boundary from destructive overvoltages.Identical drivers are used for the top and bottom devices ineach inverter leg. The gate drive circuits presented herewere tested using BUK638-500A FREDFETS andBUK438-500A MOSFETS in a 20kHz, 2.2kW ACMCsystem.

Figure 12 shows the simplest arrangement which givesindependent control of the turn-on and turn-off of theMOSFET. Increasing the gate impedance to reduce dVDS/dtlevels will raise the susceptibility to parasitic turn-onproblems. The gate-source voltage can be clamped off

Fig.12 Gate drive circuit with different turn-on andturn-off paths

Fig.13 Gate drive circuit with improved parasitic turn-onimmunity

more effectively if the dynamic impedance between gateand source is reduced as shown in the circuit of Fig.13. Theadditional gate-source capacitance ensures that vGS doesnot rise excessively during conditions when parasiticturn-on could occur (Equation 12). The external capacitorCGS‘ must be charged up at turn-on. If CGS‘ is made too largethen the current required may be beyond the rating of thedrive buffer. The speed-up diode, D2, ensures that theturn-on is not compromised by CGS‘and RGGR. At turn off theadditional capacitance slows down dID/dt since thegate-source RC time constant is increased. Itmust be notedthat one effect of the turn-off diode, D1, is to hold theoff-statevalue of vGS above 0V, and hence somewhat closerto the threshold voltage of the device.

An alternative circuit which may be used to hold theMOSFET off-state gate-source voltage below its thresholdvalue is shown in Fig.14. The pnp transistor turns on if thegate-source voltage is pulled up via CGD and CGS and thusthe device remains clamped off.

dvDS

dt=

iGCGD

=vGS(IL )

RGG .CGDRGGF 100R

RGGR 10R

D1

dvGS

dt=

CGD

CGS+CGD

.dvDS

dt

RGGF 100R

RGGR 10RCGS’

10nF

D2

D1

264


Fig.14 Alternative gate drive circuit with improvedparasitic turn immunity

Parallelling of PowerMOS devicesMoving to a system using parallelled MOSFETs requiresonly slight modifications to the gate drive circuit. Oneconsideration may be the capability of the drive buffer toprovide the currents required at the switching instants. Theswitching speed of the system can be maintained. using alower impedance gate drive. It is recommended that smalldifferential resistors, as shown in Fig.15, are used to dampout any oscillations which may occur between the switchingdevices and the rest of the circuit. The circuit of Fig.13 canbe modified for operation with parallelled devices to thatshown in Fig.16.

Circuit layout considerationsThe effects of poor circuit design and layout are to increaseRFI and noise and to compromise the performance andspeed of the system due to stray inductances. Theprecautions which must be taken to minimise the amountof stray inductance in the circuit include:

- positioning the gate drive circuits, especially zener diodesand dv/dt clamping circuits as close as possible to thepower MOSFETs.

- reducing circuit board track lengths to a minimum andusing twisted pairs for all interconnections.

- for parallelled devices, keeping the devices close to eachother and keeping all connections short and symmetrical.

Fig.15 Gate drive circuit for parallelled devices

Fig.16 Gate drive circuit for parallelled devices withimproved parasitic turn-on immunity

Modelling of parasitic turn-on

Using the simple MOSFET model of Fig.9 it is possible tostudy the susceptibility to parasitic turn-on of alternativegate drive circuits. Considering the switching instant whenthe bottom MOSFET is held off and the top MOSFET isswitched on, the voltage across the bottom MOSFETswings from the negative inverter rail to the positive one.The switching transient can be modelled by an imposeddvDS/dt across CGD and CGS and hence the effect of gatecircuit design and dvDS/dt on vGS can be studiedusing simpleSPICE models.

Typical data sheet values of CGD and CGS for a 500VMOSFET were used. The simulated results assumeconstant dvDS/dt, that freewheel diode reverse recovery canbe neglected and that the off-state gate drive buffer outputis at 0V with a sink impedance of around 5Ω. In practicethe dvDS/dt causing parasitic turn-on is not constant and isonly at its maximum value for a small proportion of thevoltage transition. Thus the results shows here representa ’worst-case’ condition for the alternative gate drive circuitsused to clamp vGS to below its threshold value, typically 2Vto 3V. (The simple circuit model used here ceases tobecome valid once vGS reaches vGS(TO) (time t1 in Fig.10)when the MOSFET starts to turn on.)

Fig.17 shows the relevant waveforms for the circuit of Fig.9with RGG=100Ω. The top waveform in Fig.17 shows animposed dvDS/dt of 3.5V/ns and a dc link voltage of 330V.The centre trace of Fig.17 shows that vGS rises quickly(reaching 3V in 25ns); at this point the MOSFET would startto turn on. The bottom trace shows the CGD charging currentsinking through the gate drive resistor RGG. For the circuitof Fig.12with RGGF=100Ω and RGGR=10Ω, Fig.18 shows thatthe gate source voltage is held down by the reduced driveimpedance but still reaches 3V after 35ns.

RGGF 47RRGG’ 10R

RGG’ 10R

CGS’

20nF

RGGF 47RRGG’ 10R

RGG’ 10R

265


Fig.17 Parasitic turn-on waveforms for circuit of Fig.9

Fig.19 Parasitic turn-on waveforms for circuit of Fig.13,CGS‘=10nF

Fig.21 Parasitic turn-on waveforms for circuit of Fig.16,CGS‘=20nF

Fig.18 Parasitic turn-on waveforms for circuit of Fig.12

Fig.20 Parasitic turn-on waveforms for circuit of Fig.13,CGS‘=4.7nF

Fig.22 Parasitic turn-on waveforms for circuit of Fig.16,Ls=20nH stray inductance

0 2E-08 4E-08 6E-08 8E-08 1E-070

5

10

15

0 2E-08 4E-08 6E-08 8E-08 1E-070

100

200

300

400

0 2E-08 4E-08 6E-08 8E-08 1E-070

0.05

0.1

0.15

vDS(V)

vGS(V)

iGG(A)

0 2E-08 4E-08 6E-08 8E-08 1E-070

2

4

6

0 2E-08 4E-08 6E-08 8E-08 1E-070

100

200

300

400

0 2E-08 4E-08 6E-08 8E-08 1E-070

0.1

0.2

0.3

0.4

vDS(V)

vGS(V)

iGG(A)

0 2E-08 4E-08 6E-08 8E-08 1E-07-0.1

0

0.1

0.2

0.3

0 2E-08 4E-08 6E-08 8E-08 1E-070

100

200

300

400

0 2E-08 4E-08 6E-08 8E-08 1E-070

1

2

3

4

5

iCG’

iRGGR

vDS (V)

vGS (V)

i GG(A)

0 2E-08 4E-08 6E-08 8E-08 1E-070

100

200

300

400

0 2E-08 4E-08 6E-08 8E-08 1E-070

1

2

3

4

0 2E-08 4E-08 6E-08 8E-08 1E-07-0.1

0

0.1

0.2

0.30.4

i RGGR

i CG’

vDS (V)

vGS (V)

i GG(A)

0 2E-08 4E-08 6E-08 8E-08 1E-070

100

200

300

400

0 2E-08 4E-08 6E-08 8E-08 1E-070

1

2

3

4

0 2E-08 4E-08 6E-08 8E-08 1E-07-1

-0.5

0

0.5

1

vDS (V)

vGS (V)

vLs (V)

0 2E-08 4E-08 6E-08 8E-08 1E-070

1

2

3

4

0 2E-08 4E-08 6E-08 8E-08 1E-070

100

200

300

400

0 2E-08 4E-08 6E-08 8E-08 1E-070

0.2

0.4

0.6

0.8

i CG’

i GG

vDS (V)

vGS

(V)

iGG

(A)

266


Figure 19 shows the response of the circuit of Figure 13with CGS‘=10nF. Here the gate-source voltage is held downduring the parasitic turn-on period and so the MOSFETstays off. If the value of CGS‘ is reduced to 4.7nF then theresults given in Fig.20 show that vGS reaches 3V after 55nsthus reducing immunity to parasitic turn-on.

Figures 21 and 22 show the conditions for parallelconnected MOSFETs using the circuit of Fig.16. In Fig.21,for RGG1=47Ω, RGG‘=10Ω and CGS‘=20nF, the bottom tracein the figure shows that a potential parasitic turn-oncondition is avoided and vGS is held below its thresholdvalue. The bottom trace in Fig.21 shows most of theparasitic turn-on current is taken by CGS‘. Figure 22 showsthe effect of stray inductance between the gate drive circuitand the PowerMOS device. The circuit of Fig.16 has beenmodified by the addition of 20nH of stray inductancebetween the gate node and the dv/dt clamping network.During switching of the top device with dv/dt=3.5V/ns thestray inductance develops over 0.6V due to coupling viaCGD. Clearly this could significantly affect the performanceof the drive during normal turn-on, and increase theprospect of the bottom MOSFET being subject to parasiticturn-on problems.

These results show that immunity to parasitic turn-on canbe greatly improved by alternative gate circuit design. TheSPICE modelled circuits show the worst case conditions ofconstant dvDS/dt and show that vGS can be held below itsthreshold voltage using the circuits shown in the previoussection. Experimental measurements have confirmedthese results in a prototype 20kHz ACMC system.

Device losses in ACMC invertersIt is important to be able to calculate the losses which occurin the switching devices in order to ensure that deviceoperating temperatures remain within safe limits. Coolingarrangements for the MOSFETs orFREDFETs in an ACMCsystem will depend on maximum allowable operatingtemperatures, ambient temperature and operatingconditions for the system. The components of loss can beexamined in more detail:

MOSFET Conduction lossesWhen a MOSFET or FREDFET is on and carrying loadcurrent from drain to source then the conduction ’i2R’ losscan be calculated. It is important to note that the devicecurrent is not the same as the output current, asdemonstratedby the waveforms ofFig.23. The figure showsa sinusoidal motor load current waveform and the top andbottom MOSFET currents. The envelopes of the MOSFET

currents are half sinusoids; however the actual devicecurrents are interrupted by the instants when the loadcurrent flows through the freewheel diodes. For thepurposes of calculating MOSFET conduction losses it isacceptable to neglect the ’gaps’ which occur when thefreewheel diodes are conducting for the following reasons:

Fig.23 Motor current and device current waveforms in aPWM inverter

-When the motor load current is near its maximum valuethe switching duty cycle is also near its maximum andso the proportion of time when the diode conducts isquite small and can be neglected.-When the motor load current is near zero then theswitching duty cycle is low but the MOSFET is onlyconducting small amounts of current. As the MOSFETcurrent is low then the contribution to total conductionloss is small.

Thus if the MOSFET is assumed to be conducting loadcurrent for the whole half-period then the conduction lossescan be calculated using the current envelope of Fig.23.These losses will be overestimated but the discrepancy willbe small. The conduction losses can be given by:

PM(ON) = IT2.RDS(ON)(Tj) (13)

where IT is the rms value of the half sinusoid MOSFETcurrent envelope.

and: RDS(ON)(Tj) = RDS(ON)(25˚C).ek(Tj-25) (14)

where k=0.007 for a 500V MOSFET, and k=0.006 for a500V FREDFET.

IT is related to the rms motor current, IL, by:

(15)

iL

i T1

iT2

Load current

Top MOSFET current

Bottom MOSFET current

IT =Imax

2=

IL

√2

267


Fig.24 Selection graphs for a 1.7A motorNB. Device selection notation: 1X655-A denotes a single BUK655-500A FREDFET, etc.

PHILIPS 500V FREDFETS

Frequency = 5kHz

0 0.4 0.8 1.2 1.6 240

50

60

70

80

90

100

Heatsink size, Rth_hs-amb (K/W)

Heatsink temperature, T_hs

PHILIPS 500V MOSFETS (+ diode network)

Frequency = 5kHz

0 0.4 0.8 1.2 1.6 240

50

60

70

80

90

100




Frequency = 20kHz

0 0.4 0.8 1.2 1.6 240

50

60

70

80

90

100

Heatsink size Rth_hs-amb (K/W)



Frequency = 20kHz

0 0.4 0.8 1.2 1.6 240

50

60

70

80

90

100



655-A 655-B 637-A 637-B 638-A 638-B

655-A 655-B 637-A 637-B 638-A 638-B

455-A 455-B 437-A 437-B 438-A 438-B

455-A 455-B 437-A 437-B 438-A 438-B

Additionally in a MOSFET inverter the series blockingSchottky diode (D3 of Fig.8) has conduction losses. Thecurrent in this diode is the main MOSFET current and soits loss is approximated by:

PSch(ON) = Vf(Tj).IT (16)

Diode conduction lossesIn a MOSFET inverter the freewheel diode losses occur ina discrete device (D2 of Fig.8) although this device is oftenmounted on the same heatsink as the main switchingdevice. In a FREDFET circuit the diode losses occur in themain device package. The freewheeling diode carries the

’gaps’ of current shown in Fig.23 during the periods whenits complimentary MOSFET is off. Following the argumentused above the diode conduction loss is small and can beneglected. Using this simplification we have effectivelytransferred the diode conduction loss and included it in thefigure for MOSFET conduction loss.

MOSFET switching lossesDuring the half-cycle of MOSFET conduction the loadcurrent switched at each instant is different (Fig.23). Theamount of current switched will also depend on the reverserecovery of the bridge leg diodes and hence on the

268




Frequency = 5kHz




Frequency = 5kHz




Frequency = 20kHz




Frequency = 20kHz



655-A 655-B 637-A 637-B 638-A 638-B

655-A 655-B 637-A 637-B 638-A 638-B

455-A 455-B 437-A 437-B 438-A 438-B

455-A 455-B 437-A 437-B 438-A 438-B

0 0.2 0.4 0.6 0.8 140

50

60

70

80

90

100

0 0.2 0.4 0.6 0.8 140

50

60

70

80

90

100

0 0.2 0.4 0.6 0.8 140

50

60

70

80

90

100

0 0.2 0.4 0.6 0.8 140

50

60

70

80

90

100

temperature of the devices. The total turn-on loss (PM(SW))will be a summation of the losses at each switching instant:

(17)

MOSFET turn-off times are usually only limited by dv/dtconsiderations and hence are as short as possible. Theturn-off loss of the MOSFETs or FREDFETs in an inverteris small compared with the turn-on loss and can usually beneglected.

Diode switching lossesDiode turn-off loss (PD(SW)) is calculated in a similar manner

to the MOSFET turn-on loss. The factors which affect thediode turn-off waveforms have been discussed earlier.Diode turn-on loss is usually small since the diode will notconduct current unless forward biassed. Thus at turn-onthe diode is never simultaneously supporting a high voltageand carrying current.

Gate drive losses

Some loss will occur in the gate drive circuit of a PowerMOSdevice. As the gate drive is only delivering short pulses ofcurrent during the switching instants then these losses arenegligibly small.

PM(SW) = ∑n = 0

∞f(Tj , In)

269




Frequency = 5kHz




Frequency = 5kHz




Frequency = 20kHz




Frequency = 20kHz



1X 638-A 2X 637-A 3X 637-A 2X 638-A 3X 638-A 1X 617-AE 1X 438-A 2X 437-A 2X 438-A 3X 437-A 3X 438-A 1X 417-AE


0 0.2 0.4 0.6 0.8 140

50

60

70

80

90

100

0 0.2 0.4 0.6 0.8 140

50

60

70

80

90

100

0 0.2 0.4 0.6 0.8 140

50

60

70

80

90

100

0 0.2 0.4 0.6 0.8 140

50

60

70

80

90

100

System operating temperaturesIn this section the device losses discussed in the previoussection are calculated and used to produce a design guidefor the correct selection of Philips PowerMOS devices andappropriate heatsink arrangements for ACMC applications.The following factors must be take into account whencalculating the total system loss, PLOSS:

-Device characteristics-Switching frequency-Operating temperature-Load current-Number of devices used in parallel.-Additional snubber or di/dt limiting networks.

PLOSS = PM(ON)+PM(SW)+PD(SW)+PSch(ON) (18)

For the results presented here the device parameters weretaken for the Philips range of 500V MOSFETs andFREDFETs. The on-state losses can be calculated fromthe equations given above. For this analysis the deviceswitching losses were measured experimentally asfunctions of device temperature and load current. As thereare six sets of devices in an ACMC inverter then the totalheatsink requirement can be found from:

Ths = Tahs + 6.PLOSS.Rth(hs-ahs) (19)

Tj=Ths + PLOSS.Rth(j-hs) (20)

270


Fig.27 Selection graphs for a 10A motorNB. Device selection notation: 2X638-A denotes two parallelled BUK638-500A FREDFETs, etc.


Frequency = 5kHz



Frequency = 5kHz




Frequency = 20kHz




Frequency = 20kHz




40

50

60

70

80

90

100

Heatsink size, Rth_hs-amb (K/W)0 0.1 0.2 0.3 0.4 0.5 0.6 0 0.1 0.2 0.3 0.4 0.5 0.6

40

50

60

70

80

90

100

0 0.1 0.2 0.3 0.4 0.5 0.640

50

60

70

80

90

100

0 0.1 0.2 0.3 0.4 0.5 0.640

50

60

70

80

90

100


Equations 18 to 20 can be used to find the heatsink size(Rth(hs-ahs)) required for a particular application which willkeep the heatsink temperature (Ths) within a required designvalue. Results are plotted in Figures 24 to 27 for motorcurrents of IL = 1.7A, 3.4A, 6.8A and 10.0A. These currentscorrespond to the ratings of several standard inductionmotor sizes. The results assume unsnubbed devices, anambient temperature of Tahs=40˚C, and are plotted forinverter switching frequencies of 5kHz and 20kHz.

Two examples showing how these results may be used aregiven below:

1) -The first selection graph in Fig.24 shows the possibledevice selections for 500V FREDFETs in a 5kHz ACMC

system where the full load RMS motor current is 1.7A.Using a BUK655-500A FREDFET, Ths can bemaintained below 70˚C with a total heatsinkrequirement of 1.2K/W (if each FREDFET was mountedon a separate heatsink then each device would need a7.2K/W heatsink). The same heatsinking arrangementwill give Ths=50˚C using a BUK638-500A. AlternativelyThs can be maintained below 70˚C using a 2K/Wheatsink (12K/W per device) and the BUK637-500B.

2) -In Fig.27 the selection graphs for a 10A system aregiven. The fourth selection graph is for a 20kHzswitching frequency using 500V MOSFETs. Here twoBUK438-500A devices connected in parallel for eachswitch will require a total heatsink size of 0.3K/W if the

271


heatsink temperature is to remain below 90˚C. Thesame temperature can be maintained using a 0.5K/Wheatsink and a single BUK417-500AE ISOTOP device.

For different motor currents or alternative PWM switchingfrequencies the appropriate device and heatsinkarrangement for a particular application can be found byinterpolating the results presented here.

ConclusionsThis section has outlined the basic principles and operationof PWM inverters for ACMC applications using PhilipsPowerMOS devices. MOSFETs and FREDFETs are themost suitable devices for ACMC systems, especially at highswitching speeds. This section has been concerned withsystems rated up to 2.2kW operating from a single phasesupply and has shown that there is a range of PhilipsPowerMOS devices ideally suited for these systems.

The characteristics and performance of MOSFETs andFREDFETs in inverter circuits and the effect of gate drivedesign on their switching performance has been discussed.The possibility of parasitic turn-on of MOSFETs in aninverter bridge leg can be avoided by appropriate gate drivecircuit design. Experimental and simulated results have

shown that good switching performance and immunity toparasitic turn-on can be achieved using the Philips rangeof PowerMOS devices in ACMC applications . Using thedevice selection graphs presented here the correctMOSFET or FREDFET for a particular application can bechosen. This guide can be used to select the heatsink sizeand device according to the required motor current,switching frequency and operating temperature.

References

1. Introduction to PWM speed control system for 3-phaseAC motors: J.A.Houldsworth, W.B.Rosink: ElectronicComponents and Applications, Vol 2, No 2, 1980.

2. A new high-quality PWM AC drive: D.A.Grant,J.A.Houldsworth, K.N.Lower: IEEE Transactions, VolIA-19, No 2, 1983.

3. Variable speed induction motor with integral ultrasonicPWM inverter: J.E.Gilliam, J.A.Houldsworth, L.Hadley:IEEE Conference, APEC, 1988, pp92-96.

4. MOSFETs and FREDFETs in motor drive equipment:Chapter 3.1.3.

272


3.1.5 A 300V, 40A High Frequency Inverter Pole UsingParalleled FREDFET Modules

IntroductionVoltage source inverters which are switched using someform of pulse width modulation are now the standard in lowto medium rated AC and brushless DC variable speeddrives. At present, because of device limitations theswitching (modulation) frequencies used in all but thelowest drive ratings are restricted to a few kHz. There ishowever a strong technical advantage in using much higherultrasonic switching frequencies in excess of 20 kHz, thebenefits of which include:

i) The low frequency distortion components in the inverteroutput waveform are negligible. As a result there is nolonger a need to derate the electrical machine in the driveas a consequence of harmonic loss.

ii) The supply derived acoustic noise is eliminated.

iii) The DC link filter component values are reduced.

The device best suited for high switching frequencies is thepower MOSFET because of its extremely fast switching

time and the absence of secondary breakdown. However,being surface conduction devices, high power ratedMOSFETs are difficult and expensive to manufacture andat present single MOSFETs are only suitable for inverterratings of typically 1-2 kVA per pole. Although higher ratedpower devices such as bipolar transistors and IGBTs canbe switched at medium to high frequencies, the switchinglosses in these circuits are such that frequencies in excessof 20 kHz are at present difficult to achieve.

Switches with high ratings and fast switching times can beconstructed by hard paralleling several lower rated powerdevices. MOSFETs are particularly suitable because thepositive temperature coefficient of the channel resistancetends toenforce good steady-state currentsharing betweenparallel devices. However to achieve good dynamic currentsharing during switching, considerable care must be takenin the geometric layout of the paralleled devices on thecommon heatsink. In addition, the device characteristicsmay need to be closely matched. As a result modules ofparalleled MOSFETs are often expensive.

Fig.1

+

-

1 2 N

DCRail

Within each mdule: Good transient + steady state load sharingIsolated drive circuit

Pole Output

273


An alternative approach to paralleling is to use smallswitching aid networks which overcome the constraints ofhard paralleling by improving the dynamic load sharing ofthe individual devices. It is possible to envisage an inverterdesign where each pole consists of a number of identicalpole modules which share a common supply and haveoutputs connected in parallel, as shown in Fig.1. Eachmodule is designed to operate individually as an inverterpole and contains two power MOSFETs with associatedisolated gate drive circuitry. When the modules areconnected in parallel their design is such that they willexhibit good transient and steady-state load sharing, theonly requirement being that they are mounted on a common

heatsink. In this manner any inverter volt-amp rating canbe accommodated by paralleling a sufficient number of polemodules.

Pole moduleThe power circuit diagram of an individual pole modulewhich is suitable for the second form of paralleling is shownin Fig.2. The design makes use of the integral body diodeof the main switching devices and for this purpose the fastrecovery characteristics of FREDFETs are particularlysuitable. Two snubber circuits and a centre tappedinductance are included in the circuit. These small switchingaid networks perform a number of functions in the circuit:

Fig.2

274


i) They act to improve the dynamic current sharing betweenthe pole modules when connected in parallel.ii) They ensure safe operation of the MOSFET integral bodydiode. The central inductance controls the peak reversecurrent of the diode and the snubber network preventssecondary breakdown of the MOSFET parasitic internaltransistor as the integral body diode recovers.iii) They reduce the switching losses within the main powerdevices and thus allows maximum use of the availablerating.

Fig.3

The operation of the circuit is typical of this form of inverterpole. The commutation of the integral body diode will bediscussed in detail since it is from this section of theoperation that the optimal component values of theswitching aid network are determined. The value of theinductor L is chosen to give a minimum energy loss in thecircuit and the snubber network is designed to ensure saferecovery of the integral diode at this condition. For exampleconsider the case when there is an inductive load currentIL flowing out of the pole via the integral body diode of thelower MOSFET just prior to the switching of the upperMOSFET. With reference to Fig.3, the subsequentoperation is described by the following regions:

Region A: Upper MOSFET is switched on. The current inthe lower integral body diode falls at a rate (dI/dt) equal tothe DC link voltage VDD divided by the total inductance L ofthe centre tapped inductance.

Region B: The diode current becomes negative andcontinues to increase until the junction stored charge hasbeen removed, at which stage the diode recoverscorresponding to a peak reverse current IRR.

Region C: The voltage across the lower device increasesat a rate (dV/dt) determined by the capacitance Cs of thelower snubber network. The current in the upper MOSFETand the inductor continues to increase and reaches a peakwhen the voltage across the lower device has risen to theDC link value. At this point the diode Dc becomes forwardbiased and the stored energy in the inductor begins todischarge through the series resistance Rc.

The energy E1 gained by the switching aid networks overthe above interval is given by:

and is ultimately dissipated in the network resistors Rs, Rc.For a given forward current, the peak reverse current IRR ofthe diode will increase with increasing dI/dt and can beapproximately represented by a constant stored charge,(QRR) model, where:

Although in practice IRR will tend to increase at a slightlyfaster rate than that given by equation (2).

Since in the inverter pole circuit

Inspection of equations (1) and (4) shows that the energyloss E1 remains approximately constant as L is varied.

During the subsequent operation of the inverter pole whenthe upper MOSFET is turned off and the load current ILreturns to the integral body diode of the lower device, anenergy loss E2 occurs in the inductor and the upper snubberequal to:

This loss can be seen to reduce with L. However as L isreducedboth IRR and the peak current in the upper MOSFETwill increase and result in higher switching loss in the diodeand higher conduction loss in the channel resistance of theupper device.

The value of L which gives minimum energy loss in the poleoccurs when there is an optimal balance between theeffects described above. Typical measured dependenciesof the total energy loss on the peak reverse diode currentas L is varied are shown in Fig.4. The characteristics of asimilarly rated conventional MOSFET and a fast recoveryFREDFET are compared in the figure. In both cases theminimum energy loss occurs at the value of L which givesa reverse recovery current approximately equal to thedesign load current. However the loss in the FREDFETcircuit is considerably lower than with the conventionaldevice. The optimal value of L can be found from themanufacturers specified value of stored charge usingequation (4), where

IRR = √2

dIdt

QRR (2)

IL

Diodecurrent

I rr

t rr

TimeQ rr

A B C

dI/dt

dIdt

=VDD

L(3)

IRR = √2VDDQRR

L(4)

E2 =12

IL2L +

12

CsVDD2 (5)

E1 =12

IRR2 L +

12

CsVDD2 (1)

275


Fig.4

The snubber capacitor value Cs is chosen to limit the dV/dtacross the integral body diode as it recovers. Experiencehas shown that a value of 1V/nS will ensure safe operation,hence:

The resistive component of the switching aid networks arechosen in the usual manner.

Parallel operation of pole modulesThe principle behind the ‘soft’ paralleling adopted here isto simply connect the outputs of the required number ofmodules together and feed them with a common DC linkand control signals. The transient load sharing between theparallel modules will be influenced by the tolerances in theindividual inductor and snubber capacitor values and anyvariations in the switching instances of the power devices,the latter being as a result of differences in devicecharacteristics and tolerances in the gate drive circuitry.These effects were investigated using the SPICE circuit

simulation package. The SPICE representation of themodules is shown in Fig.5, in which the upper MOSFETchannel is modelled by an ideal switch with a seriesresistance RDS. The full SPICE diode model is used for thelower MOSFET integral body diode, however ideal dioderepresentations are sufficient for the devices in theswitching aid networks. The load is assumed to act as aconstant current sink over the switching interval.

Fig.5

From the SPICE simulation an estimate of the peaktransient current imbalance between the MOSFETs of thetwo modules was obtained for various differences in theinductors, capacitors and device turn-on times. It was foundthat the transient current sharing was most sensitive tounequal device switching times. An example of the resultsobtained from a simulation of two paralleled modules usingBUK638-500B FREDFETs are shown in Fig.6. With goodgate drive design the difference between device switchingtimes is unlikely to exceed 50nS resulting in apeak transientcurrent mismatch of less than 10%. The load sharing wouldimprove if the value of inductor is increased but this has tobe traded off against the increase in switching loss. Theeffect of the tolerance of the inductor values on the loadsharing is given for the same module in Fig.7, where it canbe seen that a reasonable tolerance of 10% results in onlya 7% imbalance in the currents. The load sharing was foundto be relatively insensitive to tolerances in the snubbercapacitor values.

0 0.2 0.4 0.6 0.8 1 1.2 1.40

20

40

60

80

100

NORMALISED RECOVERY CURRENT (IRR/IL)

POWER LOSS (W)

STANDARD

EQUIVALENT

MOSFET

BUK638-500B

MODULE

Lopt =2VDDQRR

IL2

(6)

C = (IL) nF (7)

276


Fig.6

277

Motor

Control

Pow

er Sem

iconductor Applications

Philips S

emiconductors

Fig.7

278


A 300V, 10A pole module design usingBUK638-500B FREDFETsThe circuit diagram of a 300V, 10A pole module based onBUK638-500B FREDFETs is given in Fig.8. The inductorvalue was chosen using the criteria discussed in Section2.

The conventional R-C snubber network has been replacedby the active circuit shown in Fig.9 and involves the use ofasecond, low rated BUK455-500B MOSFET which is madeto act as a capacitance by invoking the ‘Miller’ effect. The

active snubber is more efficient at low load currentsbecause it tends to maintain a constant (dV/dt) regardlessof the load, and thus the snubber loss is proportional to thecurrent, as opposed to the conventional circuit in which theloss remains constant. In addition the active circuit iscompact and lends itself more readily to a hybrid assembly.The major component costs are the secondary MOSFETand a low voltage power diode and compare favourablywith those of the conventional high voltage capacitor andhigh voltage diode.

Fig.8

279


The gate drive circuits are given in Fig.10 and are basedupon the pulse transformer configuration described inchapter 1.2.3. A PNP transistor has been added betweenthe gate and source to reduce the drive off-stateimpedance, to improve the switching and prevent any Millereffect in the main device.

Fig.9

FREDFET module performanceThe typical voltage and current waveforms of the upper andlower switching devices are shown in Figures 11 and 12 forthe case of a single pole module sourcing the rated currentof 10 Amps from a 300V DC link. Fig.12 illustrates how theuse of the series inductor and active snubber gives acontrolled recovery of the fast integral body diode of theFREDFET.

Fig.10

5 A/div50 V/div

200 ns/div

Fig.11 Top - turn-on of the lower diodeBottom - turn-off of the MOSFET

The losses of an individual module switched at 20 kHz areplotted in Fig.13 as a function of output current. They mainlystem from conduction loss, the switching loss representingonly a third of the maximum loss. Because the switchingloss occurs mainly in the aid networks the main FREDFETscan be used at close to their full rating. Similarly operationat higher frequencies will not result in a substantialreduction in efficiency, for example at40 kHz,10A operationthe losses are 95W.

280


5 A/div50 V/div

200 ns/div

Fig.12 Top - turn-off of the lower diodeBottom - turn-on of the MOSFET

Four modules were connected in parallel and mounted ona common heatsink. The modules operated successfully at300V with total loads in excess of 40A, four times theirindividual rating. The common heatsink, which had athermal resistance to ambient of 0.33˚C/W was sufficientto achieve the full 40A, 300V continuous rating of theparallel units at 20 kHz. The current waveforms of the upperFREDFETs in each module are overlaid in Fig.14, where itcan be seen that the load sharing is very even, particularlyafter the initial switching transients.

Fig.13

5 A/div2 µs/div

Fig.14 FREDFET current waveforms

281


ConclusionParallel, separate MOSFET pole modules provide amethod of designing medium rated inverter poles, whichcan be switched efficiently at frequencies in excess of 20kHz. The approach is flexible since a single pole moduledesign can be used to achieve a range of inverter volt-ampratings by paralleling a sufficient number of units.

Through the use of small switching aid networks it ispossible to obtain excellent transient and steady-statecurrent sharing between the paralleled modules. Thecurrent sharing remains good even if there are substantialvariations in component tolerances and the power device

switching times. The switching aid networks also reducethe switching losses in the main devices and allows themto be used to their full rating.

The presented design of a 300V, 10A module based onBUK638-500B, FREDFETs has a full load loss of only 70W.Four of these modules connected in parallel and mountedon a 0.33˚C/W heatsink gave an inverter pole with a 300V,40A continuous rating when switched at 20 kHz. Excellentcurrent sharing between these modules was observed andas a result there would seem to be no technical reasonswhy further modules could not be paralleled toachieve evenhigher ratings.

282


DC Motor Control

283


3.2.1 Chopper circuits for DC motor control

DC motor drives are used for many speed and positioncontrol systems where their excellent performance, easeof control and high efficiency are desirable characteristics.DC motor speed control canbe achieved using switchmodeDC-DC chopper circuits. For both mains-fed and batterysupplied systems, power MOSFETs and FREDFETs arethe ideal switching devices for the converter stage. ThePhilips range of PowerMOS devices includes devicessuitable for most DC-DC converters for motor controlapplications. Additionally, due to the ease with whichMOSFETs and FREDFETs can be parallelled, PhilipsPowerMOS devices can easily be used in chopper circuitsfor both low power and high power DC motor drives forvehicle, industrial or domestic applications.

Introduction to DC motor drivesIn a DC motor, the static field flux is established using eitherpermanent magnets or a stator field winding. The armaturewinding, on the rotorof a dc machine, carries the main motorcurrent. The armature winding is a series of coils, eachconnected to segments of a commutator. In order that themotor develops constant torque as the rotor moves,successive armature coils must be connected to theexternaldc circuit. This is achievedusing a pair of stationarybrushes held in contact with the commutator.

The motor torque is produced by the interaction of the fieldflux and the armature current and is given by:

(1)

The back emf developed across the armature conductorsincreases with the motor speed:

(2)

Permanent magnet DC motors are limited in terms of powercapability and control capability. For field wound DC motorsthe field current controls the flux and hence the motor torqueand speed constants. The field winding can be connectedin series with the armature winding, in shunt with it, or canbe separately excited. For the separately excited dc motor,shown in Fig.1 the field flux is controlled and the motor canbe made to operate in two distinct modes: constant torqueoperation up to the rated speed of the motor, and thenconstant power operation above rated speed, as shown inFig.2. The steady state operation of the motor is describedby:

(3)

For normal motor operation Ea and Ia are positive and themotor is operating in its ’first quadrant’. The motor is saidto be operating in its second quadrant, that is braking orregenerating, by reducing Va below Ea such that Ia isnegative. These two quadrants are shown in Fig.3a). If thepolarity of the applied voltage is reversed then motoringand regenerating operation can occur with the direction ofrotation reversed. Thus by controlling the armature voltageand current polarities, full four-quadrant operation, asshown in Fig.3b), can be achieved.

Fig.1. Separately excited DC motor

Fig.2. DC motor, operating characteristics

Va

RaLa

EaLf

RfIf

Vf

Ia

Te α Ia

Rated (base)speed

Speed

Speed

Speed

VaEa

Ia

If

TorqueFlux,

CONSTANT

TORQUE

CONSTANT

POWER

Ea α ωm

Va = Ea +Ra . Ia

285


a) Two quadrant operation

b) Four quadrant operation

Fig.3. Torque speed characteristics for DC motor

Converter topologies for DC motor drives

Single quadrant (step down) converterFor single quadrant operation the chopper circuit of Fig.4can be used. The average voltage applied to the motor, andhence its speed, is controlled by varying the duty cycle ofthe switch, S. Fig.5 shows the switching waveforms for thecircuit. During the on time, ton, the supply voltage, Vdc, isapplied to the motor and the armature current starts toincrease. Neglecting the on-state resistance of the switchand the armature winding resistance the voltage across thearmature inductance is Vdc-Ea and so the rate of rise ofarmature current is given by:

(4)

When the switch turns off the energy stored in the armatureinductance must be dissipated. The polarity of the voltageacross La reverses, the diode D becomes forward biasedand the armature current continues to flow. Assuming thatthe motor speed remains constant and neglecting theforward voltage drop of the freewheeling diode the inductorvoltage is equal to -Ea. The rate of fall of armature currentis given by:

(5)

Fig.4. Single quadrant chopper circuit

Fig.5. Single quadrant chopper, switching waveforms

If this switching sequence is repeated at some frequency,then the motor voltage can be controlled by altering therelative duration of the on period and off period. Variationof the duty cycle of the switch (ton/T) to control the motorvoltage is referred to as Pulse Width Modulation (PWM)control. As the average voltage across the inductor over aperiod must be zero then:

(6)

The integral of inductor voltage for the interval ton

corresponds to the shaded area1 in Fig.5, whilst the integralof inductor voltage for the toff interval corresponds to theshaded area 2 in the Figure. These two areas must be equaland so from equations 4 to 6 or Fig.5 the transfer functionof the controller is given by:

(7)

Ea

Ia

REGENERATING

Ea

Ia

MOTORING

Torque,Current

Speed,Voltage

VaRaLa

IaVLa

Ea

S

VdcD

Ea

Ia

REGENERATING

Ea

Ia

MOTORING

Torque,Current

Speed,Voltage

Ea

Ia

REGENERATING

Ea

Ia

MOTORING

Switch, S ON ON ONOFFOFF

t

t

t

t

tton toffT

voltage, V a

current, I a

voltage, V La

current, I D

current, IS

VdcEa

Vdc- Ea

-Ea

ImaxImin

Ia

1

2

Motor

Motor

Inductor

Diode

Switch

⌠⌡0

T

vL.dt = ⌠⌡0

ton

vL.dt + ⌠⌡ton

T

vL.dt = 0dIadt

=Vdc−Ea

La

Va =ton

T.Vdc

dIadt

= −Ea

La

286


Two quadrant, half-bridge converterFigure 6 shows a half bridge circuit for two quadrant dcdrive. For motoring operation S1 and D2 operate asdescribed above for the single quadrant controller. Thefreewheel diode D2 may be the internal diode of a MOSFETor FREDFET, or a discrete device. For regenerativeoperation the DC motor acts as the active power sourceand the power flow is from right to left in Fig.6. Theregenerating current is controlled by varying the duty cycleof S2. When S2 is on, the negative armature currentincreases through the switch and the armature inductance.When S2 is turned off D1 becomes forward biased and thecurrent regenerates into the supply. The relevant circuitwaveforms are shown in Fig.7, showing the equal areas ofthe inductor volt-seconds over each period of the switchingcycle. During regeneration the transfer function of theconverter is given by:

(8)

Fig.6. Two quadrant half bridge chopper circuit

Fig.7. Two quadrant half bridge chopper, switchingwaveforms

Four quadrant, full-bridge converterIf motoring and regenerating operation are required withboth directions of rotation then the full bridge converter ofFig.8 is required. Using this configuration allows the polarityof the applied voltage to be reversed, thus reversing thedirection of rotation of the motor. Thus in a full bridgeconverter the motor current and voltage can be controlledindependently. The motor voltage Va is given by:

(9)

where V12 is controlled by switching S1 and S2 as describedabove, and V34 by switching S3 and S4. Theusual operatingmode for a full bridge converter is to group the switchingdevices so that S1 and S3 are always on simultaneouslyand that S2 and S4 are on simultaneously. This type ofcontrol is then referred to as bipolar control.

Fig.8. Four quadrant full bridge circuit

MOSFETs and FREDFETs in bridgecircuitsIn a bridge circuit, conduction transfers between theswitching devices and freewheeling diodes as the loadcurrent is controlled (eg. switch S2 and diode D1 in Fig.4).Associated with the transfer of conduction between thefreewheel diodes and the switching devices is the reverserecovery of the diode as each conducting MOSFET returnsto its on-state. Reverse recovery current flows due to theremoval of stored charge from a diode PN junction followingconduction. Fig.9 shows the device current paths in a halfbridge circuit when conduction is transferred from the topdiode to the bottom MOSFET.

The switching waveforms are shown in Fig.10 where thediode reverse recovery current is Irr and the time taken forthe reverse recovery currents to be cleared is trr. Theamount of stored charge removed from the body of thediode is represented by the area Qrr. The reverse recoverycurrent flows through the MOSFET which is being turnedon in addition to the load current and thus causes additionalturn-on losses. The amount of stored charge increases withincreasing temperature for a given diode. Both the

Va = V12−V34

Va =1−

ton

T

.Vdc

RaLa

IaVLa

S2

VdcS1 D1

D2 S3

S4 D4

D3

Ea

Va

Va

RaLa

IaVLa

EaS2

VdcS1

D1

D2

Switch, S2 ON ON ONOFFOFF

t

t

t

t

tton toffT

voltage, Va

current, I a

voltage, VLa

current, ID1

current, IS2

VdcEa

Vdc- Ea

-Ea

ImaxImin

Ia

1

2

Motor

Motor

Inductor

Diode

Switch

287


magnitude of the reverse recovery current and its durationmust be reduced in order to reduce the switching losses ofthe system.

This effect is important because inherent in the structure ofa power MOSFET there is a diode between the source anddrain of the device which can act as a freewheeling diodewhen forward biased. For most DC motor controlapplications the reverse recovery characteristics of theMOSFET intrinsic diode are acceptable and do notcompromise the switching performance of the half bridgecircuit. However, the characteristics of a MOSFET intrinsicdiode are not optimised for minimum reverse recovery andso, especially in high frequency systems, the FREDFET ismore suitable for use in half bridge circuits.

Fig.9 Current paths in half bridge circuit.

Fig.10 Diode reverse recovery waveforms.

The FREDFET is essentially a MOSFET with a very fastbuilt-in diode where the reverse recovery properties of aFREDFET diode are similar to those of a discrete fastrecovery epitaxial diode (FRED). This gives improvedswitching performance in high frequency applications.

Considerations for converter driven DCmotors

Device current ratingThe power electronic converter must be matched to therequirements of the motor and the load. DC motor drivescan be used to provide torques in excess of the maximumcontinuous rated torque of the motor for short intervals oftime. This is due to the long thermal time constants of themotor. The peak torque requirement of the motor willdetermine its peak current demand, and hence the peakcurrent requirement for the power switches. The currentrating of a PowerMOS device is limited by the maximumjunction temperature of the device, which should not beexceeded even for short periods of time due to the shortthermal time constant of the devices. The devices mustthereforeberated for thispeak currentcondition of the drive.Operation at maximum current usually occurs duringacceleration and deceleration periods necessary to meetthe performance requirements of DC servo systems.

Device voltage ratingThe voltage rating of the power switches will be determinedby the power supply DC link voltage and the motor emfs,including those which occur when the motor is operating inits constant power region at above rated speed but belowrated torque.

Motor performanceIt can be seen from the waveforms of Figures 5 and 7 thatthe armature current supplied to the motor by the switchingconverter is not constant. The presence of ripple current inaddition to the normal DC current affects the performanceof the motor in the following ways:

Torque pulsations. Ripple in the motor current waveformwill cause a corresponding ripple in the motor output torquewaveform. These torque pulsations may give rise to speedfluctuations unless they are damped out by the inertia ofthe mechanical system. The torque pulsations occur at highfrequencies where they may lead to noise and vibration inthe motor laminations and mechanical system.

Losses. Winding losses in a DC motor are proportional toiRMS

2, whereas the torque developed by the motor isproportional to iDC. Ripple in the motor current will increasethe RMS current and thus give rise to additional losses andreduce the system efficiency.

Overcurrents. If the ripple current is large then the peakdevice current will be significantly higher than the designDC value. The devices must then be rated for this highercurrent. Current ripple will also increase the current whichmust be handled by the motor brushes possibly increasingarcing at the brush contacts.

Vdc

I LI rr

IL

IL

MOSFET current

Diodecurrent

Outputvoltage I rr

t rr

Time

Time

Time

IL+ I rr

Vdc

Q rr

288


The amount of current ripple depends primarily upon theswitching frequency and amount of motor inductance (Seeequations 4 and 5). Increasing La and fs will both reduce theamount of current ripple. The motor inductance is fixed bythe motor selection but can be increased by the addition ofa discrete component. Increasing the switching frequencyof the system will reduce the amount of current ripple butwill increase the switching losses in the power devices.

Using PowerMOS devices in DC drives

For many applications the motor control system is operatedat switching speeds in the range 1kHz to 20kHz.PowerMOS devices are ideally suited for this type ofconverter giving the following advantages:

Switching performanceUnlike bipolar devices the MOSFET is a majority carrierdevice and so no minority carriers must be moved in andout of the device as it turns on and off. This gives the fastswitching performance of MOSFET devices. However, athigher switching speeds the switching losses of the systembecome important and must be considered in addition tothe device on-state losses. The device conduction lossdepends on the MOSFET on-state resistance, RDS(ON),which increases with the temperature of the device.Switching times are essentially independent of devicetemperature. PowerMOS devices have good overloadcapability and Safe Operating ARea (SOAR) which makesthem easy to us in a chopper circuit, although the need forsnubber circuits will depend on the system operating andperformance requirements.

Fig.11. MOSFET capacitances and basic gate driver

Ease of usePowerMOS devices are essentially voltage driven switchesand so the gate drive circuits required to switch the devicesare usually relatively simple low power circuits. It is onlyduring switching instants that the gate drive is that requiredprovide current in order to charge and discharge the devicecapacitances (shown in Fig.11) and thus switch the device.In order to switch the device quickly the gate driver mustbe able to rapidly sink and source currents of up to 1A. Forthe simplest gate drive circuit the MOSFET can be switchedusing a resistive drive and some gate-source overvoltageprotection, as shown in Fig.11. Alternative MOSFET gatedrive circuits are discussed more fully elsewhere in thishandbook.

Parallelling of PowerMOS devicesIt is usually straightforward to operate PowerMOS devicesin parallel to achieve higher system currents than can beachieved using single devices. The problems of parallellingPowerMOS are much less than those which occur whenusing bipolar devices. MOSFETs and FREDFETs have apositive temperature coefficient of RDS(ON) and so tend toshare the total load current equally. Any discrepancy indevice or circuit resistance which causes one device to becarrying a higher proportion of the total current will causethe losses in that device to increase. The device carryingthe increased current will then heat up, its resistance willincrease and so the current carried will be reduced. Thetotal load current will therefore be equally shared outbetween all the parallelled MOSFETs. Current sharingduring dynamic (switching) instants is achieved by ensuringgood circuit design and layout.

Fig.12. Gate drive circuit for parallelled devices

Moving to a system using parallelled MOSFETs requiresonly slight modifications to the gate drive circuit. Oneconsideration may be the capability of the drive circuit toprovide the currents required at the switching instants. It isrecommended that small differential resistors, as shown inFig.12, are used to damp out any oscillations which mayoccur between the switching devices and the rest of thecircuit.

RGGF 47RRGG’ 10R

RGG’ 10R

C DS

CGD

CGS

D

S

GR GGV

GG

289


Fig.13. DC drive system - schematic arrangement

++_ _

VoltageError

AmplifierSpeed

Command

SPEED FEEDBACK

CURRENT FEEDBACK

CurrentLimit

Motor/RegenerateAmplifier

MOTORING

REGENERATING

Gatedrive

Isolationand gate

drive

Vdc

CurrentCommand

Motor Tacho

Controller

Circuit layout considerationsThe effects of poor circuit design and layout are to increaseRFI and noise and to compromise the performance andspeed of the system due to stray inductances. Theprecautions which must be taken to minimise the amountof stray inductance in the circuit include:

• positioning the gate drive circuits as close as possible tothe power MOSFETs.

• reducing circuit board track lengths to a minimum andusing twisted pairs for all interconnections.

• for parallelled devices, keeping all connections short andsymmetrical.

DC motor control system

Figure 13 shows a schematic arrangement for a twoquadrant controller, showing the outer speed control loopand the inner current control loop. The speed feedbacksignal is derived from a tachogenerator (TGF), althoughalternatively an approximation to the motor speed can bederived by feeding back a signal proportional to the motorvoltage, (AVF). Position feedback can be included for servoapplications by using a position encoder on the motor shaft.The speed feedback loop compares the tacho- outputvoltage with a speed reference signal. The voltage errorsignal gives the current reference command.

The current command signal is compared with the actualmotor current in the inner control loop. This control loopincludes a current limit setting which protects the motor andthe devices from overcurrents. If the controller demands alarge speed change then the current demand is maintainedbelow the maximum level by this current limit setting.Motoring or regenerating operation is detected directly fromthe polarity of the voltage error signal and used to determinewhether it is the top or bottom MOSFET which is controllingthe current.Themotoring/regenerating logic circuit includessome hysteresis to ensure that control does not oscillatebetween the motoring and regenerating modes at low motorcurrents.

There are severalpossible ways of controlling motor currentby controlling the switching sequences to the mainPowerMOS devices. In tolerance band control the motorcurrent is compared with the reference signal and anallowed current ripple tolerance. During motoring operationif the actual current is greater than the allowed maximumvalue of the tolerance band then the output comparatorturns off the gate drive to the power MOSFET thus allowingthe motor current to fall. The current then freewheels untilit reaches the lower limit of the tolerance band, when thecomparator turns the MOSFET back on. Using this currentcontrol strategy the effective switching frequency isvariable, depending on the rate at which the armaturecurrent changes, but the peak to peak current ripple in thesystem is constant. Alternatively the devices can be

290


switched a constant frequency using a PWM methodcurrent control. Here the current error signal is comparedwith a fixed frequency triangular wave and the comparatoroutput is then used to provide the signal for the mainswitching devices. When the error signal is greater than thetriangular wave then the power device is switched on, whenthe error signal is less than the triangular carrier then thedevice is switched off.

ConclusionsDC motor controllers using PowerMOS devices can beused in many speed control and servo applications givingexcellent drive performance. The advantages ofPowerMOS devices include their simple gate drive

requirements, rugged performance and their ease of usein parallel configurations. The intrinsic diode between thedrain and source of MOSFETs andFREDFETs can be usedas the freewheel diode in half bridge and full bridge circuitconfigurations giving a cost effective, compact design withthe minimum of switching devices. PowerMOS chopperscan operate at much higher switching frequencies thanthyristor or power transistor controllers, giving reducedcurrent ripple, reduced noise and interference and gooddynamic system response. Using higher switchingfrequencies reduces the need for additional discreteinductances in the motor circuit whilst still achieving lowripple currents in separately excited, permanent magnetand series connected field wound motors.

291


3.2.2 A switched-mode controller for DC motors

The purpose of this paper is to demonstrate the use of anintegrated switched-mode controller generally used for DCpower conversion as the primary control and element in apractical Pulse Width Modulated (PWM) DC drive. Basicprinciples relating to DC motor specifications and drivefrequency are presented. The PWM method ofswitched-mode voltage control is discussed with referenceto armature current control, and hence output torquecontrol, of DC motors. A series of circuit configurations areshown to illustrate velocity and position servo applicationsusing a switched mode driver IC. Philips Semiconductorsproduce a wide range of control ICs for Switched ModePower Supply (SMPS) applications which can also be usedas controllers for PWM driven DC motors. This paperdemonstrates how one switched-mode controller, theNE5560, can be used to give a velocity and position servosystems using Philips power MOSFETs as the main powerswitches. Additional application ideas using the NE5560controller for constant speed and constant torque operationare also presented.

Fig.1 DC motor, equivalent circuit

Principles of the PWM DC motor drive

Pulse width modulated drives may be used with a numberof DC motor types: wound field or permanent magnet. Thediscussion here will be particularly concerned withpermanent magnet excited DC motors. This does notimpose a restriction on the applicability of switched modecontrol for DC drives since permanent magnet motors areavailable in awide range of sizes, ratings andconfigurationsto suit many applications. The design of a pulse widthmodulated drive is affected by the characteristics of the DCmotor load, and this will now be considered in more detail.

The permanent magnet DC motor may be represented bythe simplified equivalent circuit shown in Fig.1. La

represents the total armature inductance, Ra is theequivalent series resistance, and Ea the armature back emf.This induced emf represents that portion of the total input

energy which is converted to mechanical output. Themagnitude of the armature emf is proportional to motorspeed.

Motor inductance, which may vary from tens of µH to mH,will have a significant effect on PWM drive designs. This isdue to the fact that average motor current is a function ofthe electrical time constant of the motor, τa, where. τa=La/Ra.For a PWM waveform with a period T the ratio of pulse widthto switching period is denoted by δ. The average pulsecurrentwill depend upon the ratio of the current pulse-width,δT, to the motor electrical time constant, τa.

Fig.2 Instantaneous motor current waveformsa) High inductance motor, τa = 5Tb) Low inductance motor, τa = T/2

Figure 2 shows the conditions for two different motors anda fixed period PWM waveform. For the casewhen the motortime constant is much greater than the pulse width, inFig.2(a) then the current cannot be established in theinductive motor windings during the short duration of theapplied pulse. For a low inductance motor and the samepulse width, Fig.2(b), the armature current is easilyestablished. In most instances a motor which has higharmature inductance will require a lower PWM drivefrequency in order to establish the required current levels,and hence develop the necessary torque. A low inductancemotor allows the use of a high switching drive frequencythus resulting in an overall faster system response.

In general, to achieve optimum efficiency in a PWM motordrive at the highest practical frequency, the motor shouldhave an electrical time constant, τa, close to the duration ofthe applied waveform T. ( τa= kT where k is small). Theprinted circuit motor is one of the lowest inductance DCmotors available since the armature is etched from a flatdisc-like material much like a double-sided printed circuitboard. Consequential these low inductance, low inertia

dTT

Vdc

dTT

Vdc

a) b)va va

i ai a

Va

RaLa

Ea

Ia

293


motors also exhibit very fast response with quite hightorque. Electrical time constants in the order of 100µs allowthese motors to be used with switching rates as high as100kHz, with typical drive circuits being operated at 10kHz.

Thus an appropriate choice of switching frequency andmotor inductance ensures a high average motor currentduring each switching pulse. Motor current control, andhence torque control, is achieved by varying the width ofthe applied pulsed waveforms. As the base, or carrier,frequency is held constant then the pulse width relaystorque control information to the motor. Torque isdependent on average motor current (equation 1) which, inturn, is controlled by duty cycle.

(1)

Fig.3 Simplified PWM DC motor controller

PWM motor controlThe PWM method of current control will be considered byexamining the conditions at motor start-up for a simplearrangement, shown in Fig.3, where the duty cycle iscontrolled using the DC control voltage, VREF. At start-upthe duty cycle is adjusted to be long enough to give sufficientmotor starting torque. At zero rotational velocity (ω=0) theback emf, Ea, is zero and so the full DC voltage appearsacross the series Ra/La impedance. The initial motor currentis determined according to the equation:

(2)

If the duty cycle ratio, controlled using VREF, is given by δ,then the duration of the ’ON’ pulse is simply given by δT.Duringthis interval the riseof motor currentprior toarmaturerotation is shown by Equation 3.

(3)

The current in the motor windings rises exponentially at arate governed mainly by average supply voltage and motorinductance. If the pulse width is close to the time constantof the motor then the current at the end of the first pulsewill reach nearly 60% of its maximum value, Imax = Vdc/Ra.This is shown as I1 in Fig.4. For the remainder of the PWMcycle switch S1 is off and motor current decays through thediode at a rate dependant upon the external circuitconstants and internal motor leakage currents, accordingto the equation:

(4)

The motor current at the end of the period, T, remains at alevel I2, which is then the starting current for the next cycle,as shown in Fig.4. As the switching sequence repeats,sufficient current begins to flow to give an acceleratingtorque and thus cause armature rotation. As soon asrotation begins, back emf is generated which subtracts fromthe supply voltage. The motor equation then becomes:

(5)

Thecurrent drawn from the supply will consequently be lessthan that drawn at start-up due to the effect of the motorback emf term, Ea. For a given PWM duty cycle ratio, δ, themotor reaches a quiescent speed governed by the loadtorque and damping friction. Maximum motor torque isrequired at start-up in order to accelerate the motor andload inertias to the desired speed. The current required atstart-up is therefore also a maximum. At the end of thestarting ramp the controller duty cycle is reduced becauseless current is then needed to maintain the motor speed atits steady state value.

Fig.4 Motor current waveforms at start-up

ia = I1 .e−(t − δT) /τa

Te = KT Ia

Vdc

Motor

PWM

PULSE WIDTHADJUST

VREF

Load

Te

Ia

La.diadt

+ Ra.ia = Vdc−Ea

Vdc

va

iaImax

I1

I2dT

T

t

t

La.diadt

+ Ra.ia = Vdc

ia =Vdc

Ra

.1− e−t /τa

294


Fig.5 Motor current waveform, τa << T

For a low inductance motor where the electrical timeconstant is much less than the duty cycle then the motorcurrent waveform will closely follow the applied voltagewaveform, as shown in Fig.5. An approximate expressionfor the average motor current is given by:

(6)

In summary, the principle control variable in the PWM motorcontrol system is ’duty cycle’, δ. Motor torque and velocitycan be tightly controlled by controlling the PWM duty cycleand motor current.

The switched mode controllerFor the remaining portion of the paper integratedswitched-mode control will be considered with specificreference to the NE/SE5560 controller IC. This deviceincorporates control and protection functions for SMPS andDC motor control applications including internaltemperature compensation, internal reference voltages, asawtooth waveform generator, PWM amplifier and outputstage. Protection circuitry includes cycle-by-cycle currentlimiting, soft start capability, overcurrent protection, voltageprotection and feedback loop protection circuits. In thefollowing sections some of the features of the controller willbe examined and its use in a number of motor drive designswill be presented.

Current

VoltageVdc

Ea Motor emf

t

Iave= δ.(Vdc−Ea)

Ra

295


Fig.6 NE5560 Block diagram

Fig.7 Unipolar switched mode motor drive (SMMD) using the NE5560

296


The device (see Fig.6) contains an internal voltagereference which is connected to the non-inverting input ofthe error amplifier. The feedback signal is obtained fromeither a tachogenerator (TGF - tachogenerator feedback)or from a signal proportional to the armature voltage lessthe winding iR voltage drop (AVF - armature voltagefeedback). This feedback signal must be scaled to centreabout the internal voltage reference level. The erroramplifier output, in addition to being available for gainadjustment and op amp compensation, is connectedinternally to the pulse-width modulator. Frequency may befixed at any value from 50Hz to 100kHz and duty cycle

adjusted at any point from 0 to 98%. Automatic shut-downof the output stage occurs at low supply threshold voltage.The error amplifier has 60dB of open loop gain, is stablefor closed loop gains above 40dB and can also can becompensated for unity gain. The single ended switchingoutput is from either the emitter or collector of the outputstage. The device has protective features such as highspeed overcurrent sense which works on a cycle-by-cyclebasis to limit duty cycle, plus an additional second level ofslow start shutdown. It is this input which can be adaptedto act as a motor torque limit detector.

a) Unipolar drive b) Bipolar driveFig.8 Constant speed servo configurations

Vdc

Motor Load

Te

Tacho

VREF

+Vdc

Motor Load

Te

Tacho

VREF

-Vdc

297


Fig.9 Basic unidirectional drive with dynamic braking

Open loop PWM control using the NE5560For a given application the switched-mode controllerfrequency should be set to allow the best dynamic responseconsidering the starting current requirement and motorelectrical time constant, as discussed previously. The maindrive transistors or MOSFETs must be capable of carryingthe peak motor current requirement which occurs atstart-up. Device protection using snubber networks andtransient suppression networks will depend on the choiceof switching device, system ratings and the applicationrequirements. Power MOSFETs provide an excellentsolution to many DC drive designs since very low drivepower is required and they are self-protected from reversetransientsby an internal intrinsic diode. PowerMOSdevicesmay be parallelled for added power handling capability.

Figure 7 shows a simple unipolar drive capable of drivinga low voltage motor supplied from an external DC voltageand PWM controlled using the NE5560.

Constant velocity servoFigure 8 shows in block form the general circuit used toobtain a constant speed switched mode motor drive(SMMD) servo. Figure 8(a) shows a unipolar drive usingDC tachometer feedback to the PWM error amplifier. Figure8(b) shows a bidirectional drive in a half-bridge

configuration. In this case the duty cycle controls thedirection of motor rotation in addition to the motor speed.A 50% duty cycle corresponds to the standstill condition. Ifthe average duty cycle is greater than 50% (CW command)then the motor accelerates clockwise, and vice-versa forCCW rotation when the duty cycle is less than 50%. Thiscircuit configuration can be used for both velocity andposition servo-designs. The reversing switch allows thetachogenerator output to match the polarity of the PWMreference, which is always positive.

The unipolar drive circuit in Fig.9 uses the NE5560 todevelop a SMMD with constant speed control suitable fora small DC motor. The switching device is a single PhilipsBUK456-100A Power MOSFET capable of over 30 A, witha voltage rating of 100V VDSand RDS(ON)=0.057Ω. The PWMdrive from the NE5560 is applied to the gate at a nominal10kHz,although muchhigher frequencies are possible.Thepeak gate to source voltage, VGS, is 15V to ensure minimumRDS(ON) and hence minimum loss in the PowerMOS switch.

A sense resistor is placed in the source lead to monitormotor drive current on a cycle-by-cycle basis. The value ofthis resistor is set to develop the error amplifier thresholdvoltage at the desired maximum current. The NE5560 thenautomatically limits the duty cycle, should this threshold beexceeded. This is therefore used as an auto torque limitfeature in addition to simply protecting the switching device.

298


A slow start network (Pins 2,5,6) gradually ramps up theduty cycle at power on. Fixed braking duty cycle control isachieved by forcing the input error amplifier during brakingconditions. The over-current circuit is still active duringbraking.

SMMD Position servo with µP controlBy coupling the switched mode motor drive in a bidirectionalconfiguration as shown in Fig.10, and then sensing linearposition with a potentiometer or LVDT connected to a leadscrew, for instance, the position feedback loop can beclosed to give a position servo. The input to control positionof the mechanical stage may be fed as a DC offset to asumming amplifier whose output is fed to Pin 5 of theNE5560, as shown. Forward lead-lag compensation maybe combinedwith the summing amplifier function to achievea stable response. A velocity loop may be closed through

the error amplifier at Pin 3. The controller may easily beinterfaced to a microprocessor by means of a unipolar D/Aconverter working in the 1 to 6V output range as an inputto Pin 5.

Conclusions

Theswitched-mode motor drive, SMMD, using small, easilyavailable, monolithic integrated control devices designedfor switched-mode power applications may easily beadapted to perform a number of useful and efficient torque,velocity and position control operations. The readyavailability of good controller ICs, easily compatible with thePhilips range of switching power devices in both bipolar andPowerMOS technologies makes such designs even moreeffective and easily attainable by the control systemsdesigner.

Fig.10 Microprocessor control of PWM drive with four quadrant control

S2

S1D1

D2S3

S4D4

D3

POSITION

VELOCITYERROR

D/A

P

DIRECTIONLOGIC

NE5560

Vdc

0V

MOTOR

299


3.2.3 Brushless DC Motor Systems

In recent years the number of drive systems available todesigners has increased considerably. The advent andincreasing use of stepper motors, inverter-fed ac machines,switched reluctance motors and brushless machines haveall addressed particular applications and in some casesthese application areas overlap. The correct choice of adrive system for a particular application depends not onlyupon the speed and torque requirements but also onperformance, response, complexity and cost constraints.The brushless DC motor (BDCM) system is emerging asone of the most useful drive options for a wide range ofapplications ranging from small, low power fans and discdrives, through medium size domestic appliance motorsand up to larger industrial and aviational robotic and servodrives.

This section will review the theory and operation ofbrushless DC motors and describe some of theconsiderations to be made when designing BDCM drivesystems using PowerMOS devices as the main inverterswitches.

BackgroundThe principal advantage of a conventional DC machinecompared to an AC machine is the ease with which a DCmotor can be controlled to give variable speed operation,including direction reversal and regenerative brakingcapability. The main disadvantage of a DC machine is thatthe carbon brushes of a DC motor generate dust and alsorequire maintenance and eventual replacement. The RFIgenerated by the brushgear of a DC motor can be quitelarge and, in certain environments, the sparks themselvescan be unwelcome or hazardous. The brushless DC motorwas developed to achieve the performance of aconventional DC machine without the problems associatedwith its brushes.

The principal advantages of the BDCM system are:

• Long life and high reliability• High efficiency• Operation at high speeds and over a wide speed range• Peak torque capability from standstill up to high speeds• Simple rugged rotor construction• Operation in vacuum or in explosive or hazardous

environments• Elimination of RFI due to brush commutation

DC motor configurationsIn a conventional DC motor the field energy is provided byeither a permanent magnet or a field winding. Both of thesearrangements involve quite large, bulky arrangements forthe field. In the case of wound field DC motors this is due

to large number of turns needed to generate the requiredelectromagnetic field in the airgap of the machine. In thecase of permanent magnet DC machines the low energydensity of traditional permanent magnet materials meansthat large magnets are required in order to give reasonableairgap fluxes and avoid demagnetisation. If either of thesetwo options are used with the field excitation on the rotorof the machine then the inertia and weight of the rotor makethe machine impractical in terms of its size and dynamicresponse.

A conventional DC machine has a large number of armaturecoils on the rotor. Each coil is connected to one segmentof a commutator ring. The brushes, mounted on the stator,connect successive commutator segments, and hencearmature coils, to the externalDC circuitas the motor movesforward. This is necessary to maintain maximum motortorque at all times. The brush/commutator assembly is, ineffect, a rotating mechanical changeover switch whichcontrols the direction and flow of current into the armaturewindings.

In a BDCM the switching of current to the armature coils iscarried out statically and electronically rather thanmechanically. The power switches are arranged in aninverter bridge configuration in order to achievebidirectional current flow in the armature coils, i.e. twopower switches per coil. It is not possible to have a largenumber of armature coils, as is the case for a conventionalDC motor because this would require a large number ofswitching devices and hence be difficult to control andexpensive. An acceptable compromise is to have only threearmature coils and hence six power switches. Reducing thenumber of armature coils means that the motor is moreprone to developing ripple torque in addition to the requiredDC torque. This problem can be eliminated by good designof the motor. The armature of a three coil brushless DCmachine in fact looks similar to the stator of a three phaseAC machine and the term ’phase’ is more commonly usedto describe these three separate coils.

The development of brushless DC machines has madepossible by developments in two other technologies:namely those of permanent magnet materials and powersemiconductor switches.

Permanent magnet materialsTraditional permanent magnet materials, such as AlNiComagnets and ferrite magnets, are limited either by their lowremanence giving rise to a low airgap flux density inelectrical machines, or by their susceptibility todemagnetisation in the presence of high electric fields.However in recent years several new permanent magnetmaterials have been developed which have much higher

301


a) Conventional DC motorb) Brushless DC motor

Fig.1 DC motor configurations

Stator core

Field magnet

Armaturecoils

Ia

Rotor

Commutator

Brush

Stator core

winding

Fieldmagnet

Rotor

A

B

C

Phase

I

I

I

remanent flux densities, and hence airgap flux densities,and high coercivities, making them resistant todemagnetisation under normal operating conditions.Amongst these materials, called ’rare earth’ magnets,Samarium Cobalt (SmCo5 and Sm2Co17) and Neodymium--Iron-Boron (Nd-Fe-B) are the most common. Thesematerials, although still quite expensive, give vastlysuperior performance as the field excitation for a brushlessmachine.

Due to the increased energy density of rare earth magnetsthe amount of magnet material required by the applicationis greatly reduced. The magnet volume using rare earthsis small enough that it is feasible to have the permanentmagnet field on the rotor of the machine instead of on thestator. The gives a low inertia, high torque motor capableof high performance operation. This resulting motor design,with the armature on the stator and the field on the rotorand shown in Fig.1, can be considered as a conventionalDC motor turned ’inside out.’

Power electronic switchesFor the ’inside out’ BDCM is it still necessary to switch thearmature current into successive armature coils as the rotoradvances. As the coils are now on the stator of the machinethe need for a commutator and brushgear assembly hasdisappeared. The development of high voltage and highcurrent power switches, initially thyristors, bipolar powertransistors and Darlingtons, but more recently MOSFETs,FREDFETs, SensorFETs and IGBTs, has meant thatmotors of quite large powers can be controlledelectronically, giving a feasible BDCM system. Thequestion of appropriate device selection for brushless DCdrives will be considered later.

System description (Fig.2)

DC power supplyThe fixed DC voltage is derived from either a battery supply,low voltage power supply or from a rectified mains input.The input voltage may be 12V or 24V as used in manyautomotive applications, 12V-48V for applications such asdisc drives or tape drives, or 150V-550V for single-phaseor three-phase mains-fed applications such as domesticappliances or industrial servo drives or machine tools.

InverterThe inverter bridge is the main power conversion stage andit is the switching sequence of the power devices whichcontrols the direction, speed and torque delivered by themotor. The power switches can be either bipolar devicesor, more commonly, PowerMOS devices. Mixed deviceinverters, for example systems using pnp Darlingtons asthe high side power switches and MOSFETs as the low sideswitches, are also possible. The freewheel diodes in eachinverter leg may be internal to the main power switches asin the case of FREDFETs or may be separate discretedevices in the case of standard MOSFETs or IGBTs.Detailed considerations of inverter design, gate drivedesign and layout have been considered in separatearticles.

The inverter switching speed may be in the range 3kHz to20kHz and above. For many applications operation atultrasonic switching speeds (>15-20kHz) is required inorder to reduce system noise and vibration, reduce theamplitude of the switching frequency currents and toeliminate switching harmonic pulsations in the motor.Because of the high switching speed capability ofPowerMOS devices they are often the most suitable devicefor BDCM inverters.

302


Fig.2 BDCM system

S2

S1 D1

D2 S4

S3 D3

D4 S6

S5 D5

D6

DC PowerSupply

ControllerCurrent setSpeed set

NS

HallEffect

devices

Gate drives

Motor

ic

ib

ia

Inverter

The first choice for the inverter devices might appear to beone with an N-channel MOSFET for the bottom device ineach inverter leg and a P-channel device in the top half ofeach leg. The disadvantage of P-channel devices is thatthey require around three times more silicon area thanequivalent N-channel MOSFETs to achieve the same valueof RDS(ON). This makes P-channel devices uncompetitivelyexpensive for many applications. However, usingN-channel devices for both the top and bottom switches inan inverter leg means that some sort of floating drive isrequired for the upper device. Transformer coupled oroptically coupled gate driver stages are required, oralternatively, circuits such as the bootstrap circuit shown inFig.3 can be used to provide the drive for the top device.

In the circuit of Fig.3 the bootstrap capacitor is charged upvia the diode D every time the bottom MOSFET is on. Whenthis device turns off the capacitor remains charged up tothe gate supply voltage as D is now reverse biassed. Whena turn-on pulse is applied for the upper MOSFET thebootstrap capacitor provides the necessary gate sourcevoltage to turn the device on.

MotorA two pole BDCM with the field magnets mounted on thesurface of the rotor and with a conventional stator assemblywas shown in Fig.1. Machines having higher numbers ofpoles are often used depending upon the applicationrequirements for motor size, rotor speed and inverterfrequency. Alternative motor designs, such as disc motorsor interior magnet rotor machines, are also used for someapplications. The motor phases are usually connected in astar configuration as shown in Fig.2. Rotor position sensorsare required in order to control the switching sequence ofthe inverter devices. The usual arrangement has three Halleffect sensors, separated by either 60˚ or 120˚, mountedon the stator surface close to the airgap of the machine. As

the rotor advances the switching signals from these HallEffect latches are decoded into rotor position informationin order to determine the inverter firing pattern.

In order to minimise torque ripple the emf induced in eachmotor phase winding must be constant during all instantsin time when that phase is conducting current. Any variationin a motor phase emf whilst it is energised results in acorresponding variation in the torque developed by thatphase. The so-called ’trapezoidal emf’ motor, shown inFig.4, has a constant induced emf for 120˚ and so is apractical motor design which gives optimum performancein a BDCM system.

ControllerThe inverter is controlled in order to limit the device currents,and hence control the motor torque, and to set the directionand speed of rotation of the motor. The average ouputtorque is determined by the average current in each phasewhen energised. As the motor current is equal to the DClink current (Fig.2) then the output torque is proportional tothe DC input current, as in a conventional DC motor. Themotor speed is synchronous with the applied voltagewaveforms and so is controlled by setting the frequency ofthe inverter switching sequence.

Rotor position feedback signal are derived from the Halleffect devices as discussed earlier or from opto-transducers with a slotted disc arrangement mounted onthe rotor shaft. It is also possible to sense rotor position bymonitoring the emfs in the motor phase windings but thisis somewhat more complex. In some applications the Halleffect sensor outputs can be used to provide a signal whichis proportional to the motor speed. This signal can be usedin a closed loop controller if required.

303


Fig.3 Bootstrap driver circuit for upper device ininverter bridge leg

Fig.4 Trapezoidal emf motor

Fig.5 Motor waveforms for BDCM system

The controller also requires a current feedback signal.Usually this is taken from the DC link of the inverter asshown in the Fig.2. The current is controlled using eitherPWM techniques or hysteresis type of control. A currentreference command is compared with the current feedbacksignal and then used to determine the switching signal tothe main power devices. Additional controller functionsinclude undervoltage protection, thermal protection andcurrent ripple limit controls, error amplifier inputs forincorporation in closed loop servos and microprocessorcompatible inputs.

Several IC manufacturers offer dedicated ICs providing allthe functions for PWM control of brushless DC motors. ThePhilips version of the NE5570 CMOS controller is one suchdevice which can be used for three phase BDCM systemsusing a serial data input command from a microprocessorcontroller. This device contains the PWM comparator andoscillator, dynamic current loop controller and outputpre-drivers suitable for a MOSFET power stage. Itsoperation is described more fully in Philips Application NoteAN1281.

Brushless DC motor operationThe operation of a BDCM system can be explained withreference to Fig.5. At any instant in time the rotor positionis known by the output states of the three airgap mountedHall effectdevices. Theoutputstate of oneHall effectdeviceswitches for every 60˚ of rotation, thus defining sixconduction zones as shown in the figure. The switching ofthe inverter devices is arranged to give symmetrical 120˚intervals of positive and negative constant current in eachmotor phase winding. The position of the sensors andcontroller logic ensures that the applied currents are inphase with the motor emfs in order to give maximum motortorque at all times.

Referring to Figures 2 and 5, during the first 60˚ conductionzone switches S1 and S4 are on and the current flowsthrough the ’A’ and ’B’ phase windings. The ’C’ phase isinactive during this interval. At the end of this 60˚ conductionzone one of the Hall effect devices changes state and soswitchS4 turns offand S6 turns on. Theswitching sequencecontinues as the motor advances. At any instant in time twomotor phases are energised and one motor phase is off.Themotor phase current waveforms are described as being’quasi-square’ in shape. The motor windings are energisedfor two thirds of the total time and the maximum switch dutycycle ratio is one third.

The other function of the controller is to maintain the motorphase currents at their desired constant value for each 120˚interval that a particular phase is energised. The precisemethod of current limiting depends upon the controlleralgorithm. In order to limit the current to its desired valueeither one or both of the conducting devices are switchedoff thus allowing the motor current to freewheel through the

S2

S1 D1

D2

D

C

Vout

15V

Vdc

0V

60 120 180 240 300 360

eA

eB

eC

(wt)

(wt)

(wt)

S1S4

S1S6

S3S6

S3S2

S5S2

S5S4

O 60 120 180 240 300 360

iA

iB

iC

Sensoroutputs

Phasecurrents

ActiveDevices

304


bridge leg diodes. The current is limited by controlling theswitch duty cycle to ensure that device current ratings andthe motor current rating are not exceeded, especially duringstart-up conditions or low speed operation. The amount ofcurrent ripple is controlled by the switching frequency of aPWM waveform or by the width of a hysteresis band.

Power Semiconductor switches forBrushless DC motorsPhilips Semiconductors produce a range of powersemiconductor devices suitable for use in BDCM systems.The include transistors, MOSFETs, FREDFETs, LogicLevel MOSFETs (L2FETs) and IGBTs. These devices areavailable in a variety of current and voltage ratings and arange of packages, to suit individual applications.

FREDFETsFor higher voltage applications the FREDFET is anappropriate device for the inverter switches in a brushlessDC drive. The FREDFET is a PowerMOS device where thecharacteristics of the MOSFET intrinsic diode have beenupgraded to those of a discrete fast recovery diode. Thusthe FREDFET is ideally suited to bridge circuits such asthat shown in Fig.2 where the recovery properties of thebridge diodes significantly affect the switching performanceof the circuit. Fig.6 shows a conventional MOSFET inverterbridge circuit, where the MOSFETs intrinsic diode isdisabled by a series Schottky diode. A discrete antiparallelFRED carries the motor freewheeling current. Using theFREDFET reduces the component count and circuit layoutcomplexity considerably.

MOSFET inverter leg FREDFET inverter legFig.6 MOSFET and FREDFET half bridge legs

L2FETsFor many lower voltage applications logic level FETs(L2FETs) can be used to interface the power circuit withstandard TTL or CMOS drive circuits without the need forlevel shifting stages. L2FETs require gate source voltageof only 5V to be fully turned on and typically have VGS(th) =1-2V. Using Philips L2FETs in BDCM applications such as

tape or disc drives where the MOSFETs are driven directlyby a controller IC produces an efficient overall design withthe minimum of gate drive components.

IGBTsIGBTs are especially suited to higher power applicationswhere the conduction lossesof aMOSFET begin to becomeprohibitive. The IGBT is a power transistor which uses acombination of both bipolar and MOS technologies to givea device which has low on-state losses and is easy to drive.The IGBT is finding applications in mains-fed domestic andindustrial drive markets. By careful design of the devicecharacteristics the switching losses of an IGBT can beminimised without adversely affecting the conductionlosses of the device too severely. Operation of BDCMinverters is possible at switching speeds of up to 20kHzusing IGBTs.

Device selection

The first selection criterion for an inverter device is thevoltage rating. Philips PowerMOS devices have excellentavalanche ruggedness capability and so are able to survivetransient overvoltages which may occur in the invertercircuit. This gives the circuit designer the freedom to chooseappropriately rated devices for the application withoutsuffering from the extra device conduction losses whichoccur when using higher voltage grade devices. In noisyenvironments or where sustained overvoltages occur thensome external protection circuitry will usually be required.

For low voltage and automotive applications 60V devicesmay be adequate. For mains-fed applications then the DClink voltage is fixed by the external mains supply. A 240Vsupply will, depending on the DC link filtering arrangement,give a link voltage of around 330V. Using 450V or 500VMOSFETs will allow sufficient margin for transientovervoltages to be well within the device capability.

The current rating of a device is determined by the worstcase conditions that the device will experience. These willoccur during start-up, overload or stall conditions andshould be limited by the BDCM controller. Short circuitprotection must be provided by using appropriate fusing orovercurrent trip circuitry.

In addition to the normal motor currents the inverter deviceswill experience additional currents due to diode reverserecovery effects. The magnitude of these overcurrents willdepend on the properties of the freewheel diodes and onthe switching rates used in the circuit. Turn-on overcurrentscan often be greater than twice the normal load current.The peak to average current capability of MOSFETs is verygood (typically 3 to 4) and so they are able to carryovercurrents for short periods of time without damage. Forhigh power applications PowerMOS devices can easily be

VdcVdc

VoutVout

305


parallelled to give the required current ratings providing thecircuit is suitably arranged in order to ensure good currentsharing under both dynamic and static conditions.

ConclusionsThe brushless DC motor has already become an importantdrive configuration for many applications across a widerange of powers and speeds. The ease of control and

excellent performance of the brushless DC motors willensure that the number of applications using them willcontinue to grow for the foreseeable future. The Philipsrange of PowerMOS devices which includes MOSFETs,FREDFETs, L2FETs and IGBTs are particularly suited foruse in inverter circuits for motor controllers due to their lowloss characteristics, excellent switching performance andruggedness.

306


Stepper Motor Control

307


3.3.1 Stepper Motor Control

A stepper motor converts digital information intoproportional mechanical movement; it is anelectro-mechanical device whose spindle rotates indiscrete steps when operated from a source that providesprogrammed current reversals. After the appearance of thestepper motor in applications traditionally employing digitalcontrol, the advantages of precise and rapid positioning ofobjects using stepper motor drive systems became moreobvious and this, in turn, led to a greater variety ofapplications. These now include:

• paper and magnetic tape drives,• camera iris control and film transport,• co-ordinate plotters, printers, chart recorders and

variable speed chart drives,• medical equipment,• fuel control, valve control and variable speed pumps,• meters, card readers, production line pulse counters• automatic weighing and labelling systems,• digital to analogue converters and remote position

indicating equipment.

All of these applications have one thing in common -controlled motion. Wherever controlled movement and/orpositioning is necessary, the stepper motor can be used togive a fast, flexible and accurate system.

From a mechanical viewpoint, the stepper motor has simplepositional control, reliability and precision. Previously,simple, mechanically operated switches often providedadequate control for many positioning systems butincreased performance requirements have forced the needfor a better drive systems. The advantages of stepper motorsystems have been gained at the expense of controllersimplicity. The combination of fast controller ICs, low cost,high power, high efficiency switches, particularlyMOSFETs, and the ease of use of stepper motors has leadto their current widespread use.

The full benefit of a stepper motor can only be realised if itis correctly driven. It requires a dc supply, an electronicswitch and a source of control pulses (digital information).The appropriate dc supply is directed into the motor via apower electronic switching network. In effect, the motormoves through one step for each control pulse applied tothe power stage electronic switches. The angle of the stepdepends upon the type of motor and can be from as littleas 1.8˚ to as much as 15˚. Consequently, if 24 pulses arefed to the switching network, the shaft of a motor with a 15˚step-angle will complete one revolution. The time taken forthis action is entirely a function of the rate at which controlpulses are applied. These may be generated by anoscillator with adjustable frequency or from a dedicatedcontroller IC.

Principles of operation

Stepper motors can be divided into three principle types:

• permanent magnet stepper motors• variable reluctance stepper motors• hybrid stepper motors.

a)

b)

Fig.1 Unipolar 4-phase motor

Permanent magnet stepper motors

The step angle of a permanent magnet stepper motordepends upon the relationship between the number ofmagnetic poles on its stator assembly and the number ofmagnetic poles on its rotor. Since the latter is a cylindricalpermanent magnet, the poles are fixed, and their numberis limited, due to the characteristics of the magneticmaterial. Enlarging the magnet diameter to provide for alarger number of rotor poles results in a drastic increase inthe rotor inertia. This reduces the starting capabilities ofsuch a motor beyond practical use. With a permanentmagnet rotor, only relatively large step angles can beobtained. However, the operating step angle can bereduced by using more than one stator stack along thelength of the machine and then by offsetting the separatestacks.

P

QRS

S1

S2

+

N

S

NS

N

SS3

S4

R

P

QS

S1

S2

+

S

N

NS

N

S

S3

S4

309


Fig.2 Unipolar 4-phase systema) Circuit layout, b) Switching waveforms

The stator assembly comprises two or more stators, eachhaving a coil through which current is passed to form amagnetic field. By reversing the direction of current flowingin a coil the north and south poles developed by the coilscan be transposed. Reversing the current flow throughsuccessive stator coils creates a rotating magnetic fieldwhich the permanent-magnet rotor follows. Speed ofrotation is thus governed by the rate at which the stator coils(and hence the electromagnetic poles) are switched andthe direction of rotation by the actual switching sequence.

There are two methods by which the current flow throughstator coils can be reversed and this has led to two classesof stepper motor: those designed for unipolar drive andthose for bipolar drive. For ease of description, illustrationsin this section which give a diagrammatic representation ofapermanent magnet stepper motor show only a2-pole rotoralthough it could have as many as 24: the operatingprinciples, however, are the same.

Motors for Unipolar driveEach stator coil of a motor designed for unipolar drive isprovided with a centre-tap which is connected to one sideof the supply. The direction of current flowing through a coilis then determined by the end to which the other supply lineis connected via a switching device. Switching between thecoil halves results in the magnetic poles of the relevantstator being reversed.

Figure1(a) showsa 4-phase stepper motor in which phasesP and R are energised. The north poles at P and R causethe rotor to align in the position indicated. If switch S1 isturned off and S3 turned on, so that phases Q and R arenow energised, then the stator field is repositioned and sothe conditions illustrated in Fig.1(b) are obtained, ie. therotor has moved through 90˚ to align with the stator field.

From this it can be seen that by altering the switchingsequence for switches S1, S2, S3 and S4 the rotor can bemade to advance in either direction.

Figure 2(a) shows the drive configuration for a unipolar4-phase motor. The switching sequence of the powerswitches is shown in Fig.2(b). Two motor phases areenergised at any one time thus giving the rotation of thestator field and required stepping motion.

a)

b)

Fig.3 Bipolar 4-phase motor

Motors for Bipolar driveThe stator coils of a motor designed for bipolar drive haveno centre-tap. Instead of using alternate coil-halves toproduce a reversal of current-flow through the statorwindings, the current is now reversed through the entire coilby switching both supply lines. Operation of a motor withbipolar drive is identical to that of one with unipolar drive,and is shown in Fig.3. Here, when the polarity of current inphase P is reversed using switches S1 to S4 the stator fieldrealigns and the rotor moves accordingly. Figure 4(a)shows the drive configuration for a bipolar 4-phase motor.The devices are always switched as pairs, i.e. S1 and S4,S2 and S3. The switching waveforms for this configurationare shown in Fig.4(b).

The advantages of using motors with bipolar drive areshown in Fig.5. This compares the performance of aunipolar motor with its bipolar equivalent. Unipolar motors

P Q R S

S1 S3 S2 S4

S1

S2

S3

S4

Rotorposition

a)

b)

+

N

S

SN

S

N

P

Q

S2 S1 S3 S4

S5 S6 S8 S7

+

S

N

SN P

Q

N

S

S2 S1 S3 S4

S5 S6 S8 S7

310


Fig.4 Bipolar 4-phase systema) Circuit layout, b) Switching waveforms

develop less torque at low stepping rates than their bipolarcounter-parts, although at higher stepping rates the torquedeveloped by both types of motor is nearly the same.

The 4-phase unipolar motor shown in Fig.1 has two coilsper phase which must be wound on one bobbin for eachstator (bifilar winding), ie. four coils in total. Because thetwo coils occupy the same space as a single coil inequivalent bipolar types, the wire is thinner and coilresistance higher. Bipolar motors have only one coil per

bobbin so that 2-stator motors have two coils and 4-statormotors four coils. Unipolar motors require only a simpledrive circuit - only four power transistors instead of eight.Moreover, the switching time requirements are less severefor unipolar drives. For a bipolar drive, care must be takenwith switching times to ensure that two opposing transistorsare not switched on at the same time, thus shorting out thesupply. Properly operated, bipolar windings give optimummotor performance at low to medium stepping rates.

Variable reluctance stepper motorsIn a variable reluctance stepper motor the motion isachieved by using the force of attraction between amagnetised component (the stator pole excited by acontrolledcurrent) and a passive steel component (the rotorpole). As successive stator poles are energised differentrotor poles are attracted towards the nearest active pole,thus giving the required stepping motion. Figure 6 showsthe simplest variable reluctance motor configuration havingsix stator poles and four rotor poles. The rotor is simply ashaped steel shaft. The stator winding is arranged so thatone stator phase winding is on each stator pole.

Figure 6(a) shows the condition when the ’A’ phase of themotor is energised and rotor pole 1 is aligned with theenergised winding. If stator phase ’A’ is switched off andphase ’B’ is switched on then rotor pole 2 (which is thenearest rotor pole to any ’B’ phase pole) experiences anattractive force due to the energised ’B’ phase. The rotoradvances to the position shown in Fig.6(b).

S3

S2, S3

S6, S7

S1, S4

S5, S8

Rotorposition

S1

S4

S2

S7

S5

S8

S6

a)

b)

P Q

Fig.5 Torque vs. stepping rate characteristicA) Unipolar motor B) Bipolar motor

311


If, subsequentally, phase ’C’ is energised then rotor pole 1will align with the ’C’ phase, as shown in Fig.6(c). The stepangle of a variable reluctance motor can be reduced byhaving more than one set of offset rotor poles which arebuilt up along the stack length of the machine. Differentoffset rotor poles align with the stator poles at each stepposition.

Fig.6 Variable reluctance motor

Hybrid stepper motorsThe usual configuration for a hybrid stepper motor operatesusing the torque production methods found in bothpermanent magnet and variable reluctance motors. Thisgives a higher performance system with a low volume, andhence a low rotor inertia, and small step angles. The rotorof a hybrid stepper motor consists of an axially alignedmagnet and a pair of toothed discs, one at each end of therotor stack. The general layout is shown in Fig.7. The teethof the discs are misaligned with respect to each other withthe result that as the stator phase windings are energiseddifferent teeth align with the stator poles, in a similar wayto those in a variable reluctance motor. The addition of thepermanent magnet on the rotor introduces a polarity in theway that the rotor teeth align with the stator poles. Againmulti-stack motors are used to reduce the step lengthfurther. Alternative hybrid stepper motor configurationshave the magnets on the stator, but operate in a broadlysimilar manner.

Fig.7 Hybrid stepper motor, cross sectional view

Stepper motor systemsProper selection of the right stepper motor for a specificapplication calls for a thorough understanding of thecharacteristics of the motor and its drive circuitry. Figure 8

shows schematically the four constituent parts of a steppermotor system together with the most important aspects ofeach. These will be briefly considered below.

Fig.8 Stepper motor system block diagram

The stepper motorTypical standard step motor angles are shown below:

Step angle Steps per revolution

0.9˚ 4001.8˚ 2003.6˚ 1003.75˚ 967.5˚ 4815.0˚ 24

The no load step angle accuracy is specified for each typeof motor For example, a motor having a step angle of 7.5˚and will typically position to within 20’ (i.e. 5%) whether themotor is made to move for 1 step or 1000 steps. The stepangle error is non-cumulative and averages to zero everyfour steps, i.e. 360˚. Every four steps the rotor returns tothe same position with respect to magnetic polarity and fluxpaths. For this reason, when very accurate positioning isrequired, it is advisable to divide the required movementinto multiples of four steps. This is known as the 4-stepmode of operation.

TorqueThree torques are used to define stepper motor operation:

Holding torqueAt standstill, when energised, a certain amount of torqueis required to deflect a motor by one step. This is knownas the holding torque. When a torque is applied thatexceeds the holding torque the motor will rotatecontinuously. The holding torque is normally higher thanthe working torque and acts as a strong brake in holdinga load in position.

Detent torque

CONTROLLOGIC

D.C. SUPPLY

POWER DRIVER

STEPPERMOTOR

- Oscillator- Half step- Full step- Ramping

- Battery- Transformer, rectifier

- Unipolar- Bipolar- Chopper

- Step length- Step length accuracy- Holding torque- Detent torque- Dynamic torque

A

A’

1

2

3

4

B’

B

1

23

4

C

C’

a) b) c)

A phase energised B phase energised C phase energised

Rotation

1

23

4

Case

Windings

Stator

Shaft

Rotor disc

Magnet

Airgap

N

NS

S

312


Due to their permanent magnets, hybrid stepper motorsand permanent magnet stepper motors have a brakingtorque even when the stator windings are unenergised.This is referred to as the detent torque.

Working (dynamic) torqueThe dynamic characteristics of a stepper motor aredescribed by the curves of torque versus stepping rate.Typical curves were shown in Fig.5. The pull-in curveshows the load a motor can start and stop without losingsteps when operated at a constant stepping rate. Thepull-out curve shows the torque available when the motoris gradually accelerated to and decelerated from itsrequired working speed. The area between the twocurves is known as the slew range. The characteristiccurves are used to define the correct motor selection forany particular application.

OvershootAfterexecutingeach single step the rotor tends toovershootand oscillate about its final position as shown in Fig.9(a).This is normal behaviour for any pulsed dynamic system.The actual response depends on the load and on the powerinput provided by the drive. The response can be modifiedby increasing the frictional load or by adding mechanicaldamping. However, mechanical dampers such as frictiondiscs or fluid flywheels add to system cost and complexityand so it is usually better to damp electronically.

Fig.9 Dynamic step responsea) Single step undamped responseb) Electronically damped response

Two methods of electronic damping are commonly used -the simplest being to delay the final pulse in an incrementalpulse train such that the effective length of the final step isreduced. Alternatively, every pulse, or just the final pulsein a train, can be modified into three stages, as shown inFig.9(b). Using this method of damping a forward pulse isapplied at time t0, a reverse pulse is applied at t1 in order

to slow the rotor down and then finally a second forwardpulse is applied at t2 which ensures the rotor comes to restat the desired position. The accelerating torque which isdeveloped from this final pulse is less than that for a fullstep and so the shaft overshoot is significantly reduced.

Multiple steppingThere are often several alternatives available in order tomake a desired incremental movement. For example, arotation of 90˚ can be reached in 6 steps of a 15˚ motor, 12steps of 7.5˚ motor or in 50 steps of a 1.8˚ motor. Generally,a movement executed in a large number of small steps willresult in less overshoot, be stiffer and more accurate thanone executed in smaller number of large steps. Also thereis more opportunity to control the velocity by starting slowly,accelerating to full speed and then decelerating to astandstill with minimum oscillation about the final positionif small step lengths are used.

Fig.10 Controlled acceleration and deceleration profiles

A voltage controlled oscillator and charging capacitor areusually used for acceleration (or ramp) control of the motor.The RC time constant of the ramp controller is used to givedifferent ramp rates. Figure 10 shows a typical curve of steprate against time for an incremental movement with equalacceleration and deceleration times.

ResonanceA stepper motor operated at no-load over its entireoperating frequency range will exhibit resonance points thatare either audible or can be detected by vibration sensors.If any are objectionable then these drive frequencies shouldbe avoided, a softer drive used, or alternatively extra inertiaor external damping added.

Drive methodsThenormal drive method is the 4-step sequence mentionedabove. However, other methods can be used dependingon the coil configuration and the logic pattern in which thecoils are switched:

Wave driveEnergising only one winding at a time is called waveexcitation and produces the same position increment as the4-step sequence. Figure 11 shows the stepping sequencefor the bipolar 4-phase motor, which was discussed earlierand shown in Fig.4. Since only one winding is energised,

time

Steppingrate

Max steppingrate

tacc

trun

tdec

Finalposition

Finalposition

time

time

a)

b)

t0 t1 t2

313


holding torque and working torque are reduced by 30%.This can, within limits, be compensated by increasingsupply voltage. The advantage of this form of drive is higherefficiency, but at the cost of reduced step accuracy.

Half-step modeIt is also possible to step a motor in a half-step sequence,thus producing half steps, for example 3.75˚ steps from a7.5˚ motor. A possible drawback for some applications isthat the holding torque is alternately strong and weak onsuccessive motor steps. This is because on ’full’ steps onlyone phase winding is energised whilst on the ’half’ stepstwo stator windings are energised. Also, because currentand flux paths differ on alternate steps, accuracy will beworse than when full stepping. The switching sequence fora 4-phase bipolar drive is shown in Fig.12.

Fig.11 Wave drive switching for 4-phase bipolarstepper motor

Fig.12 Half stepping switching for 4-phase bipolarstepper motor

Supply considerations

When a motor is operated at a fixed rated voltage its torqueoutput decreases as step rate rises. This is because theincreasing back EMF and the rise time of the coil currentlimits the power actually delivered to the motor. The effectis governed by the motor time constant (L/R). Because oftheir higher winding resistance unipolar motors have abetter L/R ratio than their bipolar equivalents. The effectcan be compensated by either increasing the power supplyvoltage to maintain constant current as stepping rateincreases, or by increasing supply voltage by a fixedamount and adding series resistors to the circuit.

Adding series resistors to the drive circuit can improve themotor performance at high stepping rates by reducing theL/R ratio. Adding a series resistor three times the windingresistance would give a modified ratio of L/4R. Supplyvoltage would then have to be increased to four times themotor rated voltage to maintain rated current. The additionof the extra resistance greatly reduces the drive efficiency.If the increased power consumption is objectionable someother drive method such as a bi-level voltage supply or achopper supply should be used.

Bi-level driveWith a bi-level drive the motor is operated below ratedvoltage at zero step rate (holding) and above rated voltagewhen stepping. It is most efficient for fixed stepping rates.The high voltage may be turned on by current sensingresistors or, as in the circuit of Fig.13, by means of theinductively generated turn-off current spikes. At zero steprate the windings are energised from the low voltage. Asthe windings are switched in the 4-step sequence, diodesD1, D2, D3 and D4 turn on the high voltage supplytransistors S1 and S2.

Fig.13 Unipolar bi-level drive

Chopper driveA chopper drive maintains current at an average level byswitching the supply on until an upper current level isreached and then switching it off until a lower level isreached. A chopper drive is best suited to fast accelerationand variable frequency applications. It is more efficient thanan analogue constant current regulated supply. In thechopper circuit shown in Fig.14, V+ would be typically 5 to10 times the motor rated voltage.

Spike suppressionWhen windings are turned-off, high voltage spikes areinduced which could damage the drive circuit if notsuppressed. They are usually suppressed by a diodeacross each winding. A disadvantage is that torque output

S2, S3

S6, S7

S1, S4

S5, S8

Rotorposition

S2, S3

S6, S7

S1, S4

S5, S8

Rotorposition

314


is reduced unless the voltage across the transistors isallowed to build up to about twice the supply voltage. Thehigher this voltage the faster the induced fields and currentscollapse and performance is, therefore, better. For thisreason a zener diode or series resistor is usually added asin Fig.15.

Fig.14 Unipolar chopper drive

Fig.15 Voltage suppression circuit

Performance limitationsAt standstill or low step rates, increasing the supply voltageproduces proportionally higher torque until the motormagnetically saturates. Near saturation the motorbecomes less efficient so that increased power inunjustifiable. The maximum speed of a stepper motor islimited by inductance and eddy current losses. At a certainstep rate the heating effect of these losses limits any furtherattempt to get more speed or torque out of a motor by drivingit harder.

TerminologyDetent Torque: The maximum torque that can be appliedto the spindle of an unexcited motor without causingcontinuous rotation. Unit: Nm.

Deviation:The change inspindleposition fromthe unloadedholding position when a certain torque is applied to thespindle of an excited motor. Unit: degrees.

Holding Torque: The maximum steady torque that can beexternally applied to the spindle of an excited motor withoutcausing continuous rotation. Unit: Nm.

Maximum Pull-In Rate (Speed): The maximum switchingrate (speed) at which an unloaded motor can start withoutlosing steps. Unit: steps/s (revs/min).

Maximum Pull Out Rate (Speed): The maximum switchingrate (speed) which the unloaded motor can follow withoutlosing steps. Unit: steps/s (revs/min).

Maximum Working Torque: The maximum torque that canbe obtained from the motor: Unit: Nm.

Overshoot: The maximum amplitude of the oscillationaround the final holding position of the rotor after cessationof the switching pulses Unit: degrees.

Permanent Overshoot: The number of steps the rotormoves after cessation of the applied switching pulses.

Unit: steps.

Phase: Each winding connected across the supply voltage.

Pull In Rate (Speed): The maximum switching rate (speed)at which a frictionally loaded motor can start without losingsteps. Unit: steps/s (revs/min).

Pull In Torque: The maximum switching rate (speed) whicha frictionally loaded motor can follow without losing steps.

Unit: steps/s (revs/min).

Pull Out Torque: The maximum torque that can be appliedto a motor spindle when running at the pull out rate.

Unit: Nm.

Start Range: The range of switching rates within which amotor can start without losing steps.

Step Angle: The nominal angle that the motor spindle mustturn through between adjacent steps. Unit: degrees.

Stepping Rate: The number of step positions passed by afixed point on the rotor per second. Unit: steps/s.

Slew Range: The range of switching rates within which amotor can run unidirectionally and follow the switching rate(within a certain maximum acceleration) without losingsteps, but cannot start, stop or reverse.

315

Televisions and Monitors Power Semiconductor ApplicationsPhilips Semiconductors

CHAPTER 4

Televisions and Monitors

4.1 Power Devices in TV Applications(including selection guides)

4.2 Deflection Circuit Examples

4.3 SMPS Circuit Examples

4.4 Monitor Deflection and SMPS Example

317


Power Devices in TV & Monitor Applications

(including selection guides)

319


4.1.1 An Introduction to Horizontal Deflection

Introduction

This section starts with the operation of the powersemiconductors in a simple deflection test circuit leading toa functional explanation of a typical TV horizontal deflectioncircuit. The operation of the common correction circuits arediscussed and the secondary function of the horizontaldeflection circuit described.

Deflection Test Circuit

The horizontal deflection test circuit used to assess Philipsdeflection transistors is shown in Fig. 1 below. Lcrepresents the horizontal deflection coils.

Fig. 1. Test Circuit for Deflection Transistors

This circuit is a simplification of a practical horizontaldeflection circuit. It can be used to produce the voltage andcurrentwaveforms seen by both the transistor and the diodein a real horizontal deflection circuit. It is, therefore, veryuseful as a test circuit for switching times and powerdissipation. The waveforms produced by the test circuit areshown in Fig. 2.

Fig. 2. Test Circuit Waveforms

Cycle of OperationBriefly going through one cycle of operation, the sequenceof events is as follows. (This can be followed through onthe waveforms shown in detail in Fig. 3, by starting on theleft and following the stages numbered 1 to 8).

1. Turn on the deflection transistor by applying a positivecurrent drive to the base. The voltage on the collector isnow approximately0.5V because the device is fully on. Thismeans that the voltage across the coil, Lc, is the full linevoltage; in this case 150V.

2. According to the law, V = L • dI/dt, the current in the coilLc will now start to rise with a gradient given by 150V/Lc.This portion of the coil current (ILc), is the sawtooth portionof the collector current in the transistor (Ic).

3. Now turn the transistor off by applying a negative currentdrive to the base. Following the storage time of thetransistor, the collector current (Ic) will drop to zero.

4. The current in Lc (ILc) is still flowing! This current,typically 4.5A for testing the BU2508A, cannot flow throughthe transistor any more, nor can it flow through the reversebiased diode, BY228. It, therefore, flows into the flybackcapacitor, Cfb, and so the capacitor voltage rises as ILcfalls. Because Cfb is connected across the transistor, therise in capacitor voltage is seen as a rise in Vce across thetransistor.

Lc will transfer all its energy to Cfb. The capacitor voltagereaches its peak value, typically 1200V, at the point whereILc crosses zero.

5. Now we have a situation where there is zero energy inLc but there is a very large voltage across it. So ILc willrise, and since this current is supplied by Cfb, the voltageacross Cfb falls. This is, of course, a resonant LC circuitand essentially it is energy which is flowing, first from theinductor, Lc, to the capacitor, Cfb, and then from thecapacitor, Cfb, to the inductor, Lc. Note that the current inLc is now flowing in the opposite direction to what it waspreviously. It is, therefore, a negative current.

6. This resonance would continue, with the coil current andthe capacitor voltage following sinusoidal paths, were it notfor the diode, BY228. When the capacitor voltage starts togo negative the diode becomes forward biased andeffectively clamps the capacitor voltage to approximately-1.5V, the diode VF drop. This also clamps the voltageacross Lc to approximately the same value as it was whenthe transistor was conducting, ie the line voltage (150V).Note that the coil current is now being conducted by thediode, and hence ILc = Idiode.

IBon

-VBB

LB

Lc

HVT

Cfb BY228

+150V nominaladjust for Icm

Ib Ib

Ic Ic Ic IcILc ILc

Tscan Tfb

Idiode

Vce Vce

ILc=Idiode

Idiode

Tfb

ILc=Ic

321


7. So we have again a current ramp in Lc with a dI/dt equalto 150/Lc. This current starts with a value equal to the valueit had at the end of the transistor on time (neglecting circuitlosses). It is, however, flowing in the opposite (negative)direction and so the positive dI/dt will bring it back towardszero.

8. Before ILc actually reaches zero, the base drive isre-applied to the transistor. This means that when ILc doesreach zero, we arrive back at the same conditions we hadat the beginning of stage 1; ie the transistor is on, the currentin Lc is zero and the voltage across Lc is the line voltage(150V).

TV Operating Principle

In a television set, or a computer monitor, the pictureinformation is written onto the screen one line at a time.Each of these horizontal lines of picture information iswritten onto the screen by scanning the screen from left torightwith an electron beam. This electronbeam is producedbya gunsituated at the backof the tube, and it is acceleratedtowards the screen by a high potential (typically 25kV). Thebeam is deflected from left to right magnetically, by varyingthe current in a set of horizontal deflection coils positionedbetween the gun and the screen.

The screen is phosphor coated, and when the high energyelectron beam strikes the phosphor coating the phosphorgivesoff visible light. Thedensity of electrons in the electronbeam can be varied: phosphor brightness depends onbeam density, and so the instantaneous brightness of thescanning spot can be varied at a fast rate as each line ofpicture information is written onto the screen. A set ofvertical deflection coils deflect the beam vertically at theend of each horizontal scan and so lines of pictureinformation can be built up, one after the other. The verticaldeflection frequency (or field rate) for European sets is50 Hz (alternate line scanning, giving 25 complete screensof information per second).

With no current in the horizontal deflection coils, themagnetic field between them is zero and so the electronbeam hits the centre of the screen. With a negative currentin the coils , the resultant magnetic field deflects the electronbeam to the left side of the screen. With a positive coilcurrent the deflection is to the right.

Now consider the characteristic deflection waveforms,Fig. 3. The current ILc represents the current in thehorizontal deflection coils. During the period where thecurrent in the deflection coils is ramping linearly from itspeak negative value to its peak positive value, the electronbeam is scanning the screen from left to right. This is thescan time, Tscan.

Fig. 3. Test Circuit Waveforms

Ib Ib

Ic Ic Ic IcILc ILc

Tscan Tfb

Idiode

Vce Vce

ILc=Idiode

Idiode

Tfb

1

2

3

4

5

6

7

8

ILc=Ic

322


During the period where the horizontal deflection coilcurrent flows into the flyback capacitor, and then back intothe coil (the half cosine curve at the end of the scan period),the electron beam is rapidly moving from the right side ofthe screen to the left. This is called the flyback period, Tfb,and no information is written onto the screen during thispart of the cycle.

S-Correction

The actual TV horizontal deflection circuit differs from thetest circuit in a number of ways that improve the picturequality. The simplified deflection circuit shown in Fig. 1 canbe redrawn as shown in Fig. 4 where Lc is the horizontaldeflectionyoke and Cs is charged to the line voltage (150V).

Fig. 4. Simplified TV Deflection Circuit

The advantage of this arrangement is that, by carefullyselecting the value of Cs, one form of picture distortion iscorrected for as follows.

The front of the TV tube is flat, rather than curved, and soduring each horizontal scan the electron beam travels agreater distance to the edges of the screen than it does tothe middle. A linear deflection coil current would tend toover deflect the beam as it travelled towards the edges ofthe screen. This would result in a set of ’equidistant’ linesappearing on the screen as shown in Fig. 5 below.

Fig. 5. Distortion Caused By Flat Screens

The voltage on the capacitor, Cs, will be modulated by thedeflection coil current, ILc. When the diode is in forwardconduction and the current in Lc is ’negative’, the voltageon Cs will rise as Cs becomes more charged. When thetransistor is conducting and the current in Lc is ’positive’,the voltage on Cs will drop as Cs discharges. This is shownin Fig. 6 below.

Fig. 6. S-Correction

This will give an ‘S’ shape to the current ramp in thedeflection coils which corrects for the path differencebetween the centre and the edge of a flat screen tube.Hence the value of the capacitor, Cs, is quite critical. Csis known as the S-correction capacitor.

Linearity Correction

Fig. 7. Asymmetric Picture DistortionCaused by Coil Resistance

The voltage across the deflection coil is also modulated bythe voltage drop across the series resistance of the coil.This parasitic resistance (RLc) causes an asymmetricpicture distortion. A set of ‘equidistant’ vertical lines wouldappear on the screen as shown in Fig. 7. The voltageacross the coils is falling as the beam scans the screen

VCs

ILc

150V

ILcILc=0

LcCfb

Cs

+

150V

323


from left to right. The beam, therefore, travels more slowlytowards the right side of the screen and the lines are drawncloser together, see Fig. 8.

Fig. 8. Effect of Coil Resistance on Voltage Across Coil

VRLc is the voltage drop across the resistive componentof Lc. Subtracting this from the voltage across Cs (VCs)gives the voltage across the inductive component on thedeflection coils (VLc). To compensate for the voltage dropacross the parasitic coil resistance we need a componentwith a negative resistance to place in series with the coil.This negative resistance effect is mimicked by using asaturable inductance,Lsat, in series with the deflection coilsas shown in Fig. 9 below.

Fig. 9. Position of Saturable Inductor in Circuit

For an inductor with a low saturation current, therelationship between inductance and current is as shownin Fig. 10. As the current is increased much above zero,the core saturates and so the inductance drops. Thishappens if the current is conducted in either direction.

Fig. 10. L/I Characteristic of a Saturable Inductance

By taking a saturable inductance and premagnetising thecore, we add a dc bias to this characteristic as shown inFig. 11 below.

Fig. 11. DC Shift Produced by Premagnetised Core

Since Lsat has a much lower inductance than Lc, the dI/dtthrough Lsat is governed by the deflection coils, and istherefore dILc/dt. The voltage drop across Lsat is thereforegiven by V = Lsat•dILc/dt. During the scan time, Tscan,dILc/dt is approximately constant in value, and so thevoltage/current characteristics of Lsat during the scan timeare as shown in Fig. 12 below.

This is the characteristic required and so the voltagedeveloped across Lsat, the linearity correction coil,compensates for the series resistance of the deflectioncoils.

VCs

ILc

150V

0V

VRLc

VLc

ILcILc=0

150V

L

IcoilI=0

L

IcoilI=0

Cfb+

Vcc (150V)

Lsat

Lc

Cs

324


Fig. 12. V/I Characteristic of Lsat During Tscan

Cs LossesSo the circuit shown in Fig. 9 now gives the desireddeflection waveforms. The electron beam scans the screenat a uniform rate on each horizontal scan. However, thecircuit is not lossless and unless Cs is kept topped up thedc voltage on Cs, Vcc, will gradually decay. To prevent thisfrom happening a voltage supply can be added across Csbut this introduces other problems.

Fig. 13. Deflection Circuit with Voltage Supply Added

The average voltage across Lc must be zero. A dc voltageacross Lc would generatea dc current which would producea picture shift to the right. Applying Vcc directly to Cs wouldresult in a dc current component through the deflectioncoils, so Cs must be charged to Vcc by some other way.Applying Vcc to Cs via the deflection coils overcomes thisproblem.

A large choke inductance, Lp, in series with the Vcc supplyis necessary to prevent an enormous increase in the currentthrough the power switch. Without it the Vcc supply wouldbe shorted out every time the transistor was turned on.Typically the arrangement shown in Fig. 13 will result in a20% increase in the current through the power switch andthe power diode.

East-West CorrectionSo to recap on the circuit so far: the series resistance ofthe deflection coils is compensated for by the linearitycorrection coil, Lsat, and the varying length of the electronbeam path, as the beam scans the screen from left to right,

is compensated for by the S-correction capacitor, Cs. Thiscapacitor modulates the voltage across the deflection coilsduring each horizontal scan, modulating the magnetic fieldramp between them, and thus keeping the speed at whichthe electron beam scans the screen constant.

However, as the picture information is written onto thescreen, by writing one line of information after another, afurther variation in the length of the beam path is introducedas the beam scans the screen from top to bottom. Thelength of the beam path to the edge of the screen is shorterwhen the central lines of picture information are beingwritten than it is when the lines at the top or the bottom ofthe screen are being written.

This means that a higher peak magnetic field is required todeflect the beam to the screen edges when the beam iswriting the central lines of picture information, than thatrequired to deflect the beam to the screen edges when thelines of picture information at the top and bottom of thescreen are being written.

Fig. 14. Modulation of the Peak Deflection Coil Current

This requires increasing the peak deflection coil currentgradually over the first half of each vertical scan, and thenreducing it gradually over the later half of each vertical scan(seeFig. 14). This is done by modulating the voltageacrossthe deflection coils. This process is known as east-westcorrection.

The line voltage, Vcc, is supplied by a winding on the SMPStransformer. This voltage is regulated by the SMPS andduring the operation of the TV set it is constant.

In order to achieve the required modulation of the voltageacross the deflection coils, a simple linear regulator couldbe added in series with Lp. One disadvantage of thissolution is that it increases the circuit losses.

The Line Output Transformer (LOT)The horizontal deflection transistor serves another purposeas well as deflecting the beam: driving the line outputtransformer (LOT). The LOT has a number of low voltageoutputs but its primary function is to generate the EHTvoltages to accelerate and focus the electron beam.

V

II=0

CentreBottom

+4.5A+3.5A

-4.5A-3.5A

etc

Topof screen

1 verticalscan

2nd verticalscan

deflection coilcurrent ismodulated

Cfb

+

Vcc (150V)

Lsat

Vcc(150V)

Lp (typ 5mH)

(typ 12nF) Lc (typ 1mH)

Cs(typ 500nF)

325


Fortunately, this function can be combined with a featurepreviously described as a cure for Cs losses; the inductivechoke, Lp. The LOT has a large primary inductance thatserves the purpose of Lp so a separate choke is notrequired, see Fig. 15 below.

Fig. 15. Position of Line Output Transformer

A lot of power may be drawn from the LOT but the deflectionmust not be affected. In order to keep the secondarywindings of the LOT at fixed voltages, we need to keep thevoltage across the primary winding fixed. Therefore, therequirements for the LOT and a regulated supply to Lp arein conflict.

‘Real’ and ‘Dummy’ Deflection CircuitsAs a way around this problem, consider a ‘dummy’deflection circuit in series with the ‘real’ deflection circuit.This enables one circuit to meet the requirements fordeflection, including east-west correction, and the dummycircuit meets the requirements for the LOT, see Fig. 16.

Fig. 16. Position of Dummy Deflection Circuit.

The two deflection circuits operate in directsynchronisation. Vmod is a voltage between zero and 30Vthat controls the east-west correction. Thus we can varythe voltage across the deflection coils in the ‘real’ deflectioncircuit without varying the voltage across the primary of theLOT in the ‘dummy’ circuit.

Fig 17. Vmod Applied Directly to Cmod

For proper flyback tuning, the ‘real’ and ‘dummy’ deflectioncircuits and the LOT must be tuned to the same flybackfrequency. The two deflection circuits are tuned throughcareful selection of the flyback capacitors. In the case ofthe LOT the capacitance of the windings provides thenecessary capacitance (typically 2nF) for correct tuning.

Since Lmod is only an inductor and not a real deflectioncomponent, a net dc current through it is not a problem.Therefore, we can apply Vmod directly to Cmod and thisway reduce the component count by removing Lpmod, seeFig. 17.

Lmod is a quarter of the value of Lc. Cfbmod is four timesas big as Cfb. Cmod is not critical as long as it is largeenough to supply the required energy.

Suppose there is no voltage supplied externally to Cmod.The supply voltage, Vcc, will split according to the ratio ofthe impedances of the two circuits. In fact, the Vcc will splitaccording to the ratio of the two flyback capacitors, Cfb andCfbmod, as shown in Fig. 18.

The average voltage across Cfbmod will automatically be30V (for Vcc = 150V), if no external voltages are applied tothe ‘dummy’ circuit. Consequently, Cmod will becomecharged to 30V. The two deflection circuits are alwaysoperating in direct synchronisation. Under the conditionwhere Vmod is 30V the currents in the two circuits wouldalso be equal.

LcCfb

Cs

+

Vcc (150V)

Lsat

Vcc(150V)

E.H.T.

Line outputtransformer

LcCfb

Cs+

Vcc-Vmod

Lsat

Vcc

E.H.T.


Lmod

Cmod

Cfbmod+

Vmod

LcCfb

Cs+

Vcc-Vmod

Lsat

Vcc

E.H.T.


Lmod

Cmod

CfbmodVmod+

Vmod

Lpmod

326


Fig. 18. Average Voltage Across the twoFlyback Capacitors.

The range of Vmod required is 0 to 30V. Vmod is reducedbelow 30V as current is drawn from Cmod. An externalsupply to Cmod is never needed. This is the arrangementused in practice.

To draw current from Cmod a series linear regulator isadded across Cmod as shown in Fig. 19.

Fig. 19. Series Regulator Controlling Vmod

Diode Modulator CircuitThe circuit is now quite close to an actual TV horizontaldeflection circuit. As the two transistors are switching inperfect synchronisation this circuit can be simplified furtherby removing one transistor, as shown in Fig. 20. Thisarrangement makes no difference to the operation of thecircuit.

The circuit in Fig. 20 now shows all the features of thehorizontal deflection diode modulator circuit. Thesefeatures should be distinguishable when studying actualcircuit diagrams.

Fig. 20. The diode modulator circuit

Diode Modulator: Upper Diode

First consider the voltage requirements. In this respect, theworst case conditions for the upper diode are whenVmod = 0V. Under these conditions the upper diode mustsupport the full flyback voltage. Therefore, the peak voltagelimiting value on the upper diode must match the VCES limitof the transistor.

Now consider the current requirements. With no circuitlosses, the currents in the diode and the transistor are asshown in Fig. 21 where Ic is the transistor current and Idiodeis the diode current. Of this current, 80% flows in thedeflection coils and 20% flows in the LOT primary.

Fig. 21. With no load, Ic and Idiode are equal.

With circuit losses included, the transistor current willexceed the diode current. Circuit losses add a dccomponent to the waveform shown in Fig. 21. The loadingon the LOT contributes a further dc component, increasingthe transistor current and reducing the diode current stillfurther, Fig. 22.

+Vcc

Cfb

Cfbmod (= 4*Cfb)Vmod

4*VmodLcCfb

Cs+

Vcc-Vmod = 120-150V

Lsat

Vcc

E.H.T.


Lmod

Cmod

Cfbmod

+Vmod = 0-30V

Seriesregulator

(150V)

LcCfb

Cs+

Vcc-Vmod = 120-150V

Lsat

Vcc

E.H.T.


Lmod

Cmod

Cfbmod

+Vmod = 0-30V

Seriesregulator

Ic Ic

Idiode

Idiode

Idiode Ic

327


Fig. 22. With load and circuit losses, Ic > Idiode.

For example, for a current which is 12A peak to peak, 10Aof this will be deflection current and 2A will be LOT current.With no load, the peak diode current would be equal to thepeak transistor current, ie both would equal 6A. However,the LOT requires 1A dc in order to power the secondarywindings. This makes the peak diode current 5A and thepeak transistor current 7A. These are practical values fora 32 kHz black line S (ie EHT = 30kV) TV set.

The diode must conduct the full current immediately afterthe flyback period. Until the forward recovery voltage of thediode has been reached the diode cannot conduct. A highforward recovery voltage device would impede the start ofthe scan. If once the forward recovery voltage has beenreached the device takes a long time before falling to its VF

level then the voltage across the deflection coils would benon-linear and, therefore, cause picture distortion. For a32 kHz set the diode must recover to less than 5V in under0.5µs.

Diode Modulator: Lower Diode

First consider the voltage requirements. At one extreme,all the flyback voltage is across the top diode and at theother extreme, the worst case condition for the lower diodeis when the flyback voltage is split between the two diodesin the ratio 4:1 (ie when Vmod is at its maximum value of30V). The voltage limiting value on the lower diode is,therefore, usually given as one quarter of the rating of thetop diode. So, if the transistor is 1500V, the top diode isalso 1500V and the bottom diode is 400V.

However, it is not uncommon for fault conditions to occurin TV circuits that cause large voltage spikes on the lowerdiode. To accommodate such occurrences, a 600V deviceis often used as the lower diode.

Now consider the current requirements. The lower diodemust take the same current as the horizontal deflection coil,Fig. 23, and so its current requirement is the same as thatof the top diode.

Fig. 23. Situation when Vmod = 0V

As shown in Fig. 23, the lower diode is conducting its peakcurrent immediately before the flyback period and switchesoff as the transistor. Therefore, the reverse recovery of thelower diode must be very fast to minimise circuit losses.

Diode Modulator Circuit ExamplePutting the above diode requirements into the circuit ofFig. 20 enable a typical 16 kHz TV horizontal deflectioncircuit to be constructed, see Fig. 24. This circuit isrepresentative of a modern 25" TV design. The deflectiontransistor, BU2508A, will run with a peak IC of 4.5A at16 kHz. The combined inductance and capacitance willproduce a flyback pulse of typically 1200V peak and 13µswidth. The upper diode, BY228, has the same current andvoltage capability as the deflection transistor. The lowerdiode, BYW95C, has the same current capability but areduced voltage rating. More often than not, 600V devicesare used as the lower diode with 1500V upper diodes.

The dc supply comes from the TV SMPS circuit. The SMPSwill use a power switch also, typically BUT11AF in 16 kHzTV. A transformer will provide all the high power dc suppliesrequired for the TV. For a 150V supply a high voltage diodewill be used in the output stage, typically BY229-600. TheLOT generates the EHT to accelerate the electron beam,typically a voltage of 25kV is produced.

InsmallerTV’s (14-21") thiscircuit couldbe muchsimplified.For smaller screen sizes EW correction is not essential andthe diode modulator is not usually present. The circuit nowuses a single diode and capacitor. The diode can beincorporated in the deflection transistor, for example, theBU2508D. Also for the smaller screen sizes it is commonthat the tube technology allows for lower flyback voltages.In these applications the 1000V BUT11A and BUT12A areoften used.

In larger 16 kHz TV’s (28" and above) and all 32 kHz TV’sthe axial diodes will not normally be capable in terms ofcurrent handling. These diodes are replaced by devices inTO220 type power outlines: BY359 for the upper diode and

Ic

Idiode

Idiode

Ic

No losses

Withlosses

LcCfb

Cs

Lsat

ON

328


BY229-600 or BYV29-500 for the lower diode. Also largerdeflection transistors are available: BU2520A andBU2525A.

The same sort of scaling is also applicable to monitordeflectioncircuits. Allmonitors tend touse 1500V deflectiontransistors and upper diodes. The BU2508D (ie with diode)is often used so that the BY228 can be used as the upper

diode. Using a D-type deflection transistor takes somecurrent from the diode modulator but does not affect theoperating principle. For the high frequency (up to 82 kHz),multi-sync monitors BU2522A and BU2527A deflectiontransistors are used. Above 64 kHz the BY459 is used asan upper diode.

Fig. 24. The Diode Modulator for 16 kHz TV Deflection, Example

Linearity

E.H.T.


+ Vmod

Seriesregulator

BU2508A

SMPS

BUT11AF

Line scancoils

0-30V

500nF

2uF

250uH

BY228

BYW95B

6.8nF

22nF

329


4.1.2 The BU25XXA/D Range of Deflection Transistors

IntroductionThe BU25XXA range forms the heart of PhilipsSemiconductors 1500V power bipolar transistors. Thistechnology offers world class dissipation in its targetapplication of 16 kHz TV horizontal deflection circuits. Therange has been extended for state-of-the-art large screenTV (8 A, 32 kHz) and all the volume monitor applications(up to 6 A, 64 kHz). The successful application of theBU25XXA range in all sectors of TV & monitor horizontaldeflection has proved it to be a global technology.

As a further improvement, the BU25XXD range of deviceshave been introduced. Using BU25XXA technology,horizontal deflection transistors incorporating base-emitterresistive damping and a collector-emitter damper diodehave been produced. The devices in this range arespecifically aimed at the small-screen 16 kHz TV and48 kHz monitor applications where the use of a D-typedevice can offer asignificant cost-saving. The D-types offerthe same performance as the A-type equivalent with onlyslightly increased dissipation, at a similar cost.

Specification Notes

The ICsat value defines the peak current reached in ahorizontal deflection circuit during normal operation forwhich optimum performance is obtained. Unlike otherspecification points, it is not necessary to inset this valuein a real application. Operation either much above or belowthe specified ICsat value will result in less than optimumperformance. For higher frequencies the ICsat should belowered to keep the dissipation down.

The VCESM value defines the peak voltage applied under anycondition. The BU25XXA/D range could operate undercontinuous switching to 1500V in a deflection circuit withoutany degradation to performance but exceeding 1500V isneither recommended nor guaranteed. In normal runningthe peak flyback voltage is typically 1150V but a 1500Vdevice is required for fault conditions.

The storage time, ts, and fall time, tf, limits are given foroperation at the ICsat value and the frequency of operationgiven by the application limit.

The BU25XXA Range Selection Guide

Specification Application

Device ICsat VCESM ts tf TV Monitor

BU2508A/AF/AX 4.5 A 1500 V 6.0 µs 600 ns ≤ 25", 16 kHz -4.0 A 1500 V 5.5 µs 400 ns - 14", SVGA, 38 kHz

BU2520A/AF/AX 6.0 A 1500 V 5.5 µs 500 ns ≤ 29", 16 kHz 15", SVGA, 48 kHz4.0 µs 350 ns ≤ 28", 32 kHz

BU2525A/AF/AX 8.0 A 1500 V 4.0 µs 350 ns ≤ 32", 32 kHz (17", 64 kHz)

BU2522A/AF/AX 6.0 A 1500 V 2.0 µs 250 ns - 15", 64 kHz

BU2527A/AF/AX 6.0 A 1500 V 2.0 µs 200 ns - 17", 64 kHz

The BU25XXD Range Selection Guide


Device ICsat VCESM ts tf TV Monitor

BU2506DF/DX 3.0 A 1500 V 6.0 µs 500 ns ≤ 23", 16 kHz -

BU2508D/DF/DX 4.5 A 1500 V 6.0 µs 600 ns ≤ 25", 16 kHz 14", SVGA, 38 kHz

BU2520D/DF/DX 6.0 A 1500 V 5.5 µs 500 ns ≤ 29", 16 kHz 15", SVGA, 48 kHz

331


Application NotesTheapplications given in the selectionguideshould be seenas an indication of the limits that successful designs havebeen achieved for that device type. This should help in theselection of a device for a given application at the designconcept stage. For example, a 15" monitor requiringoperation up to 6 A at 64 kHz could use either a BU2522Aor BU2527A. If the design has specific constraints onswitching and dissipation then the BU2527A is the bestoption, but if cost is also a prime consideration then thesmaller chip BU2522A could be used with only slightlydegraded performance. For an optimised design theBU2525A can be used in 17", 64 kHz applications but theBU2527A is the recommended choice.

OutlinesPhilips Semiconductors recognise both the varying designcriteria and the market availability of device outlines andthis is reflected in the range of outlines offered for theBU25XXA/D range. Three different outlines are offered forthe devices available, one non-isolated (SOT93) and twoisolated/full-pack designs (SOT199, TOP3D). The outlineis defined by the last letter in the type number, for example:

BU2508A SOT93 non-isolated

BU2508AF SOT199 isolated

BU2508AX TOP3D isolated

All three outlines are high quality packages manufacturedto Philips Total Quality Management standards.

The Benefits of the D-type

Fig.1. BU2508A vs. BU2508D

The BU2508D technology incorporates the damper diodeandabase-emitter dampingresistor, seeFig.1. In the target16 kHz applications the damper diode is usually an axialtype (eg. BY228), the D-type deflection transistorincorporates this device in a monolithic structure. Thispresents a significant cost-saving in the application. Thebase-emitter resistor eliminates the need for externaldamping at the transistor base-emitter. The only

consideration for replacing an A-type with a D-type is thatthe base current required for optimised switching is slightlyhigher for the D-type.

For higher currents and frequencies where diode modulatorcircuits are used it appears at first that use of the D-typesis not possible. However, this is not so; D-type transistorscan be used WITH diode modulators in a beneficial way.For example, a 15", 48 kHz SVGA monitor utilising a diodemodulator is at the borderline between an axial upperdamper diode and a TO220 type. The dissipation is suchthat if an axial diode is used some sort of thermalmanagement may be necessary. By using a D-typetransistor some of the current is taken by the diode in theD-type relieving the discrete upper damper device. Use ofa D-type in this way has allowed an axial diode to be usedin place of a TO220 type making a significant cost saving.

Causes of DissipationIn the cycle of operation there are four distinct phases:turn-on, on, turn-off, off. Each phase is a potential causeof dissipation. Of course, for enhanced circuit performancedissipation in the deflection transistor must be minimised.

a) Turn-on. The primary function of a deflection transistoris to assist in the sweep of the beam across the screen ofthe display, ie to horizontally deflect the beam. As thedeflection transistor turns-on the beam is scanning fromjust less than half way across. At mid-screen the beam isun-deflected, ie the deflection current is zero. So, thedeflection transistor turns on with a small negative collectorcurrent, IC ramping up through zero. At turn-on there areno sudden severe load requirements that cause significantdissipation. In horizontal deflection turn-on dissipation isnegligible.

b) On-state. As the beam is deflected from the centre ofthe screen to the right - hand side the IC increases asdetermined by the voltage across the deflection coil. Theresulting voltage drop across the deflection transistor, VCE

depends not only on this IC but also on the base drive: forhigh IB the VCE will be low; for low IB the VCE will be high.For high IB the transistor is said to be overdriven giving lowon-state dissipation. For low IB the transistor is said to beunderdriven giving higher on-state dissipation.

c) Turn-off. Turn-off starts when the forward IB is stopped.This is followed 2 - 6 µs later (depending on the device andapplication) by the IC peaking. This delay is called thestorage time, ts of the device. During this time the VCE risesas the current rises causing increased dissipation: thelonger ts the higher the dissipation. As the IC peaks soscanning ends and the process of flyback begins. Now, asthe IC falls (in time tf, the fall-time) the VCE rises to the peakflyback voltage; this a phase of high dissipation.

D2Rbe

BU2508A, BE resistor, damper diode BU2508D

332


Turn-off is the dominant loss phase for all deflectiontransistors. The device characteristics in this phase are ofmuch interest to the TV & monitor design engineers.

d) Off-state. In an optimised drive circuit the device willbe off for VCE above 250V in flyback. For the rest of theflyback the collector-emitter is reverse biased while thebase-emitter will also be reverse biased: between -1 to -4V.Any leakage through the device will be the cause ofdissipation. For the BU25XXA/D range, low-contaminantprocessing ensures that the bulk leakage is very low. Also,the long-established Philips glass passivation has very lowleakage. The device characteristics coupled with the lowpulse width and duty cycle of the flyback mean that thelosses in the off-state are negligible.

In a D-type deflection transistor there is an additional causeof dissipation:

e) Diode Conduction. At the end of flyback the next scanwill start. As the flyback voltage goes negative so the diodeconducts, this clamps the voltage on the flyback capacitor.The fixed voltage provides a fixed ramp in current throughthe deflection coil and through the diode; the beam sweepsfrom the left towards the centre of the screen. At, or near,the centre this current approaches zero ending the diodeconduction phase. The dissipation here is dominated bytwo characteristics of the diode: the forward recovery andthe on-state voltage drop. This can be a significant causeof dissipation in a D-type transistor.

The effect of both underdrive and overdrive on the deviceis increased device dissipation and hence increasedjunction temperature. In general, the higher the junctiontemperature the shorter the lifetime of the device in theapplication. Optimised drive circuit design and goodthermal management can bring the device junctiontemperature down to well below the limit Tjmax. Suchconsiderations enhance the reliability of the deflectiontransistor in the application. It is essential that care is takenat the design stage to optimise the base drive for the deviceproduct spread.

Dynamic TestingThe BU25XXA/D range is assessed in a deflectionswitching test circuit designed to simulate the mostdemanding running conditions of the application. Thehorizontal deflection coils, which form the major part of thecollector load, are represented by a variable inductance Lcand the flyback and diode modulator circuits by a singlediode, BY228 and variable capacitance, Cfb. ForBU2508A/AF/AX TV applications the test circuit is shownin Fig.2 below.

This circuit generates the characteristic deflectionwaveforms, Fig.3, from which the storage time, fall time andenergy loss at turn-off can be measured. These parametersdefine the device performance in the application.

Fig.2. BU2508A/AF/AX 16 kHz DeflectionSwitching Test Circuit

Fig.3. Deflection Switching Waveforms

It is not valid to do a single-shot test for the switchingparameters as the characteristics of the nth pulse dependon the previous (n-1)th pulse. To achieve this the testerworks in a double pulse mode.

‘Bathtub’ Curves

Fig.4. BU2508A Typical Turn-Off Losses- ‘Bathtub’ curve

IBon

-VBB

LB

Lc

HVT

Cfb BY228

+150V nominaladjust for Icm

Ib Ib

Ic Ic Ic IcILc ILc

Tscan Tfb

Idiode

Vce Vce

ILc=Idiode

Idiode

Tfb

ILc=Ic

0.1 1 10IB / A

Eoff / uJ BU2508A1000

100

10

3.5A

IC = 4.5A

333


A plot of base current, IB, against turn off dissipation, Eoff,for one BU2508A measured in the switching test circuit ata peak collector current of 4.5A gives the characteristic‘bathtub’ shape shown in Fig.4 above. From this curve thetolerance to base drive variations can be assessed and theoptimum IB determined for a given IC.

The switching performance is also determined by the peakreverse base current at switch off. For a typical hFE device,of all types in the BU25XXA/D range, a peak reverse basecurrent, IBoff, equal to one half the typical peak IC isrecommended for optimum dissipation. This is largelydetermined by the drive transformer and is usually difficultto be fine-tuned. In the typical non-simultaneous base drivecircuit the level of forward base current, IB, is easilycontrolled, hence, the presentation of the turn-off lossesversus IB.

The ‘bathtub’ curves are plotted for a reverse base voltageat turn-off of -4V. This level of reverse base drive isrecommended for the BU25XXA/D range as it reduces therisk of any noise, or ring, forward biasing the base-emitterduring flyback. However, in well-engineered designs theBU25XXA/D can operate just as well with a reverse basevoltage at turn-off of only -1V. This tolerance to base driveis very useful to design engineers.

On the far left of the curve, at low IB values, the device isseverely underdriven resulting in a high turn off dissipation.As the base drive is increased the degree of underdrive isreduced and the device remains in saturation for a largerproportion of its on time. This is the reason for the initialdecrease in Eoff with increasing IB seen in the ‘bathtub’curve. Eventually, the optimum drive is reached and theturn off dissipation, Eoff, is at its minimum value. Increasingthe base drive still further results in overdrive and theappearance of an IC tail at turn off. The result of this, ascan be seen in the ‘bathtub’ curve, is increasing turn offlosses with increasing IB.

Typically, this curve has steep sides and a flatter centralportion; this gives it the shape of the cross-section througha bathtub, hence the name ‘bathtub’ curve !

The BU25XXA/D technology gives a sharper looking curvebut a much lower level of Eoff/Poff than competitor types.For optimised drive the BU25XXA/D technology offersworld class dissipation in 16 kHz TV deflection circuits.

Process ControlThe success of the BU25XXA/D range has enabledsignificant enhancements to be made to the benefit of bothour customers and ourselves. By utilising a continuouscycle of quality improvement coupled with high volumeproduction, Philips Semiconductors can demonstrate theirexcellent process control in specified hFE and dissipation

limits. This control is achieved by manufacturing capabilityrather than test selections. This process control improvesmanufacturing throughput and yield and, hence, customerdeliveries. The improvements in manufacturing result inhigher process capability indices enabling the introductionof tightened internal test specifications.

Critical Parameter Distribution Fact SheetsIndustry standard data sheets for all power semiconductordevices offer an introduction to the device fundamentalsand can usually be used for a quick comparison betweencompetitor types. Detailed use of a specific device requiresmuch more information than is contained in any data sheet.This is particularly relevant to high voltage bipolartransistors, and especially horizontal deflection transistors.A horizontal deflection transistor is only as good as the basecircuit that drives it. The growth of power MOSFET’s ismainly due to the difficulties in driving bipolar transistors.However, MOSFET technology is not suitable for horizontaldeflection applications, Philips Semiconductors areactively involved in supplying the support tools necessaryfor the successful design-in of their BU25XXA/D range.

Recognising the designers requirements PhilipsSemiconductors now provide critical parameter distributionfact sheets for the BU25XXA/D range. This additional datashould be used in conjunction with the data sheets to givea full picture of the device capabilities and characteristicsover the production spread.

The fact sheets give limit curves for the power dissipationin the device caused by turn-off, Poff, at a given operatingfrequency and range of load current, IC all at 85˚C (a typicaloperating temperature for TV and monitor applications).These curves provide limits to the typical ‘bathtub’ curvesgiven in data. It is important to recognise that these factsheet curves represent the LIMIT of production whencomparing the BU25XXA/D range with competitor typeswhich offer this information as TYPICAL only, if at all. Thisinformation displays the technical performance of thedevice and the measurement capability available.

Contained in the fact sheets is evidence of the world classdissipation limits obtained by the BU25XXA/D range. Asan example, the BU2508A/AF/AX ‘bathtub’ limit curves areshown in Figs.5-7.

These fact sheets also contain limit hFE curves for VCE = 1 Vand 5 V at three different temperatures: -40˚C, 25˚C, and85˚C. The range of temperatures chosen reflects the rangeof customer requirements. These limit curves define thedevice characteristics for all the important extremes ofoperation. As an example the BU2508A/AF/AX limit hFE

curves for VCE = 1 V and 5 V at 25˚C are shown in Figs.8-9below. The 100% test points are indicated by arrows.

334


Fig.5. BU2508A/AF/AX Fig.6. BU2508A/AF/AX Fig.7. BU2508A/AF/AXMax. Poff vs. IB Max. Poff vs. IB Max. Poff vs. IB

for IC = 3.5 A @ 85˚C for IC = 4.5 A @ 85˚C for IC = 5.5 A @ 85˚C

0.4 0.6 0.8

10

1

0.1

Poff (W)

Tj = 85C

f = 16kHz

IC = 3.5A

BU2508A/AF

1.0

IB (A)0.5 1.5

10

1

0.1 1.0 2.0

Poff (W)

Tj = 85C

f = 16kHz

IC = 4.5A

BU2508A/AF

IB (A)

1 2 3

10

1

0.1 1.5 2.5

Poff (W) BU2508A/AF

IC = 5.5A

Tj = 85C

f = 16kHz

IB (A)

Fig.8. BU2508A/AF/AX hFE vs IC @ 1 V, 25˚C Fig.9. BU2508A/AF/AX hFE vs IC @ 5 V, 25˚C

100

10

1

hFE

0.01 IC (A)0.1 1.0 10

BU2508A/AF

VCE = 1V

Tj = 25C

100

10

1

hFE

0.01 IC (A)0.1 1.0 10

BU2508A/AF

VCE = 5VTj = 25C

335


Drive CircuitsIt was stated previously that a horizontal deflectiontransistor is only as good as the base circuit that drives it.Philips Semiconductors address this problem by providingfact sheets with an example of a drive circuit for the targetapplications. The drive circuitspresented are of the industrystandard non-simultaneous base drive type utilisingcommercially available Philips components. An exampleof these drive circuits is shown for the BU2508A in Fig.10below.

This drive circuit is not an end in itself but a means to anend: it produces the waveforms at the base that enable theload set by Vcc, Lc and Cfb to be switched most efficiently.For this reason the waveforms produced by this circuit arealso presented in the fact sheet. Again, for the BU2508Aexample given above the waveforms are shown inFigs.11-15 below.

The drive circuit employed in the application could be quitedifferent to the one given above in Fig.10 but the base drivewaveforms in Figs.11 & 13 must be replicated for optimisedswitching.

The fundamental concept of the non-simultaneous basedrive is well established in the TV and monitor industry fordriving the horizontal deflection transistor. Individualdesigns, however, can differ significantly. A differenttransformer design may enable the required base currentto be generated without the addition of Lb and D1, Rb.Driving Rp from a low voltage supply could reduce the costby allowing a low voltage transistor, Q1 and capacitor, Cdto be used.

The resistor Rbe is necessary to eliminate any overshootin the Vbe at the end of the base-emitter avalanche thatcould turn the transistor on during flyback. Such an eventwould lead to an early failure of the transistor by exceedingthe forwardbiased safe-operating area (FBSOA). In circuitsoperating at higher frequencies resistive damping alone isusually not sufficient and RC damping is required.

In this application, the BU2508A could be replaced by theBU2508D in the circuit of Fig.10. This would allow theBY228 and Rbe resistor to be removed from the circuit.

Fig.10. BU2508A 4.5 A, 16 kHz Drive Circuit

Components and values: Rp = 1 kΩ, 2 W; Cr = 100 nF; Rd = 560 Ω; Cd = 470 pF, 500 V; Q1 Philips BF819;T1 Philips AT4043/87 Transformer; Lb = 0.5 µH; Rb = 0.5 Ω, 0.5 W; D1 Philips BYV28-50; Rbe = 50 Ω;

Lc = 1 mH; Cfb = 12 nF, 2 kV; D2 Philips BY228; Vcc = 115 V.

Lc

Cfb

Vcc

0V

D.U.T.

Rb

Cd

Rd

Rp

T1

Q1

Vp

Vce

VbeD1

RbeD2

0V

Cr

0V

Lb

336


Fig.11. BU2508A/AF IB vs. time Fig.12. BU2508A/AF IC vs. time

Fig.13. BU2508A/AF VBE vs. time Fig.14. BU2508A/AF VCE vs. time

IB(end) = 0.9 - 1.1 A; ICmax = 4.5 ± 0.25 A;

|- IB(off)| ≥ 2.0 A;

VCEmax = 1100 - 1200 V

Fig.15. VP vs. time

BU2508A/AFIB (1A/div)4

2

0

-2

-4 time (10us/div)

BU2508A/AF

time (10us/div)

IC (1A/div)

4

2

0

-2

BU2508A/AF

time (10us/div)

5

0

-5

-10

-15

VBE (5V/div) BU2508A/AF

time (10us/div)

VCE (200V/div)

0

200

400

600

800

1000

1200

1400

time (10us/div)

VP (50V/div)

200

150

100

50

0

250BU2508A/AF

337


4.1.3 Philips HVT’s for TV & Monitor Applications

This section simplifies the selection of the power switchesrequired for the SMPS and horizontal deflection in TV andmonitor applications. Both high voltage bipolar transistorsand power MOSFET devices are included in this review.As well as information specific to the PhilipsSemiconductors range of devices, general selectioncriteriaare established.

HVT’s for TV & Monitor SMPSThe vast majority of television and monitors have switchmode power supplies that are required to generate an90 - 170Vsupply for the linedeflection stage, plus anumberof lower voltage outputs for audio, small signal etc. By farthe easiest and most cost effective way of fulfilling theserequirements is to use a flyback topology. Discontinuousmode operation is generally preferred because it offerseasier control and smaller transformer sizes thancontinuous mode.

For the smaller screen size TV’s, where cost is a dominantfactor, bipolar HVT’s dominate. For large screen TV andmonitors power MOSFET’s are usually chosen.

Thepeak voltage across the switching transistor in a flybackconverter is twice the peak dc link voltage plus an overshootvoltage which is dependent on the transformer leakageinductance and the snubber capacitance. Thus, for a givenmains input voltage there is a minimum voltage requirementonthe transistor. Increasing the transformer leakageand/orreducing the snubber capacitance will increase theminimum voltage requirement on the transistor.

a) Power MOSFET’sFor TV’s operating just with 110/120V mains applicationsa device which can be used with peak voltages below 400Vis required. For these applications the power MOSFET isused almost exclusively. A wide variety of 400V powerMOSFET’s are available, leading to lower device costs,which coupled with the easier drive requirements of theMOSFET make this an attractive alternative to a bipolarswitch.

For 220/240V and, more recently, for universal input mainsapplications where an 800V device is generally requiredthe cost of power MOSFET was prohibitive. However,improvements both in circuit design and device quality hasmeant that a 600V device can be used in these applications.

Philips Semiconductors have a comprehensive range ofpowerMOS devices for these applications. The mainparameters of these devices most applicable to TV andmonitor SMPS applications are summarised in Table 1.

Part Number V DSS RDS(ON) @ ID

BUK454-400B 400 V 1.8 Ω 1.5 A

BUK455-400B 400 V 1.0 Ω 2.5 A

BUK457-400B 400 V 0.5 Ω 6.5 A

BUK454-600B 600 V 4.5 Ω 1.2 A

BUK455-600B 600 V 2.5 Ω 2.5 A

BUK457-600B 600 V 1.2 Ω 6.5 A

BUK454-800A 800 V 6.0 Ω 1.0 A

BUK456-800A 800 V 3.0 Ω 1.5 A

BUK438-800A 800 V 1.5 Ω 4.0 A

Table 1. Philips PowerMOS HVT’s for TV & MonitorSMPS Applications

The VDSS value is the maximum permissible drain-sourcevoltage of the powerMOS in accordance with the AbsoluteMaximum System (IEC 134). The RDS(ON) value is themaximum on-state resistance of the powerMOS at thespecified drain current, ID.

b) Bipolar HVT’sBipolar HVT’s still have an important role in TV SMPSapplications. Many new TV designs are slightimprovements on existing designs incorporating a newcontrolor signal feature (eg Fastext,SCART sockets) whichdo not demand the re-design of the SMPS. If there hasbeen a good experience with an existing SMPS it is notsurprising that these designs should continue in new TVmodels.

For 220/240V mains driven flyback converters, generally,a 1000V bipolar HVT is used. The full voltage capability ofthe transistor can be used as the limit under worst caseconditions but it must never be exceeded. In circuits wherethe transformer leakage inductance is high, and voltagesin excess of 1000V can occur, a device with a higher voltagehandling capability is required.

339


Philips Semiconductors have a comprehensive range ofbipolar HVT devices for these applications. The mainparameters of these devices most applicable to TV SMPSapplications are summarised in Table 1.

Part VCESM VCEO ICsat VCEsat

Number

BUX85 1000 V 450 V 1 A 1.0 V

BUT11A 1000 V 450 V 2.5 A 1.5 V

BUT18A 1000 V 450 V 4 A 1.5 V

BUT12A 1000 V 450 V 5 A 1.5 V

BUW13A 1000 V 450 V 8 A 1.5 V

BU506 1500 V 700 V 3 A 1.0 V

BU508A 1500 V 700 V 4.5 A 1.0 V

Table 2. Philips Bipolar HVT’s for TV SMPS Applications

The VCESM value is the maximum permissiblecollector-emitter voltage of the transistor when the base isshorted to the emitter or is at a potential lower than theemittercontact. TheVCEO value is the maximumpermissiblecollector-emitter voltage of the transistor when the base isopen circuit. Both voltage limits are in accordance with theAbsolute Maximum System (IEC 134). The VCEsat value isthe maximum collector emitter saturation voltage of thetransistor, measured at a collector current of ICsat and therecommended base current.

c) Selection proceduresSome simple calculations can be made to establish thedevice requirements. The first requirement to be met is thatthe peak voltage and current values are within thecapabilities of the device. For a flyback converter the peakvoltageandcurrent values experienced by the power switchare given by the equations in Table 3.

Peak voltage acrossthe device

Peak device current

Table 3. Peak Voltage and Current in a FlybackConverter.

where:

Vs(max) = maximum dc link voltageσ = voltage overshoot due to transformer leakageVs(min) = minimum dc link voltagePth = throughput power of SMPSδm = maximum duty cycle of SMPS

Note: in this example, the throughput power is equal to theinput power less the circuit losses up to the power switch.

MOSFET or bipolar?

The main factors influencing this decision are ease of driveand cost, given the limitation on percentage of throughputpower which can be dissipated in the power switch.MOSFETs require lower drive energy and less complicateddrive circuitry. They also have negligible switching lossesbelow 50 kHz. However, large chip sizes are required inorder to keep on state losses low (especially as breakdownvoltage is increased). Thus the larger chip size of theMOSFET is traded off against its capacity for cheaper andeasier drive circuitry and higher switching frequencies.

For 110/120V mains driven TV power supplies the 400VMOSFET dominates. At 220/240V there is a split betweenbipolar and power MOSFET

Which MOSFET?

The optimum MOSFET for a given circuit can be chosenon the basis that the device dissipation must not exceed acertain percentage of throughput power. Using this as aselection criterion, and assuming negligible switchinglosses, the maximum throughput power which a givenMOSFET is capable of switching is calculated using theequation;

where:

Pth(max) = maximum throughput powerδmax = maximum duty cycleτ = required transistor loss

(expressed as a fraction of the output power)Rds(125C) = RDS(ON) at 125˚CVs(min) = minimum dc link voltage

A transistor loss of 5% of output power gives a goodcompromise between device cost, circuit efficiency andheatsink size (ie τ = 0.05)

Note that the RDS(ON) value to be used in the calculation isat 125˚C (a practical value for junction temperature duringnormal running). The RDS(ON) specified in the device datais measured at 25˚C. As junction temperature is increasedthe RDS(ON) increases, increasing the on state losses of theMOSFET. The extent of the increase depends on thedevice voltage, see Fig. 1.

For 400V MOSFET’s Rds(125C) = 1.98 x RDS(ON) @ 25˚C,where RDS(ON) @ 25˚C is the value given in device data.

For 800V MOSFET’s Rds(125C) = 2.11 x RDS(ON) @ 25˚C.

Pth(max) =3× τ × Vs(min)

2 × δmax

4× Rds(125C)

(2× Vs(max)) + σ

2×Pth

δm × Vs(min)

340


Fig. 1. Change in RDS(ON) vs. VDSS.

Which bipolar?

For maximum utilisation of a bipolar transistor it should berun at its data ICsat. This gives a good compromise betweencost, drive requirements and switching losses. Using thisas a selection criterion the maximum output power whicha given bipolar transistor is capable of switching iscalculated using the equation;

where: Pth(max) = maximum throughput powerδmax = maximum duty cycleVs(min) = minimum dc link voltageICsat = ICsat in transistor data

d) Selection tableUsing the selection procedures just discussed, and thedevice data given previously, the following selection tableof suitable devices for flyback converters of various outputpowers has been constructed.

Output 110/120V (ac) 220/240V (ac)Power mains mains

50 W BUK454-400B BUK454-600BBUK454-800A

BUX85

100 W BUK455-400B BUK455-600BBUK456-800A

BUT11A/BU506

150 W BUK457-400B BUK457-600BBUK438-800B

BUT12A/BU506

200 W BUK457-400B BUK438-800ABUW13A/BU508A

Table 4. Power Switch Selection Table

HVT’s for TV & Monitor HorizontalDeflection

This application is one of the few remaining applicationswhich is entirely serviced by bipolar devices. Thetechnology is not yet commercially available to provideMOSFET or IGBT devices for this application. A horizontaldeflection transistor is required for each TV and monitoremploying a standard cathode ray tube display.

The deflection transistor is required to conduct a currentramp as the electron beam sweeps across the screen andthen withstand a high voltage peak as the beam flies backbefore the next scan starts. The peak current and voltagein the application define the device required. In addition tothis, the deflection transistor is required to switch betweenthe peak current and peak voltage states as quickly andefficiently as possible. In this application the switching anddissipation requirements are equally as important as thevoltage and current requirements.

Standard TV switches at a frequency of 16 kHz, rising to32 kHz for improved definition TV (IDTV). In the future,high definition TV (HDTV) will switch between 48 and64 kHz.

Standard VGA monitors switch at 31 kHz, rising to 48 kHzfor SVGA. However, many other (as yet unnamed) modesexist for PC monitors and work stations, extending up to100 kHz switching frequencies.

Vertical deflection is much lower in frequency (50 to 70 Hz)and will not be discussed as this uses lower power devices(typically 150V / 0.5A).

a) Voltage and Current Requirements

For a given scan frequency the voltage and currentrequirements of the horizontal deflection transistor are notfixed. However, the suitable transistors are all linked by therelationship;

The derivation of this law is as follows:

The horizontal deflection angle (typically 110o) covered ina given time is proportional to the magnetic field sweepbetween the horizontal deflection coils. This is in turnproportional to the product of the number of turns on thedeflection coils and the peak to peak current. The averagecurrent in the deflection coils is zero and hence the peakpositive current in the coils is half the peak to peak current.These relationships yield the following equation;

0 200 400 600 800 1,000 1,200

100, 1.74

200, 1.91

400, 1.98500, 2.01

800, 2.111,000, 2.15

1.7

1.8

1.9

2

2.1

2.2

Device voltage rating (Volts)

Rdson(125C)/Rdson(25C)

Pth(max) = δmax× Vs(min) ×ICsat

2

ICsat× VCESM = constant

B∝n × I

341


where:

B = magnetic field sweep between the horizontaldeflection coils

n = number of turns on the horizontal deflection coilsI = peak positive current in the horizontal deflection coils

The inductance of the horizontal deflection coils, L, isproportional to the square of the number of turns, ie

Combining these two equations gives

and so for a given deflection angle and horizontal scanfrequency, and therefore a given B, L x I2 is a constant.

For a given deflection frequency the flyback time is alsofixed. Flyback time is related to the deflection coilinductance, L, and the flyback capacitance, C, by theequation

During the flyback period the energy in the deflection coils(1/2.LI2) is transferred to the flyback capacitor and so thevoltage across the flyback capacitor rises. Assuming allthe energy is conserved during this transfer, the increasein voltage across the flyback capacitor, δV, is given by

So, if LI2 is a constant then CδV2 is a constant also.Therefore, as LC is a constant so is (IδV)2. So we have:

δV is the voltage rise across the flyback capacitor due tothe energy transferred from the deflection coils during theflyback period. The peak voltage across the flybackcapacitor, Vpeak, is given by

where: VCC = line voltage (typically +150 V)

The flyback capacitor is positioned across the collectoremitter of the horizontal deflection transistor. Therefore,the peak voltage across the flyback capacitor is also thepeak voltage across the collector - emitter of the deflectiontransistor.

In order to protect the transistor against overload conditions(eg picture tube flash) a good design practice is to allowVCEpeak to be 80%of the VCESM rating. VCC is generally around10% of the VCEpeak (in order to obtain the correct ratio of scantime to flyback time). This gives

All the positive current in the horizontal deflection coils isconducted by the horizontal deflection transistor. However,this is not the peak current in the transistor. The transistoris normally also required to conduct the current in theprimary of the line output transformer (LOT). Typically, thiswill increase the peak current in the deflection transistor by40%. For optimum deflection circuit design the peak currentin the transistor will be its ICsat rating, ie

Therefore, for a given deflection angle and a givenhorizontal scan frequency the horizontal deflection circuitcan be designed around any one of a number of devices.However, the suitable devices are all linked by the equation

Summary

For a given horizontal deflection angle and horizontal scanfrequency

where:

VCESM = maximum voltage rating of the horizontaldeflection transistor

ICsat = ICsat rating of the horizontal deflection transistorδV = voltage rise on the flyback capacitor due to the

energy transfer from the horizontaldeflection coilsI = peak positive current in the horizontal deflection

coilsL = inductance of the horizontal deflection coilsC = value of flyback capacitance

These relationships apply only for the assumptionsdeclared previously.

b) Switching and DissipationRequirementsIn TV, for a given scan frequency the minimum on time ofthe transistor is well defined. For 16 kHz systems thetransistor on time is not less than 26 µs and for 32 kHzsystems it is not less than 13 µs. This enables the requiredstorage time of the transistor to be well defined. For 16 kHzsystems a maximum storage time of 6.5 µs is the typicalrequirement. For 32 kHz systems the required maximumstorage time is typically 4.0 µs. For higher frequencies therequired maximum storage time is reduced still further.

L∝n2 ICsat = 1.4× I

B2∝L × I 2


tfb∝√L × CVCESM ≥ 1.25× δV + 190

ICsat = 1.4× I


L × I 2 = C × δV2 = constant

12

× L × I 2 =12

× C × δV2

δV × I = constant

Vpeak = δV + VCC

VCESM ≥ 1.25× δV + 190

342


In monitor applications, especially multi frequency models,the on time is not well defined. There are many differentfrequency modes and several control ic’s giving differentduty cycles. However, it can be said that the higher thefrequency, the shorter the storage time required.

Storage time in the circuit can always be reduced by turningthe transistor off harder. However, this eventually leads toa collector current tail at turn off and as a consequence theturn off dissipation increases. Turn off dissipation accountsfor the bulk of the losses in a deflection transistor and it iscrucial that this is kept to a minimum. The deflectiontransistor must be tolerant to drive and load variations if itis to achieve a low turn off dissipation because the east -west correction on larger screen television sets means thatcircuit conditions are not constant. Turn off can beoptimised during the design phase by ensuring that thepeak reverse base current is roughly half of the peakcollector current and the negative base drive voltage isbetween 2 and 5V.

Turn on performance is not a critical issue in deflectioncircuits. At turn on of the deflection transistor the IC is low,the VCE is low and, therefore, the dissipation is low. Theactual turn on performance of the transistor has a negligibleeffect.

c) HVT’s for Horizontal DeflectionThe deflection circuit must satisfy any specified cost,efficiency and EMC requirements before it can be calledacceptable. A very high voltage deflection transistor wouldallow a lower deflection coil current to be used, reducingthe level of EM radiation from the deflection coils, but itwould require a higher line voltage and it would also resultin higher switching losses in the transistor. A very highdeflectioncoil current would allow a lower voltage deflectiontransistor to be used and a lower line voltage. This wouldalso yield lower switching losses in the deflection transistor.However, high currents in the deflection coils could lead toEMC problems, and the need to keep the resistive coillosses low would mean that thicker wire would have to beused for the windings. Above a certain point the skin deptheffect makes it necessary to use litz wire.

For 16 kHz and 32 kHz applications the 1500V bipolartransistor has become the designers first choice, althoughmany 16 kHz systems could work well using 1000Vdevices. However, concern over fault conditions that cancause odd high voltage pulses has seen 1500V adoptedas the ‘standard’. The collector currents involved rangefrom 2.5A peak to 8A peak for TV and 3.5A peak to 7A peakfor monitors. The transistors for these applications are nowconsidered.

16 kHz applications

Table 5 lists the 1500V transistors for 16 kHz TV deflectionsystems and a summary of their main characteristics.

Part VCESM ICsat ApplicationNumber

BU505/D 1500V 2A Monochrome sets

BU506/D 1500V 3A 90˚ Colour; ≤ 23"BU2506DF

BU508A/D 1500V 4.5A 110˚ Colour; 21-25"BU2508A/D

BU2520A/D 1500V 6A 110˚ Colour; 25-29"

Table 5. Transistors for 16 kHz TV deflection

All of the above types are available in both non-isolated andisolated outlines (F-pack), except the BU2506DF - F-packonly. Isolated outlines remove the need for an insulatingspacer to be used between device and heatsink. Devicesare available both with and without a damper diode (egwithout: BU505, BU2520A and with: BU505D, BU2520D).The BU2506DF is only available with a damper diode.

The BU25XX family is a recent addition to the range ofPhilips deflection transistors. Far from being just another1500V transistor, the BU25XX has been specificallydesigned for horizontal deflection. By targeting the devicefor this very specialised application it has been possible toachieve a dissipation performance in deflection circuitswhich is exceptional.

The BU2520A uses the superior technology of the BU25XXfamily applied to a large chip area. The BU2508A has anhFE of 5 at 5V VCE and 4A IC. The BU2520A has an hFE of5 at 5V VCE and 6A IC. This gives designers working onlarge colour television sets a high hFE deflection transistorwith a high current capability. The high hFE reduces theforward base drive energy requirements. The high currentcapability enables the energy drawn from the line outputtransformer to be increased. Using a BU2520A deviceallows the EHT energy to be increased for brighter pictures(a feature of new ‘black line’ tubes) without having toincrease the forward base drive energy to the deflectiontransistor.

32 kHz applications

Table 6 gives the 1500V transistors for 32 kHz deflectionsystems and a summary of their main characteristics.


BU2520A 1500V 6A 110˚ Colour; ≤ 28"

BU2525A 1500V 8A 110˚ Colour; ≤ 32"

Table 6. Transistors for 32 kHz deflection

343


For the foreseeable future 32 kHz TV will be concentratedat the large screen sector ( ≥ 25"). These TV’s will employdiode modulator circuits lessening the need for D-typetransistors. With a switching frequency twice that ofconventional TV the dissipation in these devices will behigher. For this reason the non-isolated versions, with lowerthermal resistance, will be prevalent in these applications.

Monitor applications

The applications given in Table 7 should be seen as anindication of the limits that successful designs have beenachieved for that device type. This should help in theselection of a device for a given application at the designconcept stage. For example, a 15" monitor requiringoperation up to 6A at 64 kHz could use either a BU2522A,a BU2525A or a BU2527A. If the design has specificconstraints on switching and dissipation then the BU2525Aand BU2527A would be better. If, as well, a guaranteedRBSOA is required then the BU2527A is the best choice.

Table 7 gives the 1500V transistors for monitor deflectionsystems, concentrating on the common pc and industrystandard work station modes.


BU2508A/D 1500V 4.5A 14", SVGA, 38 kHz

BU2520A 1500V 6A 15", SVGA, 48 kHz

BU2522A 1500V 6A 15", 64 kHz

BU2525A 1500V 8A (17", 64 kHz)

BU2527A 1500V 6A 17", 64 kHz

Table 7. Transistors for Monitor deflection

All devices are available in non-isolated and isolatedoutlines. The excellent dissipation of this range of devicesmeans that, even at monitor switching frequencies, devicesin an isolated package can be used

344


4.1.4 TV and Monitor Damper Diodes

Introduction

Philips Semiconductors supply a complete range of diodesfor the horizontal deflection stage of all volume TV andmonitor applications. This note describes the range ofPhilips parts for the damper (also called efficiency) diodein horizontal deflection. The damper diode has someunusual application specific requirements that areexplained in this section.

Damper diodes form an essential part of the horizontaldeflection circuit. The choice of diode has an effect on thetotal circuit dissipation and the display integrity. A poorselection can lead to unnecessary power loss and a visiblepicture distortion.

As well as a full range of discrete devices for the damperdiode application Philips offfer a range of horizontaldeflection transistors with integrated damper diodes.These devices offer a cost and space saving, especiallybeneficial for high volume TV production.

Discrete Damper Diode Selection Guide

IFWM, IF(AV). The quoted IF(AV) values do not correspond toany particular current in the application. The values arestandard data format for selection purposes andcomparison with competitor types. In general, the larger theIF(AV) the higher the deflection coil current and/or frequencyin the application. A more meaningful specification is IFWM,this refers to the peak operating current in a 16 kHz TVapplication given a standard current characteristic. Theapplication columns in table 1 define the limit fitness for useof each diode.

VRSM. The damper diode should have a voltage capabilityequal to the deflection transistor. In most applications thiswill be 1500V. The VRSM value equates to the peak flybackvoltage. The diode data should not be viewed as that forother diodes where it is quite common to use devices withVRSM 5 or 10 times greater than the peak circuit voltage.Damper diodes will operate in horizontal deflection circuitswith peak flyback voltages up to the specified limit.However, the limit VRSM should not be exceeded in anycircumstance. In practice, a device with VRSM of 1500V willbe found inapplications with peak flyback voltages of1300Vin normal running; fault conditions do not usually see morethan a 200V rise in flyback voltage.

Outline. The Philips range spans the available outlines forthis application from axial to TO220 type. The SOD57 andSOD64 are hermetically sealed axial - leaded glassenvelopes. These outlines combine the ability to houselarge chips with proven reliability and low cost. For highambient temperatures with severe switching requirementsthe addtion of cooling fins may be necessary to achievesuccessful operation at the application limit.

For higher currents and frequencies there are devices inTO220 type outlines. TO220AC is a two-leggednon-isolated outline. The pin-out is such that the tab isalways the cathode. For an isolated equivalent outline thereare SOD100 and the newer SOD113. The SOD100 is thetraditional isolated TO220 outline allowing the device to beattached to a common heatsink without any separateisolation. The SOD113 is an enhanced version of SOD100offering an improved isolation specification. Philips offer acomplete range of mounting accessories for all theseoutlines.


Device Type IFWM,IF(AV) VRSM Outline TV Monitor

BY448 4 A 1650 V SOD57 ≤ 21", 16 kHz -

BY228 5 A 1650 V SOD64 25", 16 kHz -

BY328 6 A 1500 V SOD64 28", 16 kHz 14", SVGA, 38 kHz

BY428 4 A 1500 V SOD64 21", 32 kHz 14", 64 kHz

BY359 10 A 1500 V TO220AC 36", 32 kHz 17", 64 kHzBY359F(X) SOD100 (SOD113)

BY459 10 A 1500 V TO220AC HDTV 19", 1280x1024, 82 kHzBY459F SOD100

Table.1 Philips Semiconductors Damper Diode Selection Guide

345


Horizontal Deflection Transistors withIntegrated Damper Diode

Fig.1. BU508A/2508A vs. BU508D vs. BU2508D

The range of devices available covers most high volumeTV& Monitor applications where designers require a choiceof devices to meet their requirements. The differences areshown in Fig. 1 above. These devices are all monolithicstructures. The process of integrating the diode does notreduce the performance of the deflection transistor.

For traditional horizontal deflection circuits with a singledamper diode it is easy to see the benefits of integratingthe deflection transistor and damper diode. The additionaldissipation in the integrated damper diode should be takeninto account in the thermal management considerations.The use of the deflection transistor with integrated diodeallows a simpler layout with lower component count andcost.

For circuit designs that employ a diode modulator circuit itis still quite common to employ a deflection transistor withan integrated damper diode. In these circuits the current

is shared between the integrated diode and the discretemodulator damper diode. This technique allows smallerdiscretediodes to be used or reduced thermal managementfor the discrete device. For example, this could allow thecircuit designer to remove anycooling fins on an axial diode;or replace aTO220 type with acheaperaxial typeof discretediode in the modulator.

Table 2 below shows aselection of Philips Semiconductors’horizontal deflection transistors with an integrated damperdiode.

ICsat. This value is an indication of the peak collector currentin a 16 kHz TV horizontal deflection circuit for whichoptimum dissipation and switching can be obtained. Forthe diode the ICsat value should also be taken as the peakcurrent (ignoring any instantaneous spikes at the start ofscan). For higher frequency applications in monitors theICsat value reduces slightly.

VCESM. The voltage capability of the deflection transistorand damper diode are the same. As for discrete devices,there is no need for excessive insets. The VCESM valueequates to the peak flyback voltage and, as for the VRSM ofa discrete damper diode, should not be exceeded underany circumstance.

Outlines. Devices are available in three different outlines,one non-isolated (SOT93) and two isolated/full-packdesigns (SOT199, TOP3D). The outline is defined by thelast letter in the type number, for example:

BU2508D SOT93 non-isolated

BU2508DF SOT199 isolated

BU2508DX TOP3D isolated

All three outlines are high quality packages manufacturedto Philips Total Quality Management standards.

Rbe

BU508A, BU2508A

BU2508D

BU508D

Rbe

BE resistor, damper diode


Device Type ICsat VCESM Outline TV Monitor

BU2506DF 3.5 A 1500 V SOT199 21", 16 kHz -BU2506DX TOP3D (SOT399)

BU508D 4.5 A 1500 V SOT93 21-25", 16 kHz -BU508DF SOT199

BU2508D SOT93BU2508DF 4.5 A 1500 V SOT199 21-25", 16 kHz 14", 38 kHz, VGABU2508DX TOP3D (SOT399)

BU2520D SOT93BU2520DF 6 A 1500 V SOT199 25-29" 16 kHz 14", 48 kHz, SVGABU2520DX TOP3D (SOT399)

Table 2 Philips Semiconductors Deflection Transistors with Integrated Damper Diode Selection Guide

346


Operating CycleThe waveforms in Fig. 2 below show the deflection coilcurrent and flyback voltage in a simplified horizontaldeflection circuit. In Fig. 2 the damper diode current ishighlighted. All the flyback voltage is applied across thedamper diode. These waveforms are valid for both thetraditional type of deflection circuit (Fig. 3) and the diodemodualtor deflection circuit (Fig. 4).

Fig. 2. Horizontal Deflection Damper DiodeOperating Cycle.

During flyback the energy in the deflection coil, Lc istransferred to the flyback capacitor, Cfb. With the transferof energy the voltage on Cfb, hence the voltage across thediode, rises sinusoidally until all the energy is transferred.Now the current in Lc is zero and the diode and Cfb are atthe peak flyback voltage. The energy now transfers backto Lc. As the energy is transferred the voltage decreases

until all the energy is back in Lc when there is no voltageacross Cfb, and maximum current through Lc. If there wasno diode present, this operation would continue with theenergy transferring back to Cfb with the voltage continuingto decrease until all the energy in Lc had been transferred;the peak voltage now reversed. But with the damper diodein place across Cfb (see Figs. 3 & 4), as the voltage fallsnegative the diode will be forward biased and tend toconduct.

Consider now the application requirement which is toestablish a peak negative current in Lc before the start ofthe next scan. As the decreasing voltage on Cfb tends tozero so the current in Lc reaches a peak negative value andthe next scan can start. The transfer of energy into thecapacitor has to be stopped during the scan, hence theaddition of the damper diode.

Most TV & monitor display circuits will employ an elementof over-scanning; this means at the start of diodeconduction the beam will be off-screen. Over-scanning isintroduced to reduce the effect of any spurious switchingcharacteristics as the diode switches.

Power Dissipation

There are two significant factors contributing to powerdissipation in a damper diode: forward recovery andon-state forward bias. Reverse recovery and reverse biaslosses are negligible in this application. As a general rule,the total dissipation is half forward recovery and half forwardbias. To explain this further we have to consider theoperating cycle of the diode in detail.

scan

Idiode

ILc=Idiode

Idiode

ILc=Ic

flyback flyback

flyback

voltage

flyback

voltage

deflection

coil current

Fig. 3. Traditional Deflection Circuit. Fig. 4. Diode Modulator Circuit Example.

LcCfb

Cs

Lsat

Vcc

E.H.T.

Line OutputTransformer

HorizontalDeflectionCoil

SmoothingCapacitor

DamperDiode

+

-

DeflectionTransistor

Linearity Coil

LcCfb

Cs

Lsat

Vcc

E.H.T.

Line OutputTransformer

HorizontalDeflectionCoil

SmoothingCapacitor

DamperDiode

+

-DeflectionTransistor

Linearity Coil

Cmod

Lmod

Vmod

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Forward Recovery. As the voltage goes negative theelectric field builds up across the diode. The device designand process technology determine the point at whichconduction starts. At the start of conduction the voltage isa maximum: the forward recovery voltage, Vfr. A detailedview of the damper diode voltage and current at the startof diode conduction is given in Fig. 5 below. As the currentflows the voltage across the diode drops to its steady-stateVF value; the time this takes is called the forward recoverytime, tfr.

Fig.5. Damper Diode V & I Waveforms.

The values for Vfr and tfr are application dependent. Ingeneral, Vfr is ≤ 20V; tfr is ≤ 500ns for VF to fall to 2V; andthe rate of rise in diode current, dIF/dt, will be between 25- 90 A/µs. A ‘good’ damper diode will not only have low Vfr

and low tfr but as a result, it will also allow the current toswitch to the diode faster, giving a higher dIF/dt.

Forward Bias. As the beam scans from the left towardsthe centre the voltage drop across the diode is determinedby the device VF characteristic for a given Lc current. Asthe beam scans from left to right the diode currentdecreases.

Measurement of the VF is not possible in the application.The best indication of the losses comes from the maximumhot VF information contained in the datasheets.

Reverse Recovery & Reverse Bias. To the right of centrescreen Lc current becomes positive and, hence, current nolonger flows through the damper diode. In reverse recoverythe damper diode does not experience any high current -high voltage characteristic that would be a cause ofsignificant dissipation.

During flyback the diode is reverse biased, another possiblecause of dissipation. The combined effects of reverserecovery and reverse bias are negligible in comparison toforward recovery and forward bias.

Picture Distortion

The diode does not start to conduct until the forwardrecovery voltage is approached: a device with a highforward recovery voltage, Vfr, will take longer to startconduction than a device with a low Vfr. A delay in the startof diode conduction means that the deflection coil currentis dominated by the flyback capacitor, Cfb at the start of thescan. This can cause a visible distortion to the left-handside of the display.

The voltage across the diode modulates the voltage acrossthe coil. For a device with a long forward recovery time, tfr,the diode forward recovery characteristics will affect thevoltage across the deflection coil at the start of the scan.This can also cause a visible distortion to the left-hand sideof the display.

For display circuit optimisation it is essential that therequirements for the damper diode are understood andtaken into account in device selection.

time

time

VfrVF

IFdIFdt

tfr

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TV Deflection Circuit Examples

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4.2.1 Application Information for the 16 kHz Black LinePicture Tubes

With the introduction of the black line picture tubes newdrive circuits are required. To have full benefits, the EHTvoltage and beam current must be increased. This sectiondescribes the horizontal deflection and EHT generation.Some hints for vertical deflection and video amplifiers aregiven as well.

SummaryThis section describes the horizontal deflection circuitry ofthe black line picture tube A66EAK022X11 andA59EAK022X11. To take full advantage of this new tubeit must be driven at 27.5kV @ 1.3mA. This implies that inan ordinary combined EHT and deflection stage in the noload condition, zero beam current, the high voltageincreases to about 29.5kV. The main change to this circuit,compared with existing circuits, is the line outputtransformer (AT2077/34) uses four layer DSB technology.

For the vertical deflection a minor modification on PCALEreport ETV8831 is given. The video output stage suited tothis tube is described in PCALE report ETV8811.

1. IntroductionOne step in improving picture quality is the introduction ofthe black line picture tube. With this tube day-time TVviewing with a bright high contrast picture becomespossible. To achieve this the picture tube is provided witha dark screen and increased EHT power capability bymeans of an invar shadow mask.

When the 45AX black line picture tube is compared withthe existing 45AX tubes the following modifications in theapplication must be made.

-Increase of the EHT power to 27.5kV @ 1.8mA beamcurrent.

-Increase of the cut off voltage to 160V.

Tocope with this high EHTpower demand,anew line outputtransformer has been developed (AT2077/34). The main

part of this section is dedicated to the horizontal deflection.For supply, vertical deflection and video amplifier detailsreference will be made to separate reports.

Special care is taken to suppress certain geometricalpicture distortions which otherwise would becomenoticeable at the increased levels of dynamic EHT loadvariations. These distortions are the result of oscillationsin the line output stage.

All measurements and circuits are based and tested on the66FS picture tube. Since the 59FS tube is electricallyidentical to the 66FS tube this circuit is also suited for the59FS picture tube. With some minor circuit modifications(component values) this circuit is also suited for 33" picturetubes.

2. Circuit DescriptionThe horizontal deflection board is built up of four majorparts, see Fig. 1.

Fig. 1. Block Diagram of Horizontal Deflection Board.

In high end TV sets a lot of low voltage supply current isrequired. In this design a separate transformer in parallelto the line output transformer is foreseen for the generationof these auxiliary supplies. In applications where thisauxiliary power is not required this part can be omitted bysimply leaving out the additional transformer. The otherparts of this horizontal deflection are more or less classic.

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2.1 Drive Circuit

Fig. 2. Drive Circuit

The horizontal drive circuit is a classical transformercoupled inverting driver stage. When driver transistor T1is conducting energy is stored in the transformer. WhenT1 is turned off the magnetising current continues to flowin the secondary side of the transformer thus turning on thedeflection transistor. At this time the voltage on thesecondary side of the driver transformer is positive(VBE+IBxR6). When the driver transistor turns on again thissecondary voltage reverses and will start to turn off thedeflection transistor. At the same time energy is stored inthe transformer again.

During this turn off action the forward base drive currentdecreases with a controlled dI/dt, thereby removing thestored charge from the deflection transistor. The dI/dtdepends on the negative secondary voltage and theleakage inductance. As a rule of thumb, the deflectiontransistor stops conducting when its negative base currentis about half the collector peak current.

To prevent the deflection transistor from turning on duringflyback due to parasitic ringing on the secondary side of thedriver transformer a damper resistor is connected in parallelwith the base emitter junction of the deflection transistor.

Also at the primary side of the driver transformer a dampernetwork is added (R5 & C10) to limit the peak voltage onthe driver transistor.

D5 is added for those applications where in the standbymode the deflection stage is turned off by means ofcontinuous conduction of the driver transistor. Theexplanation is as follows:

When T1 is suddenly made to conduct continuously, a lowfrequency oscillation will occur in C9 and the primary of L3.As soon as the voltage at pin 4 of L3 becomes negative T2starts conducting until the driver transformer isdemagnetised. This will cause an extremely high collectorcurrent surge. D5 prevents pin 4 of L3 going negative andso this fault condition is avoided. For those applicationswhere this condition cannot occur, D5 can be omitted.

2.2 Deflection CircuitThe horizontal deflection stage contains the diodemodulator which not only provides east-west rastercorrection but also inner pincushion correction, picturewidth adjustment and EHT compensation. It is not easy toachieve optimum scan linearity over the whole screen.Either the linearity inside the PAL test circle is good andoutside the circle the performance is poor, or the averageperformance over the whole screen is good but inside thetest circle deviation is visible. In this application theS-correction capacitors C15 and C16 are balanced in sucha way that a good compromise for the scan linearity isachieved.

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Fig. 3. Deflection Circuit

As already stated in the introduction, due to high beamcurrent in combined EHT and deflection stages picturedistortions will occur.

One of these effects is the so called cross-hatch "noses",visible as horizontal phase ringing just below eachhorizontal white line. During a bright horizontal line the EHTat the picture tube decreases. In the next flyback the picturetube capacitor is recharged by the line output transformer.This energy is taken from the S-correction capacitor, whichmust be recharged via the primary winding of the line outputtransformer. This action has a resonance of a few kHz andthus oscillation is visible at the screen.

To avoid this a dip rectifier is connected in parallel with theS-correction capacitor (D9, C14, R8). The energy takenfrom the S-correction capacitor can now be recharged byC14.

Another geometry distortion is the "Krückstockeffekt". Dueto trapezium correction the EW-drive signal applied to L6can be discontinuous. This will cause amplitude ringing atthe top of the screen. An effective way to damp this ringingis a resistor in series with the EW-injection coil.

The consequence of the above mentioned measures is thatthe drive reserve of the diode modulator has decreased.To compensate for this a separate winding of the line outputtransformer is connected in series with the deflection coils.

2.3 EHT GenerationFor an optimum performance the black line picture tubemust be driven at an increased EHT of 27.5kV @ 1.3mAav.This implies that the EHT in the no load condition, zerobeam current, will be about 29.5kV. To generate thisincreased EHT a newly designed line output transformer isused with a 4-layer diode split EHT section. From anintegrated potentiometer the adjustable focus and grid 2voltages are taken.

Also the frame supply voltage (26V) and video supplyvoltage (180V) are taken from the line output transformer.The auxiliary windings of this transformer can be connectedrather freely so that a diverse range of auxiliary suppliescan be obtained. The only restriction is that the RMS valueof the current in a given winding may not exceed 2A.Furthermore the supply current for the heater is obtainedfrom this transformer just like the Φ2 feedback pulse(positive) and a (negative) pulse to synchronise the SMPS.

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2.4 Auxiliary Supply

Fig. 4 Auxiliary Supply

When more auxiliary power than can be handled by the lineoutput transformer is required, an auxiliary supplytransformer, as shown in Fig. 4, is a good alternative. Suchan extra transformer in parallel with the primary winding ofthe line output transformer is an efficient way to generatelow voltage high current supplies. As the transformer isoptimised for this purpose no additional stabilisation isrequired.

Due to the high inductance of the primary winding noinfluence on the collector current is noticeable. Outputvoltages are very close to the target values (fine adjustmentwith primary taps) and have low Ri (HT line is stabilised).

2.5 Additional Circuit Information12V supply:The SMPS used in this concept delivers 16V unstabilised.This needs to be regulated to supply the sync processingIC which operates at 12V. This regulation can be done onthe syncprocessing board or the horizontal deflectionboardsince this also acts as a power distribution board.

Tuning voltage:The tuning voltage is created simply by means of a seriesresistor R1 and a 30V reference diode located at the tuningboard.

EHT compensation:For proper picture performance it is essential that EHTinformation is available to compensate picture width andheight for EHT variations. For this reason the aquadag isconnected to the foot point of the line output transformer.This point is connected to ground by C18 and to the 26Vby a non linear resistor network (R12, D11, R13, R14). Thisnetwork is designed in such a way that it matches with thenon linear impedance of the line output transformer andC18 matches with the picture tube capacitance. Thus thevoltage available at the foot point of the line outputtransformer is a good representation of the EHT variation.This EHT information is sent to the geometry processorTDA8433. This information can also be used for beamcurrent limiting. It must then be fed to the video processorfor contrast/brightness reduction.

354


Fig. 5. Circuit Diagram (continued on next page)

355


Fig. 6 Circuit Diagram (continued from previous page)

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3. Oscillograms

Oscillogram 1:In this oscillogram the lower trace is the voltage across thedeflection transistor (200V/div). The middle trace is thecurrent in the horizontal deflection coil (1A/div). The uppertrace is the collector current in the deflection transistor(2A/div). The time base is 10µs/div.

Remarks:At the end of flyback there is a negative overshoot at thecollectorvoltage. This is causedby the relativeslowforwardrecovery of the damper diode. A part of this current isreverse conducted by the deflection transistor. About 12µsafter the start of the scan the deflection transistor is turnedon and starts reverse conducting and takes over a part ofthe current in the damper diodes. See also oscillogram 3.

Oscillogram 2:The upper trace is the voltage across the deflectiontransistor (200V/div). The lower two traces are theminimum and maximum voltage in the diode modulator(cathode D8) with nominal EW and amplitude settings(50V/div). The time base is 10µs/div.

Oscillogram 3:In the upper trace the current in the upper diode is shown(1A/div). The middle trace is the current in the lower diode(1A/div). The time base is 10µs/div.

Remarks:12 µs after the start of the scan the deflection transistor isturned on. Current in the diode modulator is then takenover by the deflection transistor. See also oscillogram 1.

Oscillogram 4:In the upper trace the collector voltage of the drivertransistor is shown (100V/div). The middle trace is the basedrive current of the deflection transistor (1A/div). The lowertrace is the base emitter voltage of the deflection transistor(5V/div). The time base is 10µs/div.

Remarks:Theovershoot at the collector voltageof the driver transistoris damped by R5 and C10. The current spike in the basedrive current (marked with *) is the reverse conduction ofthe deflection transistor during the forward recovery of thedamper diode. See also oscillogram 1.

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4. Vertical Deflection, Synchronisationand Geometry ControlThe vertical deflection, synchronisation and geometrycontrol circuits are based on an existing PCALE report (ref3). Because for this application another tube and line outputtransformer are used some minor modifications arerequired (component values), see Fig. 7.

- Due to the increased deflection current, the verticalfeedback resistor must be decreased: one of the 2.2Ωresistors becomes 1Ω.

- Due to the increased beam current, the EHTcompensation network at pin 24 of the TDA8433 needs tobe modified: 120kΩ → 100kΩ, 82kΩ → 150kΩ,27kΩ → 33kΩ, 68 nF → 10 nF.

- For additional phase shift pin 14 of the TDA2579 is biasedwith a current from a negative voltage source (rectified fromthe Φ2 feedback pulse). While this feedback pulse is smallerthan in the original circuit, the 240kΩ resistor must beincreased to 1.2MΩ.

Orientation values for the TDA8433 register settings are:

reg hex

00 2501 5A02 0703 2C04 2B05 1606 1607 1508 2209 210A 210B 0F0F 04

Oscillogram 5:Vertical deflection current (1A/div) and the output voltage(pin 5) of TDA3654 (10V/div). The time base is 5ms/div.

Remarks:The noise on the output voltage is cross talk from the linedeflection coils.

5. Video AmplifiersThe gun of this picture tube is a new design and has itsoptimum performance at a cut off voltage, VCO = 160V. Thisimplies that the video supply voltage should be at least 20Vhigher, so Vvideo ≥ 180V. A video amplifier very well suitedfor this purpose is the TDA6100.

The RMS voltage of the heater winding of the line outputtransformer is V10 = 7.35VRMS, so a series resistor must beused (3.9Ω; 400mW).

6. ReferencesInformation from this section was extracted from"Application information for the 16 kHz black line picturetube A66EAK022X11 and A59EAK022X11"; ETV89010 byHan Misdom.

1. "Some aspects of the diode modulator"; EDS7805 byC.H.J. Bergmans.

2. "A synchronous 200W Switched Mode Power Supplyintended for 32kHz TV"; ETV89009 by Henk Simons.

3. "Deflection processor TDA8433 with I2C-bus control";ETV8831 by D.J.A. Teuling

4. "Application of the TDA6100 video output stage";ETV8811 by D.J.A. Teuling

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Fig. 7. Vertical Deflection, Synchronisation and Geometry Control

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4.2.2 32 kHz / 100 Hz Deflection Circuits for the 66FS Black LinePicture Tube

This report contains a description of deflection circuitry(horizontal 32 kHz, vertical 50-120 Hz) for the 66FS picturetube A66EAK22X42. This design is intended for flicker freeTV applications. Provision is made to supply the power forthe frequency conversion box.

SummaryThe 66FS picture tube is compatible but not identical withthe types of the 45AX range. To obtain the typical Blackline high contrast and high brightness, the beam currentand EHT must be increased at nominal operatingconditions. This higher EHT also improves the spot quality.The deflection current is increased because of the higherEHT and reduced sensitivity of the deflection unit.

In comparison with laboratory report ETV8713, describingdeflection circuits for 45AX, most modifications are foundin the horizontal deflection stage. To generate theincreased EHT power a new line output transformer (LOT)with a four layer EHT coil is used. To handle the higherdeflection currents two transistors are used in parallel andalso two flyback capacitors are used. We have also takenthe opportunity to introduce the TDA8433. This deflectionprocessor -in BiMos technology- is the successor of theTDA8432.

The vertical deflection stage is redesigned in such a waythat vertical shift signals can be inserted without bouncingeffects. The insertion of vertical shift signals is necessaryin 100 Hz operation for a proper interlace.

1. IntroductionIn this report a description is given of double line and framefrequency (32 kHz; 100 Hz) deflection circuits for the 66FS

picture tube A66EAK22X42. The report is based on reportETV8906, describing these circuits for the 78FS picturetube 1. By changing some component values the pcb forthe 78FS can also be applied to drive the picture tubeA66EAK22X42. In the line output stage the outputtransistor BU2508 is used.

2. General description

2.1 Block diagram

The block diagram is given in Fig. 1. The maininterconnections are given as well. The separate blockscan be recognised in the circuit diagram.

The separate H and V sync and V shift are available fromthe frequency conversion box.

2.2 Circuit architecture

A key component in this set up is the deflection processorTDA8433. The horizontal and vertical picture geometry canbe controlled by means of I2C bus commands. Becausethis deflection processor has no vertical oscillator, there willbe no vertical deflection when there are no vertical syncpulses applied to the set. For laboratory purposea separatevertical oscillator is added to make the monitor part a selfcontainedunit. When incorporated in a receiver this verticaloscillator can be omitted. When there are no vertical syncpulses, the guard circuit of the vertical output stage willblank the video information. This prevents spot burn-in ofthe tube.

Fig. 1 Block diagram

HORIZONTALOSCILLATOR

HORIZONTALDRIVER AT4043/87

HORIZONTALDEFLECTION& EHTAT2077/33TDA2595

VERTICALOSCILLATOR

DEFLECTIONPROCESSOR

TDA8433

EW DRIVER

AUXILIARYSUPPLY

AT4042/32B

VERTICALDEFLECTION& DC SHIFTTDA 3654

H SYNC

V SYNC

I2C BUS V SHIFT

361


The vertical deflection stage consists of the well knownTDA3654 vertical output IC. To make vertical shift insertionpossible, the output stage is slightly redesigned. This accoupled output stage now has a quasi dc coupledbehaviour.

The EW driver is a voltage amplifier, acting as a bufferbetween the deflection processor and the diode modulator.

The block "horizontal oscillator" consists of the TDA2595with its Φ1 and Φ2 loop, the horizontal oscillator itself andsandcastle generation. The other features of this ic are notused.

Coupling between the TDA2595 and the deflection stageis made by the horizontal driver stage. This stage is atransformer coupled inverting driver stage.

The horizontal deflection stage is a classic concept. Itconsists of a combined deflection and EHT generation. Italso comprises linearity correction, S-correction, inner pincushion correction and a dc shift circuit. The LOT(AT2077/33) belongs to the transformer family DSB (diodesplit box) and has four EHT layers. It delivers the followingvoltages:

* EHT = 27.5 kV @ 1.3mA* Focus = 0.22 - 0.30 x EHT* Vg2 = 0.011 - 0.033 x EHT* Heater ≈ 10.4VRMS

* Video supply = 192V* Frame supply = 28V* Φ2 ref. pulse = +40Vpp

Furthermore the LOT has some taps which can be usefulwhen the application is modified.

In parallel to the primary winding of the LOT the auxiliarysupply transformer (AT4043/32B) is located. This auxiliarysupply delivers the following voltages:

* +5V @ 5A* +15V @ 1A* -12V @ 1A

These supply voltages are intended for the digital andanalog signal processing circuits.

The philosophy behind this circuit needs some furtherexplanation.

It is very difficult to generate exactly 5V at the output of anSMPS or LOT. Due to an optimum winding design of thiskind of transformer, the voltage ratio per turn is high (2 - 5Vper turn). This implies that a stabilizer is required. Aswitching post regulator adds to the circuit complexity andcost. A dissipative series stabiliser needs at least 2V, sofor a 5A supply the losses are already 10W.

The auxiliary transformer used in this concept is optimisedfor generating these low voltages at high currents. Thewinding design is such that no stabilizer is required afterthe rectifier. Due to the high primary inductance of thistransformer the collector current increase of the deflectiontransistor is negligible.

If the auxiliary loads are low, this auxiliary supplytransformer can be omitted and the unused taps of the LOTcan be used to generate these voltages.

3. Circuit description

Using circuit diagram blocks the total concept will beexplained. This will be done with reference to the functionblocks of Fig. 1. The complete circuit diagram is given inFigs. 11-13.

3.1 Vertical oscillator

As already stated in section 2.2 this vertical oscillator canbe omitted in a final design. The circuit is shown in Fig. 2.

This oscillator is the well known astable multivibrator builtup around T8 and T9. This oscillator is free running at 45 Hzand can be synchronised up to at least 120 Hz. T7 is anadditional sync transistor and is ac coupled to the verticalsync signal (TTL level).

Fig. 2 Vertical oscillator

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3.2 Deflection processor TDA8433The TDA8433 is an analog, I2C bus controlled, deflectionprocessor. It generates the vertical deflection currentwaveform and the EW (East-West) waveform. Thenecessary corrections on these waveforms are I2C buscontrolled. This ic also includes some DACs and ADCs.They can be used for control functions of other circuitry 2.

The resistor at pin 4 determines the reference current forthis ic. Pin 2 is the vertical sync input. At the capacitor atpin 5 (C-flyback) a triangle waveform is generated which isused for internal timing. This signal is used to generate thevertical sawtooth at pin 22 (C-saw). At pin 23 (C-amp1) astorage capacitor of the amplitude stablisation loop is foundwhose voltage determines the amplitude of the sawtooth.The V-sync input can only handle unequal spacings of thepulses if there is a 2-sequence (e.g. Teletext 312-313 lines).A 4-sequence from the 100 Hz box cannot be handled bythe amplitude loop.

The vertical sawtooth is internally connected to the"geometry control" section. In this section S-correction,vertical shift and linearity correction are added to thesawtooth by I2C commands. The amplitude is controlledby pin 24 (EHT-comp) to compensate for EHT variations.

From here the signal goes to one input of the internal erroramplifier. The other input is connected to pin 21 and theoutput to pin 20. By means of an I2C command the externalinput pin can be selected as an inverting or non-invertinginput. This provision is made to handle both non-invertingand inverting vertical output stages.

The block "geometry control" also generates the EWparabola. The I2C bus controllable functions are: parabola,corner, trapezium and picture width. By means of the signalat pin 24 this signal is corrected for EHT variations. TheEW drive output is available on pin 19.

On the digital side of this IC we find the following functions:

Pin 15 (SCL) is the Serial CLock and pin 14 (SDA) is theSerial DAta. Pin 1 is the address pin and can either beconnected to ground or +12V. The three external DAconverters can be controlled by the bus: DACA, DACB &DACC. With DACA the horizontal free funning frequencyof the TDA2595 can be adjusted. The other two DACs (pin7 & 6) are not used. They can be used for H-shift andH-phase control. See appendix A.

Pins 9 and 10 are output switch functions: not used in thisapplication. When pin 10 is programmed high, it can beused as an input pin. Together with pin 17 it forms acomparator. Pin 10 is connected to the Φ1 voltage of theTDA2595 and pin 17 to the reference voltage. In this wayan I2C bus signal is available whether the horizontaloscillator is in centre, locked and mute or coincidence soinformation can be sent to the IN-input. This also makesautomatic fO adjustment possible.

The supply part of this IC contains 4 pins. Pin 18 is groundfor the geometry and sawtooth part: pin 13 is ground for theoutput stages and I2C bus. Pin 12 is the +12V input and atpin 16 an external capacitor is required for filtering the +5V(internally generated).

Fig. 3 Deflection processor TDA8433.

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3.3 Vertical output stage

The vertical output stage is controlled by the well knownTDA3654. To make this stage suited for 100 Hz TV somemodifications of the ordinary solution are required. Thecircuit is shown in Fig. 4.

A damper network is located in parallel to the verticaldeflection coil. The values depend on the characteristicsof the deflection unit. The line ripple that is injected fromthe horizontal deflection coil is damped by the seriesconnection of R55 and C48. R55 reduces the line ripple toan acceptable value. C48 is added to block the relativelylow vertical deflection voltage in order to limit the dissipationin R55. A resonant circuit is created by C48 and theinductance of the deflection coil. R54 is a critical damperfor this circuit to minimise excessive oscillations after thevertical flyback.

The deflection current is sensed by two 1.5 Ω resistors inparallel and fed back to the deflection processor. Thenetwork C36, R45 and C35 is added for a stable looptransfer because of the non resistive load at the output ofthe TDA3654.

The output stage is ac coupled. The dc bias point is fixedby the resistors R60 and R61. By the V-shift setting of theTDA8433 vertical shift of the picture is possible.

An additional shift circuit is connected in parallel to the dcshift circuit to make an alternating frame shift possible. Itconsists of T11 and its series elements. When T11 isconducting asmall dc current will flow through the deflectioncoil. Due to the S-correction of the verticaldeflection currenta smaller current is required at the top and bottom than inthe middle of the tube to guarantee proper interlacingacross the whole screen. Therefore, the waveform of theshift current is derived from the parabola voltage of C49. Apotentiometer is provided because this interlace setting iscritical.

The drive signal required for this alternating frame shift isgenerated by the 100 Hz conversion box.

If two independent shift signals are needed, the wholecircuit must be duplicated.

3.4 Horizontal oscillatorThe horizontal oscillator used is the TDA2595. Thehorizontal sync signal (TTL level) is divided and ac coupledto the input pin 11. At pin 14 the reference current is setby a 13 kΩ resistor. The sawtooth capacitor for theoscillator is connected to pin16. The free running frequencyis 31.25 kHz and determined by the value of its capacitorand the reference current. By varying the reference currentthe free running frequency can be adjusted. This is doneusing the DAC-A output (pin 8) of the TDA8433 via resistorR25, see section 3.2.

Fig. 4 Vertical output stage

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This oscillator is locked to the incoming sync signal by aPLL (Phase Locked Loop). The starting point of thehorizontal sawtooth is compared with the horizontal sync.If this starting point is not in the middle of the horizontalsync pulse, an error signal will appear at pin 17. Via R27the current of pin 14 is affected and thus the horizontalphase can be locked. The loop filter consists of C25, R28and C26.

The output of the oscillator is internally connected to asecond PLL Φ2 and to a phase shifter. The phase shiftedsignal is available via an output stage at pin 4 (horizontaloutput). This signal drives the deflection stage. A feedbacksignal of the deflection stage is applied to the other inputof the Φ2 phase detector (pin 2). In this way the horizontalflyback of the deflection stage is locked to the oscillator andthus to the sync as well. The loop filter of Φ2 consists ofone capacitor at pin 3. This second PLL has a much largerbandwidth to compensate for the storage time variations inthe deflection transistors.

At pin 6 a two level sandcastle pulse is available. It is mixedwith the vertical blanking signal of the TDA8433 or theflyback of the TDA3654 to generate a three levelsandcastle. See also the description of TDA8433 section3.2 and TDA3654 section 3.3.

Pin 7 is the mute output. This signal is sent to the TDA8433so that "oscillator locked" information is available at the I2Cbus.

As these kinds of ic are sensitive to supply pollutionprovision is made for a local supply filter R21, C18 and C19.

For layout recommendations see section 4.

3.5 Horizontal drive circuit

The horizontal drive circuit is a classical transformercoupled inverting driver stage. When driver transistor T1is conducting, energy is stored in the transformer. WhenT1 is turned off the magnetising current continues to flowin the secondary side of the transformer thus turning on thedeflection transistor. At this time the voltage on thesecondary side of the driver transformer is positive(VBE+IB*R6). When the driver transistor turns on again thissecondary voltage reverses. At the same time energy isstored in the transformer again.

During this turn off action the forward base drive currentdecreases with a controlled dIB/dt, thereby removing thestored charge from the deflection transistor. The dIB/dtdepends on the negative secondary voltage and theleakage inductance. When the drive circuit is designedproperly, the deflection transistor stops conducting whenits negative base current is about half the collector peakcurrent.

Fig. 5 Horizontal oscillator

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Fig. 6 Horizontal drive circuits

To prevent the deflection transistor from turning on duringflyback due to parasitic ringing on the secondary side of thedriver transformer a damp resistor is connected in parallelwith the base emitter junction of the deflection transistor.

Also at the primary side of the driver transformer a dampnetwork is added (R4 & C5) to limit the peak voltage on thedriver transistor.

Fig. 7 Horizontal deflection

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3.6 Horizontal deflectionThe horizontal deflection is the classical deflection stagewith the diode modulator which not only provides the EWraster correction but also inner pincushion correction. Dueto the high frequency in combination with large currentssome problems do appear here. The horizontal deflectioncoil needs 10.4A peak-to-peak. This results in a collectorpeak current of 6-7A, too much to handle with oneBU2508A. So, two transistors are used in parallel. If theprint layout is made in a proper way no special precautionsare required to use this type of transistor in a parallelconfiguration. (NB the circuit was constructed before theBU2525A became available.)

For the flyback capacitor the current is too high as well. So,here, also, two devices are used in parallel. TheS-correction capacitors do not have problems in handlingthe current.

There are two possible solutions for the damper diodes.The BY359 is a high current damper diode available inisolated and non-isolated TO220 packages. This devicehas been re-designed for operation as a damper diodespecifically for 32 kHz deflection systems. An alternativesolution is to place a third diode in direct parallel with thecollector-emitter’s of the deflection transistors. This optionallows two cheaper axialdiodes to be used in the modulator,eg BY328. This option is shown in Fig. 7.

For full performance of scan linearity a horizontal dc shiftcircuit is incorporated. In an ordinary TV set the horizontaloff centre of the picture tube is compensated by the phaseshift of the horizontal oscillator. This, however, introducesa linearity error in the deflection. In many cases this erroris acceptable; if not, it can be compensated by means ofan adjustable linearity corrector.

Fig. 8 East - West amplifier

The most proper way of picture alignment is the following:the linearity corrector is only used for compensating thelinearity error caused by the resistive part of the impedanceof the horizontal deflection yoke. The off centre of the tubeis compensated by ashift circuit. Therefore, a dc shift circuitis incorporated. This circuit has been built up around L5.

With P1 the amount of shift current can be adjusted andwith S1 the polarity can be selected. The horizontal shiftcan be made bus controlled by using DAC-B or DAC-C ofthe TDA8433. A suggestion for a suitable interface is givenin Appendix 2.

3.7 East - West correction

Fig. 9 EHT generator

The EW waveform is generated by the deflection processorTDA8433. An external amplifier feeds this correction to thehorizontal deflection stage. It is injected in deflection via

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L2. The possible corrections are: picture width, EWparabola, corner correction, trapezium and EHTcompensation.

The EW amplifier is shown in Fig. 8. It consists of aDarlington power transistor, T6, a differential amplifier, T4& T5, and a feedback network R13 R14. R12 is added forproper dc bias. Because this amplifier has a non real load,special attention is paid to loop stability. Across T6 thereis a miller capacitor, C14. The line ripple current of L2 flowsmainly through C15 and R16.

3.8 EHT generation

The darker glass requires a higher EHT power for an equallight output. An increase of only the beam current has twodisadvantages: a larger spot size and a higher drive fromthe video amplifiers. An increase of only the high voltagewouldcome inconflict with the legislation on X-ray radiation.

As a compromise an EHT of 27.5kV @ 1.3mA is chosen.A new design of LOT is used, see Fig. 9. This LOT is afour layer diode split box (DSB) design with extra highvoltage capability. From an integrated potentiometer theadjustable focus and grid 2 voltages are taken.

3.9 Auxiliary supplySome of the auxiliary supplies are taken from the LOT suchas heater, video and frame supply. The other auxiliarysupplies are taken from a separate transformer. Thephilosophy behind this concept is explained in section 2.2.

The auxiliary transformer is connected in parallel to theLOT. On the secondaryside of this transformer the auxiliaryvoltages are taken. These outputs supply the signalprocessing circuitry (5V @ 5A, 12V @ 1A, -12V @ 1A).

Theprimary inductance of this transformer is relativelyhigh,so the increase of collector current in the deflectiontransistor is low. To adjust the output voltage the primarywinding has some taps. Due to the relative high ESR ofthe 5V smoothing capacitors a π-filter is required.

With moderate current levels all the auxiliary supplies canbe taken from the LOT.

4. PCB design considerationsFor general information see reference 3.

4.1 TDA2595The following tracks and pins of the TDA2595 are criticaland need special attention:

* The track length at pin 14 - reference pin - to itsperipherals should be kept as short as possible.

Fig. 10 Auxiliary supply

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* The peripheral components connected to pins 14, 16,3, 17 and 15 should be connected directly to the groundof this ic.

* The ground track of this ic may not carry current fromother parts of the set.

* As this ic is sensitive to high frequency ripple on thesupply rail, local decoupling is essential.

4.2 TDA8433

The following tracks and pins of the TDA8433 are criticaland need special attention:

* The components connected to pins 4, 5, 12, 16, 19, 22and 23 should be connected to the analog ground (pin18) and as close as possible.

* The track length of the pins 4, 5, 22 and 23 should beas short as possible.

* The ground track of this ic may not carry current fromother parts of the set.

* Local decoupling is essential because this ic issensitive to high frequency ripple on the supply rail.

4.3 Horizontal deflection and supplies

This kind of circuit carries currentswith high dI/dt. The loopsthat contain these currents should have an area as smallas possible to limit magnetic radiation. Examples are theloop of deflection coil with the deflection transistors, diodesand flyback capacitors. Also the loop formed by smoothingcapacitor C43, primary of LOT and deflection transistorshould be kept small.

In case of rectifiers the ground track between transformerwinding and smoothing capacitor may not be a part of anyother ground track.

4.4 Drive circuit

To ensure current balance in the deflection transistors, thebase and emitter tracks of the two transistors should be assimilar as possible to create the same impedances for bothtransistors.

5. Oscillograms

All oscillograms were taken under nominal load conditionsof the auxiliary supply and 1mA beam current.

Oscillogram 1:

In this oscillogram the upper two traces show the averagedeflection current (2A/div) and the voltage across thedeflection transistors (200V/div). The peak VCE is 1244V.

The lower two tracesare the minimum andmaximumvaluesat the mid-point of the diode modulator (100V/div) due toEW modulation.

Remarks:

At the end of flyback there is a negative over shoot at thecollector voltage. This is caused by the forward recovery ofthe damper diode.

Oscillogram 2:

The lower trace is the current in the deflection transistors.The upper trace is the current in damper diode D4 and themiddle trace is the current in the upper flyback capacitors(C7 + C8). All current settings 2A/div.

Remarks:

At the end of flyback the current in the flyback capacitor istaken over by the damper diodes. Due to parasiticcapacitance and inductance ringing occurs. 5µs later there

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is a negative current in the deflection transistor. This isreverse conducting of the base-collector of the transistorcaused by the fact that the base drive is already turned on.

Oscillogram 3:

In this oscillogram the upper trace is the current in the lowerflyback capacitors C9 + C10. The second trace is thecurrent in the diode D5. In the bottom part the current inthe bridge coil is given and the deflection current is shownonce more as a reference. All settings 2A/div.

Oscillogram 4:

In this oscillogram the deflection transistor IC and VCE aregiven as a reference. The upper trace is the current in thethird diode D3. As soon as the deflection transistor is turnedon the current of D3 is taken over by the transistors. Allcurrent settings 2A/div.

Oscillogram 5:

The upper trace is the VBE of the deflection transistors(5V/div). The middle trace is the IB of the deflectiontransistors (1A/div). The lower trace is the VCE of the drivetransistor T1 (50V/div).

Remarks:

The over shoot at the rising edge of the driver transistor iscaused by the leakage inductance of the driver transformer.By means of the damping network R4, C5 this over shootis limited. This network is chosen in such a way that theringing is critically damped.

The base drive circuit is designed in such a way that thepeak of the negative base drive current, IBoff, isapproximately half the collector current, IC. During turn offthe VBE of the deflection transistor should remain negative.To achieve this the ringing is damped by R7 and R8.

Oscillogram 6:

This split screen oscillogram was made with two differenttime base settings. In the upper grid the minimum andmaximum values of the flyback pulses across C9 + C10 ofthe diode modulator are given under nominal conditions.The lower grid shows the amplified EW drive signal(collector T6 5V/div) and the output of the TDA8433 (pin 192V/div).

Remarks:

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At the collector of T6 some line ripple is visible.

Oscillogram 7:

The upper trace gives the vertical sync signal (1V/div,100µs/div). The middle trace is the sandcastle (5V/div,100µs/div). The lower trace is the sandcastle during verticalscan (5V/div, 10µs/div).

Remark:

This three level sandcastle pulse is the sum of the two levelsandcastle of the TDA2595 and the vertical blanking of theTDA8433.

Oscillogram 8:

The upper trace is the generated sawtooth at pin 22 of theTDA8433 (5V/div). The second trace is the output signalof the error amplifier of the TDA8433 pin 20 (5V/div). Thethird trace is the sawtooth current in the vertical deflectioncoil (1A/div). The lower trace is the output signal of thevertical output amplifier TDA3654 pin 5 (20V/div).

Remark:

Due to the L/R of the vertical deflection coil the current inthe coil can not follow the fast retrace time of the sawtoothgenerator. The output amplifier clamps after the flyback to2xVb. When the control loop locks after the flyback, a slightvoltage overshoot can be found at the output of theTDA3654. This is damped by C48, R55 and R54.

Oscillogram 9:

The lower trace is the voltage at the foot point of the lineoutput transformer (10V/div). This signal is a representationof the EHT variations needed by the anti breathing.

The upper trace is the EW waveform at T6 (5V/div). Onthe EW waveform a correction signal is added to preventthe picture from breathing.

6. References

Information for this section was extracted from"32kHz/100Hz deflection circuits for the 66FS Black Linepicture tube A66EAK22X42"; ETV89012 by J.v.d.Hooff.

1. P.C.A.L.E. report ETV8906. "32 kHz / 100 Hzdeflection circuits for the 78FS picture tube" by Mr.J.A.C. Misdom.

2. C.A.B. report ETV8612. "Computer controlled TV; thedeflection processor TDA8432" by Messrs. E.M. Ponteand S.J. van Raalte.

3. C.A.B. report ETV8702: "EMC in TV receivers andmonitors" by Mr. D.J.A. Teuling.

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7. Circuit diagrams

Fig. 11 Horizontal Deflection and EW Amplifier

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Fig. 12 Deflection Processor and Horizontal & Vertical Oscillators

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Fig. 13 Auxiliary supply, EHT Generator and Vertical Output Stage

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Appendix A

Fig. A1 Bus controlled dc shift

The deflection processor TDA8433 has three DAC’s. Inthis application only one DAC (DAC-A) is used. In thissection some ideas are given to use the other two DAC’s.

DAC-B is a 6-bit DAC, like DAC-A, and is controlled by theH-PHASE register. Its output voltages can be controlledfrom 0.5V to 10.5V typically. The output resistance is lessthan 1kΩ.

DAC-C is a 2-bit DAC and is controlled by the VTRA andVTRC bits. Its typical output characteristic is:

VTRA VTRC Output voltage Output resistance

0 0 12V 7.5kΩ0 1 5.3V 3.3Ω1 0 1.7V 1.0kΩ1 1 0.3V <1kΩ

All settings in the set that are now manual controls can bemade I2C bus controlled by using one of these DAC’s. Theonly restriction is that the alignment is controlled with a dcvoltage. Otherwise an interface circuit is needed.

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Appendix B

As a degaussing circuit the following suggestion is given.

Fig. B1 Degaussing Circuit

Parts list:

Dual degaussing PTC : 2322 662 96116

Degaussing coil : 3111 268 20301

Oscillogram 10:

Current in degaussing coil 2A/div.376


SMPS Circuit Examples

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4.3.1 A 70W Full Performance TV SMPS Using The TDA8380

The following report describes the operation of a 70W fullperformance switched mode power supply for use intelevision.

The TDA8380 SMPS control ic is used in a mains isolated,asynchronous flyback converter configuration.

The power supply incorporates the following features:

· Full mains range (110 - 265Vrms)

· AT3010/110LL SMPS transformer

· BUT11A switching transistor

· Standby (suppression of output voltages by 50%)

· Standby supply (5V, 100mA)

· Facility for synchronisation (using a pulse transformer)

· Short start-up time (less than 0.3 sec at 220Vrms)

· Provision for anti-breathing circuit

· Output voltages 147V/57W, 25V/5W, 16V/7.5W

A full description of circuit operation, a circuit diagram andcircuit performance figures are given.

A further additional circuit diagram is included in which theabove power supply incorporates a power MOS switchingtransistor for a mains range of 90 - 135Vrms. Also detailsare given on an extension to the power capability of thesupply, up to 120W output, for European mains using thebipolar switching transistor.

1. IntroductionThe TDA8380 control ic has been designed to enable safe,reliable and efficient SMPS to be realised at minimum costfor TV and monitor applications. For further information onthe ic, reference should be made to ‘Integrated SMPSControl Circuit TDA8380’ (ref. 1).

The 70W design employs a currently availableAT3010/110LL foil wound transformer and the BUT11Abipolar switching transistor.

Feedback is taken from the secondary side to give less than1% line and load regulation over the whole range. Theoutput voltage is suitably divided down and compared in anerror amplifier with a fixed reference voltage. The erroramplifier then drives an optocoupler, which passes the errorsignal to the primary side directly into the TDA8380. Asecondary side error amplifier is used to reduce theimportance of the optocoupler characteristics.

Standby is achieved by injecting a signal into the feedbackloop on the secondary side, suppressing all output voltagesby 50%. A 5V standby supply is available relieving the needfor a separate standby supply. During standby conditionsthe line output oscillator is halted to disconnect the mainB+ load.

Synchronisation of the power supply to external controlcircuits is possible through a loosely coupled pulsetransformer.

Appendix A gives a circuit diagram and a short descriptionof the use of the power MOS switching transistor in the 70Wsupply. The mains range is 90 - 135Vrms.

Appendix B gives notes on how to extend the powercapability of the 70W power supply to 105W, 32 kHz and120W, 30 kHz. Both these power supplies have a mainsrange of 180 - 265Vrms.

2. TV SMPS designFlyback versus Forward Converter.

Although this ic can be applied in any type of SMPS, forexample in FORWARD (or Buck) or FLYBACK (orBuck-boost) converters, the preferred SMPS type for TVapplications is the Flyback converter. This is mainlybecause it allows for mains isolation of the TV chassis.Other advantages it affords in comparison with a forwardconverter are:

(a) It does not need ‘crow-bar’ protection against the inputvoltage appearing across the chassis in the event ofshort-circuit failure of the power switching transistor.

(b) The load permissible on auxiliary output supplies is notrelated (and, therefore, not limited) by the main linetimebase supply (B+ voltage) load. Thus the auxiliarysupply is available when there is no B+ voltage load,and this is important for servicing and fault finding on aTV chassis.

With the Flyback converter, however, mains pollution andvisible interference require to be minimised by careful PCBlayout and customarily a mains input filter is used.

Discontinuous versus Continuous Current ModeOperation:

Operation canbe in the ‘continuous’ or in the ‘discontinuous’current mode.

In the discontinuous mode the power switching transistoris not allowed to switch on until the SMPS transformer coreis demagnetised. This has the advantages:

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(a) It is inherently a safer mode of operation, since for alloperating conditions, other than a dead-short of theoutput or a very severe overload transient occurringwhen the power transistor is conducting near peakcurrent, it is not possible for the core to saturate. Toprotect for these two exceptions, the very fast (secondlevel) current protection is included.

(b) Steep current pulse edges at switch-on are eliminated(important from point of view of Radio FrequencyInterference problems).

Satisfactory performance, in terms of voltage regulationand input mains voltage range, can be obtained using thediscontinuous mode which is, therefore, preferred for TVapplications.

For this type of converter, the voltage transfer function canbe deduced from the Volt-second equilibrium condition fora unity turns ratio transformer:

(1)

where:

Taking into consideration the transformer turns ration n =Np/Ns, then:

(2)

where: = oscillator period= transformer primary turns= transformer secondary turns= on time of output transistor= conduction time of output rectifier= output B+ voltage= input DC voltage

The limit condition for ‘discontinuous’ current modeoperation occurs at minimum input voltage and maximumload.

Thus, for this condition

so that

(3)

The power output (including losses supplied via thetransformer) is:

(4)

where: = primary inductance of transformer= frequency of operation

from which general expressions for d, Lp and f can beobtained in terms of the power.

Thus, for a given transformer (n,Lp) the value of dmax canbe calculated from (3) and the required frequency ofoperation from:

(5)

The peak current in the power switching transistor is givenby:

(6)

The peak voltage across the power switching transistor(excluding ringing) is:

Since most transformers produce ringing, a clamp circuitmay be necessary and in order to slow the rising edge ofthe voltage a snubber circuit is usually required.

3. General circuit descriptionThis section gives an overall general description of thepower supply.

Fig. 1 shows a block diagram of the circuit functions.Descriptions of specific circuits will be carried out in the nextsection.

3.1 Mains filterThis is positioned at the ac mains input. Its function is tominimise mains pollution resulting from RFI generatedwithin the SMPS due to fast transients of voltage andcurrent. It is designed to meet the required mains pollutionregulations (C.I.S.P.R. Special Committee on RadioFrequency Perturbation).

3.2 Rectification and SmoothingThe mains voltage is rectified and smoothed to provide adc supply which is switched through the SMPS transformer.

3.3 SMPS ControllerThis drives the power switching transistor regulating thefrequency and the amount of current pulsed through thetransformer primary. Thus, the controller regulates theenergy transferred to the secondary windings. A voltagefeedback signal which is representative of the outputvoltage is fed back to the controller in order to regulate theoutput voltage. At start up the supply voltage for thecontroller ic is derived from the rectified mains. A ‘take-over’winding on the transformer supplies the ic once normaloperation is established.

3.4 Transformer secondary circuitsThe dc output voltage is obtained by simple rectificationand smoothing of the transformer secondary voltage.

f =dmax2 × Vimin2

2× P × Lp

Ip =Vi × dLp × f

Vi + (n × Vo)

Vi × d × T = Vo × d × T

VoVi

=d

d

d = (1− d)

n × VoVi

=d

d

TNpNsddVoVi

d = (1− d)

n × VoVimin

=dmax

(1− dmax)

P =Vi2 × d2

2× Lp × f

Lpf

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3.5 Feedback AttenuatorThe output voltage to be regulated is fed back via anattenuator to the error amplifier.

3.6 Error AmplifierThe error amplifier compares the feedback signal with afixed reference voltage to give an error signal which ispassed to the primary side via an optocoupler.

Mains isolation is provided within the optocoupler and thepower transformer, between the input primary andtake-over, and the output secondary windings.

4. Detailed circuit descriptionThis section gives a detailed description of each of thefunctions of the power supply circuit (Fig. 2).

4.1 Mains Input and RectificationDiodes V1 to V4 rectify the ac mains voltage and, togetherwith a smoothing capacitor C13, provide a dc input HTvoltage for the SMPS. R1 is placed in series with the inputto limit the initial peak inrush current whenever the powersupply is switched on when C13 is fully discharged.

C1 and C3 together with L1 form a mains filter to minimisethe feedback of RFI into the mains supply.

C6 to C9 suppress RFI signals generated by the rectifierdiodes.

Asymmetrical mains pollution is reduced by the insertion ofR26 and C18 between primary ground (‘hot side’) andsecondary earth (‘cold side’) of the power supply. Thesecomponents are required to satisfy the mains isolationrequirements.

4.2 Control ic TDA8380This section describes the function of each pin of theTDA8380 and its associated components.

Pin 1 - Emitter of Forward Drive Transistor:

The TDA8380 incorporates a direct drive outputstage consisting of two NPN transistors. Thecollector and emitter of each are connected toseparatepins of the ic (pins 1,2,15,16). The forwardbase drive current for the switching transistor islimited by R15. C16 acts as a voltage source equalto the zener voltage of V7 and is used for thenegative base drive.

When the reverse drive transistor is turned on thezener voltage appears across L2, causing storedcharge to be removed from the switching transistor,thereby ensuring correct storage time andminimum transistor dissipation during turn-off.

Pin 2 - Collector of the Forward Drive Transistor:

Connected through a resistor to the ic reservoircapacitor.

Pin 3 - Demagnetisation Sensing

Demagnetisation protects the core of thetransformer against saturation by sensing thevoltage across a transformer winding. In thisapplication operation is in the discontinuous currentmode. Sensing is achieved by resistor R10 fromthe take-over winding of the transformer to pin 3 ofthe ic. Fig. 3 illustrates demagnetisation operationat low mains where the turn-on pulse is delayeduntil demagnetisation of the transformer iscomplete.

Pin 4 - Low Supply Trip:

Connected to the ic ground (pin 14), the low supplyprotection level is 8.4V.

Pin 5 - IC supply:

On power-up the ic supply is first drawn from C15.This capacitor is charged up directly from therectified mains through bleed resistors R21 andR24.

Once the SMPS is running, the supply for the ic istakenover by the SMPS transformer. R12 preventspeak rectification of spikes. V8 rectifies the flybacksignal which is smoothed by C15 to give a dc level.R16 limits the current drawn by the forward drivetransistor. R9 and C5 provide a filtered dc supplyto pin 5.

Pin 6 - Reference Current:

This pin allows the external setting of the IC currentsource. This is set by R11.

Pin 7 - Voltage Feedback:

This is the input to the internal error amplifier forprimary side feedback. Feedback in this case istaken from the secondary side and passed througha separate secondary side error amplifier where itis compared with a reference voltage. The errorsignal is then passed directly into the duty pin (pin9) via an optocoupler.

To ensure that the Transfer CharacteristicGenerator (TCG) in the ic remains optional a‘pseudo’ feedback voltage from the ‘take-over’winding of the SMPS transformer is applied to pin7. R3 and R4 provide a nominal 2.5V level at pin7 during normal operation of the power supply.

Pin 8 - Stability:

This is the output of the error amplifier which is leftopen circuit.

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Pin 9 - Duty:

This is the input to the pulse width modulator andis directly driven by the optocoupler transistor. R2,C2 and C27 form a frequency compensationnetwork.

Pin 10- Oscillator:

The frequency of the internal oscillator is set hereby C4 and R11 on pin 6 (nominally 25 kHz).

Pin 11- Synchronisation:

This is achieved by a loosely coupled pulsetransformer passing sync pulses from thesecondary to the primary side of the power supply(see later section).

Pin 12- Slow Start:

The slow start option is selected here by the use ofcapacitor C11. Fig. 4 shows a typical slow-start.

Pin 13- Over-Current Protection:

To keep the collector current of V10 within safeoperating limits over-current protection isincorporated into the power supply. R27 is thecollector current monitoring resistor providing anegative going signal. This voltage is then shiftedto a positive level with respect to ground potentialby a reference current from the ic flowing throughR14. An extra voltage shift is provided by R34which varies with the ic supply voltage. This isparticularly useful in output short circuit conditions.If the main regulated output is progressively shortcircuited, then all SMPS transformer flybackvoltages will decrease, respectively, and hence theshift level of the current protection function leadingto lower short circuit output currents (currentfoldback). The signal at pin 13 is then comparedwith two internal voltage levels to provide the twoforms of current protection.

(The addition of R34 may not work in other powersupplies using the TDA8380 because carefulattention has to be given to the ratio of currentthrough R34 to current output at pin 13 and to thestart-up sequence of the power supply at differentmains and loads. Conventional current protectioncan be achieved by omitting R34 and changing R14to 13 kΩ and V13 to BYW95C).

Fig. 5 illustrates the current protection waveform.

Pin 14- Ground

Pin 15- Emitter of Reverse Drive Transistor:

Grounded to the emitter of the switching transistor.

Pin 16- Collector of reverse drive transistor.

4.3 Error AmplifierThe external error amplifier consists of two PNP transistors,V15 and V16, connected to form a high gain comparator.The stabilized reference voltage for the comparator isderived from a series-connected resistor R28 and zenerdiodes V5 and V6 at the SMPS output. The voltage to becompared with the reference voltage is a sample of the147V output derived from a potential divider (R29, R31 andR5). The optocoupler is directly driven with the error signalfrom the comparator. The level of the 147V output can beadjusted by R5.

4.4 StandbyIn standby mode the power supply output voltages aresuppressed to 50% of their normal level. Standby isachieved by reducing the reference voltage used in thecomparator circuit and thus the power supply regulates ata lower output voltage level. A +5V dc level is applied tothe standby input, which turns transistor V14 on. Thevoltage reference level is halved from 12.4V to 6.2V andthe main 147V output is reduced to 75V. In this conditionthe power supply still maintains a 5V standby supply. Inthe television receiver during standby the line outputoscillator should be halted to disconnect the main 147Vload.

To return the power supply to its normal operating levels,the standby input is removed.

The speed of transition to and from standby is controlledby the time constant of R13, R32 and C23.

4.5 SynchronisationSynchronisation of the power supply is achieved by aloosely coupled mains isolated pulse transformer. Syncpulses of +5V are applied to the sync input at a frequencyslightly lower than the free running frequency of the powersupply. R6 limits the current in the primary winding of thepulse transformer and R8 loads the secondary winding.The pulse transformer differentiates the sync pulse input tocreate negative and positive going transitions of the syncinput. The ac coupling (C14) shifts the entire signal positiveand the internal circuitry of the ic clamps the negative goingexcursions to 0.85V. The positive going spikes areremoved by a transistor in the ic and the negative goingspikes are used to synchronise the oscillator. Fig. 6 showsplots of how the power supply is synchronised to a lowerfrequency.

A series RC network (C28, R35) is connected from pin 11to ground to filter out high frequency noise which mayinterfere with synchronisation.

If the synchronisation option is not to be used, the syncinput may be left open circuit. Another alternative is toshort-circuit C14 and remove T2.

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4.6 Beam Current Limiting (BCL)

Anti-breathing technique, whereby the 147V voltage isreduced for increasing beam current in such a manner asto compensate for the increase in picture size due to thefall in EHT. The components concerned are R30, C24, R7.

4.7 Power Switching Transistor

Pulsing of the transformer is carried out by the BUT11Abipolar power transistor under the control of the TDA8380.

Fig. 7 shows plots of the current through and voltage acrossthe BUT11A. The base drive waveforms are shown inFigs. 8(a)-(b) during standby conditions.

Fig. 9 is a plot of the instantaneous power dissipated in thetransistor during turn-off.

4.8 Snubber Network

A snubber network has been added across the switchingtransistor to protect it from excessive switching dissipationand to suppress ringing on the SMPS transformer.

The dV/dt limiter consists of V9, C17, R22 and R23. WhenV10 is switched off, part of the energy stored in the leakageinductance of the SMPS transformerwill chargeC17. WhenV10 is switched on again this energy is dissipated in R22and R23. When such a network is omitted, this energy mustbe dissipated in the switching transistor itself.

R22 and R23 are calculated in such a way that they alsoactas anetwork,damping the residualenergy in the windingcapacitance of the transformer when the secondaryrectifiers have stopped conducting.

4.9 Outputs

There are three secondary rectifiers; the 147V (scanvoltage for deflection stage), 25V (audio supply) and 16V(small signal supply). The 5V standby supply is derivedfrom a regulator connected to the 16V output.

R25 and C25 form a damping network to dissipate theenergy in the high frequency ringing on the B+ secondarywinding. Fig. 10 shows the current through and voltageacross the B+ winding.

A short circuit or overload of these outputs will cause thepower supply to repeatedly go through the slow startprocedure.

5. Performance specificationMains input: 110 - 265V ac 50 - 60 Hz

Outputs: B+ 147 V 57 W

Audio 25 V 5 W

L.T. 16 V 7.5 W

Standby 5 V 0.5 W

Switching frequency: 25 kHz

Efficiency (normal operation): 72 %

Line and load regulation: 0.1 %

Start-up time (220V rms, 300 msec (B+)full load): 225 msec (+5 V standby)

Max. collector current: 2.3 A

Max collector voltage: 870 V

Forward base current: Normal operation 0.30 A min.0.39 A max.

Standby (*) 0.20 A min.0.24 A max.

ic supply voltage: Normal operation 18.5 V min.21.0 V max.

Standby (*) 8.8 V min.9.7 V max.

Ripple output voltage (110V rms, 50 Hz, full load):

B+ L.T. Audio StandbyFrequency (mV) (mV) (mV) (mV)

25 kHz 600 230 145 20199 Hz 230 50 60 -

* The only load in this condition is the standby load.

6. Output short-circuit foldbackThe SMPS incorporates duty factor foldback protection forshort circuits on the 147V (B+) output. Fig. 11 shows theplot of the foldback characteristic for increasing load on the147V output using conventional protection and currentfoldback techniques.

8. ReferencesRef. 1. "Integrated SMPS Control Circuit TDA8380".

Philips Components Publication Number 9398 35840011December 1988.

383


Appendix A70W FULL PERFORMANCE USING POWER MOS (BUK456-800A)

A power MOS switching transistor was incorporated intothe 70W power supply design. This new power supply hasa mains range of 90 - 135V rms. A circuit diagram is givenin Fig. 12. Oscillograms of the power MOS gate and drainswitching waveforms are given in Figs. 13 and 14.

Alterations to Existing 70W Bipolar Transistor Design

(i) The value of C17 in the snubber is smaller, hence lessdissipation in the snubber resistors. The dV/dt at the drainis now higher, but the powerMOS transistor hasmuch lowerswitching losses than the bipolar transistor.

The smaller value of C17 causes the 100 kHz ringing onthe primary winding of the SMPS transformer after flybackto be more prevalent. This ringing has an effect on thedemagnetisation function causing premature operation. Toovercome this a resistive divider network has been usedon pin 3 to minimise the effect of ringing.

(ii) The value of R14, the current protection shift register,is increased. This is to compensate for the fact that thepower MOS transistor does not suffer from storage effectsat turn-off.

(iii) The filtering on the take-over winding for the ic supplyis increased. This is because the average currentdemanded by the gate drive of the power MOS is much lessthan in the caseof the bipolar transistor. Energy inswitching

spikes on the flyback voltage cannot be channelled into thegate of the power MOS and so has to be dissipated inincreased filtering.

A smaller value for the gate-source resistor is used toprovide extra loading on the transformer winding.

(iv) C13 is increased to filter the higher current ripple atlow mains voltages.

(v) A larger heatsink for the switching transistor isnecessary due to the higher on-resistance of the powerMOS transistor facilitating the need for higher heatdissipation.

Performance Specification

Mains supply: 90 - 135V rms

Switching frequency: 20.8 kHz

Outputs: B+ 147 V 57 WAudio 25 V 5 WL.T. 16 V 7.5 WStandby 5 V 0.5 W

Regulation: 0.1 %

Peak drain voltage: 650 V

Peak drain current: 2.3 A

Start-up time 300 msec

384


AddendumAlternative Cheap BUT11A Base Drive Design Eliminating 5 W Zener Diode

Fig. A1 - Alternative Cheap BUT11A Base Drive.

An alternative base drive for the power switching transistor(BUT11A) has been designed to eliminate the 5W zenerdiode 1N5339B (V7) to reduce cost.

Alternative Low Cost Base Drive

This design has not been implemented into a PCB designyet, but the existing PCB design requires little alteration toaccommodate the changes.

When the forward drive resistor is turned on at the start ofthe duty cycle, a current defined by R15 passes throughC16 and into the base of the BUT11A. The 1 kΩ resistorin parallel with C16 discharges the capacitor when theSMPS is off to help starting at low mains. When the reversedrive transistor is turned on, the 5.1V zener diode appearsacross C16 clamping the voltage across it, thus a reverse

current flows from the base of the BUT11A through C16and L2 turning off the power switching transistor. Someforward current does flow through the 5.1V zener diode, butnot enough to warrant a power zener. The BAX12A diodeacross the inductor is to prevent large negative going spikesappearing at pin 1 of the ic; this can also be used in theprevious base drive.

Base Measurements

Forward base current: 250mA min400mA max

Standby mode 190mA min(standby load only) 250mA max

BUT11A storage time: 1.4µsec

Fig. 1 - Block Diagram of SMPS with Secondary Side Feedback via an Optocoupler

MAINS MAINS

RECTIFICATION

SMPS

TRANSFORMER

SMPS

CONTROLLER

SECONDARY

RECTIFICATION

CIRCUITS

FEEDBACK

ATTENUATOR

ERROR

AMPLIFIER

FILTER

ISOLATION

START-UP

SUPPLY

DRIVE

TAKE-OVER SUPPLY

FEEDBACK

OUTPUTS

Vref

MAINS SUPPLY

385


Fig. 2 - 70W Full Performance TV SMPS (Bipolar switch)

Fig. 3 - 70W Full Performance TV SMPS (Power MOS switch)

386


Fig. 4 - Demagnetisation operation. Oscillogram of theOscillator Waveform and Transformer Primary Current

Fig. 5 - Slow Start. Oscillogram of the Voltage at the SlowStart Pin (TDA8380) and Current through the Switching

Transistor.

Fig. 6 - Current protection. Oscillogram of voltage at Pin13 (TDA8380) and the Current through the Switching

Transistor

Fig. 7 - Synchronisation. Oscillogram of OscillatorVoltage, Voltage at Pin 11 (TDA8380) and Sync Input

Voltage

Fig. 8 - Switching waveforms. Oscillograms of the currentthrough and voltage across BUT11A.

Fig. 9 - BUT11A Base Waveforms. Oscillograms ofBase-Emitter Voltage and Base Current Waveforms for

BUT11A

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Fig. 10 - BUT11A Base Waveforms During Standby.Oscillograms of Base-Emitter and Base CurrentWaveforms for BUT11A in Standby Conditions

Fig. 11 - Turn off dissipation in BUT11A. Oscillogram ofCollector-Emitter Voltage and Collector Current for

BUT11A

Fig. 12 - B+ Winding. Oscillogram of Voltage Across andCurrent Through the B+ Winding

Fig. 13 - Plot of Duty Factor Foldback using CurrentFeedback and Conventional Foldback Techniques

Fig. 14 - Oscillogram of Drain-Source Voltage and DrainCurrent for Power MOS Transistor (BUK456-800A) at

Full Load, 110V rms

Fig. 15 - Oscillogram of Gate Current and Gate SourceVoltage for Power MOS Transistor (BU456-800A) at Full

Load, 110V rms

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4.3.2 A Synchronous 200W SMPS for 16 and 32 kHz TV

Description of 200W Switched Mode Power supplyincorporating the AT3020/01A transformer, the TDA8380control IC, one opto-coupler for feedback, synchronisationand remote on/off. The SMPS is intended for TV and canbe synchronised to 32 kHz by flyback pulses of either 32or 16 kHz. A 5V standby supply is also provided.

1. IntroductionIn this report a description is given of a 200W SMPS circuitand evaluation board, incorporating the TDA8380 controlIC, the new SMPS transformer AT3020/01A and theBUW13 power switching transistor. The SMPS is a flybackconverter that has been designed to handle a maximumaverage output power of 200W and a peak power of 250W.The free running frequency of the SMPS is 34 kHz, whileit can also be synchronised down to 32 kHz by either 16 or32 kHz line flyback pulses. For testing purposes nopre-loading is required. The circuit operates at a mainsinput voltage of 185-265VRMS, 50-60Hz. The outputvoltages are 150V, 32V and 16V. The 150V output is shortcircuit proof, while the 32V and 16V can be madeshort-circuit proof.

A new wire wound SMPS transformer has been designed.This transformer, the AT3020/01A with an EE46/46/30 core(grade 3C85), has a new winding technique which makesthe RFI screens superfluous. Thanks to its low leakageinductance, the efficiency of the system is high (88%).

The control IC TDA8380 receives its start-up supply fromthe rectified mains voltage. The takeover supply is derivedfrom a flyback and forward auxiliary winding on thetransformer. This IC offers many attractive operatingfeatures: it directly drives the powerswitching transistor andincorporates several overload protections.

Due to its high current hFE, the BUW13 was chosen as thepower switching transistor. For an output power of up to150W, the BUT12 can be used. A CNG82 opto-coupler isused for feedback. If synchronisation is not required, thecheaper CNX82A can be used.

For the supply of some digital IC’s in the standby mode, asmall self-oscillating supply is used: the so called µSOPS(5V, 300mA). In the standby mode the output voltages willbe fully suppressed.

A printed circuit board (no 3634) is available incorporatingthe 200W SMPS and µSOPS but without mains filter.

2. Circuit description

2.1 Block Diagram

Fig.1 shows the block diagram of the 200W mains isolatedflyback converter.

Fig.1. Block Diagram

MainsInputCircuit

u-SOPS

SMPSTransformer

OptoCoupler

ControlCircuit

PowerSwitchingTransistor

SecondaryRectifiers

ErrorAmplifier

5V SB

150V32V16V

SYNC IN

STAND BY

220V

389


Fig.2. Basic Circuit Diagram

The 200W SMPS evaluation board does not contain an RFIfilter, fuses or a degaussing circuit. These componentsshould be located on the inlet of the mains cord into the TVset. The mains input voltage is rectified by bridge rectifyingdiodes and the dc supply to the SMPS transformer(AT3020/01A) is smoothed by a 220µF buffer capacitor.The control IC TDA8380 derives its start-up supply fromthis dc voltage and as soon as the IC supply voltageexceeds a certain limit, the IC is initialised. Hereafter, theduty factor of the SMPS power switching transistor(BUW13) increases slowly from zero upwards and its rateof increase is controlled until the SMPS output voltagereaches its nominal level. The take over supply is derivedfroma flyback and forward rectifier connected toan auxiliarywinding of the SMPS transformer. The SMPS is a flybackconverter that operates in the discontinuous mode. At thesecondary side the flyback voltage is rectified. One of theoutput voltages is fed back via an attenuator circuit to theerror amplifier. The error signal is sent back via theopto-coupler circuit to the duty cycle control input of the ICTDA8380.

For standby purposes the µSOPS delivers a 5V supply. Inthe standby mode the output voltages will be fullysuppressed. The SMPSrunsat a fixed frequency of 34 kHz,however, it can also be synchronised down to 32 kHz byeither 16 or 32 kHz line flyback pulses.

2.2 Basic OperationFig.2 shows the basic circuit of the mains isolated flybackconverter.

The control IC TDA8380 directly drives the power outputtransistor. When the transistor conducts,a linear increasingcurrent flows through the primary winding of thetransformer. As a consequence energy is stored in the

transformer. After switching off the transistor, the storedenergy is transferred into the load via diode D. Theattenuated output voltage Vo is compared with thereference voltage, REF, in the error amplifier. The errorsignal is fed back via the opto-coupler to the control IC. Bycontrolling the duty cycle of the drive pulses the outputvoltage Vo is kept constant.

The flyback converter under discussion has been designedfor the discontinuous current mode. The principle of thiscircuit has already been described in chapter 2 "SwitchMode Power Supplies". For a nominal output voltage of150V, 185VRMS mains, a maximum load of 250W and a fixedfree running frequency of 34 kHz, the primary inductanceof the transformer can be calculated. The required primaryinductance is Lp = 420µH ± 10%.

An attractive feature of this SMPS is that it can besynchronised down to 32 kHz by either 16 or 32 kHz lineflyback pulses.

3. Circuit diagram

The circuit diagram is given in section 8, Fig.3; detailedinformation about several parts of the supply follows.

3.1 Mains input

The diode bridge D1 to D4 rectifies the mains input voltageand the dc supply to the SMPS is smoothed by C5.Capacitors C1 to C4 suppress the RFI generated by thediodes in the mains bridge rectifier. If C5 is fully discharged,the inrush current has to be limited by R1 to protect thebridge rectifier diodes. During continuous operation of theSMPS this resistor is for efficiency reasons short circuited

390


by a thyristor, THY1. After the soft start of the SMPS,thyristor THY1 is fired continuously by the peak voltageclamp of the SMPS via R3 and C6.

3.2 Start-up supplyThe control IC TDA8380 receives its start-up supply fromthe mains rectified voltage by the low wattage resistor R4.The IC is initialised as soon as the voltage on the supplypin 5 reaches 17V. This takes approximately 1.5s(Oscillogram 6). Shorter times are possible by lowering thevalue of R4. During the time leading up to the initialisationof the IC, the base coupling capacitor C10/C11 ispre-charged. So, the power switching transistor T1 isswitched off correctly during the start up period. With a dutycycle from zero onwards, the SMPS starts up. The takeover supply is derived from a forward and flyback auxiliarywinding on the transformer (AT3020/01A). The forwardrectifying diode D7 ensures that a temporary decrease ofthe supply voltage of the IC is restricted. After a while theflyback rectifying diode D6 directly provides all the currentneededby the IC. During continuous operation of the SMPSthe supply voltage for the IC is about 17V.

3.3 Control ICThe integrated SMPS control circuit TDA8380 offers manyattractive operating features. It controls the SMPS powerthroughput and regulation by pulse-width modulation. Itcan directly drive the power switching transistor and it canoperate at a fixed frequency or a line locked frequency. Adetailed description is given in Reference [1]. The functionof each pin is described below.

Pin 1 Emitter of the forward drive transistor. It directlydrives the power transistor with a source current ofabout 0.7A.

Pin 2 Collector of the forward transistor. This pin isconnected via R14 to the supply. Resistor R14 andR15 mainly determine the source current of thepower switching transistor.

Pin 3 Demagnetisation sensing. For this flybackconverter, operating in discontinuous mode, thevoltage across the SMPS transformer is sensed viaR12 and R13.

Pin 4 Low supply-voltage protection level. This pin isconnected to ground, so the min. Vcc of the IC is setat 8.4V.

Pin 5 IC supply. When the mains input is applied to theSMPS, the IC supply reservoir capacitor C9 ischarged by a current determined by resistor R4.When the voltage at pin 5 reaches 17V, the ICinitialises and diode D6 rectifies the flyback signalfrom winding 10/11 of the SMPS transformer tosupply the IC with 17V.

Pin 6 Master reference current setting. Resistor R11 setsthe master reference current for the TDA8380 to600µA.

Pin 7 Voltage feedback and overvoltage protection. Theflyback signal from winding 10/11 of the SMPStransformer is smoothed by D6/R7/C9, to give a dclevel that varies in proportion to variations in the150V output. This level is reduced by the dividerR9/R10 and fed to pin 7.

Pin 8 In this application the feedback amplifier of theTDA8380 is not used. However, an overvoltage onpin 7 will still activate a protection and slow startsequence.

Pin 9 Output of the error amplifier. Not used.

Pin 10 Oscillator. A 680pF capacitor C15 is connected tothis pin; together with resistor R11 (4k3) theoscillator frequency is set to 34 kHz.

Pin 11 Synchronisation. The trailing edge of the positivesync-pulses, which are superimposed on the linearfeedback signal, synchronise the oscillator.

Pin 12 Slow-start (capacitor C17) and maximum dutycycle (R20).

Pin 13 Over current protection. The over currentprotection safeguards the power switchingtransistor for being overloaded with a too highcollector peak current. For that reason resistorsR22 to R26 in the emitter circuit of the powerswitching transistor sense the collector current.This negative going signal is dc shifted into apositive signal with respect to ground by a dccurrent from pin 13 flowing through R21, while C18removes the spikes.

Pin 14 Ground

Pin 15 Emitter of the reverse drive transistor, connectedto ground.

Pin 16 Collector of the reverse drive transistor. See driveof the BUW13 SMPS power transistor.

3.4 SMPS TransformerAs already mentioned before, the transformer(AT3020/01A) has been designed to handle a maximumoutput power of 200W and a peak power of 250W. Thenominal primary inductance is 420µH. To keep the leakageinductance (~2%) as small as possible, a turns ratio of 1:1was chosen. The magnetic circuit of the transformercomprises two Ferroxcube E46/23/30 cores, grade 3C85.The coil is built-up in layers of copper wire, separated fromeach other by insulation foil. Thanks to a clever windingdesign no screens had to be applied, and as a result, thesize of this transformer could be reduced significantly withrespect to the transformer described in Reference [2].

391


The energy stored in the leakage inductance will bedissipated in the dV/dT limiter (D8/C13/R19) and peakvoltage clamp (D5/C7/R5); the energy stored in theparasitic winding capacitance in the power switchingtransistor T1 and damping networks (R6/C8 and R37/C28).

3.5 Power switching transistorBy fixing the primary inductance of the transformer and itsoperating frequency, the collector peak current of the powerswitching transistor is fixed. At a peak output power of250W the Ic peak is approximately 6.5A. On the other hand,the maximum base drive is determined by the control ICTDA8380: Isource max = 0.75A. The BUW13 has a sufficienthigh currentgain and, moreover, the Iboff could be kept withinthe limit of the control IC: Isink max = 2.5A. For slightly lowermaximum power (150W) the BUT12 can be used as thepower switching transistor. Note that, in that case, currentsensing resistor R21 has to be reduced.

The correct forward drive of the transistor is provided bythe supply voltage of the IC and R14/R15, resulting in anIbon of 0.7A. To obtain a correct negative base drive, thebias voltage across C10/C11 is kept constant by threeBAW62 diodes (D9 to D11). During turn off, inductor L1(1.7µH) in combination with the bias voltage, determinesthe negative base current (-dI/dt) of the power switchingtransistor. R17 and C12 damp the ringing of thebase-emitter and prevents parasitic switch on of T1 duringthe flyback.

3.6 Secondary rectifiersThe three secondary flyback rectifiers deliver the 150V (linedeflectionsupply), 32V (audio supply)and16V (small signalsupply). A 12V stabiliser is not provided on the PC board.The load determines the dissipation in the rectifying diodesand hence the size of the heatsink (D15) and copper area.The number of electrolytic capacitors is determined by theload (ripple current) and the ESR of the capacitors.

To prevent interference between the SMPS switchingfrequency and the line frequency an L-C filter has beenadded. The inductor is L2 while the capacitor is located onthe line deflection board. If the SMPS is running in thesynchronous mode, the filter action is not required and L2can be replaced by a 1 Ω resistor. The feedback voltagefor the control circuit is taken in front of this L-C filter.

To prevent cross-talk, the audio supply is brought outfloating. The negative of the 32V supply is connected toground via R38 to prevent static charge of this transformerwinding if kept unused. If there is an overload on the 32Vor 16V supply, the currents in the secondary transformerwindings can be excessive before the over-currentprotection of the IC is activated. The use of a fuse or fusibleresistor (1Ω / 4W) at position J3 and a fusible resistor(1Ω / 1W) at J4 will make the SMPS short circuit proof alsoon these two outputs.

3.7 Error amplifierThe error-amplifier consists of a single transistor T5. Thebase of this transistor receives the filtered and dividedoutput signal while the emitter is connected to the referencevoltage (ZD3). The output current of this error-amplifier isfed to the opto-coupler.As the current through T5and henceits gain will settle at a value inversely proportional to thecurrent gain of the opto-coupler, the SMPS loop gain willbe independent of tolerance or ageing of the opto-coupler.Thecurrent through ZD3 is fixed by R42 at 2mA. By keepingit constant, the temperature dependence of the Vbe of T5is compensated by that of ZD3 [3].

3.8 Opto-couplerFor feedback and mains isolation an opto-coupler (CNG82)is used. As already mentioned before, the opto-coupler isdriven in such a way, that the large variation of IC/IF of theopto-coupler is filtered by means of R27 and C19. Theemitter of the transistor drives the output-amplifier T2. Thistransistor is used for keeping the operating voltage of thephototransistor constant; this keeps the bandwidth high.

Except for feedback, the opto-coupler is also used forsynchronisation. For this purpose, the sync pulses aresuperimposed on the linear feedback signal. The slowerCNX82A can also be used at the expense of thewave-shape and delay of the sync pulse. Then at 16 kHzthe maximum power will be restricted somewhat due tounequal duty factors of the odd and even SMPS pulses.

For standby operation, the opto-coupler diode is driven inforward (IF = 2mA) either by switch-on transistor T6 or byexternally driving resistor R43. In this mode the outputvoltages will be switched off.

3.9 Standby supplyFor the supply of some digital IC’s in the standby mode, asmall self-oscillating, current-mode controlled flybackconverter delivers 5V/300mA. It uses the same mains inputfilter, bridge rectifier and RFI/safety capacitor C22 as themain SMPS. For mains isolation and power conversion asmall transformer (AT3006/300) is used. The powerswitching transistor BUX87 requires a small heatsink [4].

4. SynchronisationThe SMPS can be synchronised down to 32 kHz by either16 or 32 kHz (±4%) negative-going pulses on pin 5 of J17,with a pulse width of 18% of the line time (Eg. line flybackpulses). The amplitude of the sync-pulse measured at thesync-input, should lie between 2 and 6V. The sync-pulsesare superimposed on the linear feed back signal. This canonly be done, if they do not affect the voltage stabilisation.To obtain short rise and fall times of the sync-pulse at thesync-input of the TDA8380, the CNG82(A) should be used.Capacitor C16 ac couples the sync-pulses to pin 11 of the

392


TDA8380. Theoscillator sawtooth is triggeredby the trailingedge of the positive sync-pulse at pin 11 and all subsequentsync-pulses are ignored until the oscillator sawtooth iscompleted. The oscillator is then inhibited until the end ofthe next positive sync-pulse. The free-running oscillatorfrequency is determined by R11 (4k3) and C15 (680pF).Both components should be 1% tolerance types.

If synchronisation of the SMPS is not needed, the followingcomponents can be deleted: C19, C35; R29, R27, R49,R50, R51; D18, R19; T2. The opto-coupler CNG82 can bereplaced by the CNX82A. Jumpers J1 and J2 should be inplace.

5. Mains interferenceRFI measurementsare made of the SMPS (200W) togetherwith the µSOPS and a mains input filter, consisting of theAT4043/93 and two X-capacitors (220nF). The results muststay below the limits of EN55013, which are drawn in thegraph shown later. The measurements just meet the limits.If the SMPS is used with more than 165W input power,measures must be included to meet the IEC552-2 standardon mains pollution by higher harmonics.

6. Performance

INPUT 185-265V RMS 50/60Hz

OUTPUTS 150V 1.0A LINE SCANSTABILISED

32V 1.5A AUDIOUNSTABILISED

16V 0.2A SMALL SIGNALUNSTABILISED

RIPPLE 150V ≤10mV SWITCHINGFREQUENCY

peak to peak ≤20mV 100Hz

32V ≤150mV SWITCHINGFREQUENCY

≤10mV 100Hz

16V ≤50mV SWITCHINGFREQUENCY

≤10mV 100Hz

EFFICIENCY 88% 200W LOAD

SWITCHING 34kHzFREQ.

7. Oscillograms

The oscillograms have been made at the followingconditions, unless otherwise indicated.

Vinput = 220V RMS Load = 200W not synchronised.

Oscillogram 1. Collector Current and Collector Voltage ofthe BUW13.

Oscillogram 2. Collector Current and Collector Voltage ofthe BUW13.

Oscillogram 3. Base Emitter Voltage and Base Current ofthe BUW13.

393


Oscillogram 4. Voltage and Current at pin 13 of thetransformer.

Oscillogram 5. Voltage and Current at pin 19 of thetransformer.

Oscillogram 6. SMPS switch on behaviour.

Oscillogram 7. BUW13 Collector Current and Voltage atshort circuit 150V output.

Oscillogram 8. BUW13 Collector Current and 15.625kHzsync pulses.

ReferencesInformation for this section was extracted from"Synchronous 200W Switched Mode Power Supply for 16and 32 kHz TV"; ETV89009 by H.Simons.

[1] Integrated SMPS control circuit TDA8380.Philips Semiconductors Publication Number 9398 35840011 Date: 12/88.

[2] ETV8711 A 200W switched mode power supplyfor 32kHz TV. Author: H.Misdom.Date: 01/09/87.

[3] ETV89003 Novel optocoupler circuit for theTDA8380. Author: H.Verhees.Date: 2/89.

[4] ETV8834 A dual output miniature stand by powersupply. Author: H.Buthker.

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8. Circuit diagram.

Fig.3

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396


Monitor Deflection Circuit Example

397


4.4.1 A Versatile 30 - 64 kHz Autosync Monitor

This section describes the supply and deflection circuits fordriving the 15" FS M36EDR colour monitor tube. Keyfeatures of this monitor design are auto synchronisation,full mains range, dc control, good picture stability and highcontrast. The circuit uses a low number of componentswithout making compromises to the performance.

1. IntroductionThe increasing number ofsuppliers ofvideo interface cards,creates a variety of video standards. The most widely usedstandard at this moment is the VGA mode. Already thisstandard gives a choice of three different modes, givingresolutions between 720x350 to 640x480 pixels. Thehorizontal frequency is fixed at 31.5 kHz, while the verticalfrequency varies between 60 and 70 Hz.

New standards, with resolutions up to 800x600 and even1024x768 pixels, are becoming popular very rapidly,although the old standards are still present on these newinterface boards.

This increase in resolution calls for larger screens,compared to the nowadays widely spread standard 14"tube, due to the minimum discernible detail at a convenientviewing distance. Furthermore, the electronic drive circuitsof the picture tube have to be able to adapt to the variousstandards.

As a successor of the standard 14" high resolution colourpicture tube, the 15" FlatSquareM36EDR series tubes offera noticeable increase in useful screen area(14": 190x262 mm2; 15": 210x280 mm2), while the totalcabinet size hardly increases, and offering a resolution upto 1024x768 pixels (pitch is .28mm.). The M36EDR seriesoffers a wide range of deflection impedances and anexcellent performance with respect to convergence andgeometry distortion, resulting in simple deflectionelectronics. For the end user, the tubeoffers a verypleasantflat and square screen, with hardly any disturbing visibleeffects.

To display the new, as well as the old video standards, onthis new tube, the electronic circuits are becoming morecomplex. For example, to display 768 lines, withoutdisturbing screen flicker, the line frequency must beincreased to 57 kHz. The horizontal deflection circuitdescribed in this report is able to synchronise over acontinuous frequency range from 30 to 64 kHz, while thevertical frequency may vary between 50 and 110 Hz. Thecircuit is built around the advanced monitor deflectioncontroller TDA4851, significantly reducing the componentcount of the total circuit, while providing a high standard ofperformance. The vertical deflection output stage is the

TDA4861. This power operational amplifier offers thedesigner great flexibility with respect to input signals andsupply voltages.

The increase in resolution also demands that the videochannels are able to drive the picture tube with ever higherfrequencies, due to the increasing amount of pixels on onevideo line in a decreasing period of time (increase of linefrequency). For example, to display 1024 pixels on one lineat 57 kHz line rate, the video amplifiers must be capable ofhandling dot frequencies up to 65 MHz.

This report covers the electronic circuits for driving thehorizontal and vertical deflection coils of a 15"FS tube, forgenerating all the grid voltages necessary for this tube (thecathodes are driven by the video amplifiers), and a fullmains range supply, generating the supply voltages.

2. Supply

This autosync monitor is equipped with a full mains rangeswitchedmode power supply (90 - 265Vac) with amaximumoutput power of about 90W 1. This mains isolated powersupply is running asynchronous, because of the largefrequency range of the horizontal deflection stage.

To handle the required output power a new wire woundSMPS transformer, the CE422v, was designed. Thecontroller IC is the TDA8380 2 directly driving the powerswitch BUT11A. Feedback is obtained through anopto-coupler circuit that senses the +155V output, the linesupply voltage. The output voltages of the SMPS are:

+ 155 V @ 350 mA Horizontal deflection and EHTgeneration

+ 10.5 V @ 450 mA Vertical deflection

- 10.5 V @ 650 mA Vertical deflection and CRT heater

+ 30 V @ 30 mA Vertical deflection (flyback)

+ 12 V @ 400 mA Video, IC and small signal supply

The +12V supply is derived from the +17V supply rail bymeans of a separate voltage stabiliser.

An extra winding on the transformer, not used in this circuit,delivers a -17V supply. The rectifier and smoothingcapacitor are not implemented in this design.

As this switched mode power supply is runningasynchronous, additional measures are taken to preventinterference. All output lines are equipped with LC or RCfilters.

399


The +155V rail is protected against short circuit by meansof the TDA8380, while the +12V output is protected by theIC voltage stabiliser. To make the low voltage outputsprotected against short circuit, fuses or non flammableresistors are used in the output lines.

2.1 Degaussing

The demo monitor is equipped with a conventionalautomatic degaussing circuit, making use of one duo PTC.For full mains range application the inrush and steady statecurrent are just on the limit. If support is needed pleasecontact the local or regional sales/application office.

2.2 Provisions for full-mains range

Tomake the SMPS fullmains range the followingprovisionsare made:

Theslowstart capacitor C15 is reduced to 0.47µF toshortenthe start up time.

The overcurrent protection is extended in order to ensureproper working of the IC with respect to the first trip level.

The IC supply capacitor C13 is increased to 220µF toprevent excessive voltage drop during start up.

3. DeflectionThe deflection circuit is greatly simplified by making use ofthe advanced monitor deflection controller TDA4851. Thisis an upgraded version of the TDA4850 mainly with respectto horizontal line jitter. To accommodate a horizontalfrequency range from 30 to 64 kHz, the input frequency iscontinuously monitored by an F/V converter, in order toadapt the central frequency of the TDA4851. The minimumand maximum frequencies of this circuit are limited by anupper and lower clamp.

Fig. 1 The TDA4851 controller IC.

+12V

+12V

P60

R84*)

P55

R96

R95

R94

R92

R88

R89

P53

R87

R86

R85

R83

C69

C68C67

C66

C65

C63

C62

T51

R82R81

R80

R79

R78

IC52

CURRENTOSCILLATORHORIZONTAL

FLYBACKHORIZONTAL

DRIVEHORIZONTAL

OUTPUTMODE

OUTVERTICALEW

OUTEHT

COMP.

V-SYNC

H-SYNC

CLAMP PULSE

HEIGHT

HSHIFT

EW adj.

1M*)

33u

220n10n

1n58K2

SMDSMDSMD

SMDSMD

SMD220n

120K

100n

BC 548

220n

1K8

1K8

180K

750K

3K9

10K

10E

10K

10K

16VTDA4851

120K

120K

68K

68K

82K

82K

22K

400


The TDA4851 drives a line driver stage and a, so-called,T-on driver stage. The line driver is of the well knowntransformer coupled non-simultaneous type, giving thedesigner a free choice where to put the line output transistorwith respect to the supply voltage. The T-on driver stagedrives a switching transistor, synchronised with thehorizontal frequency to control the horizontal scan voltage.The conducting period of this switch is kept constant overthe whole frequency range, resulting in a constant picturewidth, independent of the scan frequency.

The TDA4851 also drives the vertical output stageTDA4861. DC coupling of the deflection coil to thisamplifier, together with the high linearity of the drive signalsfrom the TDA4851, offer an excellent linear verticaldeflection, without bouncing effects after a mode change.

East-west correction of the horizontal deflection and picturewidth control is performed by the width control stage.

Horizontal S-correction is performed by one fixed capacitor,plus a selection of three additional capacitors. Thisminimum set-up is chosen to keep the circuit simple, whilegiving the minimum amount of distortion at four selectedfrequencies. The S-correction capacitor selection circuitdrives floating FET switches.

Vertical S-correction is achieved by modulation of thevertical amplitude control current with a parabola voltage.

The line output transformer AT2090/01 generates theanode, focus and grid 2 voltages for the picture tube. Thebuilt-in bleeder with smoothing capacitor provides anexcellent source for retrieving EHT information. Thisinformation is used to stabilise the picture width and height.

The primary winding of the line output transformer is alsoused as the choke of the switch mode scan control stage.This architecture has the advantage of using only four wirewound components: LOT, bridge coil, base drivetransformer and horizontal linearity coil.

Theauxiliary windings on the line output transformerdeliversupply voltages for the grid-1 circuit and video outputstagesand provide information for the protection circuit.

The various circuits will now be discussed in detail in thenext sections.

3.1 Advanced monitor deflection controllerTDA4851The heart of the deflection circuit is the advanced monitordeflection controller, the TDA4851, see Fig. 1. Thisdeflection controller is driven by separate horizontal andvertical synchronisationpulses. Although the TDA4851 canprocess a sync-on-green signal, this is not implemented inthis monitor. The polarity of these pulses can be chosenfreely, except for VGA modes, their amplitude must be TTLlevel. With these pulses, the horizontal and verticaloscillators are synchronized. The horizontal output drives

the line driver, the vertical drive signals are connected tothe verticaloutputstage IC51. A parabola voltage fordrivingthe east-west correction stage and a clamping signal forthe video stages are also generated by the TDA4851.

3.1.2 Horizontal part

The horizontal oscillator is synchronized with the pulse onpin 9: TTL amplitude, positive or negative polarity andaccepting composite sync (sync-on-green is notimplemented in this design). The catching range is limitedto ±6.5%. The oscillator frequency is set by C67 and thedc current in pin 18, which in this application is set by a dccurrent source, driven by the frequency to voltageconverter. Compared to the TDA4850, the current in pin18 of the TDA4851 is approximately 10 times higher toachieve a lower phase jitter.

The low-pass filter in the first phase locked loop isconnected to pin 17. In a single frequency application, thevalues of the filter components are fixed. For a frequencyrange from 30 to 64 kHz, the values of the filter componentsare set by the lowest frequency, resulting in a less thanoptimum response for the higher frequencies. For reasonsof simplicity, the filter is fixed here, but should be adaptedto the actual frequency for best response.

Fig. 2 Horizontal flyback pulse coupling to theTDA4851.

The synchronised horizontal oscillator drives the secondphase locked loop, in which the horizontal flyback pulse isused as feedback to position the horizontal drive pulse inrelation to the horizontal sync pulse. Low-pass filtering isperformed by capacitor C68 connected to pin 20. Phaseshift can be accomplished with a dc current in pin 20.

R105

D57

T54

C74C73

C72 R104

R103

R102

R101

C61 D54

D53

R77

C60

CLAMPED FLYBACK PULSE OUT

NEGATIVE FLYBACK PULSE IN (1100Vpp)

+12V680E33u

100n

10E

16V

PH2369

18P

100K

18P

100K

100K

47P 5K6C3V3

BZX79

BAW62

BAW62

401


Nominal phase shift is set with resistor R96. Useradjustable phase control is available through P55,controlling the dc current in pin 20.

The horizontal flyback pulse is connected to pin 2. TheTDA4851 expects a positive flyback pulse, see Fig. 2. Thenegative flyback pulse from the line output stage is invertedand ac coupled to pin 2 of the TDA4851.

3.1.3 Vertical partThe vertical oscillator can be synchronized with a pulse onpin 10 (or combined sync to pin 9) over a range of 50 to110 Hz without adjustment and with constant amplitudeoutput signal. Frequency determining elements R89/C63and the amplitude stabilisation loop capacitor C62, shouldnot be changed.

The output signals of the vertical part are two balancedcurrents, available on pins 5 and 6. Both currents consistof an equal dc part and an adjustable sawtooth part. Theadjustment is achieved by means of controlling the dccurrent in pin 13. There are five signals which determinethe current in pin 13:

1. R87 sets the nominal dc current;

2. P53 allows user control of the picture height via R83;

3. By means of R82, the amplitude control current ismodulatedwith a parabola current. In thisway, verticalS-correction is achieved. The disadvantage of thismethod, is that the amount of S-correction isdependent on the setting of the east-west controlpotmeter P60.

4. R84 compensates for a change of the east-westcorrection voltage (explanation: when the east-westvoltage on pin 11 is changed by means of the ’EWpar.’ potmeter P60, the mean dc voltage on pin 11changes, influencing the vertical amplitude via R82).

The influence of the east-west setting on the verticalamplitude is small, therefore, R84 is marked optional,it’s not absolutely necessary.

5. Changes in the EHT voltage compensate the verticalamplitude via R80.

3.1.4 East-west parabola

A parabola voltage is available on pin 11, for driving thepincushion correction stage. The bottom of this parabolavoltage, equal to the middle of the screen, is set internallyon 1.2V, independent of the amplitude setting. In this way,adjusting the parabola amplitude changes the horizontalwidth in the corners only, while the amplitude in the middleof the screen remains constant.

Amplitude adjustment of the parabola voltage is achievedby a dc current in pin 14. No user control is available,adjustment is only possible with P60 on the maindeflection/supply printed circuit board. The amplitude ofthe parabola voltage is corrected for changes in the verticalamplitude setting by means of R85. The amplitude of theparabola voltage is independent of the vertical scanfrequency.

The parabola voltage from pin 11 is connected to the baseof T51. The collector current is then transferred to thepicture width driver. In that stage the amplitude is multipliedwith the horizontal frequency, to achieve a correctionindependent of the horizontal frequency.

3.5 Miscellaneous I

A clamping signal for the video pre-amplifier, ic TDA4881,is generated in the TDA4851. This clamping signal isavailable on pin 8, and is only present when horizontal syncpulses are present on pin 9.

Fig. 3 Frequency to Voltage Converter and Current Source.

P59

T52

P54

IC53A

R93

R91

R90

C64

T50

C53

C52C51

C50

IC50

R66

R65

R64

R63

R62

R61

C54

HORIZONTALOSCILLATORCURRENT

CLAMPPULSE

F/V adj.

PHI-1 adj.

1413

12

VFRQ

LM3241/4

82K

10E

220E

820E

470n

33u

Ser. 82n

100n683

180K

SMD

PH2369

33K10K

24K

220P 33K

12p

BC549C

8K2

1K8

NE555

16V

402


The mode input/output pin 7 is connected to a switchingtransistor T76. This transistor is driven by comparatorIC56B. This comparator detects whether or not theincoming horizontal frequency is below 33 kHz. In thiscase, the TDA4851 assumes a VGA signal is present,resulting in an automatic adjustment of the verticalamplitude, depending on the sync. polarity. Above 33 kHz,the internal mode detector of the TDA4851 is switched offwith T76, to prevent automatic vertical amplitudeadjustment.

3.2 Additions to the TDA4851 forauto-sync operationSince the catching range of the horizontal section of theTDA4851 is only ±6.5%, the frequency range from 30 to64 kHz cannot be covered without extra circuits. Toaccommodate the specified range, the horizontal oscillatorcurrent (pin 18) is constantly adapted to the incominghorizontal sync pulse frequency. This is achievedby meansof a frequency to voltage converter driving a current source.To protect the power output stages from too low and toohigh frequencies, voltage clamps on the drive voltage of thecurrent source keep the frequency of the horizontaloscillator of the TDA4851 within the specified limits of 30to 64 kHz.

3.2.1 F/V ConverterThe frequency to voltage converter is built around one-shotIC50, see Fig. 3. R65/66 attenuate the signal from pin 8 ofthe TDA4851 in such a way that only the horizontal clamppulses (5.5Vpeak) and the vertical blanking pulses(1.9Vpeak) do not drive T50. This has the advantage thatthe incoming horizontal sync pulse is not disturbed in anyway, and the sync pulse polarity and amplitude variationsof the incoming sync pulse are of no influence to the circuit.

The output pulses of IC50 pin 3 are attenuated and filteredwith R90/91 and C64. The dc voltage VFRQ is used todrive the current source and the S- correction capacitorselection circuit. The width of the output pulse of theone-shotcan be adjusted with P59 (F/V adj.). This potmetershould be adjusted in such a way, that the switching of theS-correction capacitors is performed at the desiredfrequencies.

The conversion factor S of this F/V converter is:

S = tc + 1.1 x (R62+P59) x C51 x R91 / (R90+R91) x Uo

where:

tc width of the TDA4851 clamp pulse: 1µs

1.1 x (R62 + P59) x C51 width of the output pulse of theone-shot IC50: 5.81 - 8.23µs

R91 / (R90 + R91) attenuation of the output pulse: 0.313

Uo amplitude of the output pulse: 10.8V

The duration of the output pulse of the one-shot is affectedby the trigger pulse. During time tc the output voltage isalready high, while the charging of C51 is halted. Thisresults in:

S = 23.0 to 31.2 mV / kHz

The voltage VFRQ can be found with the following formula:

VFRQ = FH x S

where FH is the horizontal scan frequency. With S =27.1mV/kHz, this results in:

VFRQ(31.47 kHz) = 31470 x 27.1 x 10-3

VFRQ(31.47 kHz) = 853 mV

and:

VFRQ(63.69 kHz) = 63690 x 27.1 x 10-3

VFRQ(63.69 kHz) = 1726 mV

Because the resistor divider for the s-correction capacitorsis fixed, the conversion factor S is adjusted to the voltageVREF, feeding the divider.

3.2.2 Current sourceThe current source for driving pin 18 of the TDA4851 isbuild around op. amp. IC53A and T52.

The collector current of T52 can be adjusted with P54 toadapt to the actual conversion factor S and for the toleranceon the oscillator capacitor C67 on pin 19 of IC52. This mustbe done after the conversion factor S is adjusted with P59to the correct s-correction switching frequency.

3.2.3 Voltage clamps

Fig. 4 Voltage clamps.

D83

IC53C

R179

R178

R164

IC53D

C106

R154

D82

VREF

VFRQ5

67

13

2

LM3241/4

LM3241/4

910E

91E

220E

1K1

100n

BAW62

BAW62

403


To prevent the horizontal power output stage from runningat either too low, or too high, a frequency, the drive voltagefor the current source is limited. IC53C limits the lowervoltage and IC53D the upper voltage, see Fig.4. Thefrequency range of the TDA4851 is now limited to 30 kHzminimum and 66 kHz maximum.

Reference for the comparators IC53C/D is a voltage dividernetwork, driven by IC53B. The input voltage for IC53B isthe temperature compensated reference voltage at pin 15of the TDA4851.

3.3 Horizontal scan control driver

In order to keep the picture width constant, independent ofthe horizontal scan frequency, the scan voltage iscontinuously adapted. The relation:

Vscan = L x I x fH

is valid. From this equation, it can be seen that withincreasing scan frequency, the supply voltage must alsoincrease proportionally.

Realisation of this demand is in fact quite simple. Thehorizontal drive pulse from the TDA4851 triggers one-shotIC54. The output pulse width of this one-shot is constant,independent of the trigger frequency. Therefore, theduty-cycle increases with increasing frequency. Via bufferstage T62/63, FET switch T64 is controlled. In this way,the scan voltage for the horizontal deflection output stageis controlled, according to the previously stated relation.

Fig. 5 Horizontal Scan Control Driver.

IC54 is a retriggerable one-shot, see Fig. 5, which isimportant at higher scan frequencies (above 66 kHz),where the duty-cycle becomes 1.0. In case of anon-retriggerable one- shot, the duty-cycle would suddenlydrop to 0.5. This would not only result in half the deflectionamplitude, but also in a drop of the EHT.

One other important item is the phase relation between thedrive pulses of T53 and T64. When the horizontal outputstage is in the flyback part, T64 must always conduct (inorder to keep the EHT constant). This is realised bychoosing the appropriate trigger edge (positive edge of thehorizontal drive pulse) and by a lower limit of the adjustmentrange of the pulse width, to ensure T64 is conducting allthrough the flyback period of the horizontal deflection stage.

3.4 S-correction capacitor selectionThe necessary value of the S-correction capacitor varieswith the horizontal frequency, given a certain deflection coilimpedance and screen radius. The correct capacitor valueis chosen from eight different values through a combinationof one fixed and a choice of three capacitors.

The voltage VFRQ, representing the horizontal scanfrequency, is connected to the inverting inputs of sevencomparators IC56/57. Each non-inverting input of thesecomparators is connected to a different output of a resistorladder R154/164-170/178/179. This resistor ladder is fedby a voltage VREF.

At pin 15 of IC52 a temperature compensated voltage of,typically, 3.0V is available for setting the vertical oscillatorcurrent (R89). To avoid extra loading of this pin, a voltagefollower with high input impedance IC53b is used. Theoutput of op. amp. IC53b is a stable dc voltage with verylow output impedance: VREF.

Resistors R171 to R177 provide each comparator withsome hysteresis to prevent parasitic oscillations on theswitch-over points.

Thecomparatoroutputs are connected to an8-3 multiplexerIC58. The outputs of IC58 drive transistors T73/74/75.These transistors can withstand the possible high voltages(max. 150V) that drive the S-correction capacitor switches.

D79/80/81 are added to prevent T73/74/75 from breakdown during line flyback. In this way, the selection of theresistors sets the frequencies when the circuit switches toanother S-correction capacitor value.

3.5 Picture width driverSince pin-cushion distortion is a fixed percentage of thescan voltage, the peak to peak parabola voltage, correctingthe pin-cushion distortion, must be adapted to the actualscan frequency. This multiplication is achieved in the samemanner as the scan voltage for horizontal deflection isadapted.

One-shot IC55, see Fig. 7, is triggered with pulses havingthe same frequency as the horizontal scan frequency. Butnow, also the parabola voltage modulates the width of theoutput pulse. This output pulse is integrated throughR138/C98; the voltage drives a common base stage T69.

+12V

C87

R123

T63

T62

R122

R121

C86

C85

P56

R120IC54

PULSEH-DRIVE

T64TO GATE

EHT adj.

+10.5V

C15

47K

1K

100n

220p

Ser683

4538HEF

33u22k

10E

BC558

BC548

22E

16V

404


Fig. 6 S-Correction Capacitor Selection Circuit.

+12V

+12V

R179

R178

IC58

IC56D

IC56A

IC57B

IC56C

IC57D

IC57C

IC57A

R177

R170

R176

R175

R174

R169

R168

R167

R166

R173

R172

R171

R165

R164

R157 up to R163

C108

C107

R156

R155

C106

R154

R153R152R151

T75T74T73

D79 D80 D81

TO S-CORR. CAPACITOR SWITCHES

IC57 PIN12

IC56 PIN12

IC57 PIN3

IC56 PIN3

IC53 PIN11

IC53 PIN4

VREF

VFRQ

1311

10

149

8

17

6

25

4

1311

10

149

8

17

6

910E

91E

39E

470K

470K

470K39E

240E

150E470K

470K

1/4

1/4

1/4

1/4

1/4

1/4

1/4

LM339

LM339

LM339

LM339

LM339

LM339

LM339

300E

200E

220E

33u

33u

470K

1K1

100n

22K

HEF4532

22K 22K

BAW62BAW62BAW62

MPSA42MPSA42MPSA42

470K

7X 10K

16V

10E

10E

16V

405


In this way, the modulation is converted to the collectorcurrent of T69 (IEW), simplifying the interface to theeast-west power stage, which is connected to the +155Vsupply.

Two other functions are also incorporated in this part of thecircuit:

- User control of the picture width via P58; and

- Compensation for variation of the EHT; achievedthrough R136 - the information is supplied by the EHTcompensation circuit.

Fig. 7 Picture Width Driver.

3.6 Horizontal deflection output stage

To allow a frequency range of 30 to 64 kHz, additionalmeasures have to be taken to keep the deflection currentand the EHT constant. This is realised by continuouslyadapting the scan voltage to the horizontal frequency bymeans of the horizontal scan control. The scan controlswitch T64 is connected to ground, resulting in simple gatedrive. The horizontal deflection output transistor T55 isconnected to the supply rail because the driver transformerL50 already provides isolation. The primary winding of theLine Output Transformer L54 is used as a choke.

This set-up of horizontal deflection has two disadvantages:

1. The pincushion correction stage is either floating orconnected to the same supply rail as the line outputtransistor, T55. In this concept, connection to the supplyrail is chosen, and driving it with a current IEW from thesmall-signal circuit.

2. The S-correction capacitor switches are floating, whichmakes it less simple to drive them.

The biggest advantage of this deflection stage is that aminimum of wire wound components has been used.

3.6.1 Line driver stageThe circuit is shown in Fig. 8. As driver device T53 a smallMOSFET (BSN274) is chosen. Its advantages over abipolar device on this particular application are: less powerdissipation (enabling smaller encapsulation), less drivepower required, better switching behaviour and no storagetime (so no additional stress on the Φ2 loop). To protectthe gate the standard precautions (zener diode and seriesresistor) are taken.

The driver transformer is equipped with a damper networkat the primary side (C71/R98) to damp excessive ringing.On the secondary side a damper (C76/R107) is presentbetween the base and emitter of the deflection transistorT55.

In order to achieve sufficient negative drive voltage duringflyback, resistor R106 and diode D58 are added. Proper-dIb/dT is achieved by the leakage inductance of L50.

When the X-ray protection is activated, the inverting driverstage will be turned on continuously. This will switch offT55, but also cause a low frequency swing in the drivertransformer. To prevent voltage inversion across theprimary winding of driver transformer L50, which would turnon the deflection transistor T55 for a relatively long time,D55 is added. A second measure, that must beimplemented when X-ray protection is installed, isincreasing the power rating of the current source resistorR97 to 16W (!) or using an electronic resistor with a currentfold back characteristic.

Fig. 8 Line Driver Stage.

3.6.2 Horizontal scan control output stageAt double the line frequency, the scan voltage must bedoubled as well to have the same picture width on thescreen. Furthermore, the supply voltage to the line outputtransformer must be proportional to the horizontal linefrequency to have constant EHT over the whole frequencyrange. To achieve this, a synchronous switching seriesregulator is added. This series regulator operates with aconstant T-on time.

+12V

+12V

C94

IC55

T69

R141

R140

C98

P58

C97

C96

C95

R139

R138

R137

R136

R135R134

IC50 PIN 3TRIG. INPUT

EHT COMP.EAST-WEST IEW

+155V

WIDTH

22n

220n

Ser.683220p 33u 82n

NE555

SMD

390K

330E

470E

10K

5K6

16V

10E

MPSA42

56K

1K

10K

21

34

C76

L50D58

D56

D55T55

T53

C75

C71C70

R107

R106

R100

R99

R98

R97

TO DEFLECTION CIRCUIT

LINE DRIVE PULSES FROM TDA4851 PIN 3+12V

+155V

C15

1K5 PR03

1K5

BU2520A2.7E AC04

68nBAS11

250V150u

1K

BSN274

BYD33D

22E

BZX79

250V

2E2

220n

AT4043/87

150p

406


In Fig. 9 the basic circuit diagram and in Fig. 10 the relevantwaveforms are given.

Fig. 9 T-on Switch.

Transistor T64 controls the horizontal supply voltage and,hence, the peak value of the flyback pulse which is directlyrelated to the horizontal amplitude and EHT (flyback timeis fixed, independent of frequency).

Fig. 10 Horizontal Scan Control Waveforms.

The average voltage across a coil must be equal to zero.With T-on = 100% the area under the flyback pulse mustbe equal to the scan amount. At half frequency, for equalEHT with fixed flyback time, half scan amount will besufficient. This is indicated in Fig. 10. During T-off thecurrent will flywheel in D73.

63kHz

31.5kHz

Vlot

Vlot

Tperiod

TonTfb

Ilot

L52 R124

C89

C88

D73

D72

R123

T64

C15

BUK455-200B

120E

BYV99250V22n

2n7

22E

BZX79

12uH

TO LOT+155 V

BUFFERFROM

Fig. 11 Power Output Stage.

C99

R125

L53

C80C79

L51

C78

C77

C76

D61

D60

D59

T57

T56

T55

C75R109

R108

R107

BASE DRIVE

+155 V

+155 V

1200 V

IEW

+HDEFL

-HDEFL

5n6

220n

1K PR02

15n

BU2520A BYW96D

BYW96D

5u6

BC547C250V150u

AT4042/33A

10KBD648

1600V

100V

400V

BYW95C

2KV

1E

25V47u

2E2

220n

AT4043/13

407


3.6.3 Power output stage

The power output stage, see Fig. 11, is a conventional onewith a diode modulator.

Because this stage is connected to the supply rail, theflyback pulse has negative polarity. This makes the use ofT54, see Fig. 2, necessary because the deflectioncontroller IC52 expects a positive flyback pulse.

As lower damper diodes two low voltage diodes BYW96Din series are chosen because they switch faster than onesingle high voltage device.

As deflection transistor, the BU2520A is chosen. Thisdevice performs remarkably well over the frequency rangeof 30 to 64 kHz.

The value of flyback capacitor C78 depends on theimpedance of the line deflection coils and the desiredflyback time. With 180µH deflection coil impedance, C78should be 5n6/2kV, with 220µH impedance, C78 should be4n7/2kV.

3.6.4 East-west power stage

To drive the diode modulator, the drive current "IEW" mustbe converted to a voltage by means of R109. A powerbuffer T56/57, see Fig. 12, drives the diode modulator. Toprevent high ac currents from flowing through T56, anadditional filter R108/C80 is added.

Fig. 12 EW Power Stage.

3.6.5 S-correction capacitor switchesThe curvature of the screen determines the percentageS-correction. This percentage is constant and independentof frequency. Since the scan voltage is adapted accordingto the horizontal frequency, the S-correction voltage alsohas to be adapted, according to the frequency. The valueof the S-correction capacitor is determined with thefollowing equation:

Cs = Tp2 / (8 x σ x Lh)

where:Tp = the visible line period time;σ = the percentage of S-correction;Lh = the impedance of the deflection coil.

With a constant flyback time of 3µs, this gives the resultsas shown in Fig. 14. These values are realised in the circuitshown in Fig. 13.

C80C79

L51

T57

T56R109

R108

+155 V

TO DEFLECTION CIRCUIT

IEW

5u6

BC547C

10KBD648100V

1E

25V47u

AT4043/13

Fig. 13 S-correction Capacitor Switches.

C100

C99

C105

C104

C103

C102

C101 D78

T72R150

R149

R148

T71

D77

R147

R146

R145D76

T70R144

R143

R142

C80C79

L51

T57

T56R109

R108

TO DEFLECTION COIL

+155 V

DRIVERSTO SWITCH

IEW

C15C15C15

BUK455-

150K

47K

100K120n

BUK455-

150K

47K

100K330n

BUK455-

150K

47K

100K820n

220n

5u6

BC547C

630V250V

10KBD648100V

250V

400V

22n 22n 22n

200B200B 200B

1E

25V47u

BZX79BZX79BZX79

AT4043/13

408


Fig. 14 S-correction Capacitor in Relation to theHorizontal Frequency.

Each switch contains a MOSFET with built-in anti paralleldiode, see Fig. 14. When, for instance, T75, see Fig. 5, isnot conducting, C101 will be charged via R143/144 and T70will conduct. D76 prevents the gate from too high voltages.When T75 conducts, the voltage at C101 will be zero andT70will block. Such a switch can also be build with a bipolardevice, however that would require a higher drive current,resulting in high losses because of the ac and dc voltagedifference between drive and switch.

The switch itself functions as follows. During the first partof scan the current is conducted by the MOSFET; theS-correction capacitor will be charged. During the secondpart of scan the current will be conducted by the anti paralleldiode. In case the MOSFET is not conducting, theS-correction capacitor will not be charged during first partof scan, except from a very small current through theresistors parallel to the MOSFET switches. So, during thesecond part of the scan the VDS will remain positive and theanti-parallel diode will not conduct.

3.6.6 EHT, Focus and Vg2The EHT, focus and Vg2 are generated by the Line OutputTransformer (LOT) AT2090/01. This transformer can beused up to 85 kHz and has a built-in bleeder (with focusand Vg2 potentiometers) and an EHT smoothing capacitorof 3nF. Not only the flyback but also the scan voltages arefrequency independent. So, auxiliary voltages can beextracted from the LOT in the ordinary way. There is oneexception: often the heater voltage for the CRT is takenfrom an unrectified winding of the line output transformer.Since due to T-on the RMS value is not frequencyindependent, the CRT heater must be supplied from arectified winding. For practical reasons in this design anSMPS voltage was more suited (-10.5V).

Fig. 15 EHT vs. Frequency.

3.7 Vertical deflectionThe vertical deflection output stage used in this design isthe TDA4861 (IC51), see Fig.16. This vertical output stagecan be considered as a power operational amplifier with anextra flyback generator and guard circuit.

The inputs are driven by the balanced outputs of theTDA4851. The TDA4851 supplies complementary drivecurrents, which can be directly connected to the input pinsof the output stage.

To determine the values of resistors R71/75, conventionaloperational amplifier theory is applicable. This theory saysthat, in practical cases, the differential input voltage of anoperational amplifier always equals zero:

V2 = V3

Iout x R72 - Idrive x R71 = Idrive x R75

For simplicity of design, R71 and R75 have the same valueRi:

Ri = Iout x R72 / (2 x Idrive)

Thepeak outputcurrent is the peak current for the deflectioncoil used in the design (here peak Iout = 0.75A), Idrive isthe drive current from the TDA4851: 250µA. The value ofresistor R72 can be chosen freely within certain limits:

1. The power dissipation in the resistor may not exceedthe power rating of the resistor used;

2. Thevoltage drop across R72 is subtracted from the totalavailable peak to peak coil drive voltage;

3. The minimum resistance is limited by the ground plane,which introduces a tolerance that has to be minimisedwith respect to the resistor value.

A good choice for R72 is 1Ω, the lowest available resistorvalue in the normal range. This leads to the following result:

Ri = 0.75 x 1 / (2 x 250 x 10-6)

Ri = 1500 Ω

Amplitude control is realised by adjustment of the output ofthe TDA4851.

0.8

0.6

70.064.0

60.056.748.0

35.537.831.5

0.1

0.15

0.2

0.3

0.4

1.0

1.5

2.0

3.0

4.0

FREQUENCY (kHz)

M36EDR311X170

M34EDC13X16*

*

*

*

(uF)

ECNATICAPAC

Ibeam=0.1mA X

XXX

X

XXX

EHT[kV]

25

24

23

f [kHz]60504030

Ibeam=0.0mAX

XXX

X

XX

Ibeam=0.4mA

X

XX

409


Vertical shift, a user control, is possible by P52. Injectinga dc current in one of the summation points, results in a dccurrent through the deflection coil. The 0 to +12V from thepotmeterP52 is translated into a dc current in R71 by meansof resistors R73/74. Design considerations for these tworesistors are: a potmeter in middle position (the dc currentin the coil should be zero) and the maximum shift range.

The resistors values in the circuit diagramallow ashift rangeof ±15 mm.

Theoutputof the TDA4861 is DCcoupled with the deflectioncoil, resulting in a bounce-free behaviour. Together with thefast response of the TDA4851 after a frequency change,this combination offers a stable picture within two frames.

For stability reasons, the combination R70/C56 is addedbetween the output and the most negative supply voltage.If no damping resistor is present on the deflection coil, R69should be added. Its value has to be determinedexperimentally.

The supply voltages for the TDA4861 are ± 10.5V, allowingsimple dc coupling of the deflection coil. For flyback, anextra supply voltage of +30V is connected to pin 8. Thisresults in a fast flyback of 300µs.

The vertical guard pulse, available on pin 9, is connectedto the Vg1 circuit to provide vertical blanking and protectionin case no deflection coil is connected.

Diode D52 protects the TDA4861 in case the flybackvoltage is missing or drops faster than the +10.5V atswitching off of the circuit.

Fig. 16 Vertical Deflection Output Stage.

3.8 Miscellaneous II

3.8.1 EHT compensationWith the aid of the built-in EHT capacitor and focus / Vg2divider in the LOT, the EHT voltage can be monitored in avery easy way. When the time constant of these built-incomponents is equal to the time constant of(R128+P57)/C92, then at LOT pin 12 an exact (divided)copy of the EHT can be found. This signal is buffered byT66 and inverted by T67, see Fig. 17.

Due to the tolerance on the Focus / Vg2 bleeder anadjustment is required (P57).

The EHT information signal goes to T68, the inverted signalmodulates the picture width driver, in order to compensatethe horizontal deflection for EHT variations. Thenon-inverted output of T68 is fed to the vertical amplitudecontrol pin of the TDA4851 to compensate the verticaldeflection for EHT variations.

Fig. 17 EHT Compensation.

3.8.2 Beam current limitingThe long-term average anode current for the given tube is700µA. This current is measured at the lower side of theEHT winding of the LOT, L54. The anode current flowsthrough resistor R126, connected to the +12V rail. Whenthe voltage across this resistor increases (with increasinganode current), the base voltage of T65 drops. With a highcontrast setting, 6V dc on pin 9 of connector 2, the beamcurrent limiter (BCL) will be activated at an average anodecurrent of:

Ia = +Uv - Ucontrast + Ube(T65) + U(D74) / R126 - Ibleeder

C93R133R132

T68

P57

C92 D75 R131

R130

R129

T67

T66

R128

L54

TO VERTICAL AMPLITUDE ADJ.

TO PICTURE WIDTH MODULATOR

EHT comp.

Vg2FOC

EHT

+155V

8

11123

10945

6

1

2

C24

BC548

1n5

BZX79470n

560E

22K

2M2

10K1K

MPSA92

BC549C

63V

1M

1M8

AT2090/01

+12V +30V-10.5V

+10.5V

R69*)

IC51

R76R75

R74

R73

R72

R71

P52

9

D52 R70

1

CON 6

5 1

C59C58

C57

C56

OUTPUT

GUARD

FROM TDA4851CURRENT INPUT

To DEFL. unit

+VDEFL

-VDEFL

V-shift

+HDEFL

-HDEFL

330E*)

TDA4861

15u68u

68u

5E6

47n

1K51E

1K5

BYD31D

40V

16V

16V

8K2

82K10K

10K

410


Ia = ( 12 - 6 + 0.65 + 0.5 ) / 15,000 - 25,000 / ( 300 x 106 )

Ia = 394 µA

3.8.3 Vg1 supplyThis monitor is equipped with an ac coupled video outputstage, using a supply voltage of 65V. After dc restoration,the highest black level is approximately 45V, with respectto ground. This implies that, with a tube requiring a cut-offof 125V, Vg1 must be -80V.

At C84 a negative flyback pulse is rectified (-130V). Duringnormal operation T58 is saturated and Vg1 will be -80V. IfT58 is not conducting, Vg1 will be -130V which will cut-offthe tube completely. This will be the case in the followingconditions:

vertical guard (failure in the vertical output stage;absence of vertical supply (+10.5V); andabsence of horizontal deflection (e.g. power switch off).

Vertical guard . When the vertical output stage generatesa vertical guard pulse, via D64 the base of T58 will becomehigh, which will turn off this transistor. Vg1 will be -130V.

Absence of vertical supply . When there is no verticalsupply, the vertical output stage can not generate a guardpulse either. Therefore, the Vg1 circuit is connected to thevertical supply rail. When the +10.5V supply is missing,T58 cannot conduct, resulting in Vg1 = -130V.

Fig. 18 Vg1 Supply.

Absence of horizontal deflection . When there is nohorizontal deflection the line flyback pulse will be small ornot present at all. This line flyback pulse is peak-peakrectified at C81 and thus keeping T59 blocked. Whenflyback pulses disappear, caused by a failure in the Line

Output Stage or at switch-off, T59 will conduct, causing T58to be blocked, and Vg1 will be -130V (C84 is large enoughto hold Vg1 on -130 Volts until the EHT is discharged).

3.8.4 Blanking for TDA4881Horizontal blanking pulses are derived from the line flybackpulses as delivered by the circuit around T54, see Fig. 2.The cathode of D51 is connected to the collector of T54.To limit the amplitude of the blanking pulses, D50 is added,see Fig. 19.

Fig. 19 Blanking Pulse Generator.

3.8.5 Video supplyThe ac coupled video output amplifiers require a supplyvoltage of:

Vs = Vswing + Vmin + ( Vs - Vmax )

Vs = 50 + 10 + 5 V

Vs = 65 V

The secondary windings 3-4 and 5-6 of the LOT, L54, areconnected in series and stacked on the +10.5V supply. Theoutput voltage of rectifier diode D65 and capacitor C83 is66V.

3.8.6 X-ray protectionA failure in the horizontal scan control section, could causea dangerous situation: the EHT might rise to anunacceptable high level. The thyristor, consisting ofT60/61, see Fig. 20, is fired when the flyback voltage risesto an unacceptable level. The flyback input pin 2 of theTDA4851 is forced high. This causes the horizontal driveoutput pin 3 of the TDA4851 to be turned off (output voltageis high). The line driver will be turned on, turning off theline output transistor. The T-on driver will not be triggeredany more. The result is that the complete line output stagestops working, so that the EHT will drop automatically.

Blanking is achieved, through the normal blanking circuit.Furthermore, the Vg1 voltage will also drop, in order tocut-off the tube.

+12V

D51D50

R68

R67

C55

100n

10E

C5V6BZX79

100V

BAW62

2K7

OUTPUTBLANKING

T54COLL.

R117

R116

C84

D71

D67

D66

C81

T59

T58

D64

D63D62

R113

R112R111

R110

PIN 9 LOT

PIN 6 LOT

GUARD VERTICAL

+10.5V

Vg1C39

C3910K

27K

10K 82K

1n5

C8V2BZX79

15K

BC558

1K

BAW62

BYD31J

250V

BF423

BZX79

2u2

BYD31J

BZX79

411


Fig. 20 X-ray Protection.

4. Oscillograms

The oscillograms given are meant as a guide-line indebugging and aligning the circuit and together with theabove text it can also be of help in understanding the circuit.

All oscillograms concerning the horizontal sync processingand deflection are given at two frequencies (31.5 &56.7 kHz).

The relative position of the traces in the oscillograms withrespect to ground is not given. It is assumed that the readerhas enough knowledge of the circuits to understand themwithout this indication.

In all the following figures trace 1 is at the top leading totrace 4 at the bottom of each oscillogram.

R118

R119

R117

C84

D70D69D68

C82

T61

T60

R115

R114

TO TDA4851 PIN 2

+12V

Vg1

200V4u7

82K

C56C56C561K

1n

1KBZX79 BZX79 BZX79

1K

1KBC548

BC558

31.5 kHz 56.7 kHz

Figs. 21 & 22 Horizontal Oscillator

Trace 1: H-sync pulse at pin 9 of TDA4851 (2V/div). Remark: When the sensitivity of trace 3 is enlarged smallTrace 2: Sawtooth voltage at pin 19 of TDA4851 (2V/div). triangles can be seen (100 - 150mV) pointingTrace 3: Φ1 voltage at pin 17 of TDA4851 (5V/div). downwards. These triangles coincide with the horizontalTrace 4: Drive voltage at pin 3 of TDA4851 (2V/div). syncpulse. So awider syncpulse gives wider (and larger)Horizontal: 5µs/div. triangles.

412


31.5 kHz 56.7 kHz

Figs. 23 & 24 Frequency to Voltage Converter

Trace 1: H-sync pulse at pin 9 of TDA4851 (2V/div). Remark: The output voltage of pin 3 is integrated and isTrace 2: Voltage at pin 2 of IC50 (5V/div). used for driving the horizontal oscillator and S-correctionTrace 3: Output voltage at pin 3 of IC50 (5V/div). switches.Horizontal: 5µs/div.

31.5 kHz 56.7 kHz

Figs. 25 & 26 Horizontal Driver

Trace 1: H drive pulse at pin 3 of TDA4851 (5V/div).Trace 2: Drain voltage at the driver MOSFET BSN274 (200V/div).Trace 3: Emitter voltage of the deflection transistor (500V/div).Trace 4: Current in the base of the deflection transistor (2A/div).Horizontal: 5µs/div.

413


31.5 kHz 56.7 kHz

Figs. 27 & 28 LOT & Deflection TransistorTrace 1: Emitter voltage of the deflection transistor (500V/div).Trace 2: Collector current of the deflection transistor (2A/div).Trace 3: Primary current in the LOT (0.5A/div).Trace 4: Primary voltage of the LOT (500V/div).Horizontal: 5µs/div.Remark: The switching of T64 causes ringing in the LOT. This ringing is suppressed by the damping network in serieswith the LOT (R124, C88, L52). Some small ringing remains and is visible in the oscillograms.

31.5 kHz 56.7 kHz

Figs. 29 & 30 Ton Switch

Trace 1: Primary voltage LOT (500V/div).Trace 2: Drain voltage T-on switch T64 (200V/div).Trace 3: Drain current T-on switch T64 (0.5A/div).Trace 4: Current in D73 (0.5A/div).Horizontal: 5µs/div.

414


31.5 kHz 56.7 kHz

Figs. 31 & 32 Drive Ton Switch

Trace 1: Pin 4 IC54 (5V/div). Remark: At the negative edge of the drive pulse IC50 isTrace 2: Pin 6 IC54 (5V/div). triggered. The output will give a fixed T-on (high) output.Trace 3: Drain T64 (100V/div). To prevent this one shot working at half frequencyHorizontal: 5µs/div. (fdrive > 1/Ton), this one shot must be retriggerable.

31.5 kHz 56.7 kHz

Figs. 33 & 34 Deflection Stage

Trace 1: Emitter voltage T55 (500V/div)/Trace 2: Voltage at pin 2 TDA4851 (2V/div).Trace 3: Deflection current (5A/div).Trace 4: Current in bridge coil L51 (5A/div).Horizontal: 5µs/div).

415


31.5 kHz 56.7 kHz

Figs. 35 & 36 S-correction switchesTrace 1: Emitter voltage T55 (500V/div).Trace 2: Anode voltage D61 (100V/div).Trace 3: Drain voltage S-correction switch T70/71/72 when on (100V/div).Trace 4: Drain voltage S-correction switch T70/71/72 when off (100V/div).Horizontal: 5µs/div.Remark: At 31.5 kHz all S-correction switches are conducting so in Fig. 35 trace 4 is missing.

31.5 kHz 56.7 kHz

Figs. 37 & 38 EW One ShotTrace 1: Voltage at pin 2 IC55 (5V/div).Trace 2: Voltage at pin 6 IC55 with max. pulse width (5V/div).Trace 3: Voltage at pin 6 IC55 with min. pulse width (5V/div).Horizontal: 5µs/div.Remark: Pin 5 of IC55 is modulated with the EW parabola, see Fig. 43. The output pulse width is thus EW modulatedwith the min/max pulse width given in traces 2 and 3.

416


Figs. 39 & 40 Vg1 Switch Off

Trace 1: Emitter voltage T55 (500V/div). Remark: The time constant of the picture tube and EHTTrace 2: Vg1 (50V/div). capacitor/bleeder is about 1.6s, so Vg1 is still -130V asHorizontal left: 20µs/div. the picture tube is fully discharged. Vg1 will also blankHorizontal right: 1s/div. the screen in case of vertical guard and failure of the

+10.5V supply.

Trace 1: Vertical deflection current (1A/div).Trace 2: Sync pulse at pin 10 TDA4851 (2V/div).Trace 3: Vertical oscillator voltage pin 16 TDA4851(2V/div).Trace 4: Output voltage at pin 5 TDA4861 (20V/div).Horizontal: 2ms/div.

Remark: During vertical sync pin 8 will be 2V (not visiblein this oscillogram due to sampling effect of the DSOused).

Fig. 41 Vertical Deflection

417


Trace 1: Vertical sync pulse at pin 10 TDA4851 (2V/div).Trace 2: Voltage at pin 8 TDA4851 (2V/div).Trace 3: Guard voltage at pin 9 TDA4861 (5V/div).Trace 4: Vg1 (50V/div).Horizontal: 2ms/div.

Fig. 42 Blanking and Guard

Trace 1: Vertical deflection current (1A/div).Trace 2: EW output (pin 11) of TDA4851 (1V/div).Trace 3: Pin 5 IC55 (1V/div).Trace 4: Filtered voltage of pin 3 IC55 (0.5V/div).Horizontal: 2ms/div.

Remark: In the middle of the picture tube a white bar withhigh intensity was displayed. At trace 3 the superimposedEHT compensation signal for picture width correction canbe seen. At trace 4 some line ripple is visible, seeFigs. 37&38.

Fig. 43 EW waveforms

418


Trace 1: VCE of the SMPS transistor (500V/div).Trace 2: VBE of SMPS transistor (5V/div).Trace 3: IC of SMPS transistor (1A/div).Horizontal: 10µs/div.

Fig. 44 Power supply

5. Component PlacementThe following recommendations are given for the design ofthe PCB (see also reference).

1. Keep loop areas with high currents and sensitive loopareas as small as possible.

2. Keep tracks that carry high voltage components andsensitive tracks as short as possible.

3. Do not locate the asynchronous SMPS transformerclose to the TDA4850.

4. Use a star ground without ground loops!

5. Implement local supply filtering for an IC. On theground only peripheral components of this particularIC may be grounded.

6. Try to ground sensitive components as close aspossible to the ground pin of its IC using a separateground track; for example, components of oscillator,Φ1 and Φ2.

7. Especially critical in this circuit are the componentsaround the TDA4851 (IC52), belonging to thehorizontal part. Where possible, SMD types shouldbe used. In all other cases, connecting tracks shouldbe kept as short as possible.

Fig. 45 Examples of SMD component placement

+

++PIN 1

IC52:TDA4851

R928K2

220nC65

1n5C66

220n

10nC67

C68

120KR96

PIN 1

IC50C5082n

IC5582n

C96PIN 1

419


8. IC50 and IC55, both NE555 timers, should be fittedwith an SMD supply bypass capacitor connecteddirectly across the supply pins. The reason for this is,to keep the current transient at switch-over of theoutput as small as possible.

9. The pulses from the F/V converter, IC50 in Fig. 3, andthe picture width driver, IC55 in Fig. 7, must notinterfere with the sawtooth voltage of the horizontaloscillator, IC52 in Fig. 1.

Examples of good layout solutions with SMD componentsare shown in Fig. 45.

6. ReferencesThe information in this section has been extracted from thefollowing report:

A Versatile 30 - 64 kHz Autosync Monitor

Author: H.Misdom / H.VerheesReport no.: ETV9200312NC:

For a complete understanding of this application leading toactual implementation of this design the above reportshould be consulted. Other essential reference sourcesare as follows:

Improvements on the 30 - 64 kHz Autosync Monitor

Author: H.VerheesReport no.: ETV9200812NC:

Full Mains Range 150W SMPS for TV and Monitors

Author: H.SimonsReport no.: ETV/AN9201112NC.:

Advanced Monitor Deflection Controllers TDA4851and TDA4852


Integrated SMPS Control Circuit TDA8380

Author:Report no.:12NC: 9398 358 40011

Specification of Bus Controlled Monitor

Author: J.Shy, T.H.Wu and J.ChiouReport no.: Taiwan/AN910112NC:

Improvements on the 30 to 64 kHz Autosync Monitor


Electromagnetic Compatibility and PCB Constraints

Author: M.J.CoenenReport no.: ESG8900112NC: 9398 067 20011

420

Automotive Power Semiconductor ApplicationsPhilips Semiconductors

CHAPTER 5

Automotive Power Electronics

5.1 Automotive Motor Control(including selection guides)

5.2 Automotive Lamp Control(including selection guides)

5.3 The TOPFET

5.4 Automotive Ignition

421


Automotive Motor Control


423


5.1.1 Automotive Motor Control with Philips MOSFETS

The trend for comfort and convenience features in today’scars means that more electric motors are required than ever- a glance at Table 1 will show that up to 30 motors may beused in top of the range models, and the next generationof cars will require most of these features as standard inmiddle of the range models.

All these motors need to be activated and deactivated,usually from the dashboard; that requires a lot of coppercable in the wiring harnesses - up to 4km in overall length,weighing about 20 kg. Such a harness might contain over1000 wires, each requiring connectors at either end andtaking up to six hours to build. Not only does this representa cost and weight penalty, it can also create major’bottlenecks’ at locations such as door hinges, where itbecomes almost impossible to physically accommodate the70-80 wires required. Now, if the motor switching, reversingor speed control were to be done at the load bysemiconductor switches, these in turn can be driven viamuch thinner, lighter wiring thus alleviating the bottlenecks.Even greater savings - approaching the weight of apassenger - can be achieved by incorporating multiplexwiring controlled by a serial bus.

Types of motors used in automobilesMotor design for automotive applications represents anattempt at achieving the optimum compromise betweenconflicting requirements. The torque/speed characteristicdemanded by the application must be satisfied while takingaccount of the constraints of the materials, of space and ofcost.

There are four main families of DC motors which are, orwhich have the potential to be used in automobiles.

Wound field DC Commutator Motors

Traditionally motors with wound stator fields, a rotor supplyfed via brushes and a multi-segment commutator - seeFig. 1 - have been widely used. Recently, however, theyhave been largely replaced by permanent magnet motors.Characteristically they are found with square frames. Theymay be Series wound (with high torque at start up but tendto ’run away’ on no-load), Shunt wound (with relatively flatspeed/torquecharacteristics) or (rarely)Compound wound.

Fig. 1 Wound Field DC Commutator Motor

DC

commutator

fieldwinding

stator

brushesslotted rotorwith windings

air gap

425


motor typical nominal typical type of drive typical proposed MOSFET * commentsapplication power (W) current (A) number of number of

such motors switches per standard L2FETmotor BUK- BUK-

air- 300 25 1 unidirectional, 1 456 556 Active suspension mayconditioning variable speed also require such high

power motors

radiator fan 120-240 10-20 1 unidirectional, 1 455 555 These motors may govariable speed brushless, requiring 3

to 6 lower ratedswitches

fuel pump 100 8 1 unidirectional 1 453 553

wipers: unidirectional, Reversing action is atfront 1-2 variable speed present mechanical.

This could be donerear 60-100 5-8 1 1 452/453 552/553 electronically using 2 or

4 switchesheadlamp 2

washers:front 1-2

30-60 2.5-5 undirectional 1 452 552rear 1-2

window lifter 25-120 2-10 2-4 reversible 4 452/455 552/555

sun-roof 40-100 3.5-8 1 reversible 4 452/453 552/553

seatadjustment 50 4 4-16 reversible 4 453 553(slide,recline, lift,lumbar)

seat belt 50 4 2-4 reversible 4 453 553

pop-up 50 4 2 reversible 4 453 553headlamp

radio aerial 25 2 1 reversible 4 452 552

door lock 12-36 1-3 6-9 reversible 4 451/452 551/552

mirror 12 1 2 reversible 4 451 551adjustment* These are meant for guidance only. Specific applications should be checked against individual users requirements. In addition to standard andL2FETs, FredFETs and low and high side TOPFETs might be considered. Also a variety of isolated, non-isolated and surface mount packageoptions are available

Table 1 Typical motor and switch requirements in top of range car.

426


Permanent Magnet (PM) DC CommutatorMotorsThese are now the most commonly used motors in moderncars. The permanent magnet forms the stator, the rotorconsists of slotted iron containing the copper windings - seeFig. 2. They have a lighter rotor and a smaller frame sizethan wound field machines. Typical weight ratios betweena PM and a wound field motor are:

Copper 1:10Magnets 1:7Rotor 1:2.5Case 1:1

PM motors have a linear torque/speed characteristic - seeFig. 3 for typical curves relating torque, speed, current andefficiency. (Philips 4322 010 76130). They are generallyused below 5000 rpm. Their inductance (typically 100 -500 µH) is much lower than wound field machines. Newmaterials (e.g. neodymium iron boron compounds) offereven more powerful fields in smaller volumes.

Fig. 2 Permanent Magnet Commutator Motor

Fig. 3 Performance Curves for PM Commutator Motor

PM Brushless DC Motors

Although common in EDP systems, brushless DC motorsare not yet used extensively in cars. They are underconsideration for certain specialised functions, e.g. fuelpump where their ’arc free’ operation makes themattractive. They have a wound stator field and a permanentmagnet rotor - Fig. 4. As their name suggests they haveneither mechanical commutator nor brushes, thuseliminating brush noise/wear and associated maintenance.Instead they depend on electronic commutation and theyrequire a rotor position monitor, which may incorporate Halleffect sensors, magneto resistors or induced signals in thenon energised winding. Thanks to their lightweight, lowinertia rotor they offer high efficiency, high power density,high speed operation and high acceleration. They can beused as servos.

Fig. 4 Permanent Magnet Brushless Motor

Switched Reluctance Motors

These motors - see Fig. 5 - are the wound field equivalentto the PM brushless DC machine, with similar advantagesand limitations. Again, not yet widely used, they have beenproposed for some of the larger motor applications such asradiator and air conditioning fans, where their highpower/weight ratio makes them attractive. They can alsobe used as stepper motors in such applications as ABS andthrottle control.

Motor drive configurations

The type of motor has a considerable influence on theconfiguration of the drive circuit. The two families of DCmotors, commutator and brushless need different drivecircuits. However suitably chosen MOSFETs can be usedto advantage with both.

air gap

permanent

magnetson rotor

slotted statorwith windings

3-phase sinewaveor squarewave

DC

statorslotted rotor

with windings

air gap

commutator

permanent

magnets

brushes

427


Fig. 5 Switch Reluctance Motor

Commutator MotorsBoth permanent magnet and wound field commutatormotors can be controlled by a switch in series with the DCsupply - Fig. 6. Traditionally relays have been used, butthey are not considered to be very reliable, particularly inhigh vibration environments. Semiconductors offer anattractive alternative, providing:

• low on-state voltage drop.

• low drive power requirements.

• immunity from vibration.

The Power MOSFET scores on all counts, offering ONresistances measured in mΩ and requiring only a few volts(at almost zero current) at the gate, to achieve this.

Fig. 6 Commutating Motor Switch

When a motor is switched off, it may or may not be running.If it is, then the motor acts as a voltage source and therotating mechanical energy must be dissipated either byfriction or by being transformed into electrical energy andreturned to the supply via the inherent anti-parallel diodeof the MOSFET. If it is not turning, then the motor appearsas purelyan inductance and for a low side switch the voltagetransient developed will take the MOSFET into avalanche.Now, depending on the magnitude of the energy stored inthe field and the avalanche capability of the MOSFETs, adiode in parallel with the motor may or may not be required.

As a first approximation, if

then a diode may not be needed.

Fig. 7 H Bridge using MOSFETs

Reversing the polarity of the supply, to a commutator motor,reverses the direction of rotation. This usually requires anH bridge of semiconductors, see Fig. 7. In this case the builtin diodes, inherent in MOSFETs, mean that no extra diodesare necessary. It should be noted that there are now twodevices in series with the motor. So, to maintain the samelow level of on-state voltage drop, each MOSFET must bedoubled in area. With four devices in all, this means areversing H bridge requires 8 x the crystal area needed bya unidirectional drive.

Chopping the supply, controls the mean voltage applied tothe motor, and hence its speed. In the case of the H bridgeTR1 and TR4 might be used to control direction, while achopping signal (typically 20kHz) is applied to TR3 or TR2.When reversing the direction of rotation, it is preferable toarrange the gating logic so that the system goes through acondition where TR1, TR2, TR3 and TR4 are all off.

salient poleswithfield windings

switched DC

rotor withsalient poles

air gap12

.LmIm2 < WDSS

+ V BATTR1

TR2 TR3

TR4

N-channel

MOSFET

+ V BAT

freewheeldiode

428


Switched Field MotorsPM brushless motors typically require 6 switches togenerate the rotating field, see Fig. 8. Although there aremotors, which operate at lower power density, which canbe driven from 3 switches. The circuit in Fig. 9 shows a lowside switch version of such a drive. A similar arrangementwith high side switches would be possible.

Fig. 8 MOSFET Brushless Motor Drive

Fig. 9 3 MOSFET Brushless Motor Drive

Switched reluctance motors may use as few as 4 or asmany as 12 switches to generate the rotating field, a 4switch version is shown in Fig. 10.

The speed and direction of all switched field motors iscontrolled by the timing of the field pulses. In the case ofbrushless DC machines these timing pulses can be derivedfrom a dedicated IC such as the Philips NE5570. Rotorposition sensing is required - using, for example,magnetoresistive sensors - to determine which windingsshould be energised. Compared with a DC commutatormotor, the power switches for a brushless motor have tobe fast, because they must switch at every commutation.

Fig. 10 4 MOSFET Switched Reluctance Motor Drive

PWM speed control pushes up the required switchingspeed even further. Philips MOSFETs are designed so thatboth switch and inbuilt diode are capable of efficientswitching at the highest frequencies and voltagesencountered in automotive applications.

High side drivers

Often, in automobiles, there is a requirement for the switchto be connected to the positive battery terminal with theload connected via the common chassis to negative.Negative earth reduces corrosion and low side load is saferwhen loads are being worked on or replaced. Also, whenH bridges are considered the upper arms are of course highside switches.

Fig. 11 P-channel high side switch

There are two MOSFET possibilities for high side switches:

+ V BAT

+

+

+ V BATTR1

TR2 TR4

TR3

TR6

TR5

+ V BAT

TR1 TR2 TR3+ V BAT

p-channelMOSFET

429


Fig. 12 N-channel high side switch with charge pump

• P-channel switches . These simplify the drive circuitwhich only needs referencing to the positive supply, seeFig. 11. Unfortunately p-channel devices require almostthree times the silicon area to achieve the same onresistance as n-channel MOSFETs, which increases cost.Also P-channel devices that can be operated from logiclevel signals are not readily available.

Fig. 13 Bootstrap bridge drive

•N-channel switches. To ensure that theseare fully turnedon, the gate must be driven 10 V higher than the positivesupply for conventional MOSFETs or 5 V higher for LogicLevel types. This higher voltage might be derived from anauxiliary supply, but the cost of ’bussing’ this around thevehicle is considerable.

The additional drive can be obtained locally from a chargepump, an example in shown in Fig. 12. An oscillator (e.gPhilips AU7555D) free runs to generatea rectangular 12 Vwaveform, typically at around 100kHz. A voltage doublerthen raises this to around twice the battery voltage. Thisarrangement is equally suitable for ’DC’ or chopper drives.

An alternative approach for H bridge choppers is to usethe MOSFETs themselves to generate the drive voltagewith a bootstrap circuit as shown in Fig. 13. This circuitworks well over a range of mark-space ratios from 5% to95%. Zener diodes should be used in this circuit to limitthe transients that may be introduced onto the auxiliaryline.

Fig. 14 High Side TOPFET

High Side TOPFET

The ideal high side switch to drive motor loads would beone which could be switched on and off by a groundreferenced logic signal, is fully self-protected against shortcircuit motors and over temperatures and is capable ofreporting on the load status to a central controller.

The Philips response to these requirements is a range ofhigh side TOPFETs. The range contains devices withRDS(ON) from 38 to 220 mΩ, with and without internal groundresistors. All the devices feature on board charge pump andlevel shifting, short circuit and thermal protection and statusreporting of such conditions as open or short circuit load.As can be seen in Fig. 14, the use of a TOPFET makes thecircuit for a protected high side drive for a motor very simple.

Currents in motor circuits

There are 5 classes of current that can flow in a motorcircuit:-

• nominal - this is the maximum steady state current thatwill flow when the motor is performing its function undernormal conditions. It is characterised by its relatively lowlevel and its long duration.

N-channel

MOSFET

+ V BAT

v charge pump

AU

7555

D

1

2

3

48

7

6

5GND

TRIG

O/P

RES

CV

THR

DIS

VCC

+ V BAT

input

status BUK202-50Y

TOPFET

+ V BAT

+ +

TR1

TR2 TR3

TR4

430


• overload - this is the current which flows when the motoris driving a load greater than it is capable of drivingcontinuously, but is still performing its function i.e notstalled. This is not necessarily a fault condition - someapplications where the motor is used infrequently and foronly a short time, use a smaller motor, than would beneeded for continuous operation, and over-run it. In thesecases the nominal current is often the overload current.Overload currents tend to be about twice the nominalcurrent and have a duration between 5 and 60 seconds.

• inrush - or starting currents are typical 5 to 8 times thenominal current and have a duration of around 100 ms,see Fig. 15. The starting torque of a motor is governedby this current so if high torque is required then the controlcircuit must not restrict the current. Conversely if startingtorque is not critical, then current limiting techniques canbe employed which will allow smaller devices to be usedand permit sensitive fault thresholds to be used.

Fig. 15 Start-up Current in 2 A Motor

• stall - if the motor cannot turn then the current is limitedonly by the series resistance of the motor windings andthe switch. In this case, a current of 5-8 times the runningcurrent can flow through the combination. Fig. 16 showsthe current that flows through a stalled 2 A motor - thecurrent gradually falls as the temperature, andconsequently the resistance, of the motor and theMOSFET rises.

• short circuit - if the motor is shorted out then the currentis limited only by the resistance of the switch and thewiring. The normal protection method, in this case, is afuse. Unless other current control methods are used thenit is the I2t rating of the fuse which determines how longthe current will flow.

Fig. 16 Current in stalled 2 A Motor

It is important that the devices, selected for the controlcircuit, can operate reliably with all of these currents. Withsome types of switching device, it is necessary to select onthe basis of the absolute maximum current alone. Often thisresults in a large and expensive device being used. Thecharacteristics of MOSFETs, in particular their thermallylimited SOAR (no second breakdown), allows the designerto specify a much smaller device whose performance moreclosely matches the needs of the circuit.

Device requirements

VoltageThe highest voltage encountered under normal operationis 16 V, under jump start this can rise to 22 V. In the casewhere the battery becomes disconnected with thealternator running the voltage can rise to 50 V (assumingexternal protection is present) or 60 V in the case of 24 Vvehicles see Table 2. Thus the normal voltage requirementis 50/60v, however the power supply rail in a vehicle isparticularly noisy. The switching of the numerous inductiveloads generates local voltage spikes and surges of bothpolarities. These can occur singly or in bursts, havemagnitudes of 100 V or more and durations of the order of1ms.

It is important to chose MOSFETs capable of withstandingthese stresses, either by ensuring VDS exceeds the valueof the transients or by selecting 50/60 V devices withsufficient avalanche energy capability to absorb the pulse.For transients in excess of these values it is necessary toprovide external protection.

However, the TOPFET range of devices, both low and highside, have overvoltage protection on chip. As aconsequence they are rated to withstand very much highertransient energies.

431


Voltage Range Cause

>50 (60)* coupling of spurious spikes30 to 50 clamped load dump22 to 30 voltage surge on cut-off of inductive

loads16 to 22 jump start or regulator degraded

(32 to 40)*

10.5 to 16 normal operating condition(20 to 32)*

8 to 10.5 alternator degraded6 to 8 starting a petrol engine

(9 to 12)*

0 to 6 starting a diesel engine(0 to 6)*

negative negative peaks or reverseconnected battery

* 24 V supply

Table 2 Conditions Affecting Abnormal Supply Voltages

TemperatureThe ambient temperature requirement in the passengercompartment is -40 to +85˚C , and -40 to +125˚C under thebonnet. All Philips MOSFETs shown in Table 1 haveTjmax = 175˚C.

The TOPFETs have a maximum operating Tj of 150˚Cbecause above this temperature the on chip protectioncircuits may react and turn the device off. This prevents thedevice from damage that could result from over dissipation.This protection eases the problems of the thermal designby reducing the need for large safety margins.

L2FETs

The supply voltage in an automobile derived from thebattery is only 12 V (nominal). This can vary from 10.5 V to16 V under normal operation. It is important that theMOSFET switches be fully turned on under theseconditions, not forgetting that for high side switches it maybe necessary to derive the gate drive from a charge pumpor bootstrap.

Whilst a gate source voltage of 6 V is usually sufficient toturn a conventional MOSFET on, to achieve the lowest onresistance, 10 V is required. Thus the margin betweenavailable and required gate drive voltage may be quite tightin automotive drive applications.

One way to ease the problem is to use Logic LevelMOSFETs (L2FET), such as the BUK553-60A orBUK555-60A, which achieve a very low on resistance statewith only 5 V gate-source.

Conclusions

There is an increasing demand for low cost, reliableelectronic switching of motors in automobiles. Despite thewide variety of motor types and drive configurations thereis a Philips Power MOSFET solution to all of thesedemands. The broad range of types includes standard andlogic level FETs, FredFETs, high and low side TOPFETs.The combination of low on-state resistance, ease of driveand ruggedness makes them an attractive choice in thearduous automotive environment.

432


Automotive Lamp Control


433


5.2.1 Automotive Lamp Control with Philips MOSFETS

The modern motor vehicle, with its many features, is acomplex electrical system. The safe and efficient operationof this system calls for sophisticated electronic control. Asignificant part of any control system is the device whichswitches the power to the load. It is important that the righttype of device is chosen for this job because it can have amajor influence on the overall system cost andeffectiveness. This choice should be influenced by thenature of the load. This article will discuss the features ofthe various types of switching device - both mechanical andsolid state. These factors will be put into the context of theneeds of a device for the control of resistive loads like lampsand heaters. It will be shown that solid state devices allowthe designer a greater degree of control than mechanicalswitches and that the features of Power MOSFETs makethem well suited to use in automotive applications.

Choice of switch type

Mechanical or solid-state

Designers of automotive systems now have the choice ofeither mechanical or solid-state switches. Althoughmechanical switches can prove be a cheap solution theydo have their limitations. Solid-state switches overcomethese limitations and provide the designer with severaluseful additional features.

Areas where the limitations of relays become apparentinclude:-

• Reliability - to achieve the required levels of sensitivityand efficiency means that relay coils have to be woundwith many turns of very fine wire. This wire is susceptibleto damage under conditions of high mechanical stress -vibration and shock.

• Mounting - special assembly techniques are neededwhen dealing with automotive relays. Their outlines arenot compatible with the common methods of automatedassembly like auto insertion and surface mounting.

• Dissipation - the power loss in the coil of a relay is notnegligible - the resulting temperature rise makes it unwiseto mount other components in close proximity. In somemultiple relay applications it is necessary to providecooling by ventilation.

• Temperature - the maximum operating temperature ofrelays is typically in the range 70˚C - 85˚C.

• Corrosion - the unsealed mechanism of relays arevulnerable in contaminating and corrosive environments.

• Overloads - relays can also prove to be unreliable underhigh transient load conditions. The arcing which occurswhen switching high currents andvoltages causes contactwear leading eventually to high resistance or even thecontacts welding together.

• Hazardous Materials - to achieve the prefered switchingperformance, relays need to use materials like cadmium.The use of such materials is becoming restricted bylegislation on health and safety grounds.

• Noise - the operation of a relay is not silent. This is provingto be unacceptably intrusive when relays are sited in thepassenger compartment.

Solid-stateswitchescan overcome these limitations but canalso give the designer the option of introducing the followinguseful features:-

• Current limiting - a relay has two states - on or off so thecurrent which flows depends only on the load. There is nomechanism which allows a relay to regulate the currentwhich flows through it. The best that a relay can do is totry and turn off, when a high current is detected, butbecause they are so slow, very large currents may beflowing before the relay can react and damage may havealready been caused. However the characteristics of solidstate devices like MOSFETs and bipolar transistors allowthem to control the current. This allows designers thechance to introduce systems which can handle faults in asafe and controlled manner.

• Control of switching rate - the lack control that a relayhas over the current proves to be a limitation not onlyduring fault conditions but also during normal switching.Without control, the rate at which current changes, dI/dt,depends only on the external circuit and extremely highrates can result. The combination of high dI/dt and thecontact bounce that relays are prone to, creates an’electrically’ noisy environment for surrounding systems.The control available with solid-state switches permits thedesigner to restrain the current and produce ’soft’switching eliminating any possible EMC problems.

Power MOSFET or Bipolar TransistorAll solid-state switches have significant advantages overrelays but there are different types of solid-state switch andtheir particular characteristics need to be taken into accountif an optimum choice is to be made. There are two majortypes of solid-state switches which are suitable for use inautomotive applications - power MOSFETs and bipolartransistors - and several factors need to be considered ifthe optimum choice is to be made.

435


• Overload - The choice of device type can be influencedby the magnitude and duration of overload currentsassociated with the application - for example the inrushcurrent of lamps. This factor is particularly importantbecause the maximum current that can be safelyconducted by a bipolar transistor is independent of itsduration. Whereas the safe operating area of a MOSFETallows it to handle short duration currents very muchgreater than its DC rating.

• Drive power - There can be a significant differencebetween the total power needed to drive bipolar and MOStransistors. A MOSFET’s oxide insulation makes it avoltage controlled device whereas a bipolar needs currentdrive. However, most control circuits are voltage ratherthan current orientated and the conversion to currentoperation often involves the used of loss inducingresistors.

• Reverse protection - If the switching device is requiredto survive reverse conduction conditions then it isnecessary to have a diode, connected in anti parallel,around it. If the device is a bipolar transistor then an extracomponent will be needed. However the device is aMOSFET then it has an inherent body / drain diode whichwill perform this function without the additionalexpenditure in components or board space.

Logic level and standard mosfets

The battery voltage in a car is a nominal 12 V. This can varyfrom 10.5 V to 16 V under normal operation and can fall aslow as 6 V during starting. It is important that MOSFETswitches be fully turned on at these voltages, bearing inmind that for a high-side switches it may be necessary toderive the gate voltage from a charge pump circuit. Whilea VGS of 6 V is usually sufficient to turn a standard MOSFETon, 10 V is required to achieve the lowest on-stateresistance, RDS(ON). Thus the margin between available andrequired gate drive voltage may be quite tight in automotivedrive applications. One way to overcome this problem is touse L2FETs such as the BUK553-60A or BUK555-60A,which achieve a very low RDS(ON) with a VGS of only 5 V.

Switch configuration

A load’s control circuit can be sited in either its positive ornegative feeds. These are referred to as high side and lowside switching respectively. Which configuration is chosenoften depends on the location of the load/switch and thewiring scheme of the vehicle but other factors like safetycan be overriding. The use of semiconductor switchesintroduces another element into the decision processbecause of the need to ensure that they are being drivencorrectly.

Low Side SwitchIn this arrangement the load is permanently connected(perhaps via a fuse and the ignition switch) to the positivesupply. The switching device is connected between thenegative terminal of the load and the vehicle ground. This,together with the almost universal practice of referencingcontrol signals to the vehicle ground, makes theimplementation of a low side switch with MOSFETsextremely simple. The circuit shown in Fig. 1 shows aMOSFET connected as a low side switch to a lamp load.TheSource terminalof the MOSFET is connected to groundso the control signal, which is also referenced to ground,can be connected to the Gate.

Fig. 1 Low side switch with N-channel MOSFET

High Side DriversOften, however, there is a requirement for the switch to beconnected to the positive battery terminal with the loadconnected via the common chassis to the negative. Thisarrangement reduces electrochemical corrosion and therisk of accidentally activating the device duringmaintenance.

One method of creating such a high side switch is to useP-channel rather than N-channel MOSFETs. A typicalarrangement is shown in Fig. 2. In this the source isconnected to the +ve feed and the drain to the load. TheMOSFET can be turned ON by taking the control line tozero and it will be OFF when the gate is at +ve supplyvoltage. Unfortunately P-channel MOSFETs require almostthree times the silicon area to achieve the same low on-stateresistance as N-channel types and so are much moreexpensive. An additional problem is the difficulty ofobtaining P-channel devices with low enough gatethreshold voltage to operate reliably at low battery voltages.

N-channel

MOSFET

+ V BAT

436


Fig. 2 P-channel high side switch.

Using N-channel devices overcomes these problems butinvolves a more complicated drive circuit.

To ensure that a n-channel MOSFET is fully turned on, thegate must be driven 10 V higher than its source, forconventional MOSFETs, or 5 V higher for Logic Level (L2)FETs. With the source connected to the load and with most

of the supply being dropped across the it, the gate has totaken to a voltage higher than the supply voltage. Thishigher voltage might be derived from an auxiliary supply,but the cost of ’bussing’ this around the vehicle would behigh. Figure 3 shows how this auxiliary supply could beproduced locally. It consists of an oscillator - based aroundthe Philips AU7555D - running at approximately 100 kHzwhich is driving a charge pump which nearly doubles thesupply voltage.

An alternative approach, which can be used when thedevice doesn’t have to be continuously ON, for examplePWM lamp dimming or lamp flashing, is shown in Fig. 4. Inthis bootstrap arrangement capacitor C is charged to thesupply voltage when the MOSFET is OFF. When theMOSFETis turnedON, its source terminal, and the negativeend of C, rises to the supply voltage. The potential of thepositive end of C is now higher than the +ve supply anddiode D is reverse biased preventing C from beingdischarged. C can now act as the high voltage supply forthe gate. The inevitable leakages will tend to discharge Cand hence reduce the gate/source voltage, but with goodcomponents it is easy to ensure that a voltage high enoughto keep the MOSFET fully ON is available for severalseconds.

P-channel

MOSFET

+ V BAT

Fig. 3 N-channel High-side switch with charge pump

N-channel

MOSFET

+ V BAT

AU7555D

4

3

7

6

2

5

R

Q

DIS

THRCV

TR

v charge pump

1

GND

437


Fig. 4 Bootstrap High side driver

Inrush currentAny circuit or device which is intended to drive either a lampor a heater must be able to handle not only the normalrunning current but also the inrush current at start up. Alllamps and many heaters are essentially resistors madefrom metal conductors whose resistivity will increase withtemperature.

In the case of lamps, the extremely high operatingtemperature (3000 K) means that the hot to cold resistanceratio is large. Typical values for a 60 W headlamp bulb are:-

filament currentresistance

cold (-40˚C) 0.17 Ω 70 A

hot 2.4 Ω 5 A

The figures given for the currents assume that there is 12 Vacross the lamp, in practice wiring and switch resistancewill reduce the cold current somewhat, but the ratio will stillbe large. The actual ratio depends upon the size andconstruction of the lamp but figures between 10 and 14 arecommon. For safety, the higher figure should be used.

The low thermal mass and the high power dissipation(850 W peak in 60W lamp) means that the lamp heats upvery quickly. This means that the current falls from its peakvalue equally quickly. The time it takes for the current to fallback to its normal value depends on the size andconstruction of the lamp - the larger the lamp the longer itwill take to heat up. Typically the current will have anexponentially decay with a time constant of 1 - 10 ms. Thewaveforms in Fig. 5 show the typical inrush current for a60 W lamp being switched on by a MOSFET. The initialtemperature of the lamp filament was 25˚C.

The normal operating temperature of a heater is not as highas that of a lamp, so the inrush current is rarely greater thantwice the nominal current and often less. The duration ofthe ’inrush’ can, however, last for many minutes and it maybe this current which is used to define the ’normal’ operatingcondition.

Being essentially resistive, lamps and heaters have verylow inductance. This means that the current in the load willrise as quickly as the rest of the wiring will let it. This canlead to serious interference problems.

Fig. 5 Current in 60 W lamp during start up

Switch rateThe inductance associated with the supply wires in a car,is not negligible - a figure of 5µH is often quoted. Thisinductance, combined with the high rates of change ofcurrent associated with the switching of resistive loads andlamps, results in transient voltage appearing on the supplyleads. The magnitude of the transient is given by:-

For example a current which rises as slowly as 2 A/µs willcause a 10 V dip in the supply to the switching circuit. Thiseffect can be clearly seen in the waveforms of Fig. 6a. Sucha perturbation can have an effect in two ways. In the firstcase the control circuit may be upset by having its supplyreduced to only 2 V and may, if not specifically designed tocope with it, fail to function correctly. In the second case, itis easy for a transient as large as this, with its significanthigh frequency content, to be transmitted into adjacentconductors in the wiring loom. If some of the conductorsare signal wires then false triggering ofother functions couldresult.

N-channel

MOSFET

+ V BAT

C

10uF

R2

R1BC337

BC327

BC337

Lamp Current (10A/div.)

0

10ms/div

Vtransient = −L .dIdt

438


a) Low impedance gate drive

b) 47kΩ gate drive resistor

Fig. 6 Effect of high dI/dt on supply voltage

The dip will be reduced to manageable proportions if thedI/dt can be held to 0.5 A/µs. Since the loads are resistive,achieving this means reducing the rate that the voltage isapplied to the load. This type of ’soft’ starting is relativelyeasy to implement when the controlling device is a PowerMOSFET. All that is needed is to put resistance in serieswith the gate drive.

The plots shown in Fig. 6b illustrate the effect inserting47 kΩ in series with the gate supply of a BUK455-60A. Theload for these tests was a 60W lamp being supplied froma battery via a 5 µH inductor. The dip in voltage due to dI/dtis now lost in the voltage drop from the wiring resistance.

The rate at which current falls at turn off is also important.High negative dI/dt will result in a large positive spike onthe supply rails. As with the negative dip, this spike couldcause interference in adjacent wires but it could also causeovervoltage damage. Unlike the turn on dip which can neverbe greater than 12 V, the magnitude of the turn off spike ispotentially unlimited. In practice, however, it is extremely

Fig. 7 Gate supply networks for switching rate control

unlikely that the voltage would exceed 30 V. Transientvoltages of this magnitude are relatively common in theautomotive environment and all circuits should be able towithstand them. It is still worthwhile keeping the turn offtransient under control by ensuring that the dI/dt is lowenough - a figure of <1 A/µs is standard.

Soft turn off, like soft turn on, is easy to implement if thecontrolling device is a Power MOSFET. In fact the sameseries resistor can be used to limit both the turn on and turnoff rates. With a lamp load, however, this method will givea much slower turn off than is really necessary because ofthe large difference between the current at turn on and turnoff. If this is a problem then an additional resistor and diodeput in parallel with the first resistor - see Fig. 7 - will speedup the turn off.

MOSFET selection

The type of device chosen for a particular applicationdepends upon the features that the control circuit needs tohave. Table 3 lists the available MOSFET types and someof their features that would be useful in automotiveapplications.

Having chosen the type of MOSFET it becomes necessaryto decided on the size of device. With MOSFETs thisdecision is made easier because, in its on-state, a MOSFETcan be treated as a resistance and because its safeoperating area (SOAR) is set by thermal considerationsonly (no second breakdown effects). The first stage of theselection process is to chose a device on the basis of thenominal current requirement. The next stage is to checkthat the inrush current, of the particular application and thedrive method used, does not result in the MOSFETexceeding the transient thermal ratings. Having selected adevice that is capable of switching the load the designercan then use the quoted values for the on-state resistance(RDS(ON)) to check that any on-state voltage drop

Drive

GateSupply Voltage (5V/div)

Lamp Current (10A/div)

20us/div

0

0peak dI/dt=2A/us

Supply Voltage (5V/div)

Lamp Current (10A/div)

20us/div

0

0peak dI/dt=0.5A/us

439


requirements are being met. Tables 3 and 4 lists many ofthe different of lamps and resistive loads found in cars andsuggests MOSFET types that can be used to control them.

MOSFET FeaturesType

Standard Wide range of current ratings from 5 to>100 A.Wide range of package stylesFast recovery anti-parallel diode (60 /100 V types)Extremely fast switching.

L2FET as standard+Fully operational with low voltage supply

Low side as L2FETTOPFET +

overvoltage protectionoverload protectionover temperature protection3 and 5 pin versionslinear and switching control

High side Single component providing:-TOPFET high side switch (on chip charge pump

and level shifting)device protectionload protectionstatus reportingCMOS compatible input

TABLE 1 MOSFET Types and Features

The automotive environment

The environment that circuits and devices can be subjectedto in automotive applications can prove to be extremelysevere. Knowledge of the conditions that can exist isnecessary to ensure that suitable devices and circuits arechosen. The two most stressful aspects of the environmentare the temperature and voltage.

Temperature

The lowest temperature that is likely to be reached is -40˚C.This is related to the minimum outside temperature andmay be lower under some special circumstances. Themaximum temperature depends to a great extent upon thesiting of circuits. The general ambient temperature in theengine compartment can be quite high and it is reasonableto assume that devices will see temperatures of 125˚C.Within the passenger area, conditions are somewhat morebenign, but in areas where heat is generated and air flowis restricted, the temperature will be higher than might be

expected. For this reason it is necessary to assume thatthe circuits and devices will have to work in an ambienttemperature of 85˚C.

VoltageIt is possible to split the voltage conditions that can occurinto two groups - Normal and Abnormal. ’Normal’ conditionsare essentially those which can be present for very longperiods of time. Under such conditions it is reasonable toexpect devices and circuits to be completely operationaland to suffer no ill effects. ’Abnormal’ conditions arecharacterised by their temporary nature. They are notexpected to persist for long periods and during them, someloss in device / circuit performance can be expected and,in some cases, is allowable.

Normal voltagesWhen considering the ’Normal’ environment it is importantto included both the typical and extreme cases. The crucialcondition for most devices and circuits is when the engineis running. At this time the supply voltage can be anywherebetween 10.5 and 16 V in ’12 V’ systems or between 20and 32 V in ’24 V’ systems.

The other significant ’normal’ operating mode is whenengine not running. In this state the supply voltage couldbe very low but voltages below some level must beconsidered as a fault condition. However some circuits willhave to operate with voltages as low as 6 V.

Voltage Level Cause

12 V systems 24 V systems

40 V - 50 V 60 V - 75 V external spikes30 V - 40 V 50 V - 60 V clamped load dump22 V - 30 V 22 V - 30 V inductive load switch off16 V - 22 V 32 V - 40 V jump start16 V - 22 V 32 V - 40 V faulty regulator8 V - 10.5 V 12 V - 20 V faulty alternator

6 V - 8 V 9 V - 12 V starting a petrol engine0 V - 6 V 0 V - 6 V starting a diesel engine

Table 2 Abnormal Supply Voltages

Abnormal voltagesIt is possible to envisage a situation in which nearly anyvoltage could appear on the supply wires of a vehicle. Howextreme the voltages get depends to a great extent uponthe protection, both deliberate and incidental, built into thesystem. The actual voltage that appears at the terminals ofa circuit is also influenced strongly by its location and thelocation of the protection. Analysis of the automotiveenvironment has produced a list of expected abnormalconditions. The values of voltage that these conditions canbe expected to produce are shown in Table 2.

440


Load Typical Nominal Peak Number Recommended MOSFET1

Power Current Inrush of lamps Standard FET Logic Level FETCurrent /car SOT186 TO220 SOT186 TO220

headlamp 60 W 5 A 70 A55 W 4.6 A 64 A 2 BUK445-60A BUK455-60A BUK545-60A BUK555-60A45 W 3.8 A 53 A40 W 3.3 A 47 A

spotlight 55 W 4.6 A 64 A 2 BUK445-60A BUK455-60A BUK545-60A BUK555-60A

front fog light 55 W 4.6 A 64 A 2 BUK445-60A BUK455-60A BUK545-60A BUK555-60A

rear fog light 21 W 1.8 A 25 A 2 BUK442-60A BUK452-60A BUK542-60A BUK552-60ABUK443-60A2 BUK453-60A2 BUK543-60A2 BUK553-60A2

front sidelight 5 W 0.4 A 6 A 2 BUK441-60A BUK451-60A BUK541-60A BUK551-60A

rear sidelight 5 W 0.42 A 5.8 A 2 BUK441-60A BUK451-60A BUK541-60A BUK551-60A10 W 0.83 A 12 A 2

brake light 21 W 1.8 A 25 A 2 BUK442-60A BUK452-60A BUK542-60A BUK552-60ABUK443-60A2 BUK453-60A2 BUK543-60A2 BUK553-60A2

direction indicator 21 W 1.8 A 25 A 4 BUK442-60A BUK452-60A BUK542-60A BUK552-60Alight BUK443-60A2 BUK453-60A2 BUK543-60A2 BUK553-60A2

side marker light 3 W 0.25 A 3.5 A 44 W 0.33 A 4.7 A 4 BUK441-60A BUK451-60A BUK541-60A BUK551-60A5 W 0.42 A 5.8 A 4

license plate light 3 W 0.25 A 3.5 A 2 BUK441-60A BUK451-60A BUK541-60A BUK551-60A5 W 0.42 A 5.8 A 1

reversing / 21 W 1.8 A 25 A 2 BUK442-60A BUK452-60A BUK542-60A BUK552-60Abackup light BUK443-60A2 BUK453-60A2 BUK543-60A2 BUK553-60A2

instrument panel 2.2 W 0.18 A 2.5 A 5 BUK441-60A BUK451-60A BUK541-60A BUK551-60Alight

courtesy light 2.2 W 0.18 A 2.5 A 4 BUK441-60A BUK451-60A BUK541-60A BUK551-60A

door light 2.2 W 0.18 A 2.5 A 4 BUK441-60A BUK451-60A BUK541-60A BUK551-60A

boot / bonnet light 2.2 W 0.18 A 2.5 A 4 BUK441-60A BUK451-60A BUK541-60A BUK551-60A

Notes1 These are meant for general guidance only. Specific applications should be checked against individual users’

requirements. In addition to standard and logic level MOSFETs, high and low side TOPFETs might also be considered.2 This device can be used to control two bulbs simultaneously.

TABLE 3 Automotive lamps - characteristics and recommended MOSFET drivers441


Load Typical Nominal Number Recommended MOSFET1

Power Current /car TO220 SOT186(A) CommentsF-pack

screen heater 300-600 W 25-50 A 1 2 x BUK556-60H Devices connected in parallel

seat heater 100-120 W 8-10 A 2 BUK452-60A2 BUK442-60A2

Notes1 These are meant for general guidance only. Specific applications should be checked against individual users’

requirements. In addition to standard MOSFETs, L2FETs, low and high side TOPFETs might also be considered.2 To achieve an on-state voltage drop of <1 V the BUKxx3-60A device should be used.

TABLE 4 Automotive Resistive Loads - characteristics and recommended MOSFET drivers

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The TOPFET

443


5.3.1 An Introduction to the 3 pin TOPFET

The TOPFET (Temperature and Overload ProtectedMOSFET) concept has been developed by PhilipsSemiconductors and is achieved by the addition of a seriesof dedicated on-chip protection circuits to a low voltagepower MOSFET. The resulting device has all theadvantages of a conventional power MOSFET (low RDS(on),logic level or standard gate voltage drive) with the additionalbenefit of integrated protection from hazardous overstressconditions.

TOPFETs are designed for operation in low voltage powerapplications, particularly automotive electronic systems.Theoperation andprotection featuresof the TOPFETrangeof devices also make them suitable for other low voltagepower systems. TOPFETs can be used for all common loadtypes currently controlled by conventional powerMOSFETs.

The first generation of TOPFET devices are summarisedin Table 1.

Protection strategyA functional block diagram and the circuit symbol of the firstgeneration 3-pin TOPFETs are shown in Fig. 1. Thefunctional block diagram indicates that the logic andprotection circuits are supplied directly from the input pin.This places a requirement on the user that the input voltagemust be sufficiently high to ensure that the protectioncircuits are being correctly driven.

The TOPFET includes an internal resistance between theinput pin and the power MOSFET gate. This is required toensure that the protection circuits are supplied even underconditions when the circuits have been activated to turn offthe power MOSFET stage. The value of this resistance hasbeen chosen to be a suitable compromise between therequirements of switching speed and drive capability.

Variants of this configuration with differing input resistorvalues (higher or lower) will be produced to suit differentapplication requirements.

Fig. 1 Schematic diagram and circuit of 3-pin TOPFET

POWER

MOSFET

DRAIN

SOURCE

INPUT

O/V

CLAMP

LOGIC AND

PROTECTION

TOPFET

P

D

S

I

TOPFET Package VDS (V) RDS(ON) (mΩ) at VIS = (V)

BUK100-50GL TO220 50 125 5BUK100-50GS TO220 50 100 10BUK101-50GL TO220 50 60 5BUK101-50GS TO220 50 50 10BUK102-50GL TO220 50 35 5BUK102-50GS TO220 50 28 10

Table 1. 3-pin TOPFET type range

445


Overtemperature protectionTOPFETs include an on-chip protection circuit whichmeasures the absolute temperature of the device. If thechip temperature rises to a dangerous level then theovertemperature protection circuit operates to turn off thepower MOSFET stage. Once tripped, the device remainsprotected until it is reset via the input pin. In the trippedcondition the gate of the power MOSFET stage is pulleddown by the control logic and so some current is drawn bythe input pin of the TOPFET. If the overtemperaturecondition persists after the gate has been reset then theprotection circuit is reactivated.

Short circuit protectionIn the case of short circuit faults the rate of rise oftemperature in a MOSFET switch can be very rapid.Guaranteed protection under this type of condition is bestachieved using the on-chip protection strategy which isimplemented in the TOPFET range of devices. The shortcircuit protection circuit acts rapidly to protect the device ifthe temperature of the TOPFET rises excessively.

The TOPFET does not limit the current in the power circuitunder normal operation. This ensures that the TOPFETdoes not affect the operation of circuits where large inrushcurrents are required. As with the overtemperatureprotection circuit, the short circuit protection circuit turns offthe power MOSFET gate via the control logic and is resetby taking the input pin low.

Overvoltage protection

Transient overvoltage protection is an additional feature ofthe TOPFET range. This is achieved by a combination ofa rugged avalanche breakdown characteristic in thePowerMOS stage and an internal dynamic clamp circuit.Operation is guaranteed by an overvoltage clampingenergyrating for the TOPFET. Overvoltageprotection givesguarantees against fault conditions in the system as wellas the ability for unclamped inductive load turn-off.

ESD protection

The input pin of the TOPFET is protected with an ESDprotection zener. This device protects the PowerMOS gateand the TOPFET circuit from ESD transients. The energyin the ESD pulse is dissipated in the ESD source ratherthan in the TOPFET itself. This input zener diode cannotbe used in the continuous breakdown mode and so is thedetermining factor in setting the maximum allowableTOPFET input voltage.

One feature of the implementation of the protection circuitsused in the first generationTOPFET devices is that the inputcannot be reverse biased with respect to the source. Thismust be adhered to at all times. When the TOPFET is inreverse conduction the protection circuits are not active.

446


5.3.2 An Introduction to the 5 pin TOPFET

The TOPFET (Temperature and Overload ProtectedMOSFET) concept has been developed by PhilipsSemiconductors and is achieved by the addition of a seriesof dedicated on-chip protection circuits to a low voltagepower MOSFET. The resulting device has the advantagesof a conventional power MOSFET (low RDS(on), logic levelgate voltage drive) with the additional benefit of integratedprotection from hazardous overstress conditions.

TOPFETs are designed for operation in low voltage powerapplications, particularly automotive electronic systems.Theoperation andprotection featuresof the TOPFETrangeof devices also make them suitable for other low voltagepower systems. TOPFETs can be used for all common loadtypes currently controlled by conventional powerMOSFETs.

The second generation of TOPFET devices offersenhanced protection and drive capabilities making themsuitable for a wide variety of applications, including thoserequiring fast switching (eg PWM control) or linear control.The circuit diagram for the 5-pin TOPFET types is shownin Fig. 1. The key features of these devices are:

• Overtemperature protection• Short circuit load protection• Overvoltage protection• Full ESD protection• Direct access to the gate of the Power MOSFET.• Flag signal reporting of certain fault conditions• Separate protection circuit supply

The 5-pin TOPFET range is summarised in Table 1.

Overtemperature protectionTOPFETs include an on-chip protection circuit whichmeasures the absolute temperature of the device. If the

chip temperature rises to a dangerous level then theovertemperature protection circuit operates to turn off thepower MOSFET stage. Once tripped the device remainsprotected until it is reset via the protection supply pin.

Fig. 1 Schematic diagram and circuit of 5-pin TOPFET

POWER

MOSFET

DRAIN

SOURCE

INPUT

O/V

CLAMP

LOGIC AND

PROTECTION

PROTECTION SUPPLY

FLAG

D

S

I

TOPFET

PFP

TOPFET Package VDS (V) RDS(ON) (mΩ) at VIS (V) for VPSP > (V)

BUK105-50L SOT263 50 60 5 450 7 4.4

BUK105-50S SOT263 50 60 5 550 7 5.4

Table 1. 5-pin TOPFET type range

447


In the tripped condition the gate of the power MOSFETstage is pulled down by the control logic and so current isdrawn by the input pin of the TOPFET. A minimum valueof external gate drive resistor is specified in order that theprotection circuit can turn off the PowerMOS stage and thusprotect the device. The flag pin gives a logic high output toindicate that a fault has occurred. If the overtemperatureconditionpersists after the protection supply has been resetthen the protection circuit is reactivated.

Short circuit protectionIn the case of short circuit faults the rate of rise oftemperature in a MOSFET switch can be very rapid.Guaranteed protection under this type of condition is bestachieved using the on-chip protection strategy which isimplemented in the TOPFET range of devices. The shortcircuit protection circuit acts rapidly to protect the device ifthe temperature of the TOPFET rises excessively.

The TOPFET does not limit the current in the power circuitunder normal operation. This ensures that the TOPFETdoes not affect the operation of circuits where large inrushcurrents are required. As with the overtemperatureprotection circuit the short circuit protection circuit turns offthe power MOSFET gate via the control logic and providesa flag signal. The TOPFET is reset by taking the protectionsupply pin low.

Overvoltage protection

Transient overvoltage protection is an additional feature ofthe TOPFET range. This is achieved by a combination ofa rugged avalanche breakdown characteristic in thePowerMOS stage and an internal dynamic clamp circuit.

ESD protectionThe input pin, flag pin and protection supply pins of theTOPFET are all protected with ESD protection zeners.These devices protect the PowerMOS gate and theTOPFET circuits from ESD transients. The protectiondevices cannot be used in continuous breakdown.

Protection supply

Anerror condition is recordedand the flagsignal is activatedif the protection supply is absent. Valid protection is onlyguaranteed once the protection supply is in excess of VPSP

(See Table 1).

One feature of the implementation of the protection circuitsused in this generation of TOPFET devices is that the input,flag or protection supply pins cannot be reverse biased withrespect to the source. This must be adhered to at all times.When the TOPFET is in reverse conduction the protectioncircuits are not active.

448


5.3.3 BUK101-50DL - a Microcontroller compatible TOPFET

The TOPFET version BUK101-50DL can be directlycontrolled by the port outputs of standard microcontrollersand other high impedance driver stages. This member ofthe TOPFET family has the same functional features as itspredecessors BUK101-50GS and BUK101-50GL. All theseversions are 3-pin devices for the replacement of PowerMOSFETs or partially protected Power MOSFETs. Theyare internally protected against over temperature, shortcircuit load, overvoltage and electrostatic discharge. Formore information concerning the basic technical concept ofTOPFET see Philips Technical Publication ’TOPFET - ANEW CONCEPT IN PROTECTED MOSFET’. This sectioncovers the special features of the BUK101-50DL version,criteria for driver stage design and application.

Overview on BUK101-50 versionsThe GS, GL and DL versions of the BUK101-50 TOPFETeach have the same functionality but differ in their inputcharacteristics. Table 1 gives an overview on thesecharacteristics.

Type Nominal Normal Latched Max. InputInput Input Input Voltage

Voltage Current Current (V)(V) (mA) (mA)

GS 10 1.0 4.0 11GL 5 0.35 2.0 6DL 5 0.35 0.65 6

Table 1. Comparison of GS, GL and DL versions

Table 1 shows that the GS version (S for Standard type) isspecified for 10V driver outputs while the GL and DLversions (L for Logic Level type) are specified for 5V logiclevel driver outputs. The two logic level types differ in theinput current, IISL, which flows when the device is in its’latched’ state i.e. shutdown has occurred due to overtemperature or short circuit load. The GL version is suitablefor pulsed applications up to 1kHz and needs a push-pulldriver stage while the DL version is optimised for highimpedance drive circuits and can handle pulsedapplications up to 100Hz.

Criteria for choice/design of driver stageFigure 1 shows a simplified circuit diagram for the input ofa 3-pin TOPFET. Also indicated is the high level outputimpedance of the driver stage Rout.

Fig. 1 Diagram of 3-pin TOPFET input

For all versions the internal circuits for over temperatureand short circuit load protection are supplied from the inputpin. This determines the input current IIS under normalconditions, i.e. the Power MOS transistor is on and Toff inFig. 1 is off. To ensure proper function of the protectioncircuits, a minimum input voltage VIS = 4V has to be applied.If, however, the device has turned off due to overtemperature or short circuit load (i.e. transistor Toff in Fig. 1is on), a minimum of VIS = 3.5V is required to keep the devicein its ’latched’ state. Latched means that the device will stayoff even if the error condition has disappeared. Figure 1indicates that under this condition the input current IISL willbe increased due to the additional current that has to besourced into resistor RIG. RIG allows the Power MOS gateto be pulled down internally while the input pin is at highlevel. The typical value of RIG in the GL version is 4kΩ, whilefor the DL version this value has been increased to 30kΩ.Thus the maximum input current has been reduced to allowfor high impedance driver stages such as microcontrollerport outputs.

The criteria stated above result in the followingrequirements on the driver stage output resistance Rout:

PROTECTIONLOGIC AND

DRAIN

SOURCE

INPUT

VCC

VIS

RIG

R

Toff

outTOPFET

Normal: Rout ≤Vcc − 4V

IIS(VIS = 4V)(1)

Latched: Rout ≤Vcc − 3.5V

IIS(VIS = 3.5V)(2)

449


The maximum input currents of the BUK101-50DL arespecified as follows:

IIS,max = 270µA at VIS = 4VIISL,max = 430µA at VIS = 3.5V

Considering a 5V supply, equation (2) leads to a maximumoutput resistance Rout,max = 3.5kΩ.

Fig. 2. Direct control by 80C51 microcontroller

Application example - 80C51microcontroller as TOPFET driverFigure 2 shows an application that takes advantage of thelow input current of the BUK101-50DL. As has been shownabove, the external pull-up resistor Rpull-up in this circuitshould have a maximum value of 3.5kΩ at VCC = 5V for safeoperation of the TOPFET protection circuits. An additionalrequirement is that the TOPFET must be off when the portoutput is at low level. Thus the limited sinking capability of

the port output demands a minimum value for Rpull-up. Forthe 80C51 microcontroller family a maximumoutput voltageof Vout,low = 0.45V is specified at a sink current of 1.6mA forports 1 to 3 and 3.2mA for port 0. This voltage level is safelybelow the minimum turn-on threshold VIS(TO) = 1V of theTOPFET. Considering VCC = 5V and the above specificationof the port output, the minimum value for Rpull-up is:

Thus a value of 3kΩ meets the requirements.

Other applications for the BUK101-50DL

Logic IC as driverBesidesmicrocontroller port outputs the BUK101-50DL canalso be driven by standard 5V logic IC families. Table 2givesan overviewon these families andstates- if necessary- the minimum value for a pull-up resistor.

Family Rpull-up min

TTL 300ΩLSTTL 620ΩSTTL 240Ω

HE4000B no Rpull-up requiredHCMOS no Rpull-up required

ACL no Rpull-up required

Table 2. 5 V logic IC families driving the BUK101-50DL

High Side driverThe low input current of the BUK101-50DL is alsoadvantageous, when using the device as a high side switch.In this configuration the low drive requirements mean thatsmaller capacitors are needed in charge pump or bootstrapcircuits. This subject is described more fully in section 5.3.6.

Rpullup ≥5V − 0.45V

1.6mA= 2.8kΩ

P

VCC

Vbatt

3k

PortOutput

= 5V

80C51 orDerivative

Load

BUK101-50DL

450


5.3.4 Protection with 5 pin TOPFETs

TOPFETs in the 5-pin SOT263 outline extend the range ofapplication of TOPFET to circuits requiring faster switchingor protected linear operation. 3-pin TOPFETs are ideal foruse in DC and low frequency switching applications but theneed to generate the protection supply from the input is alimitation. Providing a separate pin for the protection supplygives the designer freedom to control the input / MOSFETgate in the way he chooses.

This note will look at the organisation of the 5-pin devicesand then discuss some of the more important operationalconsiderations. Application examples will be presented inthe later sections in this chapter.

Functional description

The logic and protection circuits within this device aresimilar to those in the 3-pin TOPFETs but the configurationhas been modified (see Fig. 1) to give greater operationalversatility.

Fig. 1 Elements of a 5-pin TOPFET

These devices use pin 2 of the SOT263 as a flag and pin4 as the supply / reset to the logic and protection circuits.Separating the protection supply from the input has allowedthe internal input gate resistor to be removed. (In a 3-pinTOPFET, this resistor is needed to maintain the protectionsupply during latched fault conditions).

The operation of the protection circuits has not beenchanged. If there is an overvoltage between drain andsource, the overvoltage protection circuit will still try to turn

the MOSFET partially ON. In an overtemperature oroverload situation the TOPFET will turn on the gatepull-down transistor and attempt to turn itself OFF.

The flag indicates when the TOPFET has been tripped byan overtemperature, overload or short circuit condition. Itwill also indicate if the protection supply is absent, forexample during a reset. It should be pointed out that theflag low state does not mean that the protection supply ishigh enough, just that it is present.

The flag is the open drain of a MOS transistor which is OFFto indicate a fault. It is intended that the flag pin is connectedto a 10 kΩ pull-up resistor. This arrangement gives the flaga failsafe characteristic.

Operational considerationsSupplying the protection circuits from their own pin, ratherthan sharing a pin with the MOSFET gate drive, has severalbeneficial effects. One is that it allows the MOSFET gateto be independently controlled without adversely affectingthe protection features. This is particularly useful whenTOPFET is being used as a linear controller.

The removal of the input gate resistor gives the designerthe opportunity of selecting the most appropriate value. Itis important to understand that if TOPFET is to protect itself,it needs to control its gate by overriding the external drivecircuit. It can only do this if the impedance of the driver ishigh enough. The conditions for satisfactory operation aregiven in Table 1.

Minimum driver impedance

Protection level ON drive OFF drive

5 V 10 V input /source

Full self protection 1 kΩ 2 kΩ 100 Ω

Overvoltage 0 Ω 0 Ω 100 Ωprotection only

Overtemperature, 1 kΩ 2 kΩ 0 Ωoverload and short

circuit protection only

Table 1. Driver impedance and protection level

POWER

MOSFET

DRAIN

SOURCE

INPUT

O/V

CLAMP

LOGIC AND

PROTECTION

PROTECTION SUPPLY

FLAG

451


The simplest way of satisfying the self protectionrequirements is to fit a 2 kΩ resistor between the driver andthe input pin. This is simple in a linear controller but maynot be feasible in a switching controller where thisresistance will result in a significant turn OFF delay. Analternative may be to have an ON drive via 2 kΩ and anOFF drive via 100 Ω.

If lower turn ON drive impedance is needed then theapproach would be to use the flag output to control thesignal being fed to the driver circuit. It should be noted thatto have overvoltage protection the turn OFF impedancemust still be > 100 Ω.

The S and L versions differ only in the protection supplyvoltage range. The L types are designed to be suppliedfrom the output of 5 V logic ICs, like the 74HC/HCT families.The S types are intended to be supplied with a nominal 10 Vfrom either HEF4000 type logic, linear ICs (e.g operationalamplifiers) or discrete circuits.

One additional benefit of the independent protection supplyis that, unlike 3-pin L types, the input of a 5-pin L type canbe as high as 11 V, allowing a significantly lower RDS(ON) tobe achieved.

It is important to realise that, at high levels of input voltage,the MOSFET transfer characteristic of both L and S typeswill allow a very high current to flow during shorted loadsituations. This current, flowing through the resistance inthe connectionsbetween the chip’s source metalisation andthe source pad on the pcb, will give a significant volt drop.Since the return for the protection supply will be to the pcbsource bond pad, the volt drop will subtract from theeffective protection supply voltage. To compensate for thiseffect, the minimum protection supply voltage, VPSP, isincreased at high levels of input voltage, VIS. For examplethe minimum VPSP of the BUK105-50L is 4 V if VIS ≤ 5 V. If,however, the input is taken to 7 V, to achieve an RDS(ON) of50 mΩ, VPSP must be ≥ 4.4 V. A curve in data (reproducedas Fig. 2) gives minimum VPSP values for VIS from 0 to 11 V.

Fig. 2 Minimum protection supply for shorted loadprotection

The input, flag and protection supply pins are all protectedagainst the effects of ESD by special diodes between thepin and source. It is important to realise that these devicesare not designed to run in continuous forward or reverseconduction. This means that the continuous voltagebetween these pins and source should be > 0 and < 11 V.

Reverse Battery

There is always a risk that the car’s battery could bereversed. If this happened to a system where a TOPFETis fitted then the TOPFET will survive provided:- the current flowing through the body drain diode is

restricted by the load to a level which does not causethe TOPFET to over dissipate,

- the current flowing out of the input, flag and protectionsupply pins is < 10 mA.

0 2 4 6 8 10VIS / V

VPSP / V BUK105-50L/S

10

8

6

4

2

0

BUK105-50L

BUK105-50Smin

452


5.3.5 Driving TOPFETs

The output of a TOPFET is similar to that of a PowerMOSFET. However, the TOPFET’s protection featuresmake the input characteristics significantly different. As aconsequence,TOPFETs have different drive requirements.This fact sheet describes these requirements and suggestssuitable drivers for the different TOPFET versions.

3-Pin TOPFET

Input requirements3-pin TOPFETs can replace ordinary MOSFETs in manycircuits if the driver can meet certain conditions. The firstof these conditions is the need to keep within the TOPFET’sVIS ratings and in particular to keep the input positive withrespect to the source. The second is the need to providean adequate supply to the protection circuits even when theTOPFET has tripped and the input current is significantlyhigher.

Table 1 summarises these requirements. It gives thelimiting values of VIS, the minimum input voltage for validprotection in normal and latched mode and the normal andlatched input currents for each 3-pin TOPFET.

DriversThe complementary drive arrangement shown in Fig. 1 iswell suited to the input requirements of 3-pin TOPFETs.The transistors shown are the output of a cmos IC gate,which for some TOPFETs may have sufficient drive. If not,a push pull drive with discrete devices should be used.Suitable cmos families are given in Table 1.

The BUK101-50DL has a very low input currentrequirement, achieved by increasing the value of theinternal input resistor - at the expense of a significantincrease in switching times. This means that this device canbe driven from the output port of an 80C51 micro controlleras shown in Fig. 2. Designers should be aware that otherhigh resistance / low current TOPFETs could be producedif they are requested.

5-Pin TOPFET

Input RequirementsThe requirements of a 5-pin TOPFET are somewhatdifferent to that of a 3-pin device. The first major difference

is that both the input and the protection pins need to besupplied. The second difference is that the input resistanceisexternal and is selected by the designer. One requirementwhich remains is the need to keep both the input-sourceand protection-source voltages within the range 0 to 11 V.

The protection pin driver must be able to keep the voltageabove VPSP when supplying the protection current, IPS. Withthe 5-pin device the protection supply is independent, sothe current drawn when TOPFET trips does not change.

Fig. 1 Complementary driver for 3-pin TOPFET

Fig. 2 Micro controller drive for 3-pin TOPFET

P

D

S

I

DL

P

5V

3k

D

S

I80C51

C

453


Input voltage (V) Input Current (mA) Driver

Type limiting value for valid protection

min. max. normal latched normal latched

BUK100-50GS 0 11 5 3.5 1.0 5.0 HEF / DiscreteBUK101-50GS 0 11 5 3.5 1.0 4.0 HEF / DiscreteBUK102-50GS 0 11 5 3.5 1.0 20 Discrete

BUK100-50GL 0 6 4 3.5 0.35 2.0 HC/HCTBUK101-50GL 0 6 4 3.5 0.35 2.0 HC/HCTBUK102-50GL 0 6 4 3.5 0.35 10 Discrete

BUK101-50DL 0 6 4 3.5 0.35 0.65 Micro

Table 1 Input parameters of 3-pin TOPFETs

The input pin requirements depend on the mode ofoperation chosen by the designer. If the TOPFET isexpected to turn itself off, in overtemperature or shortedload situations, then the output impedance of the driveneeds to be > 2 kΩ. This will allow the TOPFET’s internalturn-off transistor to pull the input pin low. If, however, thecircuit uses the TOPFET flag to signal to the driver to turnoff, then driver resistance can be very much lower.

Independent of which method is used for overload turn-off,there is a separate requirement to ensure adequateovervoltage clamping. If this feature is needed then theinput to source resistance of the driver - when it is pullingthe input low - needs to be > 100 Ω. If it is lower, then theTOPFET’s internal clamping drive will be unable to raisethe gate voltage high enough to turn the MOSFET on.

Drives

The drive for the protection pin can, most conveniently, besupplied by a cmos IC gate. A 74HC or HCT for L typedevices or a HEF4000 series device for the S type. Care isneeded however to ensure that the minimum protectionvoltage, VPSP, requirements are still met when the inputvoltage, VIS is high and the load is shorted.

A typical high impedance drive arrangement, which letsTOPFET protect itself against shorted load,overtemperature and overvoltage, is shown in Fig. 3.

One method of creating a fast drive is shown in Fig. 4. Inthis arrangement a NOR gate with a low impedance outputstage drives the input via a 100 Ω resistor. One input of theNOR gate is connected to the flag pin and will be pulledhigh by the 10 kΩ pull-up resistor if the TOPFET indicates

a fault. With one input high, the output of the gate will below turning the TOPFET off. The 100 Ω resistor ensuresthat the overvoltage clamp is still operational.

Fig. 3 Self protection driver circuit

Fig. 4 Fast driver for 5-pin TOPFET

2kP

D

S

I

F

P

D

S

I

F

P

P

1

Vcc

10k

100

454


5.3.6 High Side PWM Lamp Dimmer using TOPFET

Although the 3-pin TOPFETs were designed for low sideswitch applications, they can, by using standard MOSFETbootstrap techniques, be used in applications which needhigh side control. One such application is the dimming ofautomotive headlamps and panel lamps. Theseapplications need not only a high side switch but also slow,controlled switching to reduce problems of EMI.

This note will give details of a circuit which fulfils theoperational requirements of this application and, becauseit uses a TOPFET, is well protected against shorted loadand overvoltage faults.

Circuit DescriptionThe circuit shown in Fig. 1 shows the high side PWMdimmer circuit. All the main components are shown, theonly exception being the source of the PWM control signal.This could be either the system controller or a dedicatedoscillator depending on the nature of the overall system.The circuit of Fig. 1 assumes that the signal is a rectangularpulse train of the required frequency and duty cycle, withan amplitude of 10 V.

The input signal is attenuated by R2 and R3 and fed to thebase of Q1. The combination of R1 and Q1 will invert andlevel shift the signal and feed it to the input of theBUK101-50GS TOPFET.

D1, C1 and the TOPFET form the bootstrap circuit. The lowend of C1 is connected to the TOPFET source. WhenTOPFET is OFF its source is close toground, so C1 chargesto Vbat via D1. When TOPFET turns ON, its source risesto nearly Vbat, lifting the high end of C1 well above Vbat.C1 can, therefore, provide more than enough voltage todrive the TOPFET input. In fact, when Vbat is higher thannormal, the voltage would exceed the continuous VIS ratingof the BUK101-50GS, so D3 is included to restrict the inputvoltage to below 11 V.

Capacitor C2 adds to the Miller capacitance of Q1 and limitsthe rate of change of collector voltage. The TOPFET actslike a source follower circuit, so the load voltage rises andfalls at the same rate as the collector-emitter voltage of Q1.

Fig. 1 High side lamp dimmer circuit

Component Values

With the components specified the circuit will operate at afrequency between 50 and 200 Hz and has rise and falltimes of about 300 µs. This slow switching means that theminimum OFF time, for satisfactory bootstrap operation, isabout 1 ms. At 50 Hz this gives a maximum duty cycle of95%.

The value of C1 has been chosen to ensure that TOPFETinput current does not cause the C1 voltage to fallsignificantly during the maximum ON time. This means thatthe lowest on state dissipation is being achieved. Lowervalues couldbe used but the voltagedroop would be greaterand care would be needed to ensure that the input voltagedoes not fall below the VISP of the TOPFET, otherwise theprotection features may not function.

The rate of switching can be changed by adjusting the valueof C2. Larger values would reduce switching speed.Considerable care is needed when switching times becomevery long because while the input voltage is below the VISP

the TOPFET is unprotected. Switching times can bereduced to about 50 µs by reducing the value of C2 to470 pF. To reduce the switching times further will mean achange to the input drive.

TOPFETBUK101-50GS

Lamps

P

PWM signal(10V peak)

R1

R2

R3

C1

C2

D1

D2 D3

Q1BC337

3n3

47k

10k

10uF

c10

2k2

BAW62

BAW62

100

Vbat

455


Fig. 2 5 V input stage

Switching rate, in particular the turn-off rate, is alsoinfluenced by the amplitude of the input signal. R2 and R3have been chosen to give similar rise and fall times with aninput of 10 V. If the input amplitude is lower the fall timewould increase. This can be compensated for by lowerattenuation. An input modified for 5 V input is shown inFig. 2.This arrangementalso includes D5 toclamp the inputvoltage to 5 V and R4 to allow the use of an open collectoror drain drivers.

Operation in fault conditionsTOPFET will protect itself against high voltage supply linetransients by partially turning on and restricting the appliedvoltage to about 60 V. In high side applications theremainder of high voltage may appear across the load. Inmany systems the grounding and smoothing arrangementswill ensure that this will not be problem. In someconfigurations the TOPFET source will rise above groundwhile the input is held at ground. This means that the

TOPFET input will be negative while its drain-sourcevoltage is high. This may damage the TOPFET. Thisdifficulty can be eliminated by the input circuit shown inFig. 3. In this circuit diode D4 will turn off if the sourcevoltage rises. The input is, therefore, no longer clamped bythe drive and can rise with the source, eliminating the riskof damage.

Fig. 3 Protection against negative input

If the load becomes short circuit, TOPFET will trip as soonas the temperature of the power part of the chip becomestoo high. Since this circuit is a PWM controller the TOPFETwill be reset at the end of the ON period. During the periodbetween tripping and the start of the next cycle the TOPFETwill cool. It will, therefore, turn on when the input goes highagain and the short circuit current will flow until TOPFET istripped once more.

TOPFET is able to withstand this type of operation for aconsiderable period of time but not necessarily indefinitely.The dissipation is considerable, the temperatures could behigh and operating life may be affected. It is advisable,therefore, that short circuit operation is evaluated.

PWM signal R2

R3

C2

Q1BC337

3n3

22k

10k

to Vbat

D5

c5

(5V peak)

R410k

TOPFETBUK101-50GS

P

R1

C1

D2 D3

10uF

c10

2k2

BAW62

D1

BAW62

D4

456


5.3.7 Linear Control with TOPFET

Although the pulse width modulation, PWM, method ofmotor speed control is often preferred over the linearmethod it is not without problems. Some of these are totallyeliminated in linear controllers. However, linear controltechniques have their own limitations. By using a PhilipsTOPFET as the power device some of the disadvantagesare removed giving a fully protected, linear control system.

This note will compare linear and PWM controllers. It willthen give details of a circuit based around a BUK105-50Swhich shows that, with a TOPFET, it is simple to producea fully protected, linear controller for adjusting the speed ofa car heater fan.

Linear and PWM ControlPWM is often selected as the method of controlling thespeed of a brush motor because it is more efficient thanlinear control. The reduction in energy loss results from areduction in the loss in the controlling power device. Theloss is lower because the device is only transiently in thehigh dissipation state of being partially ON. To keep theloss as low as possible, the transition time needs to be keptshort, implying fast switching and high values of dV/dt anddI/dt. It is these fast switching rates which create theelectrical noise that can be such a problem in automotiveapplications.

Linear control does not create this noise because it holdsthe output at a steady value. The power device iscontinuously in the partially ON state and its dissipation ishigh. If, however, this heat can be handled and theinefficiency is acceptable then linear control may be thebetter choice.

Device Selection FactorsIn PWM control, on-state dissipation is the major energyloss, so RDS(ON) is the main selection criterion. In linearcontrol, maximum dissipation occurs when half the supplyvoltage is being dropped across the device. In this stateRDS(ON) is not relevant as dissipation is being controlled bythe load and the supply. The limiting factor in this case isthe need to dissipate the energy and keep the junctiontemperature to a safe value. The selection, therefore, isbased on junction to mounting base and mounting base toheatsink thermal resistance. RDS(ON) cannot be ignored,however, because it sets the residual voltage loss atmaximum speed which can be important.

TOPFET in Linear Control

The circuit shown in Fig. 10. is a linear controller for a carheater fan based around a BUK105-50S. TOPFET is wellsuited to this application because it is a real power devicein a real power package giving it good thermalcharacteristics and low RDS(ON). The 5-pin TOPFET is usedbecause the protection circuits need to be suppliedindependently from the input. The on-chip overtemperatureprotection feature of TOPFET is precisely the protectionstrategy needed in this type of high dissipation application.

Input Pin

In this circuit the input of the TOPFET is connected, via R1and D1, to the output of an operational amplifier. TheTOPFET drain voltage is attenuated by R2/R3 and fed tothe positive input of the amplifier. The negative input isconnected to the wiper of the speed setting potentiometer.This TOPFET/op-amp arrangement creates anon-inverting amplifier with a gain of

In such a low frequency system the presence of R1 at2.2 kΩ will not have a significant effect on normal operation.However, if TOPFET is tripped, its internal gate sourcetransistor will be turned on and, because R1 is greater thanthe 2 kΩ needed for self protection (see RI in the datasheet), the MOSFET gate will be pulled down and theTOPFET will be OFF.

Diode D1 prevents the input of the TOPFET being pullednegative with respect to the source.

Protection Supply

To ensure that the overtemperature and shorted loadprotection circuits work, the protection supply pin needs tobe connected to an adequate supply. To allow TOPFET tobe reset, provision has to be made to switch this so it canfall below the minimum reset voltage, VPSR. Possibly theeasiest way to achieve this is by feeding the protectionsupply from a CMOS gate.

gain =(R2+ R3)

R3

457


Fig. 1 Linear speed controller circuit

TOPFETBUK105-50S

Fan motor

+

-

+

-

+

-

Vbat

100

10k

100k

100k

c10

LED

10k

100k

22k

10k 47n

2k2

47k

10k D4

R1R2

R3

R4

D2

D1

reset

P

P

F

I

D3

Two version of BUK105-50 are available, ’S’ and ’L’. Theydiffer in their protection supply requirements. L devices aredesigned to operate from a nominal 5 V. This makes themcompatible with 5 V logic families like the 74HC and HCTseries. L types can be driven at 10 V but as curves in thedata show the protection characteristics are affected. Onthe other hand, S devices are designed to work with anominal 10 V such as is available from HEF4000 logicgates.

If this circuit were part of a larger system then it is likely thatsuch a gate would be available. In the circuit given here theprotection pin is connected to the output of an op-amp wiredas a non-inverting buffer. The buffer input is pulled up tothe +ve rail with 10 kΩ. The protection supply can be takenlow - to reset the TOPFET - by a pushbutton which groundsthe input of the buffer.

Flag pinIn this circuit the flag pin is connected to a 10 kΩ pull-upresistor, R4. In a more sophisticated system this signalcould then be fed to the input of a logic gate and used toinform the system controller of a fault condition. The

controller could use this information to initiate a resetsequence or perhaps shut down the circuit and record thefact in a maintenance record store.

In this simpler system the flag output feeds the input of anop-amp wired as a comparator which in turn indicates afault by lighting a LED. The output is also fed via D3 to theinput of the speed controller op-amp. This overrides thesignal from the speed adjusting potentiometer and takesthe TOPFET input low. This arrangement has been used -even though the circuit has been designed to allow theTOPFET to self protect - to prevent the TOPFET fromturning back on when there is no protection supply, forexample during reset.

Drain pin

Freewheel diode D4 is needed if the energy stored in themotor inductance exceeds the TOPFET’s non-repetitiveinductive turn-off energy rating at the designed operatingjunction temperature. The overvoltage clamping of theTOPFET is still needed, however, to protect against supplyline transients.

458


5.3.8 PWM Control with TOPFET

Speed control of permanent magnet dc motors is requiredin many automotive and industrial applications, such asblower fan drives. The need for protected load outputs insuch systems can be met by using a TOPFET with itsinherent protection against short circuit, overtemperature,overvoltage and ESD. In section 5.3.7 the two basicmethods for speed control, linear and PWM, are comparedand discussed and a circuit example for linear control isgiven. This section gives an example of a PWM drive circuitusing a 5-pin TOPFET.

Circuit DescriptionThecircuit shown in Fig. 1 contains all the elements neededto produce a PWM circuit which can control the speed of aheater fan motor. The power device, because it is aTOPFET, can survive if the load is partially or completedshorted, if overvoltage transients appear on the supply linesor if the cooling is, or becomes, insufficient.

In a PWM control system the supply to the motor has to beswitched periodically at a frequency significantly above itsmechanical time constant. The net armature voltage andthus the motor speed is controlled by the duty cycle, i.e.on-time/period, of the control signal. With the componentvalues shown, the circuit operates at a frequency of 20kHz.This means that any mechanical noise created by theswitching is ultrasonic. The main building blocks of thecircuit are the PWM generator, the power driver and theinterface between the two.

PWM GeneratorIn Fig. 1, OP1 together with T1 and T2 form a saw-toothgenerator, whose frequency is determined by R1 and C1.OP2 compares the saw-tooth voltage waveform at itsinverting input with the voltage determined by thepotentiometer P1. The output of OP2 is high as long as thesaw-tooth voltage is less than the P1 voltage. As a result,the higher the voltage at P1, the longer the positive pulsewidth and thus the higher the duty cycle of the signal at theoutput of OP2.

Interface PWM Generator - TOPFETThe output signal of OP2 is fed to emitter-followers T4 andT5. These act as a low impedance driver for the input ofthe TOPFET. The drive is needed to achieve the shortswitching times which keep the dynamic switching lossesof the TOPFET below the on-state losses.

Resistor R15 is included between the driver T4/T5 and theTOPFET input to ensure proper function of the TOPFET’sinternal overvoltage protection. This overvoltage protectionis an active clamp circuit that will try to pull up the gate ofthe TOPFET’s power MOSFET (i.e. the input pin) if thedrain-source voltage exceeds 50V. A minimum resistanceof 100Ω between input and ground is needed for the activeclamp to succeed.

If the load is shorted or the TOPFET’s junction temperatureis too high, the internal sensors of the TOPFET will detectit and inform the protection logic which will turn off theinternal flag transistor. The flag pin, which is connected tothe drain of this transistor, will be pulled high by resistorR16. This will turn on transistor T3 pulling the input to thedriver stage, T4/T5, low and hence turning the TOPFET off.

The TOPFET will remain in this state - even if the errorcondition disappears - until a reset is applied. The 5-pinTOPFETs are reset by taking the protection SUPPLY pinbelow VPSR. In this circuit this is done by closing the resetswitch, pulling the protection pin to ground. In this statethere is no protection supply so the TOPFET is unprotected.However, the TOPFET indicates the absence of aprotection supply by the flag transistor remaining off. In thiscircuit this causes the drive to the TOPFET to be low hencethe TOPFET will stay off. The TOPFET will resume normaloperation when the reset switch is opened and theprotection supply is re-established.

Power Stage

In this circuit, the main power switch is a BUK105-50L whichhas an RDS(ON) of 60 mΩ @ VIS = 5 V. The L version of theBUK105 has been chosen so that the protection supply canbe fed from the available 5 V supply. The maximumprotection supply current, IPS, is 350 µA, the voltage dropacross R17 could be 0.42 V. Even if the voltage is regulatedas low as 4.5 V, the protection supply will still be > 4 V, theminimum VPSP for valid protection with a VIS of 5 V.

If a lower RDS(ON) were needed this could be achieved bymodifying the circuit to give a higher VIS on the TOPFET.A VIS = 7 V would give an RDS(ON) = 50 mΩ. An input voltageas high as 10 V could be used but any increase must beaccompanied by an increase in the protection supplyvoltage. A curve showing the required VPSP for the full rangeof input voltage is given in the data sheet.

459


The given circuit can be used in both 12V and 24V systemsbecause, with an input voltage of 5V, the TOPFET is shortcircuit protected up to a supply voltage of 35V. However, ifa supply this high is expected then the dissipation andvoltage rating of the regulator would need to be studied.

D1 is a freewheel diode across the motor load which mustbe present even though the TOPFET has an internal clampcircuit. This is because the dissipation resulting from

repetitively clamping at 20 kHz is very high, much higherthan any power switch of this size would be able to handle.R18/C4 are optional devices that slow down switching,reducing dV/dt and hence RF noise emission.

Capacitor C5 helps to decouple the circuit from the supplyand prevents excessive dI/dt on the power lines and theexcessive voltage spikes it would produce.

Fig. 1. PWM Control Circuit using TOPFET

10nC1

54822k BCR3 T1

54822BCR4

1k2R5

OP1+

-

6k8R1

33kR2 R6 R10

8k2 12k

R76k8

T2

R86k8

P110k

548BCT3

558BCT5

OP2+

-548BC

OP1,OP2: LM 393

T4

1kR11

LM78L05

C2 C322u 1u5

R1610k R17

1k2

R15100

R128k2

RESET

470pC4

63V1000uC5

47R18

28BYV

D1

10R17

TOPFETBUK105-

50L

M

Vbat

P

PF

I

D

S

460


5.3.9 Isolated Drive for TOPFET

An isolated drive for a power transistor is required if anelectronic replacement of an electromechanical relay is tobe realised. By using a TOPFET, with its integratedprotection functions, in combination with an isolated inputdrive, the following advantages over an electromechanicalrelay can be achieved:

o Permanent short circuit protectiono Over temperature protectiono Active clamping at inductive turn-offo Logic level controlo Higher switching frequency

This section presents a complete circuit example of atransformer isolated drive. It also discusses other isolationtechniques particularly in relation to meeting TOPFET’sspecific requirements.

Basic Methods for Isolated INPUT Drives

Opto-Isolated DrivesFor this method a light emitter (e.g. LED or lamp) and aphoto-device is needed. The latter can be subdivided intotwo groups:

Photo Resistors/TransistorsWith these devices a ’switch’ can be built to control the inputvoltage of a TOPFET. They cannot provide the powerneeded to drive the input so a separate supply is needed.In low side configurations this can be the main supplydirectly. In high side configurations an input voltage abovemain supply level is needed which could be generated bya charge pump. However, the supply connection neededfor this type of opto-isolated drive is not needed with anelectromechanical relay. So an opto-isolated drive withphoto resistors/transistors cannot serve as a universal relayreplacement.

Photo CellsThe drive energy from a control pin can be transferred tothe input pin of a power device by means of photo cells.This would eliminate the need for the additional supplyconnection. Integrated devices exist that combine an LEDand a chain of photo-cells. They are designed to driveordinary power MOSFETs so their output current, due tothe low efficiency of the photo-cells, is only a few µA. Thisis not enough to supply the protection circuits of a TOPFETso this method cannot be used to provide isolated drive fora TOPFET.

Transformer Isolated Drives

As with photo-cells, pulse transformers provide a means oftransferring energy from the control pin to the input of thepower device. However, the transfer efficiency of a pulsetransformer is much higher, so the protection circuits of aTOPFET can be supplied satisfactorily.

Extremely small pulse transformers are now available, andsomeoutlines are suitable for surface mount. It is, therefore,realistic and practical to use this method to create a relayreplacement for high and low side configurations.

Circuit Description

Figure 1 shows a transformer-isolated drive circuit forTOPFET. As discussed above, a TOPFET in combinationwith this drive circuit can be employed either in high sideor low side configuration without modifications on the driverside. The drive signal on the transformer’s primary side isapulse train that is rectifiedon the secondaryside toprovideacontinuous inputvoltage VIS for the TOPFET.For the givendimensioning, a pulse rate in the range of 100kHz is wellsuited. A high pulse rate is advantageous as it allows thedimensions of the transformer and smoothing capacitor,C2, to be minimised.

On the primary side, a voltage is applied to the transformerwhen T1 is on. The positive pulse amplitude is limited byD7 on the secondary side. The drain current of T1 and thetransformer current are limited by R1.

Duringthe offperiod of T1, the transformer’sprimary currentfreewheels through D1 and D2. Thus the absolutemaximum value for the negative pulse amplitude on theprimary winding is equal to the sum of breakdown voltageof zener diode D2 and forward diode drop across D1. At aduty cycle of 50%, this value should be at least as high asthe positive pulseamplitude. This allows the primary currentto reach zero and thus the magnetic flux in the core to bereset while T1 is off. The maximum off-state drain-sourcevoltage of T1 occurs if the secondary winding of thetransformer is left open. It is the sum of supply voltage VP,zener voltage of D2 and forward voltage drop across D1.

461


Fig. 1 Transformer-Isolated Drive Circuit for TOPFET

Using a bridge rectifier on the secondary side makes useof both positive and negative pulses to generate theinput-to-source voltage VIS for driving the TOPFET. Thisincreases the efficiency. It also reduces the ripple on VIS,therefore the ripple on the load current and hence theelectromagnetic noise emission.

Theminimum value for VIS is setby the need to have enoughvoltage for correct operation of the TOPFET’s overloadprotection circuits. The maximum is determined by thebreakdown voltage of the ESD protection diode at the inputpin. Taking this into account, VIS should be within the rangeof 4V-6V in the case of the TOPFET type BUK101-50GL.In the given circuit the lower limit of VIS is determined by

the minimum supply voltage VP on the primary side, thetransformer ratio, and the diode voltage drops at the bridgerectifier. Zener diode D7 ensures that VIS cannot exceedthe upper voltage limit.

The time constant of R2 and smoothing capacitor C2determine the fall time of VIS after the control input at theprimary side goes low. A fall time significantly longer thanthat chosen here should be avoided for the followingreason.

After a TOPFET has turned off to protect itself, it is latchedoff so it stays in the off-state as long as VIS is high. To resetthe TOPFET, VIS must go low. In this circuit this happenswhen the control input at the primary side goes low,disconnecting the drive pulses from the gate of T1. On thesecondary side, this allows C2 to be discharged by R2 andhence VIS to decrease. When VIS has fallen below theprotection reset voltage level VISR, the fault latch will resetand an internal transistor, which holds the gate low, will turnoff. The gate voltage will now rise to the C2 voltage and theTOPFET’s output MOSFET will conduct again. TheMOSFET will be fully off when VIS falls below the TOPFETthreshold voltage VIS(TO). In the range between VISR andVIS(TO) (max. 3.5V-1V for the BUK101-50GL) the outputMOSFET may conduct while the protection circuits arenon-active. For safe reset of a latched TOPFET with ashorted load, this VIS-range must be passed through withina limited time interval. With the dimensioning of R2 and C2shown in Fig. 1, this time interval is approximately 130 µs.The BUK101-50GL is guaranteed to withstand a hard shortcircuit for > 300 µs at a battery voltage of 35V and VIS=5V.So the chosen values of R2 and C2 ensure safe turn-off ofthe TOPFET.

P

D75V1

R25k6

C210n

&100kHz

ControlInput

R31k

T1

BST72A

D11N4148

D215v

VP

D3...D64x1N4148

TOPFETBUK101-50GL

R1

240

Pulse Transformere.g. PE5163X

462


5.3.10 3 pin and 5 pin TOPFET Leadforms

The TOPFET (Temperature and Overload ProtectedMOSFET) range of devices from Philips Semiconductorsis based on conventional vertical power MOSFETtechnology with the advantages of on-chip protectioncircuitry. Using this approach the devices are able toachieve the very low values of RDS(on) which are requiredin applications for automotive and other power circuits.TOPFET devices are currently available in two topologiesfor maximum compatibility with the requirements of circuitdesigners.

3-pin TOPFETs Rthj-mb 5-pin TOPFETs Rthj-mb

TO220 (K/W) SOT263 (K/W)

BUK100-50GL 3.1 BUK104-50L 3.1BUK100-50GS 3.1 BUK104-50S 3.1BUK101-50GL 1.67 BUK105-50L 1.67BUK101-50GS 1.67 BUK105-50S 1.67BUK102-50GL 1.0 BUK106-50L 1.0BUK102-50GS 1.0 BUK106-50S 1.0

Table 1. 3-pin and 5-pin TOPFET type ranges

Fig. 1 TO220AB

The 3-pin TOPFETs are assembled in the standardTO220-AB package (Fig. 1), which is also sometimesknown as SOT78. The 5-pin versions are assembled in theSOT263 PENTAWATT package (Fig. 2). Depending uponthe load and the application the devices can be operatedin free air or attached to a heatsink. When using a heatsinkthe advantage of these outlines lies in the very low thermalimpedance which can be achieved. Table 1 shows thethermal resistances for the range of TOPFET devices.

Although these outlines are industry standards, onoccasions users have the need to form the leads of thedevices to accommodate a variety of assemblyrequirements. Philips Semiconductors can offer a numberof standard pre-formed leadbend options to make thepurchase and specification of leadformed devices easier.

These pre-forms satisfy the basic rules concerning thebending and forming of copper leads and ensure that, forexample, the bend radius is not less than the thickness ofthe lead and that there is sufficient material at the base ofthe plastic moulding to enable the act of pre-forming to takeplace without damage to the crystal or its die attach andwire-bonding.

Fig. 2 SOT263

Figure 3 shows leadform option L02 for a TO220 type. Adevice with this standard leadbend can be ordered byspecifying /L02 as the suffix for the device type. Forexample, a BUK101-50GL with this leadbend is specifiedby ordering type BUK101-50GL/L02.

In addition to this, there is often the necessity to crop thetab off the device to make a low profile version, when heightabove the pcb is restricted. Again, without control, there isa risk of fracturing the crystal during this process but PhilipsSemiconductors can offer this option (SOT226), shown inFig. 4, which can be ordered by specifying the suffix /CRto the device type number, eg. BUK102-50GS/CR.

For surface mountable TOPFETs, the leadbend option L06means that the device can be used in applications wherea low profile is required. With this option an electrical contact

10.3max

3.6

2.8

2.4

0.6

4.5 min

5.9min

15.8max

1.3

13.5min

1.7

(4 x)0.9 max

(5 x)

2.4max

0.6min (4 x)

10,3max

3,7

2,8

5,1

1,3 max (2x)

2,4

0,6

4,5 min

5,9min

15,8max

1,3

2,54 2,54

0,9 max (3x)

13,5min

463


from the pcb to the tab of the device is possible. The deviceis shown in Fig. 5 and, for the BUK100-50GS would bespecified as the BUK-100-50GS/CRL06.

For the 5-pin TOPFETthe device is available in the leadbentSOT263 outline as standard (Fig. 6). For the leadformoption the device type number is modified by the additionof the suffix P to the SOT263 type name, eg BUK104-50L(SOT263) becomes BUK104-50LP (leadbent SOT263).

Fig. 3 TO220, L02 leadbend

Fig. 4 SOT226

Fig. 5 SOT226, L06 leadbend

Fig. 6 SOT263, leadbend

Bend radius 0.5

+ -0.

125

0.1

25 3.4 0.2+-

1.3 0.2

0.72 0.15 FLAT

+-

+-

1.3

1.3 MIN. TINNED

30o

2.54 +- 0.312 0.5+-

2.5 +- 0.3 Bend radius 1.0

10.3max

3.6

2.8

2.40.6

4.5 min

5.9min

15.8max

1.3

1.7

(4 x)0.9 max

(5 x)

2.4max

0.6min (4 x)

8.2

4.5

9.755.6

5

All radii >0.5

12.7 min

1.3

464


5.3.11 TOPFET Input Voltage

Low side TOPFET data sheets specify that the voltagebetween the input and source pins should not be less than0 V, in other words should not go negative. In manycircumstances, sound layout using normal logic gates willensure that this condition is always satisfied. However, insome situations it is difficult to design a circuit in which thiscondition is met under all conditions. This section explainsthe reason for the quoted rating and shows that it is a limitin only a few circumstances. The paper will also illustratehow negative inputs can be generated. Section 5.1.12shows how negative inputs can be prevented andrecommends a simple method of stopping a TOPFET beingdamaged if negative inputs do occur.

Reason for specification limitAll the pins of a low side TOPFET are protected againstESD. The input pin - the most sensitive pin of a normalMOSFET - is protected by a special diode connectedbetween the input and the source. In the presence of anESD pulse, this diode conducts and clamps the voltage onthe input pin to a safe level.

The diode is formed by an area of n++ in a p+ region whichis diffused into the n- epi layer, see Fig. 1. The input pin isconnected to the n++ region and then to the rest of thecircuits. The p+ region is connected by the metalisation tothe source area of the power MOSFET part of the TOPFET.However, the p+ region also connects to the n- epi layerand hence to the drain via the n+ substrate. The ESD diodeis formed by the n++ / p+ junction. However, the n++ andp+ diffusions in the n- epi also create a parasitic npntransistor. It is the presence of this transistor which makesthe negative input rating necessary.

Fig. 1 Cross section of TOPFET ESD diode

With an input potential lower than the source potential, theinput acts as an emitter, the drain as a collector and thesource as a base, so the potential difference will act as biasfor the parasitic transistor. The diffusion concentrationsused to create a good ESD protection diode create atransistor with a limited forward SOA. The characteristicsof the transistor mean that it can be damaged if its VCE isgreater than 30 V when its base is forward biased. For theTOPFET this means that damage could be caused only ifthe input goes negative while the drain voltage is > 30 V.

It should be noted that the conditions which may damagethe transistor assume the impedance of the bias supply islow. If the bias is restricted the limits of SOA are differentso the drain voltage needed for damage will be different. Inany event at drain voltages < 30 V, a negative input willcause the parasitic transistor to conduct but will not causedamage.

Conditions creating negative input

The most obvious effect of the minimum VIS is to precludethe use of negative drive to speed up turn off. However, thistechnique is only justifiable in very high frequency circuitsand TOPFET is intended for use in DC or low frequencyapplications, so it is unlikely that this type of drive will beunder consideration. The typical TOPFET driver stage willbe unipolar using gates or discrete transistors from positivesupply rails only. These drivers will turn the TOPFET offeither by removing the drive and allowing TOPFET to turnitself off, via its internal pull down resistor, or by pulling theinput to zero volts. It would appear, therefore, that negativeinputs should not occur, but in some situations and withsome circuit configurations they can.

High side circuits

A negative input can be created if an overvoltage transientis applied to an off-state TOPFET being used as a high sideswitch. A TOPFET will start to conduct if a supply linevoltage transient exceeds its clamping voltage. The currentnow flowing through the TOPFET will also flow through thelow side load, raising the source potential above ground.The driver stage may be designed to turn the TOPFET offby pulling the input to ground as in Fig. 2. If it is, then theconditions for harmful negative input have been created -the drain voltage is > 30 V, the input is at ground and thesource potential is higher, so the input is negative.

n+ substrate

n- epi

p+

to sourcefrom input pin

to other circuits

ESD diodeanode of

ESD diode cathode of

p++ p++n++

465


Fig. 2 Driver taking input to ground - high side

Low side circuits

Insome circumstances it is possible to createnegative inputin a low side configuration. In the previous example it wasa small current in relatively large resistance that raised thesource above ground. The same effect can be created bya large current in the low, but not negligible, resistance ofthe wiring between the source pin and ground.

Systems are often configured with separate power andsignal grounds and it is possible that the driver will bereferenced to signal ground, see Fig. 3. In this case theTOPFET input will be pulled to signal ground potential whenit is being turned off. The source will be connected to powerground and the common connection between the grounds

may a considerable distance from the TOPFET. Theresistance of the wiring will be low but even 20 mΩ may besignificant if the current is high.

Fig. 3 Low side switch - separate grounds

There are two occasions whena large enough current couldbe flowing. The first is during the turn-on of a load with ahigh inrush current, for example a cold incandescent lamp.The second is when the load is shorted out. If the TOPFETturns off while this current is flowing, the energy in theinductance of the wiring from the load to the TOPFET drainwould raise the drain voltage, possibly to greater than 30 V.The high current, as high as 60 A, in the source to groundwiring, say 20 mΩ, would raise the source 1.2 V aboveground. So, the combination of conditions which maydamage a TOPFET have been created.

The circuits and circumstances mentioned in this paper areonly examples and other hazardous negative inputsituations will exist. Methods of preventing negative inputand of stopping a TOPFET being damaged, if negativeinputs do occur, is presented in section 5.1.12.

Vbatt

LOAD

TOPFETVbatt

LOADVCC

TOPFET

powerground

signalground

466


5.3.12 Negative Input and TOPFET

Low side TOPFET data sheets specify that the voltagebetween the input and source pins should not be less than0 V, ie. should not go negative. This limit is needed toprevent the parasitic transistor, formed by the input ESDprotection diode in the n- epi, being damaged in somecircumstances. The reason for the limit and the causes ofpotentially damaging conditions are discussed more fullyin section 5.3.11. This section will show how damagingnegative inputs can be prevented and recommend a simplemethod of stopping low side TOPFETs being damaged ifnegative inputs do occur.

Fig. 1 High side driver taking input to source

Avoiding negative inputSection 5.3.11 gave examples of high and low side driveconfigurations which could, in some circumstances,generate a potentially damaging negative input. There aretwo ways to prevent the input from being taken too low. Thefirst is to fit a diode in series with the input pin. The cathodeof the diode would be connected to the TOPFET. The diodewould conduct while the driver output was high but wouldturn off and isolate the input pin when the driver tried to pullthe input low. The driver would now not be driving theTOPFET off but would be allowing it to turn itself off via itsinternal input - source resistor.

The second method is to arrange the drive so that it turnsthe TOPFET off by pulling the input to the source ratherthan to ground. The circuit shown in Fig. 1 shows a highside drive in which this has been achieved. The TOPFETis turned off by a pnp transistor being turned on and pullingthe input to the source.

Fig. 2 Low side driver taking input to source

Figure 2 shows a low side drive where the GND pin of thecmosgate is connected as close as possible to the TOPFETsource pin. Once more the effect is to turn off the TOPFETby pulling the input to source.

If negative inputs cannot be avoided

The technique of referencing drivers to the source pin helpsprevent negative inputs being generated. It is used in mostpower MOSFET switching situations and should be usedwith TOPFET wherever possible. If negative inputs cannotbe eliminated there are ways of preventing them fromcausing damage to a TOPFET.

Although published data gives 0 V as the lower limit of VIS,lower values can be acceptable. The VIS limit of 0 V ensuresthat the SOA of the parasitic transistor associated with theESD diode is never exceeded. The arrangement shown inFig. 3. can be used to ensure this. This shows the parasiticnpn transistor of the TOPFET and two additionalanti-parallel diodes in series with the input.

Vbatt

LOADVCC

TOPFET

Vbatt

LOAD

TOPFET

467


Fig. 3 Equivalent circuit of protected TOPFET input

If the drive voltage goes negative, the diode D1 (see fig. 3)is reverse biased and diodes D2 and D3 are forward biased.The voltage between Source and point A is limited by D3and the current is limited by R. This voltage is dividedbetweenD2 and the base-emitter junction of the ESD diode.The current flowing through the ESD diode’s base-emitterjunction is therefore negligible and so the SOA of thistransistor is not exceeded. This means that all theconditions needed to damage the device can be avoidedand the TOPFET is protected against negative input.

Fig. 4 High side drive with series anti-parallel diodes

In the normal on state, D1 will be forward biased but it willcreate a voltage drop of about 0.5 V between point A andthe TOPFET input. To enable a 3 pin TOPFET to protectitself, its input must be >4.0 V so the designer needs toensure that the voltage at A is >4.5 V.

During a normal turn-off the gate discharge current will flowthrough the forward biased D2. No special measures areneeded to cope with D2’s voltage drop because 0.5 V iswell below the TOPFET’s threshold voltage so it will beproperly turned off if point A is taken to 0 V.

Fig. 5 Low side drive with series anti-parallel diodes

Figure 4 shows the high side drive of Fig. 1 modified toinclude the series anti-parallel diodes, D1 and D2. D3 isalready present in the formof the input voltage limitingzenerso the only extra components are the series anti-paralleldiodes. A modified low side drive is shown in Fig. 5. HereD1 and D2 are fitted between the output of a cmos gateand the TOPFET input pin. In this circuit, diode limiting isprovided by the bipolar parasitic diode inherent in cmosoutput stages.

Series resistor values

The recommended minimum resistor values are,

Types Over-voltage Minimum seriestransient resistor

3-Pin < 200 V for 2 ms 50 Ω

3-Pin < 300 V for 2 ms 300 Ω

5-Pin < 100 V for 2 ms 200 Ω

5-Pin < 200 V for 2 ms 1000 Ω

5-Pin < 300 V for 2 ms 2000 Ω

If the negative voltage between point A and the source ispresent for a longer period of time than 2 ms then a largervalue of series resistor may be required.

INPUT DRAIN

SOURCE

A

ESDdiodeD1

D2

D3

R

Vbatt

TOPFET

LOADVCC

D1

D2

R

Vbatt

TOPFET

LOAD

D1

D2D3

R

468


5.3.13 Switching Inductive Loads with TOPFET

If there is current flowing in the coil of a solenoid or a relaythen there is energy stored in the inductance. At turn-offthis energy has to be removed from the coil and dissipatedsomewhere. During this process, an extremely high voltagewill be generated unless measures are taken to limit it. Thisvoltage can lead to breakdown and, beyond a certainenergy level, damage to the switching transistor. Commonmethods of controlling this voltage are a freewheel diodein parallel with the inductor or a suppressor diode in parallelwith the switching transistor.

A TOPFET with its overvoltage clamping feature can savethese extra elements, provided that its limiting values arenot exceeded during the turn-off procedure. This sectionshows a simplified method of estimating the dissipatedenergy and the junction temperature rise in a TOPFET atinductive turn-off. The equations given here are first orderapproximations. They act as an aid in determining the needfor an external freewheel or suppressor element.

Fig. 1 TOPFET. Switching an inductive load

TOPFET behaviour

Figure 1 shows an equivalent circuit diagram and theshapes of drain current ID and drain-source voltage VDS

versus time for a TOPFET switching an inductor. Theovervoltage clamp feature of TOPFET is represented by azener diode that drives the output power MOSFET intoconduction if VDS rises too high. In this state the TOPFETacts as an active clamp element, limiting its own VDS totypically 60V.

Saving of external overvoltage protectionThe TOPFET clamp feature is the only voltage limitingrequired if the energy associated with turn-off, Eclamp, doesnot increase the TOPFET’s junction temperature too far.The following section shows how to estimate Eclamp. Limitingvalues for the energies EDSM for non-repetitive clamping andEDRM for repetitive clamping are stated in the data sheet.EDSM relates to a peak junction temperature of 225˚Creached during clamping which is acceptable if it occursonly a few times in the lifetime of a device. Thus EDSM shouldonly be used when deciding on the necessity for externalprotection against overvoltage transients that occurextremely rarely.

However, when switching inductive loads, absorbing Eclamp

is a normal condition. So to achieve the best longtermreliability, the peak junction temperature should not exceed150˚C. A method for estimating the peak junctiontemperature is given later.

In this type of repetitive clamping application, the EDRM ratingin the data sheet can be compared with Eclamp to give aninitial indication of need for external voltage limiting. Thisinitial assessment should be followed by a temperaturecalculation to find the maximum allowable mounting basetemperature and thus the heatsink requirements.

Estimation of clamping energyThe energy stored in the coil of a solenoid valve or a relaywith the inductance L at a current I is:

The clamping energy Eclamp in the TOPFET during aninductive turn-off follows from equation (1) and the fact that,during clamping, the battery also delivers energy to theTOPFET:

In (2) ID0 is the drain current at start of turn-off, V(CL)DSS theTOPFET’s typical drain-source clamping voltage, Vbat thebattery voltage and L the load inductance. Equation (2)assumes an inductor with no resistance. In practice, therewill be some resistance, which will dissipate a fraction ofEclamp. Therefore, (2) represents a worst case situation.

0

0

ID0

V(CL)DSS

V bat

Input

Drain

Source

EquivalentTOPFET Drain-Source Voltage

TOPFET Drain Current

Figure 1a Figure 1b

to TOPFETat turn-off

EL =12

L I 2 (1)

Eclamp =12

L ID02 V(CL)DSS

V(CL)DSS-Vbat

(2)

469


Estimation of junction temperatureThe peak junction temperature during clamping can beestimated by adding the maximum temperature rise ∆Tj tothe average junction temperature, Tj0.

Measurements have shown that ∆Tj can be approximatedby

Where Zth is the transient thermal impedance for a pulse

width of of the time in clamping, which, for a coil resistance

of zero Ohms, is:

Average dissipation will make Tj0 higher than the mountingbase temperature Tmb, which can be assumed as constant,if the TOPFET is mounted on a heatsink. In repetitiveswitching applications, both on-state losses and turn-offlosses contribute to the average dissipation. So Tj0 will be:

In (6) IRMS is the root mean square value of the load currentand RDS(ON) is the on-state resistance of the TOPFET. Innon repetitive applications, the average dissipation is theon state dissipation so Tj0 is:

If these calculations indicate that the peak junctiontemperature is less than Tj max, then external voltage limitingis not needed.

Calculation examples

Both examples are carried out for Vbat=13 V and aBUK101-50GS with a clamping voltage of 60 V. Forcalculation of on-state losses, the maximum RDS(ON) atTj=150˚C of 87.5 mΩ is taken.

Example 1: An inductor with L=10 mH is switched off

non-repetitively at a dc current ID0=7 A.

(5) gives = 1.5 ms. The BUK101 data curve indicates

a Zth of about 0.28 K/W at tclamp/3 = 500 µs. (4) then givesa of about 100 K. It is a non repetitive application so

use (7) to find Tj0, which indicates that Tj is about 7˚C aboveTmb due to on-state losses. From the and Tj0 figures it

can be inferred:Tj,pk < 150˚C for Tmb < (150-100-7)˚C = 43˚C.

Example 2: An inductor with L=3 mH is switched at

ID0=4 A and a frequency of 100Hz and a duty cycle of 0.5.

(2) yields a clamp energy of 31 mJ, which is less than theEDRM rating of the BUK101 of 40 mJ so repetitive clampingis allowed. (6) yields that Tj0 will be about 8 K above Tmb.From (4) and (5), can be estimated to be < 30 K. These

figures imply that this load can be safely driven if the Tmb ofthe BUK101-50GS is < 112˚C.

Tj , pk = Tj0 + ∆Tj (3)

∆Tj =56

V(CL)DSS⋅ ID0 ⋅ Zth (4)

1

3tclamp

tclamp =L ⋅ ID0

V(CL)DSS− Vbat

(5)∆Tj

∆Tj

Tj0 = Tmb + Eclamp ⋅ f + IRMS

2 ⋅ RDS(ON) ⋅ Rth, j − mb (6)

∆Tj

Tj0 = Tmb + ID02 ⋅ RDS(ON) ⋅ Rth, j − mb (7)

470


5.3.14 Driving DC Motors with TOPFET

Examples for motor drive circuits using low side TOPFEThave already been given in section 5.3.7: "Linear Controlwith TOPFET", and section 5.3.8: "PWM Control withTOPFET". This section discusses the characteristics of DCmotors that have to be considered when designing a drivecircuit with low side TOPFET and gives examples of somebasic drive circuits.

Important motor characteristicsThe permanent magnet motor is the most common type ofmotor for driving a wide range of applications includingsmall industrial drives, cooling fans and model cars.Therefore, the following discussions are based on this type.The equivalent circuit of these motors is shown in Fig. 1,where RA and LA represent the resistance and inductanceof the armature.

Fig. 1 Equivalent circuit for PM DC motor

Inrush currentCorrect operation of some mechanical loads creates aspecial starting torque requirement for the motor. Sincemotor torque is proportional to motor current, high startingtorque can only be achieved if the inrush current is allowedto be high. The TOPFETs BUK100...BUK106 do not usecurrent limiting techniques to provide overload protection,so the inrush current they can deliver to a motor is limitedonly by the forward transconductance gfs. To meet extremestarting torque requirements, an ’S’type with 10 V controlis to be preferred over an ’L’ type with 5 V control because’S’ types can deliver approximately twice the current of ’L’types. Typical currents can be judged from the data sheetID(SC) in the section TRANSFER CHARACTERISTICS.

Stall currentThe stall current of a dc motor is limited by the armatureresistance, RA in Fig. 1, and can reach values of 5-8 times

the nominal current. This current will cause overheating inthe motor which may damage the winding insulation ordemagnetize the stator magnets.

The current would also cause extra dissipation in the driverbut a TOPFET, with its over temperature protection, wouldsurvive a permanent stall condition. In addition, with carefulthermal design, the TOPFET can also be used to preventdamage to the motor.

Inductive kick back at turn-offThe energy stored in the armature inductance, LA, has tobe removed when the motor is turning off. As in the caseof inductive loads such as solenoid valves and relay coils,this is usually done by a freewheel diode. Provided that theenergy is within its EDRM rating, a TOPFET’s overvoltageprotection feature can be used insteadof a freewheel diode.Section 5.3.13: "Switching Inductive Loads with TOPFET",covers this topic in more detail and gives a simplecalculation method to assess the need for a freewheeldiode. If overtemperature shutdown due to a stalled motorcan occur, a freewheel diode is generally recommended.Without freewheel diode the TOPFET would have to absorba very high energy at a junction temperature of at least150 ˚C.

In the case of pulsed operation of the motor (e.g. pulsewidth modulation for speed control), the use of a freewheeldiode is advisable. Without it, motor current ripple would behigher and the loss in the switching device could be as highas it would be in a linear control circuit.

Special effects of back EMF

Effects at running outThebackEMF, EA, of amotor is proportional to the rotationalspeed. When the TOPFET is turned off, the motor acts asa generator and EA can serve as the feedback signal in aPWM control system.

Although the back EMF voltage of many motors is, duringnormal running, below its terminal voltage, in somesituations and with some motors the peak back EMF canexceed the terminal voltage. Shortly after turn-off theseEMF peaks may even exceed the battery voltage plus onediode drop. In this case the EMF can supply current intothe battery circuit by forward biasing the TOPFET’sSource-Drain diode (see Fig. 2a). As a result of the internalstructure of a low side TOPFET, the Source-Drain diodecurrent will create a conduction path from the Input to theDrain. The current through this path can be limited to a safe

R AL A

E A V M

I A

471


value by including a series resistance Ri as shown inFig. 2a. Recommended values for Ri are 100Ω for 5Vdrivers and 220Ω for drivers above 6V.

For 5 pin TOPFETs a path is also created from theProtection Supply and Flag pins. In this case, sufficientcurrent limiting is often provided by the resistors that arefitted to connect the Flag and Protection Supply pins to Vcc(see Fig. 2c). The actual resistor values must bedetermined from consideration of the TOPFET and controlcircuit data sheets.

Effects of intermittent short circuit

When a TOPFET’s short circuit protection has tripped dueto a short circuited motor, the motor will continue to turn. Inthis situation the motor acts as a generator and its currentis reversed. The motor will lose rotational energy and, if theshort circuit remains long enough, will stop. In practicehowever, contact sparking can cause intermittent shortcircuits. In this case the short circuit may be interruptedbefore the motor has stopped. After the interruption thegenerator current will continue to flow, forced by thearmature inductance LA. A path for this negative current intothe battery is provided via TOPFET’s Source-Drain diode.As described in the above section, currents into Input,Protection Supply and Flag terminals should then be limitedby means of series resistances.

Besides this, TOPFET’s internal circuits are non-activewhile its Source-Drain diode is forward biased and aprevious overload shutdown will not stay latched. As aconsequence, a TOPFET that has turned off due to a shortcircuit across its motor load may turn on again if the short

circuit opens before the motor has stopped. This behaviourwill not damage the TOPFET. However, Figs 2b and 2cshow ways of avoiding it if it is not acceptable.

The first method (Fig. 2b) is to avoid forward biasing ofTOPFET’s Source-Drain diode by means of a series diodeD1. An alternative path for the generator current is providedby zener diode D2. (It is worth noting that interruption of thecurrent path with D1 will be required in applications wherereverse battery must not activate the motor.) If the inclusionof a power diode into the motor circuit is not acceptable thealternative shown in Fig. 2c can be used. In this approachthe flag signal sets an external latch when the TOPFET istripped by the short circuit. In this way the TOPFET statusis stored even when its Source-Drain diode is forwardbiased. If the TOPFET is being driven from amicrocontroller, the ’latch’ function could be implementedin software.

Fig. 2 Basic motor drive circuits with TOPFET

a) Simplestcircuit

b) Reverseblocking

c) Externallatching

Ri Ri

VbatVbat

Vbat

Vcc

D DD

SSS

I II

F

P

D1

D2M M

P PPCtrlCtrl

M

CtrlLatch

472


5.3.15 An Introduction to the High Side TOPFET

The introduction of high side TOPFETs enhances the rangeof protected power MOSFETs available from Philips. Thesedevices combine the real power handling ability of lowRDS(ON) MOSFETs with protection circuitsand the interfacingto allow ground referenced logic signals to control a highside switch.

Type rangeTable 1 shows the range of high side TOPFETs. Includedin the range are devices with on-state resistance in therange 38 to 220 mΩ. For each of the types an ’X’ or ’Y’variant canbe supplied (’Y’ typeshave an additional internalresistor in the ground line). All the devices are 50 V typesdesigned for use in 12 V automotive systems.

Type RDS(ON)

( mΩ)

BUK200-50X / BUK200-50Y 100

BUK201-50X / BUK201-50Y 60

BUK202-50X / BUK202-50Y 38

BUK203-50X / BUK203-50Y 220

Table 1. High side TOPFET type range

FeaturesParticular care has been taken during the development ofthe high side TOPFET to make a device which closelymatches the requirements of the automotive designer.

Overload Protection -High side TOPFETs are protected from the full range ofoverload conditions. Low level overloads which result inhigher than expected dissipation can cause the TOPFETto overheat. In this case the overtemperature sensor willtrip and the TOPFET will turn itself off until the chiptemperature falls below the reset point. In the event of amedium level overload, which could allow a high current toflow, TOPFET will limit the current, and hence dissipation,to a level which allows the overtemperature sensor time toreact and turn the TOPFET off until it cools sufficiently. Inhigh overload situations, like hard short circuits, the voltage

developed across the TOPFET will cause the short circuitdetector to react and latch the TOPFET off until it is resetby toggling the input. Both modes of overload turn-off arereported by pulling the status pin low.

Supply undervoltage lockout -If the battery to ground voltage is too low for its circuits towork correctly a high side TOPFET will turn off.

Open load detection -TOPFET monitors its own on-state voltage drop. If the dropis too low, indicating that the current is very small probablybecause the load is open circuit, TOPFET will report thisby pulling the status pin low.

Quiescent current -One factor of great importance, particularly as the numberof devices in a car increases, is quiescent current. InTOPFETs, the supply which feeds the circuits is turned offwhen the input is low. This reduces off state currentconsumption from typically 25 µA to less than 1 µA.

Ground resistor -For the fullest protection against the harsh automotiveelectrical environment, it is often necessary to fit a resistorbetween the ground pin of a high side device and moduleground. To help with this the Y types of the TOPFET rangehave this resistor integrated on the chip. Apart from theobvious saving in component count, this approach has theadvantage that the resistor is now in a package where itsdissipation can be easily handled. (This feature isparticularly useful when long duration reverse batterysituations are being considered).

Inductive load turn-off clamping -TOPFETs have a network between the MOSFET gate andthe ground pin. This network sets the maximum negativepotential between the load and ground pins. If the potentialtries to exceed this figure, for example during inductive loadturn-off, TOPFET will partially turn on, clamping the voltageat the load pin.

473


EMCElectromagnetic compatibility is an increasingly importantfactor in all electronic designs. EMC covers the immunityand the emissions, both conducted and radiated, ofelectronic units and systems. The directives and tests arerarely applicable to individual electronic componentsalthough the behaviour of devices can have a significantinfluence on EMC performance. In recognition of this,TOPFET has been designed to create as few EMCproblems as possible.

Test Voltage Pulse width

Pulse 1a -100 V 0.05 ms

Pulse 1b 2 ms

Pulse 2a +100 V 0.05 ms

Pulse 2b 0.5 ms

Pulse 3a -200 V 0.1 µs

Pulse 3b +200 V 0.1 µs

Pulse 5 +46.5 V 400 ms

Table 2. TOPFET transient tests

Conducted immunity -Onearea whereTOPFEThelps with EMCis with its inherentimmunity to conducted transients. The voltage supply of avehicle is notorious for its transients and circuits andsystems have to be designed to handle them. On theTOPFET chip are separate circuits which allow the outputMOSFET and the control circuits to withstand transientsbetween the battery and both the load and ground pins. Therange of transients which high side TOPFETs can surviveis shown in Table 2.

Low emission -High side switch devices generate their gate drive voltagewith oscillators and charge pumps running at highfrequency - often in excess of 1 MHz. Unless care is takenin the basic design of the device, emissions at the oscillatorfrequency or its harmonics can appear at the ground andload pins.

The TOPFET designers have taken the necessary care.The appropriate choice of oscillator and charge pumpcircuits and the inclusion of on-chip filtering have reducedemissions considerably. Some indication of the

improvement can be obtained by simply looking at thecurrent in the ground pin with an AC coupled current probe.Waveforms for the ground pin current of a Philips TOPFETand another manufacturer’s high side switch are shown inFig. 1.

a) Philips TOPFET

b) Manufacturer ’B’

Fig. 11. High side switch Ground pin current

Conclusions

High side TOPFETs are real power devices designed forcontrolling a wide range of automotive loads. The caretaken during their design means that TOPFETs arecompatible with circuit designers’ protection and EMCrequirements.

Average ground pin current (0.5 mA/div)

time (1 us/div)

Average ground pin current (0.5 mA/div)

time (1 us/div)

474


5.3.16 High Side Linear Drive with TOPFET

This section describes a complete high side linear drivecircuit using a TOPFET. A low side linear TOPFET drivecircuit is described in section 5.3.7 and the principal prosand cons of linear versus PWM drivers are discussed there.The most important differences between high and low sidelinear drives are:

- Thehigh side drive needs a charge pump circuit to providean input voltage higher than the battery voltage.

- In the high side drive the load provides negative feedbackfor the output transistor. Therefore, the control loop circuitneeded to maintain stability in a low side drive can besaved.

The circuit described in this paper was designed for andtested with a 200W fan motor for cars.

Circuit descriptionThe complete high side linear drive circuit can be split upinto two blocks:

- The drive circuit

- The charge pump

Drive circuitFigure 1 shows the drive circuit. Motor speed is controlledby changing the TOPFET’s input voltage and therefore itsvoltage drop. A 5-pin TOPFET is used because this typeallows the protection circuit to be supplied independentlyof the input. This is necessary because in this applicationthe input-source voltage may become too low to supply theprotection circuit of a 3-pin TOPFET.

The TOPFET’s input voltage and therefore the speed of thefan motor is determined by potentiometer R5. The TOPFETis operating as a source follower. The inherent negativefeedback of this configuration will automatically ensure thatthe source potential will equal the input potential (minus thegate-source voltage) no matter what current is flowing inthe motor.

An increase in motor load will tend to slow the motorreducing its back EMF and creating a demand for extracurrent. The extra current would increase the voltage dropacross the TOPFET, lowering the source potential. Sincethe input potential has been set, the lower source potential

increases the gate-source voltage turning the TOPFET onharder. The voltage drop will now reduce, returning thesource - hence motor voltage - to its original value but at ahigher current level. All of this means that even without anexternal feedback network, motor speed is inherentlystable, although not absolutely constant, under the fullrange of motor loads.

Transistor T2 works as a current generator and suppliesthe protection circuit of the TOPFET. T2 is switchable viatransistor T1 and Schottky diode D3. If the potentiometeris in position A, transistors T1 and T2 are switched offallowing R11 to pull the protection supply voltage to 0 V.This feature means the TOPFET, if it has tripped due toover temperature or overload, can be reset by turning thepotentiometer to position A.

Position A is also the standby mode. With both transistorsswitched off, the drive circuit has a very small currentconsumption. This means that in standby the currentconsumption of the whole circuit (drive and charge pump)is about 0.3mA.

Fig. 1 Drive circuit

B

A

R5

1M

R6

1M

R715k

R8

7.5k

BAW622x

D4

BAS83

T1

BC548

T2

BC558

D5

D6

R9

110k

R10240

R11

100k

R12100k

R13100k

Motor

Vbat

Z2BZX79/C10

BUK106-

D7

BAW62

50L

Vcp

0V

P

F

I

D3

P

Fan

D

S

475


TOPFET interfaceNegative potentials are not permitted between a TOPFET’sprotection supply (P), input (I) or flag (F) and its source.This must be considered, especially when designing highside drivers, where the source potential is determined bythe load voltage.

If an overvoltage pulse occurs at the supply terminal whilethe TOPFET is off, the source potential will rise with theovervoltage as soon as the TOPFET’s clamp voltage isexceeded. At this time the P,F and I pins should not beclamped with reference to ground, but should be allowedto rise with the source potential. In this circuit this isachieved by diodes D5 and D6 in the feeds to the I,P andF pins.

Zener diode Z2 limits the maximum protection supply andflag voltages to about 10 V and, via D4, the input-sourcevoltage to about 10.6 V. Resistor R7 has a value highenough to allow the TOPFET’s internal protection circuitsto turn off the device in the event of an over temperature orshort circuit load.

Charge pumpFigure 2 shows the charge pump circuit. IC1 works as anastable pulse generator at a frequency of 20 kHz which,together with D1, D2, C4, C5 produces a voltage doubler.The ICM7555 is a type with low current consumption. Thisis an important feature because the circuit consumescurrent, even when the driver circuit is in standby mode.

In its normal operating mode, the drive circuit has a typicalcurrent consumption of 1.5mA which determines the valuesof C4 and C5. R4 is included to limit the output current ofIC1. The charge pump generates an output voltage of about22V at a battery voltage of 12.6V. Z1, R1 and C1 will smoothand limit the supply to the circuit and provide protectionfrom voltage spikes.

For correct operation of TOPFET’s active protectioncircuits, sufficient voltage has to be applied to its protectionpin. The minimum protection supply voltage for theBUK106-50L is 4V for input voltages Vis up to 6.5V (seedata sheet Fig. 17). For the circuit presented and thecomponent values given, this requirement is met with abattery voltage as low as 8 V. If operation at a lower batteryvoltage is needed then a voltage tripler charge pump couldbe used in place of the voltage doubler proposed in thispaper.

Fig. 2 Charge pump circuit

Z1

BZD23/C15

R1

200

10u/22V

R2

C1

330k

R3160k

C2

100p

8

7

6

2 5

3

4

ICM7555

D2

BAW62

C322n

+ +

C410u/22V

C510u/22V

BAW62

R4

160

Vbat

Vcp

0V

D1

IC1

1

476


Automotive Ignition

477


5.4.1 An Introduction to Electronic Automotive Ignition

The function of an automotive ignition circuit is to providea spark of sufficient energy to ignite the compressed air-fuelmixture at the appropriate time. Increasingly, electronics isbeing used to optimise the ignition event. This is nownecessary to ensure conformance with emissionregulations and to achieve maximum engine performance,fuel economy and engine efficiency. This section will lookat some important aspects of the power stage of anelectronic ignition system. Other sections in this chapter willlook more closely at the power devices for this application.

Electronic ignition circuitThere are several different configurations for electronicignition. Some are still being studied and there are severalalready in use. But by far the most common configurationfor the power stage is that shown in Fig. 1. With thisarrangement there is no distributor. The circuit shown is fora four cylinder engine and has two separate power circuitseach feeding two cylinders. Extra power stages can beadded for 6 and 8 cylinder engines. When one power stagefires, bothplugs will sparkbut, by choosingpairs of cylinderswhich are 360˚ out of phase in the 4-stroke cycle, only onewill have a mixture that can be ignited - the other will beapproaching tdc at the end of the exhaust stroke.

OperationDuring normal operation the transistor will be turned onsome time before the spark is needed (t1 in Fig. 2). Currentwill now rise at a rate given by the equation

where V is the voltage across the primary of the coil. Whenthe spark is needed (t3), the transistor is turned off. Thecurrent in the inductance will try to stop flowing but it canonly change at the rate given by (1). This means that voltageon the primary is forced to become large and negative.Transformer action increases the secondary voltage untilit reaches the voltage needed to create a spark at the plugs- minimum 5 kV but may be 10 to 30 kV. Current now flowsthrough the spark and the secondary winding, the voltagenow falls back to that necessary to maintain the current inthe spark, t5. When all the coil energy has been delivered,t6, the voltage at the collector falls to the battery voltage.

Fig. 1 Typical automotive ignition circuit

Spark energy

Under ideal conditions the mixture can be ignited with aspark energy of 0.3 mJ but, for reliable ignition under allpossible engine conditions, spark energies in the range60mJ to 150mJ are needed. The energy comes from thecoil and is the energy stored as flux generated by the currentthat was allowed to build up in the primary. The energystored in the magnetic field of the coil is:

Timing

The timing of the spark is one of the most critical factors inachieving optimum engine performance. The controlleruses informationabout engine speed, temperature, fuel etc.to decide how far before tdc the spark is needed. It thenuses data from crankshaft position sensors to decide whento signal for a spark.

One factor which the controller cannot control is the delaybetween it issuing the command to spark and the sparkbeing generated. Part of this delay is the time it takes thetransistor to start turning off together with the rate at whichthe transistor voltage rises. The controller can makeallowance for this delay but in many systems this is no morethan a fixed offset. In practice the delay will vary withvariations in the drive circuit, temperature and betweendevices - with some transistor types beingmore susceptibleto variation than others.

IgnitionSwitch

- +

Battery

ClampDynamic

Ignition

Controller

ElectronicSwitch

Coil

Eprim =12

Lprimi 2 (2)

rateofrise=didt

=VL

(1)

479


a) Coil current

b) Transistor collector voltageFig. 2 Ignition circuit waveforms

DwellAs mentioned earlier, proper ignition means there must beenough energy stored in the coil when the spark is needed,so the transistor must be turned on soon enough to allowtime for the current to reach the required level. However,turning on too soon will mean that the current is higher thanit needs to be. Although proper spark timing and energy ismore important, optimum coil current is also significant.Higher currents create higher loss which reduces efficiencyand increases the problems of thermal management. Theycan also reduce the life and reliability of the coil and createmajor difficulties when designing for survival under faultconditions like open circuit secondary.

The time to turn on the transistor is governed by (1). Coilinductance is an attribute of the coil but the primary voltagedepends on battery voltage and the voltage drop across thetransistor. Battery voltage can vary widely and can be very

low particularly during engine cranking. Ensuring that thecircuit operates reasonably well at these low voltagesmeans keeping the transistor voltage drop as low aspossible.

Fault conditions

Automotive systems must be reliable. Achieving highreliability means designing systems that can survive all theoperating environments that the automobile can produce.Some of the harshest conditions are the fault conditions.

Open circuit secondary

Disconnection of a spark plug lead means that the storedcoil energy cannot be dissipated in the spark. Unless stepsare taken to prevent it, the voltage will be forced higher untilit reaches the breakdown voltage of the transistor. Thecombination of high current and voltage would probablydestroy the device. Thesolution to this problem is tooperatethe transistor in dynamic clamping. This can be achievedeither by connecting a network between collector and thegate/base or by using a device with the network alreadyintegrated into it. With this arrangement the voltage risesto the clamping voltage, the transistor then turns onpartially, with enough drive to allow the coil current to flowat a collector emitter voltage equal to the clamping voltage.Theclamping voltage is sethigher than the voltage normallyneeded to generate the spark.

Reverse Battery

Another condition which must be survived is when thebattery connections are reversed. Ideally no current shouldflow and this can be achieved with some transistors whichhave a reverse blocking voltage greater than the batteryvoltage. With many transistors, however, reverse blockingis not guaranteed and to block the current means adding adiode in series. This is rarely acceptable because the diodeforward voltage drop adds too much to the effective voltagedrop. The alternatives are to allow the current to flow eitherby using a transistor which is rated to operate with reversecurrentor by fitting a diode in anti-parallel with the transistor.

0

2.0

4.0

6.0

2.0 4.0 6.0 8.0 t(ms)

I(A)

t2

t3

t4

0

100

200

300

2.0 4.0 6.0 8.0 t(ms)

Vce(V)

t1

t3 t4

t6t5

480


5.4.2 IGBTs for Automotive Ignition

This publication describes a range of power transistors forautomotive ignition applications from PhilipsSemiconductors. This range of IGBTs has been specificallyoptimised for the demanding conditions of ignition circuits.The IGBT is a voltage controlled, low loss, high powertransistor which gives the ease of drive and low conductionlosses that are required in automotive ignition circuits. ThePhilips range of ignition IGBTs includes conventional IGBTdevices with standard gate drive input. It also includes arange of standard and logic level input protected IGBTs withintegral gate drain and gate source clamping diodes.

Introduction to the IGBTThe structure of an IGBT is similar to that of a PowerMOSFET, both being created by the parallel connection ofmany thousands of identical cells. Figure 1 shows the crosssection of one IGBT cell. The only difference between thisdrawing and one for a MOSFET would be the polarity ofthe substrate - the MOSFET would be n+ rather than thep+ of the IGBT. Since the gate structures are identical theIGBT like the MOSFET is a voltage driven device with anextremely high input impedance.

Fig. 1 Cross section of IGBT cell

Bipolar operationWhere the IGBT differs is in the characteristics of the outputdevice. Conduction in a MOSFET is by majority carriersonly but the p substrate silicon used for IGBTs promotesinjection and gives bipolar conduction with both majorityand minority carriers. The effect of this is to make the onstate voltage drop of a high voltage IGBT much lower thanthat of the same size and voltage MOSFET. This feature isparticularly useful in automotive ignition where high voltagedevices are needed which can operate from low voltagesupplies. In recognition of its combination of MOSFET inputand bipolar output, the terminals of an IGBT are calledCollector, Emitter and Gate.

Input Voltage

IGBTs, like MOSFETs, can have standard or logic levelgate sensitivity. A standard device has a threshold voltageof typically 3.5 V - the threshold voltage is the gate voltageneeded to allow the IGBT to conduct 1 mA, i.e just startedto turn on. To be fully on, with an acceptable low VCE, thegate voltage needs to be 8.5 V. In some situations, suchas engine cranking, the battery voltage falls to less than 6 Vand achieving adequate drive may be a problem.

An alternative would be to use a logic level IGBT which hasa threshold of typically 1.5 V and is fully on with 5 V.

Another factor in the choice between standard or logic level,is that of noise immunity. In this application it can be veryimportant that the IGBT is fully off, in a very low leakagestate, when the driver stage output is LOW. Unfortunately,the LOW that a driver produces may not create a gate toemitter voltage of 0 V.

The threshold voltage of an IGBT falls as temperature rises.So the gate emitter voltage of a logic level IGBT (atTj = 120˚C) needs to be < 0.7V to ensure that it is off. Astandard level part, with its higher threshold, has moreimmunity and it would still be off if the voltage was < 1.4 V.

Turn off control

The time between the gate signal arriving at the IGBT andthe collector voltage rising is known as the delay time, td.An ignition system produces a spark when the collectorvoltage rises. Since the timing of the spark is critical, it isadvantageous to have good control of td. With the IGBT,unlike some other ignition switches, td is dominated by gatecharge and so can be very low and is easily controlled bythe resistance of the driver circuit.

Safe Operating Area

One of the worst situations for creating IGBT latch up isinductive turn off. Such a turn off takes place in electronicignition. IGBTs, for ignition applications, are specified witha safe operating area (SOA) and limiting value of collectorcurrent that canbe safely switched under clamped inductiveload conditions (ICLM). Providing that the device is operatedwithin its safe operating area (SOA) dynamic latch-up (orSOA failure) cannot occur. Philips ignition IGBTs have alarge turn-off SOA and a large energy handling capabilitymaking them easy to use in ignition circuits.

ppn n

n-

p+

Collector

Emitter Emitter

Gate

481


Feature Advantage

IGBTs

•Voltage driven -Low gate drive power-Simple gate circuit

•Logic level capability -Low battery operation

•Bipolar operation -Low conduction loss-Small device size

•PowerMOS/bipolar -Negligible Storage timestructure -Reverse blocking

-Energy handling

•Large SOA -No snubber required-Design flexibility

Clamped IGBTs

•Integral clamp diodes -Design simplicity-Overvoltage protection-Clamp voltage control-Improved reliability-ESD protection

Table 1. Advantages of IGBTs

Reverse BatteryThe n- p+ junction, see Fig. 1, which is inherent in thestructure of the IGBT, creates a reverse blocking junction.This junction, although unable to support very high reversevoltages, is able to block voltages in excess of a batteryvoltage. This gives the IGBT a reverse battery blockingcapability which ensures that reverse battery faultconditions will not give rise to high currents which coulddamage the IGBT or any other components in the ignitioncircuit.

Clamped IGBTA refinement of the conventional IGBT is the clamped orprotected IGBT. This is produced by adding extra

processing stages which allows polysilicon diodes, ofknown breakdown voltage, to be integrated with the IGBTstructure. A short chain of diodes is connected between thegate and the emitter. This gives ESD protection by clampingthe voltage, which can be applied across the gate emitteroxide, to a safe value.

A much longer chain, with a combined breakdown voltageof several hundreds of volts, is connected between thecollector and the gate. This chain makes the IGBT into adynamic clamp - possibly the best way of ensuring survivalduring ignition faults like open circuit secondary. Theposition of the diode chains is shown in the circuit symbol,see Fig. 2.

Fig. 2 IGBT circuit symbols

Conclusions

The Philips Semiconductors BUK854-500IS ignition IGBTsand clamped IGBTs BUK856-400IZ and BUK856-450IXare specifically designed to give a low loss, easy to driveand rugged solution to the demanding applications ofautomotive ignition circuits. IGBTs require the minimum ofexternal components in the gate drive circuit and givenegligible drive losses. The energy handling and reverseblocking capabilities of the device make it suitable for usein automotive environments - even under fault conditions.Voltage clamping and ESD protection give ease of designanduse, improved reliability and performance in the ignitioncontroller circuit.

gate

collector

emitteremitter

collector

gate

482


5.4.3 Electronic Switches for Automotive Ignition

Earlier sections in this chapter have discussed the natureof automotive electronic ignition and looked at a range ofIGBTs which have been optimised for use in this type ofapplication. This section will compare ignition IGBTs withignition darlington transistors and come to the conclusionsthat IGBTs have several advantages which would be usefulto the automotive designer.

Darlington transistorsIn the past, the darlington transistor has been the favouredpower transistor for ignition applications. The darlingtonconnection is, in fact, a cascade of two separate bipolartransistors. The combination increases the gain allowingthe high voltage device to be controlled by a relatively lowpower driver stage.

Fig. 1 Typical ignition circuit with darlington switch

As the darlington is a bipolar device it has a relatively lowon-state voltage drop even though it can block a highvoltage. The low voltage drop keeps conduction losses lowand allows the ignition circuit to function at low batteryvoltages.

The disadvantage of a darlington is the complexity and costof the base drive. Even though the gain is improved, by thedarlington connection, a large gate current is still needed(approx. 100 mA) a circuit similar to that shown in Fig. 1 willbe needed. It would be inefficient and costly to supply acurrent this large from the stabilised 5 V rail, so the supplycould be the battery. This means that the drive dissipationwhen the transistor is on, is about 1.2 W and the averagedissipation about 0.5 W. This level of dissipation requiresa special driver IC or a circuit using discretes. All of thisadds to the cost complexity and thermal problems of theignition system.

The low on-state voltage drop of a bipolar device is theresult of minority carrier injection. However, the minoritycarrier injection also introduces ’stored charge’ into thedevice which must be removed at turn-off. The charge isextracted, at least partially, as negative base current duringthe period known as the storage time, ts. How long thistakes, depends on the amount of stored charge and therate it is extracted. The amount of charge varies from deviceto device, with the level of the current and with temperature.The rate of extraction depends on the drive circuit andwhether a ’simple’ circuit like that of Fig. 1 is used or onewhich uses negative drive to remove the charge morequickly.

Fig. 2 Ignition IGBT circuit

Storage time adds to the delay between the input changingstate and the spark being produced and the uncertainty instorage time, which results from the large number ofvariables, adds to the inaccuracy of the ignition timing.

Typical ignition darlingtons often include an internalantiparallel diode connected across the mainemitter-collector terminals as shown in Fig. 1. This diode isnot necessary for the normal operation of the ignition circuitand its function is simply to protect the darlington fromreverse battery faults. However, during this condition, thediode does allow large reverse currents to flow through theignition circuit.

IGBTs

The IGBT is a combination of bipolar transistor and PowerMOSFET technologies. It has the advantage of the lowon-state voltage drop of a bipolar darlington and can alsobe voltage driven in the same way as a Power MOSFET.This gives a highly efficient, easy to drive, minimum losssolution for the switching transistor in an ignition circuit.

Coil

bat

Sparkgap

PrimaryCoilSecondary

V

iC

vCEin

RG

V

BUK854-500ISIGBTVin

Vbat

BUV90

Coil

483


A typical ignition circuit using the Philips BUK854-500ISIGBT is shown in Fig. 2; the saving in gate drivecomponents is self evident. The need for a special driverstage is eliminated because drive dissipation for an IGBTwill be approximately 10 µW which can be easily suppliedby standard ICs. The BUK854-500IS has a voltage ratingof 500V and standard gate threshold voltage, and isassembled in the TO220 package.

Clamped IGBTsOne of the most exciting features of IGBT technology is theability to integrate protection functions into the IGBT to givesignificant advantages to the designer of power circuits.The BUK856-400IZ and BUK856-450IX are two suchdevices which have been specifically designed forautomotive ignition circuits. The BUK856-400IZ is a logiclevel device, the BUK856-450IX has a standard gatethreshold. The nominal clamp voltages are 400V and 450Vrespectively.

In these devices the dynamic clamp network shown in Fig. 2is fabricated directly onto the IGBT. This gives guaranteedclamping of the IGBT at a fixed clamp voltage without theneed for an external circuit. The clamp voltage is held tovery tight tolerances over the full temperature range (-40˚Cto +150˚C) required in automotive applications.

In both these devices gate-source protection diodes havealso been incorporated into the structure of the devices togive full protection against ESD damage during handlingand assembly of the device into engine management units.

IGBTs and darlingtons - A performancecomparisonThe performance of the BUK856-400IZ ignition IGBT hasbeen compared with that of a typical ignition darlington inthe ignition circuit of Fig. 1.

At turn-off the darlington switched considerably slower thanthe IGBT. The time between the input going low and thespark was 32 µs for the darlington and only 19 µs for theIGBT.

Table 1 shows a breakdown of the ignition system lossesand demonstrates that whilst the device losses are slightlyhigher in the IGBT, the overall losses are higher in thedarlington circuit due to extra loss in the base drive.

Power loss (W) Vclamp=400V, ICmax=6.0A

100Hz, (3000rpm) IGBT darlington

Conduction 1.37 1.16

Switching 0.71 0.79

Drive 0.00001 0.5

Total 2.08 2.45

Table 1. IGBT and darlington ignition circuit losses

Conclusion

Table 2 summarises the comparison between the IGBT andthe darlington as the power switch in automotive ignition.The comparison shows that the darlington is good in theapplication but that the IGBT has some clear advantagesmaking it significantly better.

IGBT darlington

Driver component count Low HighSpeed of response, ’time to Fast Slowspark’Total loss Better GoodDrive power Low HighLogic level operation Yes YesOpen circuit load Yes YesReverse blocking Yes NoPackage size Small LargeInbuilt voltage clamp Possible PossibleInbuilt protection Yes No

Table 2. Performance comparison

484

Thyristors and Triacs Power Semiconductor ApplicationsPhilips Semiconductors

CHAPTER 6

Power Control with Thyristors and Triacs

6.1 Using Thyristors and Triacs

6.2 Thyristor and Triac Applications

6.3 Hi-Com Triacs

485


Using Thyristors and Triacs

487


6.1.1 Introduction to Thyristors and Triacs

Brief summary of the thyristor familyThe term thyristor is a generic name for a semiconductorswitch having four or more layers and is, in essence, ap-n-p-n sandwich. Thyristors form a large family and it ishelpful to consider the constituents which determine thetype of any given thyristor. If an ohmic connection is madeto the first p region and the last n region, and no otherconnection is made, the device is a diode thyristor. If anadditional ohmic connection is made to the intermediate nregion (n gate type) or the intermediate p region (p gatetype), the device is a triode thyristor. If an ohmic connectionis made to both intermediate regions, the device is a tetrodethyristor. All such devices have a forward characteristic ofthe general form shown in Fig. 1.

There are three types of thyristor reverse characteristic:blocking (as in normal diodes), conducting (large reversecurrents at low reverse voltages) and approximate mirrorimage of the forward characteristic (bidirectional thyristors).Reverse blocking devices usually have four layers or lesswhereas reverse conducting and mirror image devicesusually have five layers.

The simplest thyristor structure, and the most common, isthe reverse blocking triode thyristor (usually simply referredto as the ’thyristor’ or SCR ’silicon controlled rectifier’). Itscircuit symbol and basic structure are shown in Fig. 2.

The most complex common thyristor structure is thebidirectional triode thyristor, or triac. The triac (shown inFig. 3) is able to pass current bidirectionally and is thereforean a.c. power control device. Its performance is that of apair of thyristors in anti-parallel with a single gate terminal.The triac needs only one heatsink, but this must be largeenough to remove the heat caused by bidirectional currentflow. Triac gate triggering circuits must be designed withcare to ensure that unwanted conduction, ie. loss of control,does not occur when triggering lasts too long.

Thyristors and triacs are both bipolar devices. They havevery low on-state voltages but, because the minority chargecarriers in the devices must be removed before they canblock an applied voltage, the switching times arecomparatively long. This limits thyristor switching circuits tolow frequency applications. Triacs are used almostexclusively atmains supply frequencies of 50 or 60Hz, whilein some applications this extends up to the 400Hz supplyfrequency as used in aircraft.

The voltage blocking capabilities of thyristors and triacs arequite high: the highest voltage rating for the Philips rangeis 800V, while the currents (IT(RMS)) range from 0.8A to 25A.

The devices are available as surface mount components,or as non-isolated or isolated discrete devices, dependingon the device rating.

Fig. 1 Thyristor static characteristic

Fig. 2 Thyristor circuit symbol and basic structure

Fig. 3 Triac circuit symbol and basic structure

On-statecharacteristic

Off-statecharacteristic

Avalanchebreakdownregion

Reversecharacteristic

Reversecurrent

Forwardcurrent

Reversevoltage

Forwardvoltage

ILIH

V(BO)

I = 0GI > 0G

Anode Anode

Gate

Gate

Cathode Cathode

p

n

p

n

J1J2J3

MT1

MT2

Gate Gate

MT1

MT2

n

n

n

n

p

p

489


Thyristor operation

Theoperationof the thyristor can be understood from Fig. 2.When the thyristor cathode is more positive than the anodethen junctions J1 and J3 are reverse biased and the deviceblocks. When the anode is more positive than the cathode,junctions J1 and J3 are forward biased. As J2 is reversebiased, then the device still blocks forward voltage. If thereverse voltage across J2 is made to reach its avalanchebreakdown level then the device conducts like a singleforward-biased junction.

The ’two transistor’ model of Fig. 4 can be used to considerthe p-n-p-n structure of a thyristor as the interconnection ofan npn transistor T1 and a pnp transistor T2. The collectorof T1 provides the base current for T2. Base current for T1

is provided by the external gate current in addition to thecollector current from T2. If the gain in the base-collectorloop of T1 and T2 exceeds unity then the loop current canbe maintained regeneratively. When this condition occursthen both T1 and T2 are driven into saturation and thethyristor is said tobe ’latched’. Theanode tocathode currentis then only limited by the external circuit.

Fig. 4 ’Two transistor’ model of a thyristor

There are several mechanisms by which a thyristor can belatched. The usual method is by a current applied to thegate. This gate current starts the regenerative action in thethyristor and causes the anode current to increase. Thegains of transistors T1 and T2 are current dependent andincrease as the current through T1 and T2 increases. Withincreasing anode current the loop gain increasessufficiently such that the gate current can be removedwithout T1 and T2 coming out of saturation.

Thus a thyristor can be switched on by a signal at the gateterminal but, because of the way that the current thenlatches, the thyristor cannot be turned off by the gate. Thethyristor must be turned off by using the external circuit tobreak the regenerative current loop between transistors T1

and T2. Reverse biasing the device will initiate turn-off oncethe anode current drops below a minimum specified value,called the holding current value, IH.

Thyristor turn-on methods

Turn-on by exceeding the breakovervoltageWhen the breakover voltage, VBO, across a thyristor isexceeded, the thyristor turns on. The breakover voltage ofa thyristor will be greater than the rated maximum voltageof the device. At the breakover voltage the value of thethyristor anode current is called the latching current, IL.

Breakover voltage triggering is not normally used as atriggering method,and most circuit designs attempt to avoidits occurrence. When a thyristor is triggered by exceedingVBO the fall time of the forward voltage is quite low (about1/20th of the time taken when the thyristor isgate-triggered). As a general rule, however, although athyristor switches faster with VBO turn-on than with gateturn-on, the permitted di/dt for breakover voltage turn-on islower.

Turn-on by leakage currentAs the junction temperature of a thyristor rises, the leakagecurrent also increases. Eventually, if the junctiontemperature is allowed to rise sufficiently, leakage currentwould become large enough to initiate latching of theregenerative loop of the thyristor and allow forwardconduction. At a certain critical temperature (above Tj(max))the thyristor will not support any blocking voltage at all.

Turn-on by dV/dtAny p-n junction has capacitance - the larger the junctionarea the larger the capacitance. If a voltage ramp is appliedacross the anode-to-cathode of a p-n-p-n device, a currentwill flow in the device to charge the device capacitanceaccording to the relation:

If the charging current becomes large enough, the densityof moving current carriers in the device induces switch-on.

Turn-on by gate triggeringGate triggering is the usual method of turning a thyristor on.Application of current to the thyristor gate initiates thelatching mechanism discussed in the previous section. Thecharacteristic of Fig. 1 showed that the thyristor will switchto its on-state condition with forward bias voltages less thanVBO when the gate current is greater than zero. The gatecurrent and voltage requirements which ensure triggeringof a particular device are always quoted in the device data.As thyristor triggering characteristics are temperaturedependant, the amplitude and duration of the gate pulsemust be sufficient to ensure that the thyristor latches underall possible conditions.

T1

T2

Anode

Cathode

Gate

iA

iG

iC = C.dvdt

(1)

490


During gate turn-on, the rate of rise of thyristor anodecurrent dIF/dt is determined by the external circuitconditions. However, the whole active area of the thyristor(or triac) cannot be turned on simultaneously: the areanearest to the gate turns on first, followed by the remainderof the device. At turn-on it is important that the rate of riseof current does not exceed the specified rating. If dIF/dt isexcessive then only a limited area of the device will havebeen turned on as the anode current increases. Theresulting localised heating of the device will causedegradation and could lead to eventual device failure.

A suitably high gate current and large rate of rise of gatecurrent (dIG/dt) ensures that the thyristor turns on quickly(providing that the gate power ratings are not exceeded)thus increasing the thyristor turn-on di/dt capability. Oncethe thyristor has latched then the gate drive can be reducedor removed completely. Gate power dissipation can alsobe reduced by triggering the thyristor using a pulsed signal.

Triac operationThe triac can be considered as two thyristors connected inantiparallel as shown in Fig. 5. The single gate terminal iscommon to both thyristors. The main terminals MT1 andMT2 are connected to both p and n regions of the deviceand the current path through the layers of the devicedepends upon the polarity of the applied voltage betweenthe main terminals. The device polarity is usually describedwith reference to MT1, where the term MT2+ denotes thatterminal MT2 is positive with respect to terminal MT1.

Fig. 5 Anti parallel thyristor representation of a triac

The on-state characteristic of the triac is similar to that of athyristor and is shown in Fig. 6. Table 1 and Fig. 7summarise the different gate triggering configurations fortriacs.

Due to the physical layout of the semiconductor layers in atriac, the values of latching current (IL), holding current (IH)and gate trigger current (IGT) vary slightly between thedifferent operating quadrants. In general, for any triac, thelatching current is slightly higher in the second (MT2+, G-)quadrant than the other quadrants, whilst the gate triggercurrent is slightly higher in fourth (MT2-, G+) quadrant.

Fig. 6 Triac static characteristic

Quadrant Polarity of MT2 wrt MT1 Gate polarity

1 (1+) MT2+ G+2 (1-) MT2+ G-3 (3-) MT2- G-4 (3+) MT2- G+

Table 1. Operating quadrants for triacs

Fig. 7 Triac triggering quadrants

For applications where the gate sensitivity is critical andwhere the device must trigger reliablyand evenly for appliedvoltages in both directions it may be preferable to use anegative current triggering circuit. If the gate drive circuit isarranged so that only quadrants 2 and 3 are used (i.e. G-operation) then the triac is never used in the fourth quadrantwhere IGT is highest.

On-state

Off-state

Reversecurrent

Forwardcurrent

Reversevoltage

Forwardvoltage

ILIH

V(BO)

I = 0GI > 0G

On-state

Off-state

LIHI

(BO)V

I = 0GI > 0G

T2-

T2+

Quadrant 1Quadrant 2


G+G-

MT2+

MT2-

IG

IG

IG

IG

++

- -

+

-

+

-

MT2

MT1

491


For some applications it is advantageous to trigger triacswith a pulsating signal and thus reduce the gate powerdissipation. To ensure bidirectional conduction, especiallywith a very inductive load, the trigger pulses must continueuntil the end of each mains half-cycle. If single triggerpulsesare used, one-way conduction (rectification) results whenthe trigger angle is smaller than the load phase angle.

Philips produce ranges of triacs having the same currentand voltage ratings but with different gate sensitivities. Adevice with a relatively insensitive gate will be more immuneto false triggering due to noise on the gate signal and alsowill be more immune to commutating dv/dt turn-on.Sensitive gate triacs are used in applications where thedevice is driven from a controller IC or low power gatecircuit.

The diacIt is also worthwhile to consider the operation andcharacteristics of the diac in the context of multilayer bipolardevices.The diac is more strictlya transistor thana thyristor,but has an important role in many thyristor and triactriggering circuits. It is manufactured by diffusing an n-typeimpurity into both sides of a p-type slice to give a twoterminal device with symmetrical electrical characteristics.As shown in the characteristic of Fig. 8, the diac blocksapplied voltages in either direction until the breakovervoltage, VBO is reached. The diac voltage then breaks backto a lower output voltage VO. Important diac parameters arebreakover voltage, breakover current and breakbackvoltage as shown in the figure.

Fig. 8 Diac static characteristic and circuit symbol

Gate requirements for triggeringTo a first approximation, the gate-to-cathode junction of athyristor or triac acts as a p-n diode. The forwardcharacteristic is as shown in Fig. 9. For a given thyristortype there will be a spread in forward characteristics of gatejunctions and a spread with temperature.

Fig. 9 Thyristor gate characteristic

The gate triggering characteristic is limited by the gatepower dissipation. Figure 9 also shows the continuouspower rating curve (PG(AV)=0.5W) for a typical device andthe peak gate power curve (PGM(max)=5W). When designinga gate circuit to reliably trigger a triac or thyristor the gatesignal must lie on a locus within the area of certain devicetriggering. Continuous steady operation would demand thatthe 0.5W curve be used to limit the load line of the gatedrive circuit. For pulsed operation the triggering locus canbe increased. If the 5W peak gate power curve is used, theduty cycle must not exceed

At the other endof the scale, the level below which triggeringbecomes uncertain is determined by the minimum numberof carriers needed in the gate-cathode junction to bring thethyristor into conduction by regenerative action. The triggercircuit load line must not encroach into the failure to triggerregion shown in Fig. 9 if triggering is to be guaranteed. Theminimum voltage and minimum current to trigger all devices(VGT and IGT) decreases with increasing temperature. Datasheets for Philips thyristors and triacs show the variation ofVGT and IGT with temperature.

Thyristor commutation

A thyristor turns off by a mechanism known as ’naturalturn-off’, that is, when the main anode-cathode currentdrops below the holding value. It is important to remember,however, that the thyristor will turn on again if the reappliedforward voltage occurs before a minimum time period haselapsed; this is because the charge carriers in the thyristorat the time of turn-off take a finite time to recombine.Thyristor turn-off is achieved by two main methods - selfcommutation or external commutation.

Gate voltage, V G (V)

Gate current, I G (A)

P = 5W= 0.1

= 1.0

VGT

IGT

Failureto trigger

GM(max)

P = 0.5WG(AV)

Gate powerratings

Gate-cathodecharacteristic

δmax =PG(AV)

PGM

=0.55

= 0.1 (2)

Reversecurrent

Forwardcurrent

Reversevoltage

Forwardvoltage

V(BO)

(BO)V

I(BO)

I(BO)

VO

VO

Breakbackvoltage

492


Self CommutationIn self-commutation circuits the thyristor will automaticallyturn off at a predetermined time after triggering. Thethyristor conduction period is determined by a property ofthe commutation circuit, such as the resonant cycle of anLC-circuit or the Volt-Second capability of a saturableinductor. The energy needed for commutation is deliveredby a capacitor included in the commutation circuit.

LC circuit in series with the thyristorWhen the thyristor is triggered, the resulting main currentexcites the resonant circuit. After half a resonant cycle, theLC circuit starts to reverse the anode current and turns thethyristor off. The thyristor conduction interval is half aresonant cycle. It is essential for proper commutation thatthe resonant circuit be less than critically damped. Fig. 10shows the circuit diagram and the relevant waveforms forthis arrangement.

LC Circuit in parallel with the thyristor

Initially the capacitor charges to the supply voltage. Whenthe thyristor is triggered the load current flows but at thesame time the capacitor discharges through the thyristor inthe forward direction. When the capacitor has discharged(i.e. after one resonant half-cycle of the LC circuit), it beginsto charge in the opposite direction and, when this chargingcurrent is greater than the thyristor forward current, thethyristor turns off. The circuit diagram and commutationwaveforms are shown in Fig. 11.

External commutation

If the supply is an alternating voltage, the thyristor canconduct only during the positive half cycle. The thyristornaturally switches off at the end of each positive half cycle.The circuit and device waveforms for this method ofcommutation are shown in Fig. 12. It is important to ensurethat the duration of a half cycle is greater than the thyristorturn-off time.

Reverse recovery

In typical thyristors the reverse recovery time is of the orderof a few micro-seconds. This time increases with increaseof forward current and also increases as the forward currentdecay rate, dIT/dt, decreases. Reverse recovery time is theperiod during which reverse recovery current flows (t1 to t3in Fig. 13) and it is the period between the point at whichforward current ceases and the earliest point at which thereverse recovery current has dropped to 10% of its peakvalue.

Fig. 10 Commutation using a series LC circuit

Fig. 11 Commutation using a parallel LC circuit

RR leakage

L

C

E

+

I thyristor

R

L

C

E

IR

+ I thyristor

493


Reverse recovery current can cause high values of turn-oncurrent in full-wave rectifier circuits (where thyristors areused as rectifying elements) and in certain inverter circuits.It should also be remembered that, if thyristors areconnected in series, the reverse voltage distribution can beseriously affected by mismatch of reverse recovery times.

Fig. 12 Thyristor commutation in an a.c. circuit

Fig. 13 Thyristor turn-off characteristics

Turn-off timeTurn-off time is the interval between the instant whenthyristor current reverses and the point at which the thyristorcan block reapplied forward voltage (t1 to t4 in Fig. 13). Ifforward voltage is applied to a thyristor too soon after themain current has ceased to flow, the thyristor will turn on.The circuit commutated turn-off time increases with:

-junction temperature-forward current amplitude-rate of fall of forward current-rate of rise of forward blocking voltage-forward blocking voltage.

Thus the turn-off time is specified for defined operatingconditions. Circuit turn-off time is the turn-off time that thecircuit presents to the thyristor; it must, of course, be greaterthan the thyristor turn-off time.

Triac commutationUnlike the thyristor, the triac can conduct irrespective of thepolarity of the applied voltage. Thus the triac does notexperience a circuit-imposed turn-off time which allowseach anti-parallel thyristor to fully recover from itsconducting state as it is reverse biased. As the voltageacross the triac passes through zero and starts to increase,then the alternate thyristor of the triac can fail to block theapplied voltage and immediately conduct in the oppositedirection. Triac-controlled circuits therefore require carefuldesign in order to ensure that the triac does not fail tocommutate (switch off) at the end of each half-cycle asexpected.

It is important to consider the commutation performance ofdevices in circuits where either dI/dt or dV/dt can be large.In resistive load applications (e.g. lamp loads) currentsurges at turn-on or during temporary over-currentconditions may introduce abnormally high rates of changeof current which may cause the triac to fail to commutate.In inductive circuits, such as motor control applications orcircuits where a dc load is controlled by a triac via a bridgerectifier, it is usually necessary to protect the triac againstunwanted commutation due to dv(com)/dt.

The commutating dv(com)/dt limit for a triac is less than thestatic dv/dt limit because at commutation the recentlyconducting portion of the triac which is being switched offhas introduced stored charge to the triac. The amount ofstored charge depends upon the reverse recoverycharacteristics of the triac. It is significantly affected byjunction temperature and the rate of fall of anode currentprior to commutation (dI(com)/dt). Following high rates ofchange of current the capacity of the triac to withstand highreapplied rates of change of voltage is reduced. Data sheetspecifications for triacs give characteristics showing the

R

i thyristor

IT

IR

VD

VR

dIT

dt

dVD

dt

t0 t1 t2 t3 t4

494


maximum allowable rate of rise of commutating voltageagainst device temperature and rate of fall of anode currentwhich will not cause a device to trigger.

Fig. 14 Inductive load commutation with a triac

Consider the situation when a triac is conducting in onedirection and the applied ac voltage changes polarity. Forthe case of an inductive load the current in the triac doesnot fall to its holding current level until some time later. Thisis shown in Fig. 14. At the time that the triac current hasreached the holding current the mains voltage has risen tosome value and so the triac must immediately block thatvoltage. The rate of rise of blocking voltage followingcommutation (dv(com)/dt) can be quite high.

The usual method is to place a dv/dt-limiting R-C snubberin parallel with the triac. Additionally, because commutatingdv/dt turn-on is dependent upon the rate of fall of triaccurrent, then in circuits with large rates of change of anodecurrent, the ability of a triac to withstand high rates of riseof reapplied voltage is improved by limiting the di/dt usinga series inductor. This topic is discussed more fully in thesection entitled ’Using thyristors and triacs’.

Conclusions

This article has presented the basic parameters andcharacteristics of triacs and thyristors and shown how thestructure of the devices determines their operation.Important turn-on and turn-off conditions and limitations ofthe devices have been presented in order to demonstratethe capabilities of the devices and show the designer thoseareas which require careful consideration. The devicecharacteristics which determine gate triggeringrequirements of thyristors and triacs have been presented.

Subsequent articles in this chapter will deal with the use,operation and limitations of thyristors and triacs in practicalapplications, and will present some detailed design andoperational considerations for thyristors and triacs in phasecontrol and integral cycle control applications.

VDWM

-dI/dtdVcom/dt

Time

Time

Time

Supplyvoltage

Loadcurrent

Voltageacrosstriac

Triggerpulses

Current

495


6.1.2 Using Thyristors and Triacs

This chapter is concerned with the uses, operation andprotection of thyristors and triacs. Two types of circuit coverthe vast majority of applications for thyristors and triacs:static switching circuits and phase control circuits. Thecharacteristics and uses of these two types of circuit will bediscussed. Various gate drive circuits and protectioncircuits for thyristor and triacs are also presented. The useof these circuits will enable designers to operate the devicesreliably and within their specified limits.

Thyristor and triac control techniquesThere are two main techniques of controlling thyristors andtriacs - on-off triggering (or static switching) and phasecontrol. In on-off triggering, the power switch is allowed toconduct for a certain number of half-cycles and then it iskept off for a number of half-cycles. Thus, by varying theratio of "on-time" to "off-time", the average power suppliedto the load can be controlled. The switching device eithercompletely activates or deactivates the load circuit. Inphase control circuits, the thyristor or triac is triggered intoconduction at some point after the start of each half-cycle.Control is achieved on a cycle-by-cycle basis by variationof the point in the cycle at which the thyristor is triggered.

Static switching applicationsThyristors and triacs are the ideal power switching devicesfor many high power circuits such as heaters, enabling theload to be controlled by a low power signal, in place of arelay or other electro-mechanical switch.

In a high power circuit where the power switch may connector disconnect the load at any point of the mains cycle thenlarge amounts of RFI (radio frequency interference) arelikely to occur at the instants of switching. The largevariations in load may also cause disruptions to the supplyvoltage. The RFI and voltage variation produced by highpower switching in a.c. mains circuits is unacceptable inmany environments and is controlled by statutory limits.The limits depend upon the type of environment (industrialor domestic) and the rating of the load being switched.

RFI occurs at any time when there is a step change incurrent caused by the closing of a switch (mechanical orsemiconductor). The energy levels of this interference canbe quite high in circuits suchas heating elements. However,if the switch is closed at the moment the supply voltagepasses through zero there is no step rise in current andthus no radio frequency interference. Similarly, at turn-off,a large amount of high frequency interference can becaused by di/dt imposed voltage transients in inductivecircuits.

Circuit-generated RFI can be almost completely eliminatedby ensuring that the turn-on switching instants correspondto the zero-crossing points of the a.c. mains supply. Thistechnique is known as synchronous (or zero voltage)switching control as opposed to the technique of allowingthe switching points to occur at any time during the a.c.cycle, which is referred to as asynchronous control.

In a.c. circuits using thyristors and triacs the devicesnaturally switch off when the current falls below the deviceholding current. Thus turn-off RFI does not occur.

Asynchronous control

In asynchronous control the thyristor or triac may betriggered at a point in the mains voltage other than the zerovoltage crossover point. Asynchronous control circuits areusually relatively cheap but liable to produce RFI.

Synchronous control

In synchronous control systems the switching instants aresynchronised with zero crossings of the supply voltage.They also have the advantage that, as the thyristorsconduct over complete half cycles, the power factor is verygood.This method of power control is mostly used to controltemperature. The repetition period, T, is adjusted to suit thecontrolled process (within statutory limits). Temperatureripple is eliminated when the repetition period is made muchsmaller than the thermal time constant of the system.

Figure 1 shows the principle of time-proportional control.RFI and turn-on di/dt are reduced, and the best power factor(sinusoidal load current) is obtained by triggeringsynchronously. The average power delivered to a resistiveload, RL, is proportional to ton/T (i.e. linear control) and isgiven by equation 1.

where: T is the controller repetition periodton is controller ’on’ timeV(RMS) is the rms a.c. input voltage.

Elsewhere in this handbook the operation of a controller i.c.(the TDA1023) is described. This device is specificallydesigned to implement time-proportional control of heatersusing Philips triacs.

Pout =V(RMS)

2

RL

.ton

T(1)

497


Fig. 1 Synchronous time-proportional control

Phase controlPhase control circuits are used for low power applicationssuch as lamp control or universal motor speed control,where RFI emissions can be filtered relatively easily. Thepower delivered to the load is controlled by the timing ofthe thyristor (or triac) turn-on point.

The two most common phase controller configurations are’half wave control’, where the controlling device is a singlethyristor and ’full wave control’, where the controlling deviceis a triac or a pair of anti-parallel thyristors. These twocontrol strategies are considered in more detail below:

Resistive loadsThe operation of a phase controller with a resistive load isthe simplest situation to analyse. Waveforms for a full wavecontrolled resistive load are shown in Fig. 2. The triac istriggered at angle δ, and applies the supply voltage to theload. The triac then conducts for the remainder of thepositive half-cycle, turning off when the anode current dropsbelow the holding current, as the voltage becomes zero atθ=180˚. The triac is then re-triggered at angle (180+δ)˚, andconducts for the remainder of the negative half-cycle,turning off when its anode voltage becomes zero at 360˚.

The sequence is repeated giving current pulses ofalternating polarity which are fed to the load. The durationof each pulse is the conduction angle α, that is (180-δ)˚.The output power is therefore controlled by variation of thetrigger angle δ.

For all values of α other than α=180˚ the load current isnon-sinusoidal. Thus, because of the generation ofharmonics, the power factor presented to the a.c. supplywill be less than unity except when δ=0.

For a sinusoidal current the rectified mean current, IT(AV),and the rms current, IT(RMS), are related to the peak current,IT(MAX), by equation 2.

Fig. 2 Phase controller - resistive load

where

From equation 2 the ’crest factor’, c, (also known as the’peak factor’) of the current waveform is defined as:

The current ’form factor,’ a, is defined by:

Thus, for sinusoidal currents:

For the non-sinusoidal waveforms which occur in a phasecontrolled circuit, the device currents are modified due tothe delay which occurs before the power device is triggered.Thecrest factor of equation 4and the form factor of equation5 can be used to describe variation of the currentwaveshape from the sinusoidal case.

tON

T

Inputvoltage

Triggersignal

Outputcurrent

Trigger

Conduction

angle,

Voltage

Current

Supply

voltage

Triac

Triac

Device

triggers

Trigger

angle,

O = wt

O = wt

O = wt

IT(AV) =2.IT(MAX )

π= 0.637IT(MAX )

IT(RMS) =IT(MAX )

√2= 0.707IT(MAX ) (2)

IT(MAX ) =VT(MAX )

RL

=√2V(RMS)

RL

(3)

Crest factor, c =IT(MAX )

IT(RMS)(4)

Form factor, a =IT(RMS)

IT(AV)(5)

a =IT(RMS)

IT(AV)= 1.111; c =

IT(MAX )

IT(RMS)= 1.414 (6)

498


Half wave controllerFigure 3a) shows the simplest type of thyristor half-wavephase controller for a resistive load. The load currentwaveform is given in Fig. 3b). The variation of average loadcurrent, IT(AV), rms load current, IT(RMS) and load power overthe full period of the a.c mains, with trigger angle are givenin equation 7.

N.B. When using equation 7 all values of α must be inradians. For each case the maximum value occurs whenα=180˚ (α=π radians).

At α=180˚ the crest factor and form factor for a half wavecontroller are given by:

Full wave controllerFigure 4 shows the circuit and load current waveforms fora full-wave controller using two antiparallel thyristors, or atriac, as the controlling device. The variation of rectifiedmean current, IT(AV), rms current, IT(RMS), and load power withtrigger angle are given by equation 9.

N.B. When using equation 9 all value of α must be inradians. For each case the maximum value occurs whenα=180˚ (α=π radians).

Fig. 3 Half wave control

Fig. 4 Full wave control

The variation of normalised average current, IT(AV)/IT(AV)max,rms current IT(RMS)/IT(RMS)max, and power, P(out)/P(out)max, forequations 7 and 9 are plotted in Fig. 5.

Figure 6 shows the variation of current form factor withconduction angle for the half wave controller and the fullwave controller of Figs. 3 and 4.

Fig. 5 Current and power control using conductionangle

a) b)

Trigger

Voltage

Current

Supplyvoltage

Thyristor

Thyristor

IT(MAX)

IT(AV) = IT(AV)max.(1− cosα)

2

IT(RMS) = IT(RMS)max.

α − 1

2sin2απ

1

2

P(out) = P(out)max.

α − 1

2sin2απ

IT(AV)max =IT(MAX )

π

IT(RMS)max =IT(MAX )

2

P(out)max =IT(MAX )

2 RL

4(7)

a) b)

Trigger

Voltage

Current

Supplyvoltage

Triac

Triac

I T(MAX)

I T(MAX)

a =IT(RMS)

IT(AV)= 1.571; c =

IT(MAX )

IT(RMS)= 2.0 (8)

IT(AV)IT(AV)max

IT(RMS)

IT(RMS)max

P(OUT)P(OUT)max

Am

plitu

de

Conduction angle

0 30 60 90 120 150 1800

0.2

0.4

0.6

0.8

1

IT(AV) = IT(AV)max.(1− cosα)

2

IT(RMS) = IT(RMS)max.

α − 1

2sin2απ

1

2

P(out) = P(out)max.

α − 1

2sin2απ

IT(AV)max =2IT(MAX )

π

IT(RMS)max =IT(MAX )

√2

P(out)max =IT(MAX )

2 RL

2(9)

499


Fig. 6 Variation of form factor with conduction angle

Inductive loads

The circuit waveforms for a phase controller with aninductive load or an active load (for example, a motor) aremore complex than those for a purely resistive load. Thecircuit waveforms depend on the load power factor (whichmay be variable) as well as the triggering angle.

For a bidirectional controller (i.e triac or pair of anti-parallelthyristors),maximumoutput, that is, sinusoidal loadcurrent,occurs when the trigger angle equals the phase angle.When the trigger angle, δ, is greater than the load phaseangle, ϕ, then the load current will become discontinuousand the triac (or thyristor) will block some portion of the inputvoltage until it is retriggered.

If the trigger angle is less than the phase angle then theload current in one direction will not have fallen back to zeroat the time that the device is retriggered in the oppositedirection. This is shown in Fig. 7. The triac fails to betriggered as the gate pulse has finished and so the triacthen acts as a rectifier. In Fig. 7 the triac is only triggeredby the gate pulses when the applied supply voltage ispositive (1+ quadrant). However, the gate pulses whichoccur one half period later have no effect because the triacis still conducting in the opposite direction. Thusunidirectional current flows in the main circuit, eventuallysaturating the load inductance.

This problem can be avoided by using a trigger pulse trainas shown in Fig. 8. The triac triggers on the first gate pulseafter the load current has reached the latching current IL inthe 3+ quadrant. The trigger pulse train must cease beforethe mains voltage passes through zero otherwise the triacwill continue to conduct in the reverse direction.

Fig. 7 Triac triggering signals - single pulse

Fig. 8 Triac triggering signals - pulse train

Gate circuits for thyristors and triacsAs discussed in the introductory article of this chapter, athyristor or triac can be triggered into conduction when avoltageof the appropriate polarity is appliedacross the mainterminals and a suitable current is applied to the gate. Thiscan be achieved using a delay network of the type shownin Fig. 9a). Greater triggering stability and noise immunitycan be achieved if a diac is used (see Fig. 9b). This givesa trigger circuit which is suitable for both thyristors andtriacs.

Figure 10 shows several alternative gate drive circuitssuitable for typical triac and thyristor applications. In eachcircuit the gate-cathode resistor protects the device fromfalse triggering due to noise - this is especially importantfor sensitive gate devices. In addition opto-isolated thyristorand triac drivers are available which are compatible withthe Philips range of devices.

Formfactor

I T(RMS)

I T(AV)

Conduction angle

0 30 60 90 120 150 1800

1

2

3

4

5

6

Half-wave rectifier

Full-wave rectifier

Trigger

Device failsto trigger

Conductionangle

Voltage

Current

Supplyvoltage

Triac

Triac Inductoriron coresaturation

Devicetriggers

Trigger

Conductionangle

Voltage

Current

Supplyvoltage

Triac

Triac

Devicetriggers

Devicetriggers

Fails totrigger

500


Fig. 10 Alternative triac triggering circuits

1k0

220R

BT145

Load

1k0BT145

Load

180R

10k

12V

BC337

1k0

Load

10k

12V

1k0

Load

10k

12V

BC337

4k7 100nF

BT145

BT145BAW62

2:1

a)

b)

Fig. 9 Basic triac triggering circuits

In some applications it may be necessary to cascade asensitive gate device with a larger power device to give asensitive gate circuit with a high power handling capability.A typical solution which involves triggering the smallerdevice (BT169) from a logic-level controller to turn on thelarger device (BT151) is shown in Fig. 11.

Figure 12 shows an isolated triac triggering circuit suitablefor zero voltage switching applications. This type of circuitis also known as a solid state relay (SSR). The function of

the Q1/R2/R3 stage is that the BC547 is on at all instantsin time when the applied voltage waveform is high and thusholds the BT169 off. If the BT169 is off then no gate signalis applied to the triac and the load is switched off.

Fig. 11 Master-slave thyristor triggering circuit

Fig. 12 Opto-isolated triac triggering circuit

R

E

IR

+

R

E

IR

+ BT151BT169

R

IR

+

-

R1R3

R2 R4

BC547

BT169

100R

1K0

BT138100R

100nF

Q1

501


If the input signal is switched high then the photo-transistorturns on. If this occurs when the mains voltage is high thenQ1 remains on. When the line voltage passes through itsnext zero crossing in either direction the photo transistorensures that Q1 stays off long enough for the BT169 totrigger. This then turns the triac on. Once the thyristor turnson, the drive circuit is deprived of its power due to the lowervoltage drop of the BT169. The triac is retriggered everyhalf cycle.

Voltage transient protectionThere are three major sources of transient which may affectthyristor and triac circuits:

-the mains supply (e.g. lightning)-other mains and load switches (opening and closing)-the rectifying and load circuit (commutation)

In order to ensure reliable circuit operation these transientsmust be suppressed by additional components, removedat source or allowed for in component ratings.

Three types of circuit are commonly employed to suppressvoltage transients - a snubber network across the device,a choke between the power device and external circuit oran overvoltage protection such as a varistor.

Series line chokesA series choke may be used to limit peak fault currents toassist in the fuse protection of thyristors and triacs. If thechoke is used in conjunction with fuse protection, it mustretain its inductance to very large values of current, and sofor this reason it is usually an air-cored component.Alternatively, if the choke is only required to reduce the dv/dtacross non-conducting devices then the inductance needsonly to be maintained up to quite low currents. Ferrite-coredchokes may be adequate provided that the windings arecapable of carrying the full-load current. Usually only a fewmicrohenries of inductance are required to limit the circuitdi/dt to an acceptable level. This protects the devices fromturning on too quickly and avoids potential devicedegradation.

For instance, a 220V a.c. supply with 20µH sourceinductance gives a maximum di/dt of (220√2)/20=16A/µs.Chokes used to soften commutation should preferably besaturable so as to maintain regulation and avoiddeterioration of the power factor. As their impedancereduces at high current, they have very little effect on theinrush current.

The addition of di/dt limiting chokes is especially importantin triac circuits where the load is controlled via a bridgerectifier. At the voltage zero-crossing points the conductiontransfers between diodes in the bridge network, and therate of fall of triac current is limited only by the strayinductance in the a.c. circuit. The large value ofcommutating di/dt may cause the triac to retrigger due to

commutating dv(com)/dt. A small choke in the a.c circuit willlimit the di(com)/dt to an acceptable level. An alternativetopology which avoids triac commutation problems is tocontrol the load on the d.c. side.

Snubber networks

Snubber networks ensure that the device is not exposed toexcessive rates of change of voltage during transientconditions. This is particularly important when consideringthe commutation behaviour of triacs, which has beendiscussed elsewhere.

Fig. 13 Triac protection

The following equations can be used to calculate the valuesof the snubber components required to keep the reapplieddv/dt for a triac within the dv(com)/dt rating for that device.The parameters which affect the choice of snubbercomponents are the value of load inductance, frequency ofthe a.c. supply and rms load current. The value of thesnubber resistor needs to be large enough to damp thecircuitand avoidvoltage overshoots. Thesnubbercapacitorshould be rated for the full a.c. voltage of the system. Thesnubber resistor needs to be rated at 0.5W.

For circuits where the load power factor, cosϕ, ≥ 0.7 thesnubber values are given approximately by:

where: L is the load inductancef is the supply frequencyIT(RMS) is the rms device currentdv(com)/dt is the device commutating dv/dt rating.

The presence of a snubber across the device can improvethe turn-on performance of the triac by using the snubbercapacitor discharge current in addition to the load currentto ensure that the triac latches at turn-on. The value of thesnubber resistor must be large enough to limit the peakcapacitor discharge current through the triac to within theturn-on di/dt limit of the device.

Load

SnubberVaristor

Choke

C ≥ 25L

f IT(RMS)

dV(com)/dt

2

R = √ 3LC

(9)

502


VaristorThe use of a metal oxide varistor (MOV), as shown inFig. 13, protects the device from transient overvoltageswhich may occur due to mains disturbances.

Overcurrent protectionLike all other semiconductor devices, triacs have an infinitelife if they are used within their ratings. However, theyrapidly overheat when passing excessive current becausethe thermal capacitance of their junction is small.Overcurrent protective devices (circuit breakers, fuses)must, therefore, be fast-acting.

Inrush conditionMotors, incandescent lamp or transformer loads give riseto an inrush condition. Lamp and motor inrush currents areavoided by starting the control at a large trigger angle.Transformer inrush currents are avoided by adjusting theinitial triggerangle toa value roughly equal to the load phaseangle. No damage occurs when the amount of inrushcurrent is below the inrush current rating curve quoted inthe device data sheet (see the chapter ’Understandingthyristor and triac data’).

Short-circuit condition

Fuses for protecting triacs should be fast acting, and theamount of fuse I2t to clear the circuit must be less than theI2t rating of the triac. Because the fuses open the circuitrapidly, they have a current limiting action in the event of ashort-circuit. High voltage fuses exhibit low clearing I2t butthe fuse arc voltage may be dangerous unless triacs witha sufficiently high voltage rating are used.

Conclusions

This paper has outlined the most common uses andapplications of thyristor and triac circuits. The type of circuitused depends upon the degree of control required and thenature of the load. Several types of gate circuit and deviceprotection circuit have been presented. The amount ofdevice protection required will depend upon the conditionsimposed on the device by the application circuit. Theprotection circuits presented here will be suitable for themajority of applications giving a cheap, efficient overalldesign which uses the device to its full capability withcomplete protection and confidence.

503


6.1.3 The Peak Current Handling Capability of Thyristors

The ability of a thyristor to withstand peak currents manytimes the size of its average rating is well known. However,there is little information about the factors affecting the peakcurrent capability. This section will investigate the effect ofpulse duration on the peak current capability of thyristors.

Data sheets for thyristors always quote a figure for themaximum surge current that the device can survive. Thisfigure assumes a half sine pulse with a width of either 10 msor 8.3 ms, which are the conditions applicable for 50/60 Hzmains operation. This limit is not absolute; narrow pulseswith much higher peaks can be handled without damagebut little information is available to enable the designer todetermine how high this current is. This section will discusssome of the factors affecting a thyristor’s peak currentcapability and review the existing prediction methods. It willgo on to present the results of an evaluation of the peakcurrent handling capabilities for pulses as narrow as 10 µsfor the BT151, BT152 and BT145 thyristors. It will alsopropose a method for estimating a thyristor’s peak currentcapability for ahalf sine pulsewith a durationbetween 10 µsand 10 ms from its quoted surge rating.

Energy Handling

In addition to the maximum surge current, data sheets oftenquote a figure called "I2t for fusing". This number is used toselect appopriate fuses for device protection. I2t representsthe energy that can be passed by the device withoutdamage. In fact it is not the passage of the energy whichcauses damage, but the heating of the crystal by the energyabsorbed by the device which causes damage.

If the period over which the energy is delivered is long, theabsorbed energy has time to spread to all areas of thedevice capable of storing it - like the edges of the crystal,the plastic encapsulation, the mounting tab and for verylong times the heatsink - therefore the temperature rise inthe crystal is moderated. If, however, the delivery period isshort - say a single half sine pulse of current with a durationof <10 ms - the areas to which the energy can spread forthe actual duration of the pulse are limited. This means thatthe crystal keeps all the energy giving a much biggertemperature rise. For very short pulses (<0.1 ms) and largecrystal, the problem is even worse because not all of theactive area of a thyristor crystal is turned on simultaneously- conduction tends to spread out from the gate area - sothe current pulse passes through only part of the crystalresulting in a higher level of dissipation and an even morerestricted area for absorbing it.

Expected ResultsI2t is normally quoted at 10 ms, assuming that the surge isa half sine pulse, and is derived from the surge current from:

This calculates the RMS current by dividing by

Under the simplest of analyses I2t would be assumed to beconstant so a device’s peak current capability could becalculated from:

where Ipk is the peak of a half sine current pulse with aduration of tp. However, experience and experiments haveshown that such an approach is inaccurate. To overcomethis, other ’rules’ have been derived.

One of these ’rules’ suggests that it is not I2t which isconstant but I3t or I4t. Another suggestion is that the’constancy’ continuously changes from I2t to I4t as thepulses become shorter. All these rules are expressed in thegeneral equation:

where is N is either constant or a function of the pulse width,for example:

The graph shown in Fig. 1 shows what several of these’rules’ predict would happen to the peak current capabilityif they were true. Unfortunately little or no real informationcurrently exists to indicate the validity of these rules. Testshave been performed on three groups of devices - BT151,BT152 and BT145 - to gather the data which would,hopefully, decide which was correct.

Test CircuitThe technique chosen to measure the peak currentcapability of the devices was the stepped surge method. Inthis test, the device is subjected to a series of current pulsesof increasing magnitude until it receives a surge whichcauses measurable degradation.

I 2t =

ITSM

√2

2

0.01

√2ITSM

Ipk = ITSM

0.01tp

1

2

Ipk = ITSM

0.01tp

1

N

N = log

1tp

505


Fig. 1 Predicted ITSM multiplying factors

Circuit Description

The circuits used to perform the required measurementswere of the form shown in Fig. 2. They produce half sinepulses of current from the resonant discharge of C via L.Triggering of the device under test (DUT) itself is used toinitiate the discharge. The gate signal used for all the testswas a 100 mA / 1 µs pulse fed from a pulse generator insingle-shot mode.

The magnitude of the current pulse is adjusted by changingthe voltage to which C is initially charged by varying theoutput of the PSU. The pulse is monitored by viewing thevoltage across R3 on an digital storage oscilloscope. R1and D protect the power supply. R1 limits the current fromthe supply when DUT fails and during the recharging of C.D attempts to prevent any high voltage spikes being fedback into the PSU.

Fig. 2 Surge current test circuit

Pushbutton S1 and resistor R2 are a safety feature. R2keeps C discharged until S1 is pressed. The trigger pulseneeds a button on the pulse generator to be pressed whichmeans both hands are occupied and kept away from thetest circuit high voltages.

Choice of L & CThe width of the half sine pulse from an LC circuit is:

and the theoretical peak value of the current is:

These equations assume that the circuit has no seriesresistance to damp the resonant action which would resultin a longer but lower pulse. Minimising these effects wasconsidered to be important so care was taken during thebuilding of the circuits to keep the resistance to a minimum.To this end capacitors with low ESR were chosen, theinductors were wound using heavy gauge wire and the loopC / L / DUT / R3 was kept as short as possible.

It was decided to test the devices at three different pulsewidths - 10 µs, 100 µs and 1 ms - so three sets of L and Cwere needed. The values were selected with the help of a’spreadsheet’ program running on an PC compatiblecomputer. The values which were finally chosen are shownin Table 1. Also given in Table 1 are the theoretical peakcurrents that the L / C combination would produce for ainitial voltage on C of 600 V.

Test ProcedureAs mentionedearlier, the test method called for each deviceto be subjected to a series of current pulses of increasingamplitude. The resolution with which the current capabilityis assessed is defined by the size of each increase incurrent. It was decided that steps of approximately 5%would give reasonable resolution.

Experimentation indicated that the clearest indication ofdevice damage was obtained by looking for changes in theoff-state breakdown voltage. So after each current pulsethe DUT was removed from the test circuit and checked ona curve tracer. This procedure did slow the testing but itwas felt that it would result in greater accuracy.

Pulse Width C (µF) L (µH) Ipeak (A)

10 µs 13.6 0.75 2564

100 µs 100 10 1885

1 ms 660 154 1244

Table 1. Inductor and Capacitor Values

It was also decided that, since this work was attempting todetermine the current that a device could survive - not whichkilled it, the figure actually quoted in the results for adevice’scurrent capability would be the value of the pulse prior tothe one which caused damage.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1 10us 100us 1ms 10ms

Width of Half Sine Pulse

I t = const.I t = const.

I t = const.I t = const.log(1/t)

2

3

4

Pea

k C

urre

nt M

ultip

lyin

g F

acto

r

tpulse = π √L C

Ipeak = V √ CL

DC PSU

0-600V

DR1 L

CR2

DUT

R3

S1 Vak

Trigger

Ia

Pulse

506


Fig. 3 Peak current capability measurements

Test ResultsFigure 3 is a graph showing the measured currentcapabilities of all of the tested devices. Table 2 summarisesthe measurements by giving the mean of the results for thethree device types at each of the pulse widths. Table 3expresses the mean values as factors of the device ITSM

rating. This table also gives the factors that the various’rules’ would have predicted for the various pulse widths.

Mean Peak Current Capability (Amps)

Pulse Width BT151 BT152 BT145

10 µs 912 1092 1333

100 µs 595 1021 1328

1 ms 264 490 697

Table 2. Measured Current Capability

Measured Predicted FactorFactor (by Int rule)

Pulse BT BT BT n=2 n=3 n=4 n=Width 151 152 145 log(1/t)

10 µs 9.1 5.5 4.4 31.6 10.0 5.6 4.0

100 µs 6.0 5.1 4.4 10.0 4.6 3.2 3.2

1 ms 2.6 2.4 2.3 3.2 2.2 1.8 2.2

Table 3. Measured and Predicted ITSM MultiplicationFactors

Interpretation of ResultsIt had been hoped that the measurements would give clearindication of which of the ’rules’ would give the mostaccurate prediction of performance. However, aninspection of Table 3 clearly shows that there is no

correlation between any of the predicted factors and themeasured factors. In fact the variation in the factorsbetween the various device types would indicated that norule based on an Int function alone can give an accurateprediction. This implies that something else will have to betaken into account.

Furtherstudy of Fig. 3 reveals that the difference in the peakcurrent capability of the three device types is becoming lessas the pulses become shorter. This could be explained bya reduction in the active area of the larger crystals, makingthem appear to be smaller than they actually are. This isconsistent with the known fact that not all areas of a thyristorturn on simultaneously - the conduction region tends tospread out from the gate. If the pulse duration is less thanthe time it takes for all areas of the device to turn on, thenthe current flows through only part of the crystal, reducingthe effective size of the device. If the rate at which theconduction area turns on is constant then the time takenfor a small device to be completely ON is shorter than fora large device. This would explain why the performanceincrease of the BT145 starts falling off before that of theBT151.

Proposed Prediction MethodThe above interpretation leads one to believe that theoriginal energy handling rule, which says that I2t is aconstant, may still be correct but that the performance itpredicts will ’roll off’ if the pulse duration is less than somecritical value. The equation which was developed to havethe necessary characteristics is:

which simplifies to:-

where tcrit is proportional to - but not necessarily equal to -the time taken to turn on all the active area of the crystaland is calculated from:-

where: A = crystal areaR = constant expressing the rate at which the areais turned on.

Preferably, A should be the area of the cathode but thisinformation is not always available. As an alternative thetotal crystal area can be used if the value of R is adjustedaccordingly. This will inevitably introduce an error becausecathode and crystal areas are not directly proportional, butit should be relatively small.

#####

########

#####

@@@@ @@@@@@

@

@@@@

*** ******

*

***

****

10us 100us 1ms 10ms100

1000

Width of half-sine pulse

Pea

k C

urre

nt (

amps

)

# BT151 @ BT152 * BT145

Ipk = ITSM

0.01tp

1

2

tp

tp + tcrit

1

2

Ipk = ITSM √

0.01tp + tcrit

tcrit =AR

507


R was determinedempirically tobe approximately 0.02 m2/sUsing this value of R gives the values of tcrit shown in Table3. Using these values in the above equation predicts thatthe peak current handling capability of the BT151, BT152and BT145 would be as shown in Fig. 4.

Device tcrit

BT151 148 µsBT152 410 µsBT145 563 µs

Table 3. Calculated Values of tcrit

ConclusionsThe first conclusion that can be drawn from this work is thata thyristor, with average rating of only 7.5A, is capable ofconducting, without damage, a peak current greater than100 times this value in a short pulse. Furthermore the powerrequired to trigger the device into conducting this currentcan be <1 µW. This capability has always been known andindeed the surge rating given in the data sheet gives a valuefor it at pulse widths of around 10 ms. What has beenmissing is a reliable method of predicting what the peakcurrent capability of a device is for much shorter pulses.

The results obtained using the test methods indicate thatthe previously suggested ’rules’ fail to take into account theeffect that crystal size has on the increase in performance.

In this section, an equation has been proposed which takescrystal size into account by using it to calculate a factorcalled tcrit. This time is then used to ’roll off’ the performanceincrease predicted by the original energy handlingequation - I2t = constant. This results in what is believedto be a more accurate means of estimating the capabilityof a device for a half sine pulse with a duration between10 µs and 10 ms.

Fig. 4 Predicted peak current handling using ’Rolled-offI2t’ rule

Width of half-sine pulse

Pea

k C

urre

nt (

amps

)

BT151 BT152 BT145

10us 100us 1ms 10ms100

1000

508


6.1.4 Understanding Thyristor and Triac Data

The importance of reliable and comprehensive data forpower semiconductor devices, together with theadvantages of the absolute maximum rating system, isclear. This present article describes the data sheetdescriptions of Philips thyristors and triacs, and aims toenable the circuit designer to use our published data to thefull and to be confident that it truly describes theperformance of the devices.

A brief survey of short-form catalogues is an insufficientmethod of comparing different devices. Published ratingsand characteristics require supporting information to trulydescribe the capabilities of devices; thus comparisonsbetween devices whose performance appears to be similarshould not be made on economic grounds alone.Manufacturers have been known to quote ratings in sucha way as to give a false impression of the capabilities oftheir devices.

Ratings and characteristics given in published data shouldalways be quoted with the conditions to which they apply,and these conditions should be those likely to occur inoperation. Furthermore, it is important to define the ratingor characteristic being quoted. Only if data is both completeand unambiguous can a true comparison be made betweenthe capabilities of different types.

ThyristorsThyristor is a generic term for asemiconductor device whichhas four semiconductor layers and operates as a switch,having stable on and off states. A thyristor can have two,three, or four terminals but common usage has confinedthe term thyristor to three terminal devices. Two-terminaldevices are known as switching diodes, and four-terminaldevices are known as silicon controlled switches. Thecommon, or three-terminal, thyristor is also known as thereverse blocking triode thyristor or the silicon controlledrectifier (SCR). Fig. 1 shows the circuit symbol and aschematic diagram of the thyristor. All Philips thyristors arep-gate types; that is, the anode is connected to the metaltab.

The thyristor will conduct a load current in one directiononly, as will a rectifier diode. However, the thyristor will onlyconduct this load current when it has been ’triggered’; thisis the essential property of the thyristor.

Fig. 2 shows the static characteristic of the thyristor. Whena small negative voltage is applied to the device, only asmall reverse leakage current flows. As the reverse voltageis increased, the leakage current increases until avalanchebreakdown occurs. If a positive voltage is applied, thenagain a small forward leakage current flows whichincreases as the forward voltage increases. When the

forward voltage reaches the breakover voltage V(BO),turn-on is initiated by avalanche breakdown and the voltageacross the thyristor falls to the on state voltage VT.

However, turn-on can occur when the forward(anode-to-cathode) voltage is less than V(BO) if the thyristoris triggered by injecting a pulse of current into the gate. Ifthe device is to remain in the on state, this trigger pulsemust remain until the current through the thyristor exceedsthe latching current IL. Once the on state is established, theholding current IH is the minimum current that can flowthrough the thyristor and still maintain conduction. The loadcurrent must be reduced to below IH to turn the thyristor off;for instance, by reducing the voltage across the thyristorand load to zero.

Fig. 1 Thyristor circuit symbol and basic structure

Fig. 2 Thyristor static characteristic

Thyristors are normally turned on by triggering with a gatesignal but they can also be turned on by exceeding eitherthe forward breakover voltage or the permitted rate of rise

Anode Anode

Gate

Gate

Cathode Cathode

p

n

p

n

On-statecharacteristic

Off-statecharacteristic

Avalanchebreakdownregion

Reversecharacteristic

Reversecurrent

Forwardcurrent

Reversevoltage

Forwardvoltage

ILIH

V(BO)

509


of anode voltage dVD/dt. However, these alternativemethods of switching to the conducting state should beavoided by suitable circuit design.

Triacs

The triac, or bidirectional triode thyristor, is a device thatcan be used to pass or block current in either direction. Itis therefore an a.c. power control device. It is equivalent totwo thyristors in anti-parallel with a common gate electrode.However, it only requires one heatsink compared to the twoheatsinks required for the anti-parallel thyristorconfiguration. Thus the triac saves both cost and space ina.c. applications.

Figure 3 shows the triac circuit symbol and a simplifiedcross-section of the device. The triac has two mainterminals MT1 and MT2 (the load connections) and a singlegate. The main terminals are connected to both p and nregions since current can be conducted in both directions.The gate is similarly connected, since a triac can betriggered by both negative and positive pulses.

Fig. 3 Triac circuit symbol and basic structure

Fig. 4 Triac static characteristic

The on state voltage/current characteristic of a triacresembles that of a thyristor. The triac static characteristicof Fig. 4 shows that the triac is a bidirectional switch. Thecondition when terminal 2 of the triac is positive with respectto terminal 1 is denoted in data by the term ’T2+’. If the triacis not triggered, the small leakage current increases as thevoltage increases until the breakover voltage V(BO) isreached and the triac then turns on. As with the thyristor,however, the triac can be triggered below V(BO) by a gatepulse, provided that the current through the device exceedsthe latching current IL before the trigger pulse is removed.The triac, like the thyristor, has holding current values belowwhich conduction cannot be maintained.

When terminal 2 is negative with respect to terminal 1 (T2-)the blocking and conducting characteristics are similar tothose in the T2+ condition, but the polarities are reversed.The triac can be triggered in both directions by eithernegative (G-) or positive (G+) pulses on the gate, as shownin Table 1. The actual values of gate trigger current, holdingcurrent and latching current may be slightly different in thedifferent operating quadrants of the triac due to the internalstructure of the device.

Quadrant Polarity of T2 wrt T1 Gate polarity

1 (1+) T2+ G+2 (1-) T2+ G-3 (3-) T2- G-4 (3+) T2- G+

Table 1. Operating quadrants for triacs

Device data

Anode to cathode voltage ratingsThe voltage of the a.c. mains is usually regarded as asmooth sinewave. In practice, however, there is a varietyof transients, some occurring regularly and others onlyoccasionally (Fig. 5). Although some transients may beremoved by filters, thyristors must still handle anode tocathode voltages in excess of the nominal mains value.

The following reverse off-state voltage ratings are given inour published data:

VRSM: the non-repetitive peak reverse voltage. This is theallowable peak value of non-repetitive voltage transients,and is quoted with the maximum duration of transient thatcan be handled (usually t < 10ms).

VRRM: the repetitive peak reverse voltage. This is theallowable peak value of transients occurring every cycle.

VRWM: the peak working reverse voltage. This is themaximum continuous peak voltage rating in the reversedirection, neglecting transients. It corresponds to the peaknegative value (often with a safety factor) of the sinusoidalsupply voltage.

MT1

MT2

Gate Gate

MT1

MT2

n

n

n

n

p

p

Reversecurrent

Forwardcurrent

Reversevoltage

Forwardvoltage

IHIL

V(BO)

Blocking

Blocking

ILIHV(BO)

T2+

T2-

510


Fig. 5 Diagrammatic voltage waveform showing deviceanode voltage ratings

The forward off-state voltages corresponding to VRSM, VRRM

and VRWM are listed below.

VDSM: the non-repetitive peak off-state voltage applied inthe forward direction.

VDRM: the repetitive peak off-state voltage applied in theforward direction.

VDWM: the peak working off-state voltage applied in theforward direction.

Both the repetitive and non-repetitive voltage ratings aredetermined partly by the voltage limit that prevents thethyristor being driven into forward or reverse breakdown,and partly by the instantaneous energy (resulting from anincrease in leakage current) that can be dissipated in thedevice without exceeding the rated junction temperature.

Whena thyristor is to operate directly fromthe mains supply,it is advisable to choose a device whose repetitive peakvoltage ratings VRRM and VDRM are at least 1.5 times the peakvalue of the sinusoidal supply voltage. This figure formspart of the device type number; for example BT151-650R,where 650 corresponds to VDRM, VRRM=650V and the finalR (for Reverse) indicates that the anode of the device isconnected to the metal tab.

Anode-to-cathode current ratingsThe following current ratings, described by the waveformsshown in Fig. 6, are given in our published data. Note thatthe suffix T implies that the thyristor is in the on state.

IT(AV): the average value of the idealised mains currentwaveform taken over one cycle, assuming conduction over180˚. For devices mounted on heatsinks, the IT(AV) ratingshould be quoted for a particular mounting-basetemperature Tmb; our devices are generally characterisedat a mounting-base temperature of at least 85˚C. A devicecan have an artificially high current rating if the

mounting-base temperature is unrealistically low; ratingswith no associated mounting-base temperature should beregarded with suspicion.

IT(RMS): the rms on-state current. This rating gives themaximum rms current that the thyristor can handle. It isimportant for applications when the device currentwaveform is described by a high value form factor. For suchconditions the rms current rather than the average currentmay be the limiting rating.

ITRM: the repetitive peak forward current. This rating is thepeak current that can be drawn each cycle providing thatthe average and rms current ratings are not exceeded.

ITSM: the non-repetitive (surge) peak forward current. Thisrating is the peak permitted value of non-repetitivetransients, and depends on the duration of the surge. Ourpublished data quotes the ITSM rating for t=10ms, theduration of a half-cycle of 50Hz mains. However, somemanufacturers quote ITSM for t=8.3ms (half-cycle of 60Hzmains), and thus surge ratings for devices quoted att=8.3ms should be approximately downrated (multiplied by0.83) before comparing them with t=10ms surge ratings.

The surge rating also depends on the conditions underwhich it occurs. Our data sheets quote ITSM rating under theworst probable conditions, that is, Tj=Tj(max) immediatelyprior to the surge, followed by reapplied VRWM(max)

immediately after the surge. An unrealistically high ITSM

rating could be quoted if, for example, Tj<Tj(max) prior to thesurge and then the full rated voltage is not reapplied.

Published data also includes curves for ITSM against timewhich show the maximum allowable rms current which canoccur during inrush or start-up conditions. The duration ofthe inrush transient and the mounting base temperatureprior to operation determine the maximum allowable rmsinrush current.

Fig. 6 Diagrammatic current waveform showing deviceanode current ratings

VD

VDSM

VDRM

VDWM

VRWM

VRRM

VRSM

VR

Time

Mainswaveform

IT

ITSM

ITRM

IT(RMS)

IT(AV)

Time

511


dI/dt: the rate of rise of on-state current permissible aftertriggering. An excessive rate of rise of current causes localheating and thus damage to the device. The rate of rise ofcurrent is determined by both the supply and loadimpedances, and can be limited by additional seriesinductance in the circuit.

Fig. 7 Non-repetitive surge current as a function of time

I2t: a dimensional convenience specifying the capability ofa thyristor to absorb energy. This rating is required for theselection of fuses to protect the thyristor against excessivecurrents caused by fault conditions. It is normally only validover the range 3 to 10ms. In our published data, a value isquoted for 10ms, in which case:

The user should match the minimum I2t capability of thethyristor to the worst case I2t let-through of a range ofnominally rated fuses in order to select a fuse that willprotect the device under worst probable conditions.

Values of I2t other than those quoted for 10ms can beestimated by referring to the appropriate published curvesof non-repetitive surge current against time. For example,Fig. 7 is the non repetitive surge current curve for a thyristorwhose I2t at 10ms is 800A2s. From Fig. 7, ITS(RMS) at 3ms is470A and therefore I2t at 3ms is given by:

To summarise, when selecting an appropriate fuse thefollowing conditions must be taken into account.

1. The fuse must have an rms current rating equal to, orless than, that of the thyristor it is to protect.

2. The I2t at the rms working voltage must be less thanthat of the thyristor taken over the fuse operating time.

3. The arc voltage of the fuse must be less than the VRSM

rating of the thyristor.

Gate-to-cathode ratingsThe following gate-to-cathode ratings are given in thepublished data.

VRGM: the gate peak reverse voltage.

PG(AV): the mean gate power, averaged over a 20ms period.

PGM: the peak gate power dissipation.

The gate-to-cathode power ratings should not be exceededif over-heating of the gate-cathode junction is to be avoided.

Temperature ratingsTwo temperature ratings are given in the published data.

Tstg : the storage temperature. Both maximumand minimumvalues of the temperature at which a device can be storedare given.

Tj: the junction temperature. This is one of the principalsemiconductor ratings since it limits the maximum powerthat a device can handle. The junction temperature ratingquoted in our published data is the highest value of junctiontemperature at which the device may be continuouslyoperated to ensure a long life.

Thermal characteristicsThe following thermal resistances and impedances aregiven in our data.

Rth(j-a) : the thermal resistance between the junction of thedevice and ambient (assumed to be the surrounding air).

Rth(j-mb) : the thermal resistance between the junction andmounting base of the device.

Rth(mb-h) : the thermal resistance between the mounting baseof the device and the heatsink (contact thermal resistance).

Zth(j-mb) : the transient thermal impedance between thejunction and mounting-base of the device. The value givenin the published data is for non-repetitive conditions and aparticular pulse duration. Under pulse conditions, thermalimpedances rather than thermal resistances should beconsidered. Higher peak power dissipation is permittedunder pulse conditions since the materials in a thyristorhave a definite thermal capacity, and thus the criticaljunction temperature will not be reached instantaneously,even when excessive power is being dissipated in thedevice. The published data also contains graphs of Zth(j-mb)

against time (for non-repetitive conditions) such as thoseshown in Fig. 8.

0.001 0.003 0.01 0.03 0.1 0.3 1 3 100

100

200

300

400

500

600

Duration (s)

ITS(RMS)

I 2t = ⌠⌡ i 2.dt (1)

=

ITSM

√2

2

× 10.10−3 (A2s)

I 2t (3ms) = ITS(RMS)2 × t

= 4702 × 3.10−3

= 662.7A2s

512


Fig. 8 Thermal impedance between the junction andmounting-base as a function of time

The values of the various thermal resistances between thethyristor junction and the surroundings must be consideredto ensure that the junction temperature rating is notexceeded. The heat generated in a semiconductor chipflows by various paths to the surroundings. Fig. 9 showsthe various thermal resistances to be taken into account inthis process. With no heatsink, the thermal resistance fromthe mounting-base to the surroundings is given by Rth(mb-a).When a heatsink is used, the heat loss direct to thesurroundings from the mounting-base is negligible owingto the relatively high value of Rth(mb-a) and thus:

Fig. 9 Heat flow paths

Rth(mb-a) = Rth(mb-h) + Rth(h-a) (2)

Where appropriate, our published data contains powergraphs such as that in Fig. 10. These characteristics relatethe total power P dissipated in the thyristor, the averageforward current IT(AV), the ambient temperature Ta, and thethermal resistance Rth(mb-a), with the form factor, a, as aparameter. They enable the designer to work out therequired mounting arrangement from the conditions underwhich the thyristor is to be operated.

1E-05 0.0001 0.001 0.01 0.1 1 100.001

0.003

0.01

0.03

0.1

0.3

1

3

10

Time (s)

Z th(j-mb) (K/W) Tj

Tmb

Th

Ta

Rth(j-mb)

R’th(mb-a)

Rth(mb-h)

Rth(h-a)

Fig. 10 Derivation of the appropriate Rth(mb-a) for a given value of IT(AV), a and Tamb

0 5 10 15 200

5

10

15

20

25

30

35

40

45

50

0 20 40 60 80 100 120125

120

115

110

105

100

95

90

85

80

75

a=4

a=2.8 2.2 1.9 1.6

Rth(mb-a)

=0.5K/W1K/W2K/W

3

4

6

10

P(W) Tmb (oC)

IT(AV) (A) Ta( oC)

513


Usually, the characteristics are designed for use in 50Hzsinusoidal applications, when the procedure below shouldbe followed.

1. Determine the values of IT(AV) and IT(RMS) for the relevantapplication.

2. Determine the form factor, which is given by:

3. Starting from the appropriate value of IT(AV) on a curvesuch as Fig. 10, move vertically upwards to intersectthe appropriate form factor curve (interpolating ifnecessary).

4. This intersection gives the power dissipated in thethyristor on the left-hand axis of the combined graphand the mounting base temperature on the right handaxis.

5. Moving horizontally across from this intersection to theappropriate value of ambient temperature gives therequired mounting base to ambient thermal resistanceRth(mb-a).

6. The required heatsink thermal resistance Rth(h-a) cannow be calculated from Equation 2 since the mountingbase to heatsink thermal resistance Rth(mb-h) is given inthe published data.

Example

The thyristor to which Fig. 10 applies is operated at anaverage forward current IT(AV) of 12A and an rms forwardcurrent IT(RMS) of 19.2A. The maximum anticipated ambienttemperature is 25˚C. Now, Equation 3 gives,

Figure 10 gives the power as P=20W and themounting-base temperature as Tmb=105˚C. Also, at thispower and ambient temperature of 25˚C, Fig. 10 gives thevalue of Rth(mb-a) to be 4˚C/W. The published data gives thevalue of Rth(mb-h) (using a heatsink compound) to be 0.2˚C/Wand then Equation 2 gives

Mounting torqueTwo values of mounting torque are given in the publisheddata. A minimum value is quoted below which the contactthermal resistance rises owing to poor contact, and amaximum value is given above which the contact thermalresistance again rises owing to deformation of the tab orcracking of the crystal.

Fig. 11 Forward current vs. forward voltage

The surface of a device case and heatsink cannot beperfectly flat, and thus contact will take place on severalpoints only, with a small air-gap over the rest of the contactarea. The use of a soft substance to fill this gap will lowerthe contact thermal resistance. We recommend the use ofproprietary heatsinking compounds which consist of asilicone grease loaded with an electrically insulating andgood thermal conducting powder such as alumina.

Anode-to-cathode characteristicsThe following anode-to-cathode characteristics areincluded in the published data.

IR: the reverse current. This parameter is given for the worstprobable conditions; that is, the reverse voltageVR=VRWM(max) and a high Tj.

ID: the off-state current. This parameter is again given forthe worst probable conditions; that is, the forward voltageVD=VDWM(max) and a high Tj.

IL: the latching current (Fig. 2). This parameter is quoted ata particular value of junction temperature.

IH: the holding current (Fig. 2). This parameter is quoted ata particular value of junction temperature.

VT: the forward voltage when the thyristor is conducting.This parameter is measured at particular values of forwardcurrent and junction temperature. The junction temperatureis usually low (Tj=25˚C, for example) since this is the worstcase. The measurement must be performed under pulseconditions to maintain the low junction temperature. Thepublished data also contains curves of forward currentagainst forward voltage, usually for two values of thejunction temperature: 25˚C and Tj(max) (Fig. 11).

0 0.2 0.4 0.6 0.8 1.00

1.0

2.0

3.0IF(A)

VF(V)

MAX

TYP

25 C

150 C

a =IT(RMS)

IT(AV)(3)

a =19.212

= 1.6

Rth(h − a) = 4− 0.2= 3.8°C/W

514


Fig. 12 Definition of rate of rise of off-state voltagedVD/dt

dV/dt: the rate of rise of off-state voltage that will not triggerany device. This parameter is given at maximum values ofjunction temperature Tj(max) and forward voltageVD=VDRM(max).

The values of dVD/dt quoted in our published data arenormally specified assuming an exponential waveform.This facilitates the design of RC snubber circuits for deviceprotection when required. Fig. 12 illustrates the definitionof dVD/dt. The final voltage applied to the device VDM ischosenas VDRM(max) and the junction temperature is Tj=Tj(max).

Fig. 12 shows that dVD/dt is given by the expression:

where T is the exponential time constant.

The dVD/dt capability of a thyristor increases as the junctiontemperature decreases. Thus curves such as those shownin Fig. 13a) are provided in the published data so thatdesigners can uprate devices operated at lower junctiontemperatures.

The dVD/dt characteristic can also be increased byoperating the device at a low supply voltage. Thus thepublished data also contains curves such as Fig. 13b)which shows how dVD/dt increases as the ratio VDM/VDRM

max decreases. Note that VDM is unlikely to be greater than2/3VDRM(max) (usually owing to the restriction of VDWM(max)) andtherefore the fact that dVD/dt approaches zero as VDM

increases above the value of 2/3VDRM(max) does not causeproblems.

dVDdt

VDM

0.63V DM

T 2T 3T 4T Time

dVD

dt=

0.63VDM

T

=0.63× 2/3VDRM(max)

T

=0.42VDRM(max)

T(V/µs)

a) Junction temperature, Tj b) Applied voltage, VD

Fig. 13 Derating of maximum rate of rise of off-state voltage

0 20 40 60 80 1000

200

400

600

800

1,000

1,200

1,400

Exp l

dVDdt

Exp l

dVDdt

Ratingpoint

Ratingpoint

Tj

( o C) VD /VDRM(max) (%)20 40 60 80 100 120 140

0

250

500

750

1,000

1,250

1,500

1,750

2,000

515


a) Minimum VGT that will trigger all devices b) Minimum IGT that will trigger all devices

Fig. 14 Gate characteristics vs. junction temperature

-50 0 50 100 150Tj ( C)

VGT (V)3

2

1

0 0

50

100

150

0 50 100 150-50

IGT (mA)

Tj ( C)Tj ( C)

Gate-to-cathode characteristicsThe following gate-to-cathode characteristics are given inthe published data.

VGT: the gate-to-cathode voltage that will trigger all devices.This characteristic should be quoted for particular valuesof applied voltage VD and low junction temperature.

IGT: the gate-to-cathode current that will trigger all devices.This characteristic should be quoted for the sameconditions given above.

A gate drive circuit must be designed which is capable ofsupplyingat least the required minimum voltageand currentwithout exceeding the maximum power rating of the gatejunction. Curves such as those shown in Fig. 14 (whichrelate the minimum values of VGT and IGT for safe triggeringto the junction temperature) are provided in data. Thefollowing design procedure is recommended to construct agate drive circuit load-line on the power curves shown inFig. 15.

1. Determine the maximum average gate powerdissipation PG(AV) from the published data (normally0.5W, 1.0W, or 2.0W) and then use the appropriatechoice of x-axis scaling in Fig. 15.

2. Estimate the minimum ambient temperature at whichthe device will operate, and then determine theminimum values of VGT and IGT from curves such asFigs. 14a) and 14b) in the published data. Note that itis assumed that at switch-on Tj=Ta.

3. Determine the minimum open-circuit voltage of thetrigger pulse drive circuit: this is the first co-ordinate onthe load line at IG=0.

4. Using the appropriate horizontal scaling for the device(PG(AV)=0.5W, 1.0W or 2.0W), plot a second point on thepower curve whose co-ordinates are given by VGT(min)

and 5×IGT(min). Construct a load line between these twopoints. The slope of this load gives the maximumallowable source resistance for the drive circuit.

5. Check the power dissipation by ensuring that the loadline must not intersect the curve for the maximum peakgate power PGM(max) which is the outermost (δ=0.1) curveofFig. 15. The load line must also not intersect the curvewhich represents the maximum average gate powerPG(AV) modified by the pulse mark-space ratio, where:

For instance, in Fig. 15, for a thyristor with PG(AV)=1W,the δ=0.25 curve can be used for a gate drive with a 1:3mark-space ratio giving an allowable maximum gatepower dissipation of PGM(max)=4W.

An illustration of how the above design procedure operatesto give an acceptable gate drive circuit is presented in thefollowing example.

Example

A thyristor has the VGT/Tj and IGT/Tj characteristics shownin Fig. 14 and is rated with PG(AV)=0.5W and PGM(max)=5W. Asuitable trigger circuit operating with δmax=0.25,VGT(min)=4.5V, IGT(max)=620mA and Ta(min)=-10˚C is to bedesigned. Determine its suitability for this device.

PGM(max) =PAV

δ(5)

516


Fig. 15 Gate circuit design procedure - power curves

0

2.5

5.0

7.5

10.0

12.5

15.0

17.5

20.0

22.5

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0

= 0.100= 0.111= 0.125= 0.143= 0.167= 0.200= 0.250= 0.333= 0.500= 1.000

Gate current, IG

(A)

Gate voltage, VG

(V)

(PG(AV)=0.5W)

(PG(AV)=1.0W)

(PG(AV)=2.0W)

A

B C

1. Select the top x-axis scale of Fig. 15 (PG(AV)=0.5W).

2. From Fig. 14, VGT(min)=1.75V, and IGT(min)=66mA.

3. At minimum supply voltage, the open-circuit gatevoltage is 4.5V, giving point ’A’ in Fig. 15. Point B isplotted at the co-ordinates VGT(min) and 5xIGT(min), that isat 1.75V and 330mA, and load line ABC is constructedas shown. Note that point C is the maximum currentrequired at IG=570mA and is within the capability of thedrive circuit.

4. As required the load line does not intersect the PG(max)

(δ=0.1). The gate drive duty cycle, δ, is 0.25. ThereforePGM(max) = PG(AV)/δ = 0.5/0.25 = 2W. As required, the loadline ABC does not intersect the δ=0.25 curve.

Switching characteristicsTwo important switching characteristics are usuallyincluded in our published data. They are the gate-controlledturn-on time tgt (divided into a turn-on delay time, td, and arise time, tr) and the circuit-commutated turn-off time, tq.

Gate-controlled turn-on time, t gt

Anode current does not commence flowing in the thyristorat the instant that the gate current is applied. There is aperiod which elapses between the application of the trigger

pulse and the onset of the anode current which is knownas the delay time td (Fig. 16). The time taken for the anodevoltage to fall from 90% to 10% of its initial value is knownas the rise time tr. The sum of the delay time and the risetime is known as the gate-controlled turn-on time tgt.

The gate controlled turn-on time depends on the conditionsunder which it is measured, and thus the followingconditions should be specified in the published data.

-Off-state voltage; usually VD=VDWM(max).-On-state current.-Gate trigger current; high gate currents reduce tgt.-Rate of rise of gate current; high values reduce tgt.-Junction temperature; high temperatures reduce tgt.

Circuit-commutated turn-off time

When a thyristor has been conducting and isreverse-biased, it does not immediately go into the forwardblocking state: minority charge carriers have to be clearedaway by recombination and diffusion processes before thedevice can block reapplied off-state voltage. The time fromthe instant that the anode current passes through zero tothe instant that the thyristor is capable of blocking reappliedoff-state voltage is the circuit-commutated turn-off time tq(Fig. 17).

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Fig. 16 Thyristor gate-controlled turn-on characteristics

Fig. 17 Thyristor turn-off characteristics

The following conditions should be given when tq is quoted.

-On-state current; high currents increase tq.-Reverse voltage; low voltages increase tq.-Rate of fall of anode current; high rates increase tq.-Rate of rise of reapplied off-state voltage; high ratesincrease tq.-Junction temperature; high temperatures increase tq.-Gate bias; negative voltages decrease tq.

Triac ratingsThe ratings and characteristics of the triac are similar tothose of the thyristor, except that the triac does not haveany reverse voltage ratings (a reverse voltage in onequadrant is the forward voltage in the opposite quadrant).However, one characteristic requires special attentionwhen choosing triacs; the rate of re-applied voltage that thetriac will withstand without uncontrolled turn-on.

If a triac is turned off by simply rapidly reversing the supplyvoltage, the recovery current in the device would simplyswitch iton in the opposite direction. Toguarantee reductionof the current below its holding value, the supply voltagemust be reduced to zero and held there for a sufficient time

to allow the recombination of any stored charge in thedevice. To ensure turn-off, the rate of fall of current duringthe commutation interval (turn-off period) and the rate ofrise of re-applied voltage after commutation must both berestricted. An excessive rate of fall of current creates a largenumber of residual charge carriers which are then availableto initiate turn-on when the voltage across the triac rises.

With supply frequencies up to around 400Hz and asinusoidal waveform, commutation does not present anyproblems when the load is purely resistive, since the currentand voltage are in phase. As shown in Fig. 18 the rate offall of on-state current -dI/dt, given by Equation 6, and therate of rise of commutating voltage dVcom/dt, given byequation 7, are sufficiently low to allow the stored chargein the device to fully recombine. The triac is thus easily ableto block the rising reapplied voltage dVcom/dt.

(6)

(7)

Fig. 18 Triac commutation waveforms (resistive load)

Fig. 19 Triac commutation waveforms (inductive load)

90%

10%

10%

V D

I GT

I T

t rt dt gt

dI/dt = 2πf .√2IT(RMS)

t q

IT

IR

VD

VR

dI Tdt

dVD

dt

dVcom/dt = 2πf .√2V(RMS)

VDWM

-dI/dtdVcom/dt

Time

Time

Time

Supplyvoltage

Loadcurrent

Voltageacross

triac

Triggerpulses

Current

VT

VDWM

-dI/dtdVcom/dt

Time

Time

Time

Supplyvoltage

Loadcurrent

Voltageacrosstriac

Triggerpulses

Current

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Fig. 20 Rate of rise of commutating voltage with rate of fall of on-state current and temperature

20 40 60 80 100 12001

10

100

1000

dV/dt (V/us)

5.1 3.9 3.0 2.3 1.8 1.4-dI/dt=

dVD/dt limit

Tj (C)

However, with an inductive load (Fig. 19) the current lagsbehind the voltage and consequently commutation canpresent special difficulties. When the on-state current hasfallen to zero after a triac has been conducting in onedirection the supply voltage in the opposite direction willhave already reached a significant value. The rate of fall oftriac current will still be given by Equation 6 but the rate ofrise of reapplied voltage, dVcom/dt will be very large. Thetriac may switch on immediately unless dV/dt is held lessthan that quoted in the published data by suitable circuitdesign. Alternatively, the circuit design can remain simpleif Hi-Com triacs are employed instead. Sections 6.3.1 and6.3.2 explain the advantages of using Hi-Com triacs in suchinductive circuits.

The maximum rate of rise of commutating voltage whichwill not cause the device to trigger spuriously is an essentialpart of the triac published data. However, dVcom/dt ismeaningless unless the conditions which are applicable areprovided, particularly the rate of fall of on-state current-dIT/dt. Our published data also contains graphs such as

Fig. 20 which relate dVcom/dt to junction temperature with-dIT/dt as a parameter. The characteristic dVcom/dt isspecified under the worst probable conditions, namely:

-mounting base temperature, Tmb=Tmb(max)

-reapplied off-state voltage, VD=VDWM(max)

-rms current, IT(RMS) = IT(RMS)(max).

In order that designers may economise their circuits as faras possible, we offer device selections with the samecurrent ratings but with different values of dVcom/dt (at thesame value of -dIT/dt) for some of our triac families. ThedV/dt capability can be traded off against the gate sensitivity(IGT(max)) of the device. Sensitive gate triacs (i.e. those whichrequire only a small amount of gate current to trigger thedevice) have less ability to withstand high values of dVcom/dtbefore sufficient current flows within the device to initiateturn-on. These different device selections are differentiatedby suffices which are added to the device type number eg.BT137-600F.

Detailed design considerations for dVcom/dt limiting ininductive circuits when using triacs are considered inseparate articles in this handbook.

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Thyristor and Triac Applications

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6.2.1 Triac Control of DC Inductive Loads

The problem of inductive loads

This publication investigates the commutation problemencountered when triacs are used in phase control circuitswith inductive loads. Commutation failure is likely to occurowing to circuit inductance imposing a sudden rise ofvoltage on the triac after conduction. Control oftransformers supplying an inductively loaded bridgerectifier is particularly troublesome because of the addedeffect of rapid current decay during commutation. For abetter understanding of the nature of the problem, thecommutation behaviour is summarised here.

Triacs are bipolar power control elements that may turn onwith either polarity of voltage applied between their mainterminals. Unlike thyristors there is no circuit-imposedturn-off time. To ensure commutation the decay rate ofcurrent before turn-off and the rate of rise of reappliedvoltage must both be held below specified limits. Anexcessive current decay rate has a profound effect on themaximum rate of rise of voltage that can be sustained, asthen a large amount of stored charge is available to initiatethe turn-on in the next half cycle.

Figure 1 shows the condition for a triac controlledtransformer followed by a rectifier with inductive load. Theload inductance forces the rectifier diodes into conductionwhenever the instantaneous dc output voltage drops tozero. The transformer secondary is thus shorted for sometime after the zero transitions of the mains voltage and areverse voltage is applied to the triac, turning it off. Becauseof transformer leakage inductance the triac does not turnoff immediately but continues to conduct over what is calledthe commutation interval (see Fig. 1).

During the commutation interval a high rate of decay ofcurrent (dIcom/dt) results for two reasons. Firstly the rate offall of current is high because the leakage inductance ofmost transformers is low. This is necessary to achieve asmall dc output voltage loss (represented by the shadedareas in the voltage waveform of Fig. 1) in the transformer.Secondly, with an inductive rectifier load a substantialcurrent flows when commutation starts to occur.

The large value of dIcom/dt results in a high rate of rise ofvoltage, dv/dt. Since the current decays rapidly the peakreverse recovery current IRRM is fairly large. Upon turn-off,IRRM is abruptly transferred to the snubber elements R andCso the voltage abruptly rises to the levelR.IRRM (C is initiallydischarged). Owing to the high value of both dIcom/dt anddv/dt, loss of control follows unless measures are taken toprevent it.

Fig. 1 Triac control of transformer suppling rectifier withan inductive load (α = trigger angle)

Obtaining reliable commutationA saturable choke in series with the transformer primaryproves effective in achieving reliable commutation (Fig. 2).Saturation should occur at a fraction of the rated loadcurrent so that the loss in the rectifier output voltage isminimised. At low currents the total inductance is large, thussoftening the commutation and eliminating transients. Thechoke delays the rise in voltage so a quiescent period of afew tens of microseconds is introduced, during which time

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the triac can recover. There is usually no difficulty indesigning a choke such that the decay rate of current(dIcom/dt) and the rate of rise of voltage (dv/dt) are sufficientlyreduced to ensure reliable control.

Fig. 2 Use of a saturable choke to ensure commutation

Circuit analysisOver the commutation interval the transformer secondaryis shorted as the load inductance keeps the rectifier diodesin conduction, so the simplified diagram of Fig. 3 applies.If the load time constant is much larger than the mainsperiod then the load current can be assumed to be purelydc. The waveforms of triac voltage and current are given inFig. 4. The mains voltage is given by vi= Vsinωt. As thecommutation interval is a fraction of the ac period then therate of change of voltage during the commutation intervalcan be assumed to be linear, giving:

Over the period 0 to t2 the voltage across the saturablechoke Ls and leakage inductance Lleak is equal to vi

(assuming the triac on-state voltage to be negligible).Assuming for this analysis that Ls remains in saturation(dashed portion in it waveform) then if Lsat is the saturatedinductance, the following expression can be derived:

where di/dt is the rate of change of triac current.

Fig. 3 Equivalent circuit diagram

Fig. 4 Commutation voltage and current waveforms(Dashed portion of It shows current waveform if Ls

remains saturated. Period t1 to t2 is shown expanded)

Integrating equation (2) gives:

where It is the current prior to commutation.

(Lleak + Lsat).di /dt = −Vωt (2)

i t = It −Vωt2

2(Lleak + Lsat)(3)

vi = −Vωt (1)

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At time t1, current it passes through zero, so, from (3):

At t1 the mains voltage has attained the value V1 which isfound by combining equations (1) and (4) to give:

Choke Ls comes out of saturation at low current levels sothe triac turn-off point is delayed to time t2. Since in apractical circuit the delay is only of the order of 50µs, themains voltage V2 at the instant of turn-off is very nearlyequal to V1. Thus from equation 5:

The triac conducts until time t2. Denoting the value ofunsaturated inductance as Lunsat, the current decay rate atzero current is given by:

The initial rate of rise of off-state voltage, dvcom/dt, can nowbe derived. This parameter is decisive for the behaviour ofthe triac, since a much greater dv/dt can be sustained aftercarrier recombination, that is, when the off-state voltagehas reached a substantial value.

At time t2 the triac turns off but the voltage across it is stillzero. The voltage drop across Ls and Lleak is equal to V2 andthe rate of rise of current carried by these inductances,diL/dt, is given in equation (7). The rate of rise of triac voltagedv/dt is determined by diL/dt and the values of the snubbercomponents R and C.

When the interval t1 to t2 is long enough, the triac has fullyrecovered at time t2, and so the current i to be taken overby the parallel RC snubber network is zero. At time t2, dv/dtis equal to the initial rate of rise of voltage dv0/dt. Fromequations (7) and (8):

In circuits where no transformer is interposed between thetriac and rectifier, some series inductance is still needed torestrict turn-on di/dt. In that case Equations (7) and (9) arestill valid by omitting Lleak.

Example - DC motor load

The motor control circuit of Fig. 5 illustrates the use of thedesign method proposed in the previous section. Since themotor has a fairly high inductance it may be considered asa constant current source, giving a severe test condition fortriac commutation.

Fig. 5 DC Motor test circuit.

Choke Lunsat=2.25mH, 30 turns on 36x23x10mm3

toriod core

Transformer 220V/150V, 6kVA, 0.9mH leakageinductance

Motor Series wound DC motor, Leakageinductance = 30mH

With Lleak = 0.9mH, Lunsat = 2.25mH and Lsat<<Lleak the circuitconditions can be calculated for a triac current of It = 20Aand a 220V, 50Hz supply. Using equations (7) and (9) givesdic/dt = -18.3A/ms and dv0/dt = 0.6V/µs. These values canbe compared with the commutation limits of the device toensure that reliable commutation can be expected.

The inductance in the ac circuit also restricts turn-on di/dtwhich, for a continuous dc load current is:

where vi is the instantaneous ac input voltage, ton is theturn-on time of the triac and R is the snubber resistance.Maximum turn-on di/dt occurs at the peak value of inputvoltage, vi. The initial rise of on-state current depends onthe snubber discharge current through R as well as thelimiting effect of the circuit inductance.

t1 = √2It(Lleak + Lsat)Vω

(4)

V1 = −√2ωVIt(Lleak + Lsat) (5)

V2 ≈ −√2ωVIt(Lleak + Lsat) (6)

dicdt

=V2

(Lleak + Lunsat)

= −√2ωVIt(Lleak + Lsat)Lleak + Lunsat

(7)

dvdt

= R.diLdt

+iC

(8)dion

dt≈

vi

tonR+

vi

Lleak + Lunsat

(10)

dv0

dt=

RLleak + Lunsat

√2ωVIt(Lleak + Lsat) (9)

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The oscillograms of Figs. 6 to 10 illustrate circuitperformance. With no choke added a large dv/dt wasobserved (Figs. 6 and 7) and so consequently commutationfailed when motor current was increased to around 9A. Asseen from Figs. 8 to 10 the choke softens commutation sothat dependable control results even at 23A motor current.At this current (Fig. 10) the quiescent interval is about 30µs,which is adequate time for the triac to recover.

Fig. 6 Triac voltage and current. No series choke.7A motor current. Timebase: 2ms/div

Upper trace: Triac voltage, vt (100V/div)Lower trace: Triac current, it (5A/div)

Fig. 7 Triac voltage and current. No series choke.7A motor current. N.B. Snap-off current

Timebase: 100µs/divUpper trace: Triac voltage, vt (20V/div)Lower trace: Triac current, it (1A/div)

Fig. 8 Triac voltage and current. Series choke added.7A motor current. Timebase: 100µs/divUpper trace: Triac voltage, vt (20V/div)Lower trace: Triac current, it (1A/div)

Fig. 9 Triac voltage and current. Series choke added.23A motor current. Timebase: 100µs/divUpper trace: Triac voltage, vt (10V/div)Lower trace: Triac current, it (5A/div)

Fig. 10 Triac voltage and current.Series choke added23A motor current. N.B. slight reverse recovery current

Timebase: 50µs/divUpper trace: Triac voltage, vt (10V/div)Lower trace: Triac current, it (1A/div)

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6.2.2 Domestic Power Control with Triacs and Thyristors

The increasing demand for more sophisticated domesticproducts can, in part, be met by providing the user withsome form of electronic power control. This control can beused, for example, to adjust the suction of a vacuumcleaner, the brightness of room lighting or the speed of foodmixers and electric drills.

It might be assumed that the cost of the electronics wouldbe high, but this is not necessarily the case. With triacs andthyristors it is possible to produce high performance mainscontrollers which use only a few simple components. Thefollowing notes give details of some typical control circuitsand highlight areas for special attention when adapting thedesigns for specific applications.

Vacuum cleaner suction controlThe competitive nature of the vacuum cleaner market hasled to the development of a wide variety of machine typesand accessories. In many cases, the speed of the motorremains constant and, if suction control is attempted, itconsists merely of an adjustable vent in the air flow path.Electronic suction control sounds somewhat expensive andunnecessarily complicated for such an elementaryapplication. In fact, by using a BT138 triac, a simple butnevertheless effective and reliable suction control circuit(Fig. 1) can be constructed very economically, and issuitable for all types of cleaner with a power consumptionof up to 900W.

The heart of the circuit is the BT138. This is a glasspassivated triac which can withstand high voltagebidirectional transients and has a very high thermal cyclingperformance. Furthermore its very low thermal impedanceminimizes heatsink requirements.

Fig. 1 Vacuum cleaner suction control circuit

Circuit DescriptionIn Fig. 1 the BT138 is the power control element. Its actionis controlled by a diac which is switched on by a charge onC1 under the control of potentiometer R2. The resistance ofthe diac is virtually infinite as long as the voltage across it

remains within the breakover voltage limits, -VBO to +VBO.During each half cycle of the mains sinewave, C1 chargesuntil the voltage across it exceeds the diac breakovervoltage. The diac then switches on and C1 discharges itselfinto the gate of the triac and switches it on. Diodes D1 andD2 stabilise the supply voltage to the charging circuit so thatits operation is independent of mains voltage fluctuations.If -VBO and +VBO are equal and opposite, the triac will betriggered at the same time after the start of either a positiveor negative half cycle. The conduction angle, and thereforethe speed of the motor and the cleaner suction, isdetermined by the adjustment of R2. Preset potentiometerR3 is used to set the minimum suction level. The width andamplitude of the trigger pulses are kept constant by gateresistor R4. The zinc oxide voltage dependent resistor (U)minimises the possibility of damage to the triac due to veryhigh voltage transients that may be superimposed on themains supply voltage. Figure 2 shows the current andvoltage waveforms for the triac when the conduction angleis 30˚.

a) Triac Voltage (100 V/div. 5ms/div.)

b) Triac Current (1 A/div. 5ms/div.)Fig. 2 Vacuum cleaner - Triac waveforms

Circuit PerformanceA laboratory model of the circuit has been tested todetermine the range of control that it has over the suctionpower of a typical vacuum cleaner. For the test, the cleanerwas loaded with a water column. The result of the test isshown graphically in Fig. 3. The measured range of watercolumn height (100 to 1100 mm) translates into a wide airflow range - from little more than a whisper to full suction.

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Fig. 3 Suction power as a function of motor speed

As suction power is a function of the speed of the vacuumcleaner motor, a second test was carried out to determinethe range of motor speed control under conditions ofminimum and maximum air flow (i.e. with the suctionblocked and unrestricted). This test also checked the motorspeed variation due to ±10% variation of a nominal 220 VAC mains supply. The initial test conditions were:unrestricted flow; mains supply 198 V (220 V - 10%); R2 atmaximum resistance, and R3 set so that the motor just ran.Table 1 shows the results of the test. Nmin is the speed atwhich the motor just runs and Nmax is the speed of the motorwith R2 set at minimum resistance.

mains blocked air flow unrestricted air flowvoltage Nmin Nmax Nmin Nmax

(V) (rpm) (rpm) (rpm) (rpm)

198 5300 17100 4300 15400220 6250 19000 5000 17100242 7400 20000 6000 18200

Table 1. Motor speed figures for circuit of Fig. 1

The table shows that the speed setting range is wide. Theratio of Nmax to Nmin is 3.42:1, for 220 V mains andunrestricted airflow. The variation of motor speed due tovariation of the mains input is quite small and represents anegligible change of suction. If D1 and D2 are omitted fromthe circuit, the speed setting ratio is reduced to 1.82:1 underthe same conditions. The table also shows that thedifference between the Nmin for minimum and maximum airflow is quite small. This implies that speed stabilisation isunnecessary.

Special Design ConsiderationsThe circuit shown in Fig. 1 has been shown to work well ina typical vacuum cleaner application. But motors andenvironments do vary, so some aspects of the designshould be looked at carefully before it is finalised.

Circuit positioningThe siting of the circuit, within the case of the cleaner, isparticularly important. In some areas within the cleaner thetemperature can be quite high. The circuit, and in particularthe triac and its heatsink, should not be placed in one ofthese areas if the designer is to avoid problems keepingthe temperature of the triac below Tjmax.

Starting currentAnother factor that may lead to thermal problems is that ofinrush current. The starting current of a vacuum cleanermotor is typically as shown in Fig. 4. The rms current duringthe first 20 ms could be 20 A or more. The current decaysto its steady state value in about 1 s. To ensure that thetriac does not overheat, reference should be made to theinrush current curves in the triac data sheet, the curve forthe BT138 is reproduced in Fig. 5.

Fig. 4 Starting current (20 A/div, 50 ms/div.)

cycle time peak rms ’limit’number. (ms) current current current

(A) (A) (A)

1 20 49 22 242 40 41 18 213 60 35 13 19.54 80 32 14 18.55 100 29 13 18

10 200 20 9 15.520 400 14 6.3 14

Table 2. Currents during starting

The first step in checking for a problem is to estimate themounting base temperature, Tmb, prior to starting. Areasonable figure would be the worst case steady statevalue of Tmb during normal running.

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Fig. 5 Inrush current curve for BT138

Step 2 is to calculate the rms value of one cycle of thestarting current at several times during start up and step 3is to compare these figures with the values taken from theappropriate line of the inrush current curve.

As an example consider the performance of the BT138driving a motor whose starting current is shown in Fig. 4.Direct measurement indicated that during normal runningthe Tmb of a BT138 mounted on a particular heatsink, wouldbe no more than 22˚C above ambient. From othermeasurements it was estimated that the ambienttemperature would not exceed 73˚C. These figures give aworst case steady state Tmb of 95˚C. It can be assumed thatthis is the highest temperature that the mounting base couldbe, prior to starting - a reasonable assumption which coversthe case where the motor has been running for a long time,is turned off and then started again before there has beenany cooling.

The rms values of cycles 1 to 5, 10 and 20 of the startingcurrent are given in Table 2. Since the current is not anideal sine wave these have been calculated from the peakcurrent by assuming a crest factor (peak to rms) of 2.23.Also shown are the relevant IO(RMS) figures from the 95˚Cline of Fig. 5. Since ’actual’ inrush current is always lessthan the ’allowed’ current it is safe to use the BT138 underthe proposed conditions to control the motor. It should benoted that because the crest factor is >√2 the dissipationof the BT138 will be less than assumed by the inrush currentcurves of Fig. 5.

CommutationThe circuit shown in Fig. 1 has no RC snubber. This wasbecause the values of dI/dt and dV/dt generated by thecircuit were well within the capability of the BT138. This willoften be the case with vacuum cleaner motors for tworeasons:

- these motors introduce only a small phase shift in thecurrent, so the voltage step is small and the dV/dt is low,

- the steady state value of the current is much less thanthe maximum rating of the BT138, this amounts to a dI/dtwell within the capability of the BT138.

However care must be taken to ensure that this is true inall applications. In particular, care should be taken to ensurethat the triac switches correctly even during starting. If asnubber is found to be necessary then a 100 Ω 0.5 Wresistor in series with a 0.1µF capacitor will be more thanadequate in most circumstances.

InterferenceIt is, of course, necessary to check that the overallequipment complies with local regulations for conductedand radiated interference. However, the measures taken tosuppress the electrical ’noise’ of the motor combined withthe motor itself will often be more than sufficient toovercome the interference generated by the switching ofthe triac but this must be checked in all applications.

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Domestic lamp dimmer

The use of light dimmers, once the prerogative ofentertainment centres, has now become widespread in thehome. It is necessary to ensure that the component partsof these units are simple and reliable so that they arecompatible with the domestic environment.

The glass passivated BT138 triac meets theserequirements. Firstly, it has a peak non-repetitive on-statecurrent handling capability of up to 90 A which means it caneasily withstand the inrush current that occurs when a coldlamp is switched on. It can also withstand high voltagebidirectional transients and its low thermal impedanceminimizes heatsink requirements.

Fig. 6 Lamp dimmer circuit

Circuit Description

A simple circuit of a light dimmer using the BT138 is givenin Fig. 6. The BT138 is the power control element, triggeredvia the diac. The setting of potentiometer R2 determines thephase difference between the mains sine wave and thevoltage across C2. This in turn sets the triac triggering angleand the lamp intensity.

The resistance of the diac is very high as long as the voltageacross it remains within its breakover voltage limits, -VBO to+VBO. Each half cycle of the mains charges C2 via R1, R2

and R3 until the voltage being applied to the diac reachesone of its breakover levels. The diac then conducts and C2

discharges into the gate of the triac, switching it on. If -VBO

and +VBO are equal and opposite, the triac will be triggeredat the same time after the start of either a positive ornegative half cycle. If C1 were not included in the circuit,the voltage across C2 would change abruptly after triggeringand cause the phase relationship between the mainsvoltage and voltage across C2 to progressively alter. Thiswould cause an undesirable hysteresis effect. The voltageacross C1 partially restores the voltage across C2 aftertriggering and thereby minimizes the hysteresis effect. Thewidth and amplitude of the trigger pulses are kept constantby gate resistor R4. The VDR minimizes the possibility ofthe triac being damaged by high voltage transients that maybe superimposed on the mains supply voltage.

Special Design Considerations

Circuit ratingTheBT138 has an rms current rating of 12 A. It is, therefore,capable of controlling loads with a rating of 2 kW or more.However, the load of this circuit must be restricted to a muchlower level. There are two reasons for this. The first is tokeep mains distortion within the allowed limits, without thenecessity of expensive filter networks. The second reasonis to limit dissipation. If, as is likely, the circuit is to bemounted in the wall in place of a conventional switch, thenair circulation is going to be very restricted and the ambienttemperature around the circuit will be quite high. It isimportant for reliability reasons to ensure that thetemperature of the BT138 never exceeds Tjmax, so thedissipation of the triac must be kept to a low level.

Fig. 7 Interference on mains supply

InterferenceRegulations concerning conducted and radiatedinterference vary considerably form country to country butit is likely that some form of filter will be needed. The simpleLC filter shown within the dashed-lined box in Fig. 6 is oftenall that is needed. The values of the filter components willvary, but a combination of 0.15 µF capacitor and a low Qinductor of 2.5 µH was found to be sufficient for the circuitto meet the C.I.S.P.R. limits. This is illustrated by the plotsshown in Fig. 7. Curves (a) and (b) show the level of noiseon the mains supply for the circuit, without filter, when

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controlling 550 W and 25 W loads respectively. Curves (d)and (e) are for the circuit with filter connected showing thatthe C.I.S.P.R. limit, which is curve (c), has been met.

Filter inductorHaving selected the value of filter inductor, the designerhas then to decide how to make it. Construction will not betoo critical - it is not necessary to achieve a high Q - andthere will be considerable room for reducing its size.However, care must be taken to ensure that the inductordoes not saturate when the inrush current of a cold lampflows through it. If the inductor does saturate then the filtercapacitor will, effectively, be shorted out by the triac. In thiscase the triac current could rise faster than the dI/dt ratingallows. This could cause progressive damage to the triacresulting in premature failure.

Speed control for food mixers and electricdrillsFood mixers and electric hand drills are products whoseuseability is improved by the addition of electronic speedcontrol. But they are products where costs have to be tightlycontrolled so the choice of circuit is very important. Thisdecision is made harder by the need to have a good speedregulation under the widely varying loads that theseproducts are subjected to.

The circuits to be described provide continuous control ofmotor speed over a wide speed range by adjusting theconduction angle of a BT151 thyristor. They compensatefor load variation by adjusting the firing angle when thereis a change in the motor speed - as indicated by a changein its back EMF.

Back EMF Feedback CircuitsA simple motor speed control circuit that employs backEMFto compensate for changes in motor load and mains voltageis shown in Fig. 8(a). The resistor chain R1, R2,R3 and diodeD1 provide a positive going reference potential to thethyristor gate via diode D2. Diode D1 is used to reduce thedissipation in the resistor chain by some 50% and diode D2

isolates the trigger circuit with the thyristor in the on-state.When the thyristor is not conducting the motor produces aback EMF voltage across the armature proportional toresidual flux and motor speed. This appears as a positivepotential at the thyristor cathode.

A thyristor fires when its gate potential is greater thancathode potential by some fixed amount. Depending on thewaveform shape and amplitude at the gate, the circuit mayfunction in several modes.

a) Basic Controller

b) Improved Low Speed Controller

c) Improved Low and High Speed ControllerFig. 8 Thyristor Speed Control Circuit Using Back EMF

Feedback

R15k6 6W

R21k0 1W

R3150

D1

D2 BT151

R4500

R15k6 6W

R22k0 1W

R3150

D1

D2 BT151

R4500

C125uF 25V

R15k6 6W

R22k0 1W

R3150

D2 BT151

R4500

D1

C150uF 40V

531


Fig. 9 Waveforms with DC Gate Supply

If, for example, during positive half cycles a constant DCpotential was applied at the gate (see Fig. 9), the thyristorwould continue to fire at the beginning of each cycle untilthe back EMF was large enough to prevent firing. Thyristorfiring would then continue intermittently at the beginning ofthe positive cycles to maintain some average motor speed.

Referring to Fig. 8(a) the waveform appearing at thethyristor gate will approximate to a half sine wave,Fig. 10(a). As a result it is impossible for the firing angle tobe later than 90˚ - the most positive value of the triggerpotential. At lower motor speeds the firing angle might needto be 130˚ for smooth operation. If the maximum firing angleis limited to 90˚ then intermittent firing and roughness ofmotor operation will result.

If, however, the waveform at the gate has a positive slopevalue to an angle of at least 130˚ then it will be possible tohave a stable firing point at low speeds. Such a waveformcan be produced if there is some phase shift in the triggernetwork.

Stable Firing at Small Conduction AnglesThe trigger network of the circuit shown in Fig. 8(b) hasbeen modified by the addition of a capacitor C1 and diodeD1. The diode clamps the capacitor potential at zero duringthe negative going half cycles of the mains input. Thewaveform developed across the capacitor has a positiveslope to some 140˚, allowing thyristor triggering to bedelayed to this point.

a) Basic Controller

b) Improved Low Speed Controller

c) Improved Low and High Speed ControllerFig. 10 Gate Voltage Waveforms

v MainsVoltage

backEMF

0 90 180

3

2

1

v123

v MainsVoltage

0 90 180

3

2

1

v1

23

v MainsVoltage

0 90 180

3

2

1

v123

v MainsVoltage

0 90 180

532


As the slider of R2 is moved towards R1, the peak of thewaveform at the gate will move towards 90˚ as shown inFig. 10(b). As the speed increases, the no load firing anglewill also advance by a similar amount so stability will bemaintained. This circuit will give smoother and more stableperformance than the circuit of Fig. 8(a). It will, however,give a marginally greater speed drop for a given motorloading at low speed settings. At the maximum speedsettings the circuit of Fig. 8(a) approximates to that ofFig. 8(b).

Fig. 11 Simplified Firing Circuit

Improved Motor Performance With StableFiring

Both the circuits so far discussed have gate voltagewaveforms that are of near linear slope from the zero pointof each positive half cycle, see Figs. 10(a) and (b). Thismeans that the only time that the thyristor can be fired earlyin the mains cycle, say at 20˚, is when the back EMF andhence motor speed is very low. This effect tends to preventsmooth running at high speeds and high loads.

Stable triggering, at low angles, can be achieved if the gatevoltage ramp starts each cycle at a small positive level. Thismeans that the time to reach the minimum trigger voltageis reduced. The circuit of Fig. 8(c) is one way of achievingthis. In this circuit capacitor C1 is charged during positivehalf cycles via resistor R1 and diode D1. During negativehalf cycles the only discharge path for capacitor C1 is viaresistors R2 and R3.

Diode D1 also prevents C1 from being discharged as thethyristor switches off by the inductively generated pulsefrom the motor. As the value of resistor R2 is increased,capacitor C1 is discharged less during negative half cyclesbut its charging waveform remains substantiallyunchanged. Hence the result of varying R2 is to shift the DClevel of the ramp waveform produced across C1.

Diode D2 isolates the triggering circuit when the thyristor isON. Resistor R4 adjusts minimum speed, and by effectivelybleeding a constant current, in conjunction with the gatecurrent from the triggering circuit, it enables resistor R2 togive consistent speed settings.

Fig. 12 Calculated Gate Waveforms

Circuit DesignIf the speed controller is to be effective it must have stablethyristor firing angles at all speeds and give the bestpossible speed regulation with variations of motor load. Thecircuit of Fig. 8(c) gives a motor performance that satisfiesboth of the above requirements.

There are two factors that are important in the circuitoperation in order to obtain the above requirements.

- The value of positive slope of the waveform appearing atthe thyristor gate.

- The phase angle at which the positive peak gate voltageis reached during a positive half cycle of mains input.

R1

R2

D2

D1

C1

v

i

i1i2

0 50 100 150 200 2500

5

10

15

20

25

30

35

Phase Angle

Gate Voltage

C1=32uF C1=50uF C1=64uF

R2=1500

R2=800

R2=200

533


As previously described the charging of capacitor C1 byresistor R1 determines the rate of rise of voltage at thethyristor gate during the positive half cycle. However,resistor R1 must also have a value such that several timesthe maximum thyristor gate current passes through the RCnetwork to D1. This current will then give consistent speedsettings with the spread of thyristor gate currents when theminimum speed is set by resistor R4.

The positive slope value of the thyristor gate voltage willhave to be fixed according to the motor used. A motor thatgives a smooth back EMF voltage will allow a low slopevalue to be used, giving good torque speed characteristics.Some motors have coarser back EMF waveforms, withvoltage undulations and spikes, and a steeper slope ofthyristor gate voltage must be used in order to obtain stablemotor operation. The value of capacitor C1 is chosen toprovide the required positive slope of the thyristor gatevoltage.

b) measurement circuit

b) typical waveform.Fig. 13 Back EMF Measurement Arrangement

Some calculations have been made on the circuit ofFig. 8(c) simplified to the form of Fig. 11, where it isassumed that current flowing to the thyristor gate is smallcompared with the current flowing through resistor R1. Anexpression has been derived for the voltage that wouldappear at the anode of D2 in terms of R1, R2 and C1 and isgiven later. Component values have been substituted intothe expression to give the thyristor gate waveforms shownin Fig. 12.

In order to adjust the circuit to suit a given motor, the backEMF of the motor must be known. This may be measuredusing the arrangement shown in Fig. 13. The voltageappearing across the motor is measured during the periodwhen the series diode is not conducting (period A). Thevoltage so obtained will be the motor back EMF at its topspeed on half wave operation, and corresponds to the backEMF that would be obtained from the unloaded motor at itshighest speed when thyristor controlled. In practice, sincethe mains input is a sine wave, there is little increase in the’no load’ speed when the firing angle is reduced to less thanabout 70˚.

The value of resistor R2 in Fig. 8(c) determines the motor’no load’ speed setting. The waveforms of Fig. 12 may beused as a guide to obtaining the value of this resistor. Itmust be chosen so that at 70˚ and at its highest value, thegate voltage is higher than the measured back EMF byabout2 V - the forward gate/cathode voltage of the thyristor.

The thyristor is turned ON when a trigger waveform, shownin Fig. 12, exceeds the back EMF by the gate/cathodevoltage. So, if the back EMF varies within a cycle then therewill be a cycle to cycle variation in the firing angle. Normally,random variations of the firing angle by 20˚ are tolerable.If, for example, there were variations in the back EMF of1 V, then with a firing angle of 70˚and a capacitor of 32 µF,the variation of firing angle would be about 12˚. Withcapacitor values of 50 µF and 64 µF the firing anglesvariations would be 19˚ and 25˚ respectively. Therefore, acapacitor value of 50 µF would be suitable.

PerformanceThe torque speed characteristics of the three circuits, whenused to drive an electric drill, are compared in Fig. 14. Itmay be seen that the circuit of Fig. 8(b) has a poorerperformance than the two other circuits. That of Fig. 8(c)may be seen to give a similar performance to the circuit ofFig. 8(a) at low speeds but, at high speeds and torques, itis better. It should be noted that the circuits of Figs. 8(b)and (c) provide low speed operation free from theintermittent firing and noise of the Fig. 8(a) circuit. Figure15 compares the circuits of Fig. 8(a) and 8(c) when the loadis a food mixer motor.

to

oscilloscope

back

EMF

period

diode

conductiong

period

BA

back EMF

534


Fig. 14 Performance with Hand Drill Load

Fig. 15 Performance with Food Mixer Load

Circuit CalculationsThe following analysis derives an expression for voltage ’v’at the anode of D2. This expression can be used to produce

the gate voltage waveforms shown in Fig. 12. The analysisassumes that the current drawn by the thyristor gate isnegligible in comparison with the current flowing in R1.

The charging current i1 for capacitor C1 in Fig. 11, is givenby:

and

Representing a mains half sine wave by where is thepeak mains voltage.

therfore,

where i, i1, i2 are instantaneous currents.

Simplifying:-

Fourier analysis of a half sinewave gives:-

neglecting terms of the Fourier series with n > 2, then

then

simplifies to

where A, B, D, X, Y are constants.

Put

where a, b, c, d are constants.

0 0.5 1 1.5 2 2.50

500

1,000

1,500

2,000

2,500

3,000

Motor Torque (Nm)

Motor Speed (rpm)

Seriesdiode

Fig.8(a)circuit

Fig.8(b)circuit

Fig.8(c)circuit

i1 =dqdt

= C1

dvdt

i2 =vR2

f(E) E

i =f(E) − v

R1

= i1 + i2

f(E) − vR1

= C1

dvdt

+vR2

C1

dvdt

+ v

1R1

+1R2

=f(E)R1

0 0.1 0.2 0.3 0.4 0.5 0.60

2,000

4,000

6,000

8,000

10,000

12,000

Motor Torque (Nm)

Motor Speed (rpm)

seriesdiode

Fig.8(c)circuit

Fig.8(a)circuit

f(E) = E

1π

+12

sin(θ) −2π

∑n = 2, 4, 6...

n = 0 cos(nθ)n2 − 1

C1

dvdt

+ v

1R1

+1R2

=ER1

1π

+12

sin(ωt) −23π

cos(2ωt)

C1

dvdt

+ v

1R1

+1R2

−E

R1π=

ER1

12

sin(ωt) −23π

cos(2ωt)

(1)

Advdt

+ Bv − D = X sin(ωt) − Ycos(2ωt) (2)

v = a sin(ωt) + b cos(ωt)

+ csin(2ωt) + d cos(2ωt) +DB

(3)

535


substituting (3) and (4) in equation (2) and equating termsin , then

substituting for the constants in equation (2) gives:

This may be simplified since

So the voltage that the trigger circuit would apply to the gate(assuming the gate draws no current) is given by:

Solving this equation for a different values of C1 andpositions of R2 gives the curves shown in Fig. 12.

ConclusionsThe addition of electronic control can enhance the overalluseability of many domestic products. Cost andperformance requirements are major factors whendetermining the type of control circuit to be used in theseapplications. It is possible, using thyristors and triacs, toconstruct a range of phase control circuits which can meetmany of these cost and operational requirements.

Although these circuits are not complex and use only simplecomponents, it is still important to design with care to ensurethat the best performance is achieved.This report has givenexamples of some of these circuits and has highlighted theareas of their design requiring particular care.

dvdt

= aωcos(ωt) − bωsin(ωt)

+ 2cωcos(2ωt) − 2dωsin(2ωt) (4)

v =R2E

π(R1 + R2)

+R2E

2ω2C12R1

2R22(R1 + R2)sin(ωt)

− ωC1R1R2cos(ωt)

−23π

ωC1R1R2sin(2ωt)

−13π

(R1 + R2)cos(2ωt)

cos(ωt),cos(2ωt),sin(ωt),sin(2ωt)

v =BX

A2ω2 + B2.sin(ωt) −

AωX

A2ω2 + B2.cos(ωt)

−2AωY

4A2ω2 + B2.sin(2ωt)

−BY

4A2ω2 + B2.cos(2ωt) +

DB

v = R2E.(R1 + R2)sin(ωt) − ωC1R1R2cos(ωt)

2ω2C12R1

2R22 + (R1 + R2)2

+ R2E.1

π(R1 + R2)

− R2E.4ωC1R1R2sin(2ωt) + 4(R1 + R2)cos(2ωt)

3π[4ω2C12R1

2R22 + (R1 + R2)2]

(R1 + R2)2 2ω2C2R1

2R22

536


6.2.3 Design of a Time Proportional Temperature Controller

Electronic temperature control is no longer new: phase andon/off controls for heaters have been widely used to replacemechanical switches. However, both phase control andon/off control have disadvantages. Conventional phasecontrol allows fully-proportional control of the powerdissipated in the load, but the high rates ofchange of currentand voltage cause RFI and transients on the mains supply.Because of this effect, phase control is not allowed to beused for domestic heaters. Simple on/off control withzero-voltage switching avoids generation of RFI but theamount of hysteresis required to prevent temperatureoscillations does not give the required control accuracy.

The principle of time-proportional control

Time proportional control combines the zero-voltageswitching of on/off control with the accuracy of proportionalcontrol and so eliminates the disadvantages of these twoalternative systems. Time-proportional control regulatesthe load power such that there will be no overshoot orundershoot of the desired temperature as is the case withnormal on/off systems. The TDA1023 has been designedto provide time-proportional control for room heaters andelectric heating elements using a minimum number ofexternal components. It incorporates additional features toprovide fail-safe operation and fine control of thetemperature.

There are three states of operation when usingtime-proportional control:

• load switched fully off,

• load power proportional to the difference between actualand desired temperatures,

• load switched fully on.

Figure 1 illustrates the principle; the load is switched ononce and off once in a fixed repetition period, the ratio ofthe on and off periods providing the proportional control.This method of control can cause mains flicker; the mainsvoltage changes slightly each time the load is switched onor off.

CENELEC, the European Committee for Electro-technicalStandardisation, has published rules which limit the rate atwhich domestic heating apparatus may be switched on andoff. Table 1 gives the minimum repetition period for a rangeof load powers and common mains voltages fromCENELEC publication EN50.006.

Fig. 1 Duty cycle control

Appliance Repetition period, to (s)

Power (W) 220V 240V 380V

600 0.2 0.2800 0.8 0.3 0.1

1000 2.0 1.0 0.21200 4.6 2.0 0.21400 7.0 4.3 0.21600 10.0 6.3 0.31800 16.0 8.9 0.52000 24.0 13.0 0.92200 32.0 17.0 1.32400 40.0 24.0 1.92600 31.0 2.62800 3.6

Table 1. CENELEC minimum repetition periods forDomestic Heater Applications

Description of the TDA1023The TDA1023 is a 16-pin dual in-line integrated circuitdesigned to provide time-proportional power control ofelectrical heating elements. The TDA1023 is ideally suitedfor the control of:

• Panel heaters

• Cooker elements

• Electric irons

• Water heaters

• Industrial applications, e.g. temperature controlled oilbaths, air conditioners.

The TDA1023 Incorporates the following functions:

• A stabilised power supply. The TDA1023 may beconnected directly to the AC mains using either adropping resistor or capacitor. It provides a stabilisedreference voltage for the temperature-sensing network.

ON

OFF

Input

Output

t0

tON

Temperaturereference

Ramp voltage

537


Fig. 2 Triac trigger pulse width requirement

• A zero-crossing detector to synchronise the outputtrigger pulses to the zero-crossings of the mains supply.The detector produces a pulse, the duration of which isdetermined by an external resistor, centred on thezero-crossing of the mains voltage.

• A comparator with adjustable hysteresis, preventingspurious triggering of the output. This compares athermistor voltage, a function of the room temperature,with the voltage from the temperature selection dial.

• A voltage translation circuit for the potentiometer input.Normally, the relatively small temperature variation in aroom (5˚C to 30˚C) corresponds to a narrow angle ofrotation of a potentiometer shaft. Use of this circuitdoubles the angle of rotation of the potentiometer shaftfor the same temperature range.

• A sensor fail-safe circuit to prevent triggering if thethermistor input becomes open or short-circuited.

• A timing generator with an adjustable proportional band.This allows a full 100% control of the load current overa temperature range of only 1˚C or 5˚C. The repetitionperiod of the timing generator may be set by an externalcapacitor to conform to the CENELEC specifications formains load switching.

• An output amplifier with a current-limited output. Theamplifier has an output current capability of at least200mA and is stabilised to 10V while the current limit isnot exceeded.

• Input buffers, to isolate the voltage translation circuitand comparator from external influences.

• A control gate circuit to activate the output if there is amains zero-crossing, the comparator is ON and thefail-safe comparator is OFF.

Although designed specifically for time proportional control,the TDA1023 is also suitable for applications requiringon/off control if the timing generator is not used.

Required Duration of Triac Trigger PulseThe main advantage of triggering at the instant when theapplied voltage passes through zero is that this mode ofoperation renders the use of RF suppression componentsunnecessary. For time-proportional control, continuousconduction of the triac may be required for many cycles ofthe mains supply. To maintain conduction while the loadcurrent is approaching the zero-crossing, the trigger pulsemust last from the time when the load current falls to thevalue of the triac holding current (IH), until the time whenthe load current reaches the triac latching current (IL).

IL

IHIL

tp(min)

ITTriac current

Trigger pulse

Fig. 3 TDA1023 block diagram and external components

1

3

13457812

9

6

11 14 10 16

AC line

AC line

D1

RD

RS

R1

RP

CS

RNTC

Load

RG

CT

C1Varistor

Inputbuffers

Timinggenerator

Voltagetranslation

Zerocrossingdetector

Powersupply

Outputamplifier

Comparator

TDA1023

T1

538


Fig. 4 Minimum pulse width as a function of supply voltage and latching current

In general, the latching current of a triac is higher than theholding current, so the minimum trigger pulse duration maybe taken as twice the time for the load current in the triac(IT) to rise fromzero to the triac’s latchingcurrent. See Fig. 2.The current passed by the triac is a function of its on-statevoltage, the load resistance, and the applied voltage. Thetrigger pulse width is therefore a function of:

• triac latching current (IL)

• applied AC voltage (v = Vsinωt)

• load resistance (R)

• on-state voltage of the triac (VT) at IL.

The load resistance is related to the nominal load power,P and nominal supply voltage, Vs by R=Vs

2/P. Assumingthat the load resistance has a tolerance of 5% and the ACvoltage variation is 10%, the minimum required width of the

trigger pulse in the worst case can be calculated. Thegraphs of Fig. 4 show tp(MIN) as a function of P for fourcommon mains voltages with values of 30mA, 60mA,100mA, and 200mA for the triac latching current IL and amaximum on-state voltage of VT=1.2V at IL.

Selection of external componentsThe external components required by the TDA1023determine the operation of the device. The followingparagraphs describe the selection of these components toensure reliable operation under worst-case conditions.

Synchronisation Resistor, R S

A current comparator is used as a zero-crossing detectorto provide trigger pulse synchronisation. It compares thecurrent through the synchronisation resistor (RS) with areference current. As the supply voltage passes through

539


zero, the current in the synchronisation resistor becomesless than the reference current and a trigger pulse is givenuntil the current in RS increases above the reference level.

Thus, the duration of the trigger pulse depends upon therate of change of current in RS at the supply voltagezero-crossing point. This rate of change is affected by:

• -the AC supply voltage

• the supply frequency

• the value of the synchronisation resistor.

Fig. 5 shows the value of RS as a function of trigger pulsewidth, with the AC supply voltage as a parameter.

Fig. 5 Synchronisation resistor values as a function ofpulse width and AC voltage

Gate Resistor R G

The guaranteed minimum amplitude of the output triggerpulse of the TDA1023 is specified as 10V at an outputcurrent less than 200mA. The output stage is protectedagainst damage due to short-circuits by current-limitingaction when the current rises above 200mA.

Although the output is current-limited, it is stilladvantageous to include a gate series resistor in the circuit.Inclusion of a gate resistor to limit the gate current to theminimum value required reduces the overall currentconsumption and the power dissipation in the mainsdropping resistor. Furthermore, the point at which currentlimiting occurs is subject to considerable variation betweensamples of the TDA1023: a gate resistor will reduce theeffect of this in production circuits.

The rectangular output V/I characteristic of the TDA1023is shown in Fig. 6. Load lines for various values of gateresistor have been plotted on this diagram so that themaximum value of gate resistor can be selected by plottinghorizontal and vertical lines to represent the requiredminimum gate current and voltage. The following exampleillustrates the use of Fig. 6.

The triac tobe triggered is a Philips BT139.At0˚C the triggerpulse requirements for a standard BT139 are:

IGT = 98 mAVGT = 1.6 V

These figures are for triggering with a positive gate pulsewhen MT2 is negative with respect to MT1. The linesrepresenting VGT= 1.6V and IGT=98 mA cross the load linefor a gate resistor value of 82 Ω. The maximum value ofgate resistor is therefore 82 Ω.

Fig. 6 Gate voltage as a function of output current andgate resistor values

Gate Termination Resistor R PD

The TDA1023 has a resistor approximately 1.5kΩ betweenPin 1 and Pin 13. This is intended for use as a pull-downresistor when sensitive triacs are being used.

The Proportional Band Resistor R 5

The proportional band is the input voltage range thatprovides control of 0% to 100% of the load power. TheTDA1023 has a built-in proportional band of Vpb=80mV(corresponding to about 1˚C) which can be increased bythe addition of resistor R5 between Pin 5 and ground. Themaximum proportional band of 400mV is obtained byshorting Pin 5 to ground.

Hysteresis Resistor R 4

The comparator of the TDA1023 is designed with built-inhysteresis to eliminate instability and oscillation of theoutput which would cause spurious triggering of the triac.Apart from providing a stable two-state output, thehysteresis gives the comparator increased noise immunityand prevents half-waving.

Figure 7 shows the application of hysteresis to thecomparator and the transfer characteristic obtained. Thebuilt-in hysteresis is 20mV; this may be increased by addinga resistor (R4) from Pin 4 to ground which increases thecurrent IH. Pin 4 shorted to ground gives a maximum of320mV. Table 2 gives the value of R4 for a range ofhysteresis settings.

0 50 100 150 2000

2

4

6

8

10

RG=22R

27

33

39

47566882100120180270RG=390R

IG (mA)

VGT (V)

0 100 200 300 4000

100

200

300

400

500

600

Vs=380V 240V 220V

110V

tp (us)

R5 (kOhm)

540


Fig. 7 Temperature control hysteresis characteristic

When the proportional band (Vpb) is increased, it may benecessary to increase the hysteresis voltage (Vh). Table 2also showsa range of proportional band settings, the valuesof R5 required for these, the corresponding minimumhysteresis voltage and the maximum value of hysteresisresistor R4.

Proportional R5 (kΩ) R4 (kΩ) HysteresisBand (mV) band (mV)

80 - - 20160 3.3 9.1 40240 1.1 4.3 60320 0.43 2.7 80400 0.0 1.8 100

Table 2. Choice of components R4 and R5

Voltage AC DC Catalogue(V) rating (µF) value (µF) Number

25 47 68 2222 016 9012940 33 47 2222 016 9013125 22 33 2222 015 9010240 15 22 2222 015 9010125 10 15 2222 015 9009940 6.8 10 2222 015 90098

Table 3. Preferred capacitors for use with TDA1023

Power CENELEC CT(DC) t0(nom) t0(min) t0(max)

(W) t0 (s) (µF) (s) (s) (s)

2000 24.0 68 41 22 651800 16.0 47 28 15 451600 10.0 33 20 11 321400 7.0 22 13 7 211200 4.6 15 9 4.8 141000 2.0 10 6 3.2 9.6800 0.8 10 6 3.2 9.6600 0.3 10 6 3.2 9.6

Table 4. Timing capacitor values for 220V operation

Smoothing Capacitor, C S

The smoothing capacitor is required to provide the supplycurrent to the TDA1023 during the negative half cycles ofthe mains voltage waveform. As the TDA1023 possessesan internal voltage stabilization circuit, a high input ripplevoltage can be tolerated. A practical preferred value of CS

is 220µF, 16V.

Timing Capacitor, C T

The minimum repetition period required for a particularapplication was given in Table 1. This timing is selectedusing the external capacitor CT. Typical electrolyticcapacitors have wide tolerances: up to -10% to +50%.Moreover, the effective DC capacitance is different from themarked (AC) value, usually greater. Thus, the use ofstandard capacitors may lead to repetition periods far inexcess of those required. A range of electrolytic capacitorshas been developed for use with the TDA1023 (Table 3).All further references to CT assume the use of the preferredcapacitors which have the following advantages:

• DC capacitance is known for each marked AC value.

• Tolerance for the DC capacitance is ±20%.

• Very low leakage current (<1µA).

• Long lifetime (>100,000 hours at 40˚C).

Fig. 8 Temperature-sensing bridge circuit

Fig. 9 Temperature-sensing voltage translation circuit

V7 V6Increasing temperature

VOUT Ih.Rh

V9V6

R1

RNTC

RP

V11

BufferTranslationcircuit

BufferComparator

Fail-safeComparator

0.95V11

6

7

8 9

TDA1023

V11

RPR

V11

R1

NTC

541


Fig. 10 Average gate current as a function of RG with RS and AC voltage as parameters

The timing circuitThe TDA1023 employs a triangular waveform for timingpurposes. The advantages of using a triangular waveformare that for a given capacitor value the triangular waveformprovides twice the repetition period that the sawtooth gives.This allows the use of smaller capacitors and minimises theeffects of the capacitor leakage current thus reducing thespread in repetition periods.

The published data for the TDA1023 specifies the repetitionperiod as 0.6 s ± 0.2 s/µF. Table 4 shows the minimumpreferred value of CT (DC value) to provide the requiredminimum repetition time for a range of appliance powersoperating at 220V AC. The resulting nominal, minimum,and maximum repetition times are also given.

Input voltage translation circuitFigure 8 shows a temperature sensing network whichrequires a minimum of components and eliminatesperformance spreads due to potentiometer tolerances. Forapplications where the input voltage variation is very much

less than the available voltage then the requiredtemperature will be controlled by a small angle of rotationof the potentiometer shaft. The TDA1023 voltagetranslationcircuit allows the use of 80%of the potentiometerrotation giving accurate control of the temperature. If thevoltage translation circuit is not used then pins 9 and 11must be shorted together to disable the circuit. A blockdiagram of the translation circuit is shown in Fig. 9.

Fail-safe circuits

The TDA1023 is fail-safe for both short-circuit andopen-circuit conditions. Either of these conditions willprevent production of trigger pulses for the triac.

Short-circuit sensing is automatically obtained from thenormal temperature sensing circuit. When the thermistorinput voltage is zero, the triac will never be triggeredbecause the potentiometer slider voltage will be higher. Tosense the open-circuit thermistor condition, an extracomparator is used. This fail-safe comparator will inhibitoutput pulses if the thermistor input voltage rises above a

542


reference value (see Fig. 9).

Determination of required supply current

Before any calculations concerning the required supplycurrent can be made, the maximum average output currentof the TDA1023 must be determined. The minimum supplycurrent required is the sum of the following currents:

• the maximum average output current• the current drawn by the temperature-sense circuit• the current required by the integrated circuit.

For worst-case conditions, a 5% tolerance for RS and RG

and a 10% variation of the mains is assumed. Figure 10shows graphs of IG(AV)max as a function of RG and RS for four50Hz supply voltages. Below RG=22Ω there is no furtherincrease in IG as the output current is limited. The currentdrawn by the temperature-sensing circuit must not begreater than 1mA. The current consumption of the

TDA1023 depends upon the hysteresis and proportionalband settings. Figure11 shows the minimum supply currentas a function of the average output current for limit settings.

Fig. 11 Maximum required input current as function ofgate current for limits of hysteresis band settings

5 10 15 20 25 300

5

10

15

20

25GatecurrentI3 (mA)

Supply current I16 (mA)

I4=0I5=0

V4=0V5=0

Fig. 12 Input current as a function of RD and power dissipation (with and without series diode)

543


The mains dropping resistor, R D

The value of the mains dropping resistor must be chosensuch that the average supply current to the input of theTDA1023 is at least equal to the required minimum. Thevalue of the resistor RD is defined by the maximum currentthat can flow into Pin 16, the maximum peak mains voltage,and the minimum voltage at Pin 16. Table 5 shows practicalvalues for RD(min) for four common mains supply voltages

Supply voltage Vs (V) RD(min) (kΩ)

110 2.0220 3.9240 4.3380 7.5

Table 5. Mains dropping resistor values

Fig. 13 Use of a mains dropping capacitor, CD

The power dissipated by the dropping resistor has beencomputed for four mains voltages as a function of RD andthe results plotted on the graphs of Fig. 12. The powerdissipated in RD may be considerably reduced by theaddition of a series diode as in Fig. 14. In this case thereis no conduction through RD during the negative half-cycleof the supply voltage, giving a reduction of more than 50%of the power dissipated in RD.

Use of a mains dropping capacitorIt is possible to replace the mains dropping resistor andseries diode with a capacitor, Fig. 13, and thereby reducethe power dissipation in the voltage reduction componentsstill further. However, for mains voltages below 200V, thepower dissipated by the dropping resistor is comparativelysmall and the use of a capacitor is not considered to benecessary. For mains voltages above 240V, the additionalcost of the required high-voltage capacitor is not justified.For these reasons, it is recommended that capacitivevoltage reduction is only used with mains supplies of200V(RMS) or 240V(RMS).

When selecting a capacitor for mains voltage reduction, thefollowing points must be considered:

• AC voltage rating

• Suppression of mains-borne transients - Avoltage-dependent resistor must be connectedacross the mains input to limit mains borne transients.For RSD=390Ω this yields a maximum transientvoltage of about 740V. For 220V operation, a VDR(catalogue number 2322 594 13512) will limit thesupply voltage to the required level during currenttransients of up to about 200A. For 240V operation,a VDR (catalogue number 2322 594 13912) will limitthe supply voltage to the required level during currenttransients of up to about 80A.

• Limit of Inrush current - The capacitor CD must notbe chosen so large that the input current to theTDA1023 violates the absolute maximum specified inthe published data. A practical value for CD is 680nF.Resistor RSD must also limit the peak value of theinrush current to less than 2A under worst caseoperating conditions. With a 240V (+10%) supply, thevalue of 390Ω (-5%) will limit the worst case peakvalue of the inrush current to:

Triac protectionIf the mains dropping circuit consists of capacitor CD andresistor RSD, a VDR must be included in the circuit asdescribedabove. This VDR will also protect the triac againstcurrent surges in the mains supply. If the mains droppingcircuit consists of resistor RD and diode D1, the VDR maybe connected directly across the triac, giving improvedprotection due to the series resistance of the heater.Currentsurges in the supply will not harm the TDA1023 as thedropping resistor will limit the current to a safe level.

Application examplesThe TDA1023 is intended primarily for room temperaturecontrol using electric panel heaters. The controllable heaterpower range is from 400W to 2000W, although the upperlimit may be increased by suitable choice of triacs and/orheatsinks. The TDA1023 may also be used as a timeproportional switch for cooker elements and similardevices, giving 100% control of the power dissipation.

1. Domestic panel heater controllerFigure 3 showed the design for a time proportional heatercontrol using the TDA1023. Economies may be gained bythe use of smaller or lower power components and so twoversions are described in Table 6. Version A, for heatersfrom 400W to 1200W, uses a BT138 triac and a 15µF timingcapacitor, version B, for heaters from 1200W to 2000W,uses a BT139 triac and a 68µF timing capacitor. Table 6gives the necessary component values under worst caseconditions for each of these versions for use with mainssupplies of 220V, 50Hz.

13

16

CDRSD

VaristorTDA1023

240× 1.10.95× 390

√2 = 1.01A

544


The capacitor C1 has been included in the circuit of Fig. 3to minimise sensor line interference pick-up. This is onlynecessary when the sensor is remote from the controlcircuit. The built-in hysteresis and proportional bandprovides optimum performance for panel heaters so pins 4and 5 are not connected.

Component Version A Version B400W - 1200W 1200W - 2000W

T1 BT138-500 BT139-500VDR 1 350V, 1mA 350V, 1mA

D1 BYX10G BYX10GR1

2 18.7kΩ 18.7kΩRNTC 3 R25=22kΩ,B=4200k R25=22kΩ, B=4200k

RP 22kΩ 22kΩRD 4.3kΩ 6.2kΩRG 82Ω 82ΩRS 430kΩ 180kΩC1 47nF 47nFCS 220µF, 16V 220µF, 16VCT 15µF (DC) 68µF (DC)

CD 4 680nF 470nFRSD 4 390Ω 390Ω

Notes: 1. Cat. No. 2322 594 135122. 1% tolerance3. Cat. No. 2322 642 122234. Only required if used in place of D1 and RD

Table 6. 220V, 50Hz temperature controller components

2. Temperature control of 2kW load.

For a load power of 2kW the BT139 triac must be used. Thecircuit is also that shown in Fig. 3. Table 7 gives a summaryof the required component values.

Component Value Remarks

T1 BT139-500VDR 350V, 1mA No. 2322 594 13912D1 BYX10GR1 18.7kΩ 1% tolerance

RNTC R25=22kΩ, B=4200k No. 2322 642 12223RP 22kΩRD 6.8kΩRG 82ΩRS 150kΩC1 47nFCS 220µF, 16VCT 47µF (DC) No. 2222 016 90129

Table 7. 2000W, 220V, 50Hz temperature controller

Value of R S

The required trigger pulse width can be found from Fig. 4as a function of the load power, latch current and supplyvoltage (2000W, 60mA, and 220V, 50Hz, respectively):tp(min)=64µs. A value of RS=135kΩ provides a trigger pulseof the required duration. The next preferred value abovethis is 150kΩ, providing a tp(min) of approximately 70µs.

Value of R G

The maximum value of RG that may be used is determinedby the minimum conditions to reliably trigger all samples ofthe triac. In Fig. 6 it can be seen that the operation point of1.6V and 98 mA lies on the load line for 82Ω and this is thevalue chosen.

Value of C T

For a load of 2kW, the repetition period must be at least24s (from Table 1). From Table 4 the minimum preferredvalue of CT to provide this period is 68µF. However, due tothe different performance under AC and DC conditions,then from Table 3, the actual capacitor used should be47µF, 25V.

Value of R 1 and RP

For control over the range 5˚C to 35˚C and a thermistorcharacteristics with R25=22kΩ, a suitable value of R1 is18.7kΩ ±1%. A suitable value for RP is 22kΩ.

Value of R D

First, the maximum average output current must be found.From Fig. 10 the maximum gate current IG is given as afunction of the values of resistors RS and RG. For this circuitIG(AV)max=5 mA. Once the maximum average output currentis known, the minimum required supply current can befound from Fig. 11. With minimum hysteresis andproportional band, the average value of the supply currentis 12.5 mA. Using this value of input current the requiredvalue of RD can be found from Fig. 12 giving RD = 5.6 kΩ.The power dissipation in the resistor when diode D1 ispresent in the circuit is then 5 W.

3. Time proportional power controlThe TDA1023 may be used to provide proportional controlof devices such as electric cooker elements. Thetemperature-sensing bridge is replaced by apotentiometer,the power in the load being proportional to thepotentiometer setting. Proportional power control is thusobtained while the potentiometer voltage lies between theupper and lower limits of the triangular waveformcomparator input.

As the timing capacitor is charged and discharged bycurrent sources, the voltage across it will never reach zero,so that load power will be zero before the potentiometerreaches its minimum setting. Similarly, maximum loadpower is reached before the maximum setting of thepotentiometer. This effect can be reduced by the additionof resistors R1 and R2. To ensure that 0% and 100% load

545


power can be selected by the potentiometer setting, thevalues of R1 and R2 should each be limited to 10% of thevalue of RP.

All the circuit components are calculated in the same wayas for the temperature controller, including the timingcapacitor CT. An example circuit, with components suitablefor the control of loads from 1kW to 2kW from 220V, 50Hzsupplies, is shown in Fig. 14 and Table 8.

Component Value

T1 BT139-500VDR ZnO, 350V, 1mAD1 BYX10GR1 4.7kΩR2 4.7kΩRP 47kΩRD 5.6kΩRG 82ΩRS 220kΩCS 220µF, 16VCT 47µF, 25V

Table 8. Time proportional power controller

Fig. 14 Time-proportional power regulation circuit

4. Phase control circuit using the TDA1023

Figure 15 shows an adjustable phase control trigger circuitsuitable for thyristor or triac controller applications. Thecircuit uses the TDA1023 control chip and an NE555 timerdevice to give output phase control proportional to the inputvoltage command.

AC line

AC line

D1

RD

RS

CS

Load

RG

CT

VaristorTDA1023

R1

R2

RP

11 14 10 16

3

1312

76

9

T1

Fig. 15 Adjustable phase SCR/Triac trigger circuit

546


Hi-Com Triacs

547


6.3.1 Understanding Hi-Com Triacs

Hi-Com triacs from Philips Semiconductors are specificallydesigned to give superior triac commutation performancein the control of motors for domestic equipment and tools.These devices are suitable for use with a wide variety ofmotor and inductive loads without the need for a protectivesnubber. The use of a Hi-Com triac greatly simplifies circuitdesign and gives significant cost savings to the designer.

This product information sheet explains how the superiorcharacteristics and performance of Hi-Com triacs removesdesign limitations of standard devices.

Triac commutation explainedA triac is an AC conduction device, and may be thought ofas two antiparallel thyristors monolithically integrated ontothe same silicon chip.

In phase control circuits the triac often has to be triggeredinto conduction part way into each half cycle. This meansthat at the end of each half cycle the on-state current in onedirection must drop to zero and not resume in the otherdirection until the device is triggered again. This"commutation" turn-off capability is at the heart of triacpower control applications.

If the triac were truly two separate thyristors thisrequirement would not present any problems. However, asthe two are on the same piece of silicon there is thepossibility that the "reverse recovery current" (due tounrecombined charge carriers) of one thyristor as it turnsoff, may act as gate current to trigger the other thyristor asthe voltage rises in the opposite direction. This is describedas a "commutation failure" and results in the triac continuingto conduct in the opposite direction instead of blocking.

The probability of any device failing commutation isdependent on the rate of rise of reverse voltage (dV/dt) andthe rate of decrease of conduction current (dI/dt). Thehigher the dI/dt the more unrecombined charge carriers areleft at the instant of turn-off. The higher the dV/dt the moreprobable it is that some of these carriers will act as gatecurrent. Thus the commutation capability of any device isusually specified in terms of the turn-off dI/dt and there-applied dV/dt it can withstand, at any particular junctiontemperature.

If a triac has to be operated in an inductive load circuit witha combination of dI/dt and dV/dt that exceeds itsspecification, it is necessary to use an RC-snubber networkin parallel with the device to limit the dV/dt. This is at apenalty of extra circuit complexity and dissipation in thesnubber. The "High Commutation" triacs (Hi-Com triacs)are designed to have superior commutation capability, sothat even at a high rate of turn-off (dI/dt) and a high rate ofre-applied dV/dt they can be used without the aid of a

snubber network, thus greatly simplifying the circuit. Thedesign features of Hi-Com devices that have made thispossible are:

Geometric separation of the twoantiparallel thyristors

Commutation failure can be avoided by physicallyseparating the two ’thyristor halves’ of a triac. However,separating them into two discrete chips would remove theadvantage of a triac being triggerable in both directions bythe same gate connection. Within the integrated structureof a Hi-Com triac the two halves of the device are keptfurther apart by modifying the layout of the chip in order tolessen the chance of conduction in one half affecting theother half.

Emitter shorting

"Emitter shorts" refer to the on-chip resistive paths betweenemitter and base of a transistor. A higher degree of emittershorting means the presence of more such paths and lowerresistance values in them. The use of emitter shorts in atriac has two effects on commutation.

Fig. 1 Standard triac triggering quadrants

Firstly it reduces the gain of the internal transistors thatmake up the triac. This means there will be fewer carriersleft to recombine when the conduction current falls to zero,and therefore a smaller probability that a sufficient numberwill be available to re-trigger the triac. The second way inwhich emitter shorts help commutation is that anyunrecombined carriers in the conducting thyristor at turn-off



G+G-

MT2+

MT2-

IG

IG

IG

IG

++

- -

+

-

+

-

549


will have more chance of flowing out through the emittershorts (of the opposite thyristor) rather than acting as gatecurrent to trigger that thyristor on.

The Hi-Com triacs have a higher degree of emitter shortingboth around the periphery of the device and in the centralpart of the active area. This both reduces the number ofcarriers available, and lessens the danger of any availablecarriers acting as gate current for undesirable triggering.

Modified gate structureThe gate of a triac allows conduction in both directions tobe initiated by either a positive or a negative current pulsebetween gate (G) and main terminal (MT1). The fourdifferent modes of triggering are often called 1+, 1-, 3- and3+ (or sometimes quadrants 1, 2, 3 and 4) and are shownin Fig. 1.

This triggering versatility arises from the fact that the gateconsists of some elements which conduct temporarilyduring the turn-on phase. In particular, one of the triggeringmodes, 3+ (or quadrant 4), relies on the main terminal 1supplying electrons to trigger a thyristor element in thegate-MT1 boundary. Conduction then spreads to the mainthyristor element from this boundary.

Unfortunately the carrier distribution in this triggering modeof operation is very similar to that existing when the triac iscommutating in the 1-to-3 direction (i.e changing from

conduction with MT2positive to blocking with MT1positive).The presence of the element in the gate to allow 3+triggering will therefore always also underminecommutation capability in the 1-to-3 direction. For thisreason the Hi-Com triacs have a modified gate design toremove this structure. This incurs the penalty that the 3+trigger mode cannot be used, but it greatly improves thecommutation performance of the device.

Conclusions

By modifications to the internal design and layout of thetriac it is possible to achieve a high commutation capabilitytriac for use in inductive and motor load applications. Thesemodifications have been implemented in the Hi-Com rangeof devices from Philips Semiconductors. The devices canbe used in all typical motor control applications without theneed for a snubber circuit. The commutation capability ofthe devices is well in excess of the operating conditions intypical applications.

As the loss of the fourth trigger quadrant can usually betolerated in most designs, Hi-Com triacs can be used inexisting motor control applications without the snubbernetwork required for a standard device. This gives thedesigner significant savings in design simplicity, boardspace and system cost.

550


6.3.2 Using Hi-Com Triacs

Hi-Com triacs from Philips Semiconductors are specificallydesigned to give superior triac commutation performancein the control of motors for domestic equipment and tools.These devices are suitable for use with a wide variety ofmotor and inductive loads without the need for a snubber.The use of a Hi-Com triac greatly simplifies circuit designand gives significant cost savings to the designer.

This product information sheet explains how the need fora triac snubber arises and how the superior performanceof Hi-Com triacs removes design limitations of standarddevices. The Hi-Com range is summarised in Table 1.

Triac commutationFor resistive loads the device current is in phase with theline voltage. Under such conditions triac turn-off(commutation) occurs at the voltage "zero-crossover" point.This is not a very severe condition for triac commutation:the slow rising dV/dt gives time for the triac to turn off(commutate) easily.

The situation is quite different with inductive or motor loads.For these circuits conduction current lags behind the linevoltage as shown in Fig. 1. When triac commutation occursthe rate of rise of voltage in the opposite direction can bevery rapid and is governed by the circuit and device

characteristics. This high dV/dt means there is a muchhigher probability of charge carriers in the devicere-triggering the triac and causing a commutation failure.

Hi-Com triacs

Hi-Com triacs are specifically designed for use with acinductive loads such as motors. As commutation capabilityis not an issue for resistive load applications then standardtriacs are still the most appropriate devices for theseapplications. The significant advantage of a Hi-Com triacis that it has no limitation on the rate of rise of reappliedvoltage at commutation. This removes the requirement fora snubber circuit in inductive load circuits. An additionaladvantage of the Hi-Com design is that the off-state (static)dv/dt capability of the device is also significantly improved.

When using Hi-Com triacs in inductive load applications thetrigger circuit cannot trigger the device in the fourth (3+)quadrant (Fig. 2). Fortunately the vast majority of circuitdesigns do not require this mode of operation and so aresuitable for use with Hi-Com triacswithout modification. Thecircuit of Fig. 3 is a typical example of the simplest type oftrigger circuit. Hi-Com triacs are equally suitable for usewith microcontroller trigger circuits.

Parameter BTA212-600B BTA212-800B BTA216-600B BTA216-800B

Repetitive peak voltage VDRM (V) 600 800 600 800RMS on-state current IT(RMS) (A) 12 12 16 16Gate trigger current IGT (mA) 2 - 50 2 - 50 2 - 50 2 - 50Off state dv/dt dVD/dt (V/µs) 1000 1000 1000 1000Commutating di/dt dIcom/dt (A/ms) 24 24 28 28Turn-on di/dt dIT/dt (A/µs) 50 50 50 50Package TO220 TO220 TO220 TO220

Table 1. Philips Semiconductors Hi-Com Triac range

551


Fig. 1 Triac commutation waveforms (inductive load)

Fig. 2 Hi-Com triac triggering quadrants

Device limiting valuesi) Trigger current, I GT

Trigger current for the Hi-Com triacs is in the range 2mA to50mA. This means that gate currents due to noise that arebelow 2mA in amplitude can be guaranteed not to triggerthe devices. This gives the devices a noise immunity featurethat is important in many applications. The trigger currentdelivered by the trigger circuit must be greater than 50mAunder all conditions in order to guarantee triggering of thedevice when required. As discussed above, triggering is

only possible in the 1+, 1- and 3- quadrants.

Fig. 3 Phase control circuit using Hi-Com triac

ii) Rate of change of current, dI com/dtHi-Com triacs do not require a snubber network providingthat the rate of change of current prior to commutation isless than the rating specified in the device data sheet. ThisdIcom/dt limit is well in excess of the currents that occur inthe device under normal operating conditions, duringtransients such as start-up and faults such as the stalledmotor condition.

For the 12A Hi-Com triacs the limit commutating current istypically 24A/ms at 125˚C. This corresponds to an RMScurrent of 54A at 50Hz. For the 16A Hi-Com triacs the limitcommutating current is typically 28A/ms at 125˚C. Thiscorresponds to an RMS current of 63A at 50Hz. Typicalstall currents for an 800W domestic appliance motor are inthe range 15A to 20A and so the commutation capability ofthe Hi-Com triacs is well above the requirement for this typeof application.

Conclusions

The Hi-Com range of devices from Philips Semiconductorscan be used in all typical motor control applications withoutthe need for a snubber circuit. The commutation capabilityof the devices is well in excess of the operating conditionsin typical applications.

As the loss of the fourth trigger quadrant can usually betolerated in most designs, Hi-Com triacs can be used inexisting motor control applications. By removing thesnubber the use of a Hi-Com triac gives the designersignificant savings in design simplicity, board space andsystem cost.

VDWM

-dI/dtdVcom/dt

Time

Time

Time

Supplyvoltage

Loadcurrent

Voltageacrosstriac

Triggerpulses

Current

Hi-Com triac

M



G+G-

MT2+

MT2-

IG

IG

IG

++

- -

+

-

No triggering

possible

552

Thermal Management Power Semiconductor ApplicationsPhilips Semiconductors

CHAPTER 7

Thermal Management

7.1 Thermal Considerations

553


Thermal Considerations

555


7.1.1 Thermal Considerations for Power Semiconductors

The perfect power switch is not yet available. All powersemiconductors dissipate power internally both during theon-state and during the transition between the on and offstates. The amount of power dissipated internally generallyspeaking increases in line with the power being switchedby the semiconductor. The capability of a switch to operatein a particular circuit will therefore depend upon the amountof power dissipated internally and the rise in the operatingtemperature of the silicon junction that this powerdissipation causes. It is therefore important that circuitdesigners are familiar with the thermal characteristics ofpower semiconductors and are able to calculate powerdissipation limits and junction operating temperatures.

This chapter is divided into two parts. Part One describesthe essential thermal properties of semiconductors andexplains the concept of a limit in terms of continuous modeand pulse mode operation. Part Two gives workedexamples showing junction temperature calculations for avariety of applied power pulse waveforms.

PART ONE

The power dissipation limitThe maximum allowable power dissipation forms a limit tothe safe operating area of power transistors. Powerdissipation causes a rise in junction temperature which will,in turn, start chemical and metallurgical changes. The rateat which these changes proceed is exponentially related totemperature, and thus prolonged operation of a powertransistor above its junction temperature rating is liable toresult in reduced life. Operation of a device at, or below, itspower dissipation rating (together with carefulconsideration of thermal resistances associated with thedevice) ensures that the junction temperature rating is notexceeded.

All power semiconductors have a power dissipationlimitation. For rectifier products such as diodes, thyristorsand triacs, the power dissipation rating can be easilytranslated in terms of current ratings; in the on-state thevoltage drop is well defined. Transistors are, however,somewhat more complicated. A transistor, be it a powerMOSFET or a bipolar, can operate in its on-state at anyvoltage up to its maximum rating depending on the circuitconditions. It is therefore necessary to specify a SafeOperating Area (SOA) for transistors which specifies thepower dissipation limit in terms of a series of boundaries inthe current and voltage plane. These operating areas areusuallypresented for mounting base temperatures of 25 ˚C.At higher temperatures, operating conditions must bechecked to ensure that junction temperatures are notexceeding the desired operating level.

Continuous power dissipation

The total power dissipation in a semiconductor may becalculated from the product of the on-state voltage and theforward conduction current. The heat dissipated in thejunction of the device flows through the thermal resistancebetween the junction and the mounting base, Rthj-mb. Thethermal equivalent circuit of Fig. 1 illustrates this heat flow;Ptot can be regarded as a thermal current, and thetemperature difference between the junction and mountingbase ∆Tj-mb as a thermal voltage. By analogy with Ohm’slaw, it follows that:

Fig. 1 Heat transport in a transistor with powerdissipation constant with respect to time

Fig. 2 shows the dependence of the maximum powerdissipation on the temperature of the mounting base. Ptotmax

is limited either by a maximum temperature difference:

or by the maximum junction temperature Tjmax (Tmb K isusually 25˚C and is the value of Tmb above which themaximum power dissipation must be reduced to maintainthe operating point within the safe operating area).

In the first case, Tmb ≤ Tmb K :

that is, the power dissipation has a fixed limit value (Ptot max K

is the maximum d.c. power dissipation below Tmb K). If thetransistor is subjected to a mounting-base temperatureTmb 1, its junction temperature will be less than Tjmax by anamount (TmbK - Tmb 1), as shown by the broken line in Fig. 2.

Ptot =Tj − Tmb

Rthj − mb

1

∆Tj − mbmax = Tjmax − Tmb K 2

Ptot maxK =∆Tj − mbmax

Rthj − mb

; 3

557


Fig. 2 Maximum d.c. power dissipation in a transistoras a function of the mounting-base temperature

In the second case, Tmb > Tmb K :

that is, the power dissipation must be reduced as themounting base temperature increases along the slopingstraight line in Fig. 2. Equation 4 shows that the lower thethermal resistance Rthj-mb, the steeper is the slope of theline. In this case, Tmb is the maximum mounting-basetemperature that can occur in operation.

Example

The following data is provided for a particular transistor.

Ptot maxK = 75 W

Tjmax = 175 ˚C

Rthj-mb ≤ 2 K/W

Themaximumpermissible power dissipation for continuousoperation at a maximum mounting-base temperature ofTmb = 80 ˚C is required.

Note that the maximum value of Tmb is chosen to besignificantly higher than the maximumambient temperatureto prevent an excessively large heatsink being required.

From Eq. 4 we obtain:

Provided that the transistor is operated within SOA limits,this value is permissible since it is below Ptot max K. The sameresult can be obtained graphically from the Ptot max diagram(Fig. 3) for the relevant transistor.

Fig. 3 Example of the determination of maximum powerdissipation

Pulse power operationWhen a power transistor is subjected to a pulsed load,higher peak power dissipation is permitted. The materialsin a power transistor have a definite thermal capacity, andthus the critical junction temperature will not be reachedinstantaneously, even when excessive power is beingdissipated in the device. The power dissipation limit maybe extended for intermittent operation. The size of theextension will depend on the duration of the operationperiod (that is, pulse duration) and the frequency with whichoperation occurs (that is, duty factor).

Fig. 4 Heating of a transistor chip

If power isapplied to a transistor, the device will immediatelystart to warm up (Fig. 4). If the power dissipation continues,a balance will be struck between heat generation andremoval resulting in the stabilisation of Tj and ∆Tj-mb. Someheat energy will be stored by the thermal capacity of thedevice, and the stable conditions will be determined by thethermal resistances associated with the transistor and itsthermal environment. When the power dissipation ceases,the device will cool (the heating and cooling laws will beidentical, see Fig. 5). However, if the power dissipationceases before the temperature of the transistor stabilises,the peak values of Tj and ∆Tj-mb will be less than the values

0 20 40 60 80 100 120 140 160 180Tmb / C

Ptotmax / W100

90

80

70

60

50

40

30

20

10

0

47.5

Ptot max =Tjmax − Tmb

Rthj − mb

; 4

Ptot max =175−80

2W, =47.5W

558


reached for the same level of continuous power dissipation(Fig. 6). If the second pulse is identical to the first, the peaktemperature attained by the device at the end of the secondpulse will be greater than that at the end of the first pulse.Further pulses will build up the temperature until some newstable situation is attained (Fig. 7). The temperature of thedevice in this stable condition will fluctuate above andbelowthe mean. If the upward excursions extend into the regionof excessive Tj then the life expectancy of the device maybe reduced. This can happen with high-powerlow-duty-factor pulses, even though the average power isbelow the d.c. rating of the device.

Fig. 5 Heating and cooling follow the same law

Fig. 6 The peak temperature caused by a short powerpulse can be less than the steady-state temperature

resulting from the same power

Fig. 8 shows a typical safe operating area for d.c. operationof a power MOSFET. The corresponding rectangular-pulseoperating areas with a fixed duty factor, δ = 0, and the pulsetime tp as a parameter, are also shown. These boundariesrepresent the largest possible extension of the operatingarea for particular pulse times. When the pulse timebecomes very short, the power dissipation does not havea limiting action and the pulsecurrent and maximumvoltageform the only limits. This rectangle represents the largestpossible pulse operating area.

Fig. 7 A train of power pulses increases the averagetemperature if the device does not have time to cool

between pulses

Fig. 8 D.C. and rectangular pulse operating areas withfixed parameters δ=0, tp and Tmb=25˚C

In general, the shorter the pulse and the lower thefrequency, the lower the temperature that the junctionreaches. By analogy with Eq. 3, it follows that:

where Zthj-mb is the transient thermal impedance betweenthe junction and mounting base of the device. It dependson the pulse duration tp, and the duty factor δ, where:

1 100VDS / V

ID / A100

10

1

0.1

10 us

100 us

1 ms

10 ms

RDS(ON) =

VDS/ID

100 ms DC

tp =

BUK553-100

10

B

A

Ptot M =Tj −Tmb

Zthj − mb

, 5

559


and T is the pulse period. Fig. 9 shows a typical family ofcurves for thermal impedance against pulse duration, withduty factor as a parameter.

Fig. 9 Example of the presentation of the transientthermal impedance as a function of the pulse time with

duty factor as parameter

Again, the maximum pulse power dissipation is limitedeither by the maximum temperature difference ∆Tj-mb max

(Eq. 2), or by the maximum junction temperature Tjmax, andso by analogy with Eqs. 3 and 4:

when Tmb ≤ Tmb K, and:

when Tmb > Tmb K. That is, below a mounting-basetemperature of Tmb K, the maximum power dissipation hasa fixed limit value; and above Tmb K, the power dissipationmust be reduced linearly with increasing mounting-basetemperature.

Short pulse duration (Fig. 10a)As the pulse duration becomes very short, the fluctuationsof junction temperature become negligible, owing to theinternal thermal capacity of the transistor. Consequently,the only factor to be considered is the heating of the junctionby the average power dissipation; that is:

The transient thermal impedance becomes:

The Zthj-mb curves approach this value asymptotically as tpdecreases. Fig. 9 shows that, for duty factors in the range0.1 to 0.5, the limit values given by Eq. 10 have virtuallybeen reached at tp = 10-6 s.

Fig. 10 Three limit cases of rectangular pulse loads:(a) short pulse duration(b) long pulse duration(c) single-shot pulse

Long pulse duration (Fig. 10b)As the pulse duration increases, the junction temperatureapproaches a stationary value towards the end of a pulse.The transient thermal impedance tends to the thermalresistance for continuous power dissipation; that is:

Fig. 9 shows thatZthj-mb approaches this valueas tp becomeslarge. In general, transient thermal effects die out in mostpower transistors within 0.1 to 1.0 seconds. This timedepends on the material and construction of the case, thesize of the chip, the way it is mounted, and other factors.Power pulses with a duration in excess of this time haveapproximately the same effect as a continuous load.

δ =tp

T, 6

limtp →0

Zthj − mb= δRthj − mb 10

1E-07 1E-05 1E-03 1E-01 1E+01t / s


1E+00

1E-01

1E-02

1E-03

0

0.5

0.2

0.1

0.05

0.02

=tp tp

T

TP

t

D

=

BUK553-100A

Ptot maxK =∆Tj − mbmax

Zthj − mb

, 7

Ptot M max =Tjmax−Tmb

Zthj − mb

, 8

limtp → ∞

Zthj − mb=Rthj − mb 11

Ptot(av) = δPtot M 9

560


Single-shot pulses (Fig. 10c)As the duty factor becomes very small, the junction tendsto cool down completely between pulses so that each pulsecan be treated individually. When considering singlepulses, the Zthj-mb values for δ = 0 (Fig. 9) give sufficientlyaccurate results.

PART TWO

Calculating junction temperaturesMost applications which include power semiconductorsusually involve some form of pulse mode operation. Thissection gives several worked examples showing howjunction temperatures can be simply calculated. Examplesare given for a variety of waveforms:

(1) Periodic Waveforms

(2) Single Shot Waveforms

(3) Composite Waveforms

(4) A Pulse Burst

(5) Non Rectangular Pulses

From the point of view of reliability it is most important toknow what the peak junction temperature will be when thepower waveform is applied and also what the averagejunction temperature is going to be.

Peak junction temperature will usually occur at the end ofan applied pulse and its calculation will involve transientthermal impedance. The average junction temperature(where applicable) is calculated by working out the averagepower dissipation using the d.c. thermal resistance.

Fig. 11 Periodic Rectangular Pulse

When considering the junction temperature in a device, thefollowing formula is used:

where ∆Tj-mb is found from a rearrangement of equation 7.In all the following examples the mounting basetemperature (Tmb) is assumed to be 75˚C.

Periodic rectangular pulseFig. 11 shows an example of a periodic rectangular pulse.This type of pulse is commonly found in switchingapplications. 100W is dissipated every 400µs for a periodof 20µs, representing a duty cycle (δ) of 0.05. The peakjunction temperature is calculated as follows:

The value for Zth j-mb is taken from the δ=0.05 curve shownin Fig. 12 (This diagram repeats Fig. 9 but has beensimplified for clarity). The above calculation shows that thepeak junction temperature will be 85˚C.

Single shot rectangular pulseFig. 13 shows an example of a single shot rectangularpulse. The pulse used is the same as in the previousexample, which should highlight the differences betweenperiodic and single shot thermal calculations. For a singleshot pulse, the time period between pulses is infinity, ie theduty cycle δ=0. In this example 100W is dissipated for aperiod of 20µs. To work out the peak junction temperaturethe following steps are used:

The value for Zth j-mb is taken from the δ=0 curve shown inFig. 12. The above calculation shows that the peak junctiontemperature will be 4˚C above the mounting basetemperature.

Peak Tj: t = 2× 10−5s

P = 100W

δ =20400

= 0.05

Zthj − mb = 0.12K/W

∆Tj − mb = P × Zthj − mb = 100× 0.12= 12°C

Tj = Tmb + ∆Tj − mb = 75+ 12= 87°C

Average Tj: Pav = P × δ = 100× 0.05= 5W

∆Tj − mb(av) = Pav × Zthj − mb(δ = 1) = 5× 2 = 10°C

Tj (av) = Tmb + ∆Tj − mb(av) = 75+ 10= 85°C

0102030405060708090

100110

0 20 40 60 80 100 400 420 440 460 480

POWER(W)

TIME(uS)

0 20 40 60 80 100 400 420 440 460 480TIME(uS)

Tmb

Tjpeak

Tj t = 2× 10−5s

P = 100W

δ = 0

Zthj − mb = 0.04K/W

∆Tj − mb = P × Zthj − mb = 100× 0.04= 4°C

Tj = Tmb + ∆Tj − mb 14

561


Fig. 12 Thermal impedance curves for δ=0.05 and δ=0

Fig. 13 Single Shot Pulse

For a single shot pulse, the average power dissipated andaverage junction temperature are not relevant.

Composite rectangular pulseIn practice, a power device frequently has to handlecomposite waveforms, rather than the simple rectangularpulses shown so far. This type of signal can be simulatedby superimposing several rectangular pulses which have acommon period, but both positive and negative amplitudes,in addition to suitable values of tp and δ.

By way of an example, consider the composite waveformshown in Fig. 14. To show the way in which the methodused for periodic rectangular pulses is extended to covercomposite waveforms, the waveform shown has beenchosen to be an extension of the periodic rectangular pulseexample. The period is 400µs, and the waveform consistsof three rectangular pulses, namely 40W for 10µs, 20W for150µs and 100W for 20µs. The peak junction temperaturemay be calculated at any point in the cycle. To be able toadd the various effects of the pulses at this time, all thepulses, both positive and negative, must end at time tx inthe first calculation and ty in the second calculation. Positivepulses increase the junction temperature, while negativepulses decrease it.

Calculation for time t x

In equation 15, the values for P1, P2 and P3 are known:P1=40W, P2=20W and P3=100W. The Zth values are takenfrom Fig. 9. For each term in the equation, the equivalentduty cycle must be worked out. For instance the firstsuperimposed pulse in Fig. 14 lasts for a time t1 = 180µs,representing a duty cycle of 180/400 = 0.45 = δ. Thesevalues can then be used in conjunction with Fig. 9 to find avalue for Zth, which in this case is 0.9K/W. Table 1a givesthe values calculated for this example.

t1 t2 t3 t4

180µs 170µs 150µs 20µs

Repetitive δ 0.450 0.425 0.375 0.050T=400µs Zth 0.900 0.850 0.800 0.130

Single Shot δ 0.000 0.000 0.000 0.000T=∞ Zth 0.130 0.125 0.120 0.040

Table 1a. Composite pulse parameters for time tx

1E-07 1E-05 1E-03 1E-01 1E+01t / s


1E+00

1E-01

1E-02

1E-03

0

0.05

=tp tp

T

TP

t

D

=

0.04

0.12

0

10

20

30

40

50

60

70

80

90

100

110

0 20 40 60 80 100

POWER(W)

0 20 40 60 80 100Tmb

Tjpeak

Tj

∆Tj − mb@x = P1.Zthj − mb(t1) + P2.Zthj − mb(t3)

+ P3.Zthj − mb(t4) − P1.Zthj − mb(t2)

− P2.Zthj − mb(t4) 15

562


Fig. 14 Periodic Composite Waveform

0 20 40 60 80 100

0

20

40

60

80

100

200

180

160

140

120

100

80

60

40

20

0

20

40

60

120 140 160 180 200 220

P3

P2

P1

P1

P2

t1t2

t3t4

360 380 400 420 440 460 480 500

tx tyPOWER (W)

Time (uS)

160

140

120

100

80

60

40

20

0

20

40

60

80

100

t5t6

t7t8

120

P2

P3

P1

P2

P3

POWER (W)

POWER (W)Time (uS)

Time (uS)

Substituting these values into equation 15 for Tj-mb@x gives

Hence the peak values of Tj are 104.4˚C for the repetitivecase, and 80.9˚C for the single shot case.

Single Shot: ∆Tj − mb@x = 40× 0.13+ 20× 0.125

+ 100× 0.04− 40× 0.125

− 20× 0.04

= 5.9°C

Tj = Tmb + ∆Tj − mb = 75+ 5.9= 80.9°C

Repetitive: ∆Tj − mb@x = 40× 0.9+ 20× 0.85

+ 100× 0.13− 40× 0.85

− 20× 0.13

= 29.4°C

Tj = Tmb + ∆Tj − mb = 75+ 29.4= 104.4°C

563


Calculation for time t y

where Zthj-mb(t) is the transient thermal impedance for a pulsetime t.

t5 t6 t7 t8380µs 250µs 230µs 10µs

Repetitive δ 0.950 0.625 0.575 0.025T=400µs Zth 1.950 1.300 1.250 0.080

Single Shot δ 0.000 0.000 0.000 0.000T=∞ Zth 0.200 0.160 0.150 0.030

Table 1b. Composite pulse parameters for time ty

Substituting these values into equation 16 for Tj-mb@y gives

Hence the peak values of Tj are 96.2˚C for the repetitivecase, and 78˚C for the single shot case.

The average power dissipation and the average junctiontemperature can be calculated as follows:

Clearly, the junction temperature at time tx should be higherthan that at time ty, and this is proven in the abovecalculations.

Burst pulsesPower devices are frequently subjected to a burst of pulses.This type of signal can be treated as a composite waveformandas in the previous example simulated by superimposingseveral rectangular pulses which have a common period,but both positive and negative amplitudes, in addition tosuitable values of tp and δ.

Fig. 15 Burst Mode Waveform

Consider the waveform shown in Fig. 15. The period is240µs, and the burst consists of three rectangular pulsesof 100W power and 20µs duration, separated by 30µs. Thepeak junction temperaturewill occurat the endof each burstat time t = tx = 140µs. To be able to add the various effectsof the pulses at this time, all the pulses, both positive andnegative, must end at time tx. Positive pulses increase thejunction temperature, while negative pulses decrease it.

where Zthj-mb(t) is the transient thermal impedance for a pulsetime t.

The Zth values are taken from Fig. 9. For each term in theequation, the equivalent duty cycle must be worked out.These values can then be used in conjunction with Fig. 9to find a value for Zth. Table 2 gives the values calculatedfor this example.

t1 t2 t3 t4 t5

120µs 100µs 70µs 50µs 20µs

Repetitive δ 0.500 0.420 0.290 0.210 0.083T=240µs Zth 1.100 0.800 0.600 0.430 0.210

Single Shot δ 0.000 0.000 0.000 0.000 0.000T=∞ Zth 0.100 0.090 0.075 0.060 0.040

Table 2. Burst Mode pulse parameters

Substituting these values into equation 17 gives

∆Tj − mb@y = P2.Zthj − mb(t5) + P3.Zthj − mb(t6)

+ P1.Zthj − mb(t8) − P2.Zthj − mb(t6)

− P3.Zthj − mb(t7) 16

050

100150

350300250200150100

500

50100150200250300350

0 20 40 60 80 100 120 140 160 240 260 280 300

T=240usPOWER (W)

Time (us)

Time (us)

t4

t2

t1

t3

t5

Repetitive: ∆Tj − mb@y = 20× 1.95+ 100× 1.3

+ 40× 0.08− 20× 1.3

− 100× 1.25

= 21.2°C

Tj = Tmb + ∆Tj − mb = 75+ 21.2= 96.2°C

Single Shot: ∆Tj − mb@y = 20× 0.2+ 100× 0.16

+ 40× 0.03− 20× 0.16

− 100× 0.15

= 3°C

Tj = Tmb + ∆Tj − mb = 75+ 3 = 78°C

∆Tj − mb@x = P.Zthj − mb(t1) + P.Zthj − mb(t3)

+ P.Zthj − mb(t5) − P.Zthj − mb(t2)

− P.Zthj − mb(t4) 17

Pav =25× 10+ 5× 130+ 20× 100

400

= 7.25W

∆Tj − mb(av) = Pav × Zthj − mb(δ = 1) = 7.25× 2 = 14.5°C

Tj (av) = Tmb + ∆Tj − mb(av) = 75+ 14.5= 89.5°C

564


Hence the peak value of Tj is 143˚C for the repetitive caseand 81.5˚C for the single shot case. To calculate theaverage junction temperature Tj(av):

The above example for the repetitive waveform highlightsa case where the average junction temperature (125˚C) iswell within limits but the composite pulse calculation showsthe peak junction temperature to be significantly higher. Forreasons of improved long term reliability it is usual tooperate devices with a peak junction temperature below125˚C.

Non-rectangular pulsesSo far, the worked examples have only covered rectangularwaveforms. However, triangular, trapeziodal andsinusoidal waveforms are also common. In order to applythe above thermal calculations to non rectangularwaveforms, the waveform is approximated by a series ofrectangles. Each rectangle represents part of thewaveform. The equivalent rectangle must be equal in areato the section of the waveform it represents (ie the sameenergy)andalso be of the samepeak power.With referenceto Fig. 16, a triangular waveform has been approximatedto one rectangle in the first example, and two rectangles inthe second. Obviously, increasing the number of sectionsthe waveform is split into will improve the accuracy of thethermal calculations.

In the first example, there is only one rectanglular pulse ,of duration 50µs, dissipating 50W. So again using equation14 and a rearrangement of equation 7:

Fig. 16 Non Rectangular Waveform

When the waveform is split into two rectangular pulses:

For this example P1 = 25W, P2 = 25W, P3 = 50W. Table 3below shows the rest of the parameters:

t1 t2 t3

75µs 50µs 37.5µs

Single Shot D 0.000 0.000 0.000T=∞ Zth 0.085 0.065 0.055

10% Duty Cycle D 0.075 0.050 0.037T=1000µs Zth 0.210 0.140 0.120

50% Duty Cycle D 0.375 0.250 0.188T=200µs Zth 0.700 0.500 0.420

Table 3. Non Rectangular Pulse Calculations

Repetitive: ∆Tj − mb@x = 100× 1.10+ 100× 0.60

+ 100× 0.21− 100× 0.80

− 100× 0.43

= 68°C

Tj = 75+ 68= 143°C0 20 40 60 80 100

0

10

20

30

40

50

100

90

80

70

60

50

40

30

20

10

0

10

20

30

0 20 40 60 80 100

0

10

20

30

40

50

100

90

80

70

60

50

40

30

20

10

0

10

20

30

P3

P2

P1

t3

t2

t1

Single Shot: ∆Tj − mb@x = 100× 0.10+ 100× 0.075

+ 100× 0.04− 100× 0.09

− 100× 0.06

= 6.5°C

Tj = 75+ 6.5= 81.5°C

Pav =3× 100× 20

240

= 25W

∆Tj − mb(av) = Pav × Zthj − mb(δ = 1) = 25× 2 = 50°C

Tj (av) = 75+ 50= 125°C

∆Tj − mb = Ptot M × Zthj − mb

Single Shot ∆Tj − mb = 50× 0.065= 3.25°C

Tjpeak = 75+ 3.25= 78.5°C

10% Duty cycle ∆Tj − mb = 50× 0.230= 11.5°C

Tjpeak = 75+ 11.5= 86.5°C

50% Duty cycle ∆Tj − mb = 50× 1.000= 50°C

Tjpeak = 75+ 50= 125°C

∆Tj − mb = P3.Zthj − mb(t3) + P1.Zthj − mb(t1) − P2.Zthj − mb(t2) 18

565


Sustituting these values into equation 18 gives:

To calculate the average junction temperature:

Conclusion

A method has been presented to allow the calculation ofaverage and peak junction temperatures for a variety ofpulse types. Several worked examples have showncalculations for various common waveforms. The methodfor non rectangular pulses can be applied to any waveshape, allowing temperature calculations for waveformssuch as exponential and sinusoidal power pulses. Forpulses such as these, care must be taken to ensure thatthe calculation gives the peak junction temperature, as itmay not occur at the end of the pulse. In this instanceseveral calculations must be performed with differentendpoints to find the maximum junction temperature.

Single shot ∆Tj − mb = 50× 0.055+ 25× 0.085− 25× 0.065

= 3.25°C

Tjpeak = 75+ 3.25= 78.5°C

10% Duty cycle ∆Tj − mb = 50× 0.12+ 25× 0.21− 25× 0.14

= 7.75°C

Tjpeak = 75+ 7.75= 82.5°C

50% Duty cycle ∆Tj − mb = 50× 0.42+ 25× 0.7− 25× 0.5

= 26°C

Tjpeak = 75+ 26= 101°C

50% Duty Cycle Pav =50× 50

200

= 12.5W

∆Tj − mb(av) = Pav × Zthj − mb(δ = 1) = 12.5× 2 = 25°C

Tj (av) = 75+ 25= 100°C

10% Duty Cycle Pav =50× 501000

= 2.5W

∆Tj − mb(av) = Pav × Zthj − mb(δ = 1) = 2.5× 2 = 5°C

Tj (av) = 75+ 5 = 80°C

566


7.1.2 Heat Dissipation

All semiconductor failure mechanisms are temperaturedependent and so the lower the junction temperature, thehigher the reliability of the circuit. Thus our data specifiesa maximum junction temperature which should not beexceeded under the worst probable conditions. However,derating the operating temperature from Tjmax is alwaysdesirable to improve the reliability still further. The junctiontemperature depends on both the power dissipated in thedevice and the thermal resistances (or impedances)associated with the device. Thus careful consideration ofthese thermal resistances (or impedances) allows the userto calculate the maximum power dissipation that will keepthe junction temperature below a chosen value.

The formulae and diagrams given in this section can onlybe considered as a guide for determining the nature of aheatsink. This is because the thermal resistance of aheatsink depends on numerous parameters which cannotbe predetermined. They include the position of thetransistor on the heatsink, the extent to which air can flowunhindered, the ratio of the lengths of the sides of theheatsink, the screening effect of nearby components, andheating from these components. It is always advisable tocheck important temperatures in the finished equipmentunder the worst probable operating conditions. The morecomplex the heat dissipation conditions, the more importantit becomes to carry out such checks.

Heat flow pathThe heat generated in a semiconductor chip flows byvarious paths to the surroundings. Small signal devices donot usually require heatsinking; the heat flows from thejunction to the mounting base which is in close contact withthe case. Heat is then lost by the case to the surroundingsby convection and radiation (Fig. 1a). Power transistors,however, are usually mounted on heatsinks because of thehigher power dissipation they experience. Heat flows fromthe transistor case to the heatsink by way of contactpressure, and the heatsink loses heat to the surroundingsby convection and radiation, or by conduction to coolingwater (Fig. 1b). Generally air cooling is used so that theambient referred to in Fig.1 is usually the surrounding air.Note that if this is the air inside an equipment case, theadditional thermal resistance between the inside andoutsideof the equipment caseshould be taken into account.

Contact thermal resistance R th mb-h

The thermal resistance between the transistor mountingbase and the heatsink depends on the quality and size ofthe contact areas, the type of any intermediate plates used,and the contact pressure. Care should be taken whendrilling holes in heatsinks to avoid burring and distorting the

metal, and both mating surfaces should be clean. Paintfinishes of normal thickness, up to 50 um (as a protectionagainst electrolytic voltage corrosion), barely affect thethermal resistance. Transistor case and heatsink surfacescan never be perfectly flat, and so contact will take placeon several points only, with a small air-gap over the rest ofthe area. The use of a soft substance to fill this gap lowersthe contact thermal resistance. Normally, the gap is filledwith a heatsinking compound which remains fairly viscousat normal transistor operating temperatures and has a highthermal conductivity. The use of such a compound alsoprevents moisture from penetrating between the contactsurfaces. Proprietary heatsinking compounds are availablewhich consist of a silicone grease loaded with someelectrically insulating good thermally conducting powdersuch as alumina. The contact thermal resistance Rth mb-h isusually small with respect to (Rth j-mb + Rth h-amb) when coolingis by natural convection. However, the heatsink thermalresistance Rth h-amb can be very small when either forcedventilation or water cooling are used, and thus a closethermal contact between the transistor case and heatsinkbecomes particularly important.

Fig. 1 Thermal resistances in the heat flow process:(a) Without a heatsink

(b) With a heatsink

Thermal resistance calculationsFig. 1a shows that, when a heatsink is not used, the totalthermal resistance between junction and ambient is givenby:

However, power transistors are generally mounted on aheatsink since Rth j-amb is not usually small enough tomaintain temperatures within the chip below desired levels.

Fig. 1b shows that, when a heatsink is used, the totalthermal resistance is given by:

Rthj − amb = Rthj − mb + Rthmb− amb 1

Rthj − amb = Rthj − mb + Rthmb− h + Rthh − amb 2

567


Note that the direct heat loss from the transistor case to thesurroundings through Rth mb-amb is negligibly small.

The first stage in determining the size and nature of therequired heatsink is to calculate the maximum heatsinkthermal resistance Rth h-amb that will maintain the junctiontemperature below the desired value

Continuous operationUnder dc conditions, the maximum heatsink thermalresistance can be calculated directly from the maximumdesired junction temperature.

Combining equations 2 and 3 gives:

and substituting Eq 4 into Eq 5 gives:

The values of Rth j-mb and Rth mb-h are given in the publisheddata. Thus, either Eq. 5 or Eq.6 can be used to find themaximum heatsink thermal resistance.

Intermittent operationThe thermal equivalent circuits of Fig. 1 are inappropriatefor intermittent operation, and the thermal impedance Zth j-mb

should be considered.

The mounting-base temperature has always beenassumed to remain constant under intermittent operation.This assumption is known to be valid in practice providedthat the pulse time is less than about one second. Themounting-base temperature does not change significantlyunder these conditions as indicated in Fig. 2. This isbecause heatsinks have a high thermal capacity and thusa high thermal time-constant.

Thus Eq.6 is valid for intermittent operation, provided thatthe pulse time is less than one second. The value of Tmbcan be calculated from Eq. 7, and the heatsink thermalresistance can be obtained from Eq.6.

Fig. 2 Variation of junction and mounting basetemperature when the pulse time is small compared

with the thermal time constant of the heatsink

The thermal time constant of a transistor is defined as thattime at which the junction temperature has reached 70%of its final value after being subjected to a constant powerdissipation at a constant mounting base temperature.

Now, if the pulse duration tp exceeds one second, thetransistor is temporarily in thermal equilibrium since sucha pulse duration is significantly greater than the thermaltime-constant of most transistors. Consequently, for pulsetimes of more than one second, the temperature differenceTj - Tmb reaches a stationary final value (Fig. 3) and Eq.7should be replaced by:

In addition, it is no longer valid to assume that the mountingbase temperature is constant since the pulse time is alsono longer small with respect to the thermal time constantof the heatsink.

Fig. 3 Variation of junction and mounting basetemperature when the pulse time is not small compared

with the thermal time constant of the heatsink

Rthj − amb =Tj − Tamb

Ptot(av)3

and Rthj − mb =Tj − Tmb

Ptot(av)4

Rthh − amb =Tj − Tamb

Ptot(av)− Rthj − mb − Rthmb− h 5

Rthh − amb =Tmb − Tamb

Ptot(av)− Rthmb− h 6

Tmb = Tj − PtotM.Rthj − mb 8

PtotM =Tj − Tmb

Zth j − mb

thus: Tmb = Tj − PtotM.Zth j − mb 7

568


Smaller heatsinks for intermittentoperationIn many instances, the thermal capacity of a heatsink canbe utilised to design a smaller heatsink for intermittentoperation than would be necessary for the same level ofcontinuous power dissipation. The average powerdissipation in Eq. 6 is replaced by the peak powerdissipation to obtain the value of the thermal impedancebetween the heatsink and the surroundings

The value of Zth h-amb will be less than the comparablethermal resistance and thus a smaller heatsink can bedesigned than that obtained using the too large valuecalculated from Eq.6.

HeatsinksThree varieties of heatsink are in common use: flat plates(including chassis), diecast finned heatsinks, and extrudedfinned heatsinks. The material normally used for heatsinkconstruction is aluminium although copper may be usedwith advantage for flat-sheet heatsinks. Small finned clipsaresometimes used to improve the dissipationof low-powertransistors.

Heatsink finishHeatsink thermal resistance is a function of surface finish.A painted surface will have a greater emissivity than a brightunpainted one. The effect is most marked with flat plateheatsinks, where about one third of the heat is dissipatedby radiation. The colour of the paint used is relativelyunimportant, and the thermal resistance of a flat plateheatsink painted gloss white will be only about 3% higherthan that of the same heatsink painted matt black. Withfinned heatsinks, painting is less effective since heatradiated from most fins will fall on adjacent fins but it is stillworthwhile. Both anodising and etching will decrease thethermal resistivity. Metallic type paints, such as aluminiumpaint, have the lowest emissivities, although they areapproximately ten times better than a bright aluminiummetal finish.

Flat-plate heatsinksThe simplest type of heatsink is a flat metal plate to whichthe transistor is attached. Such heatsinks are used both inthe form of separate plates and as the equipment chassisitself. The thermal resistance obtained depends on thethickness, area and orientation of the plate, as well as onthe finish and power dissipated. A plate mountedhorizontally will have about twice the thermal resistance ofa vertically mounted plate. This is particularly importantwhere the equipment chassis itself is used as the heatsink.

In Fig. 4, the thermal resistance of a blackened heatsink isplotted against surface area (one side) with powerdissipation as a parameter. The graph is accurate to within25% for nearly square plates, where the ratio of the lengthsof the sides is less than 1.25:1.

Finned heatsinks

Finned heatsinks may be made by stacking flat plates,although it is usually more economical to use ready madediecast or extruded heatsinks. Since most commerciallyavailable finned heatsinks are of reasonably optimumdesign, it is possible to compare them on the basis of theoverallvolume whichthey occupy. Thiscomparison is madein Fig. 5 for heatsinks with their fins mounted vertically;again, the graph is accurate to 25%.

Fig. 4 Generalised heatsink characteristics: flat verticalblack aluminium plates, 3mm thick, approximately

square

Fig. 5 Generalised heatsink characteristic: blackenedaluminium finned heatsinks

Zthh − amb =Tmb − Tamb

PtotM

− Rthmb− h 9

569


Fig. 6 Heatsink nomogram

1

10

100

10

10

10

3

4

5

10 100 1000

Bright HorizontalBright Vertical

Blackened HorizontalBlackened Vertical

1W2W5W10W20W50W100W

1mm

2mm3mm

30D

40DEXTRUDED

FLAT PLATE

SOT93TO220SOT82

Length of Extruded Heatsink (mm)

Areaofonesidemm2

Heatsink dimensionsThe maximum thermal resistance through which sufficientpower can be dissipated without damaging the transistorcan be calculated as discussed previously. This sectionexplains how to arrive at a type and size of heatsink thatgives a sufficiently low thermal resistance.

Natural air coolingThe required size of aluminium heatsinks - whether flat orextruded (finned) can be derived from the nomogram inFig. 6. Like all heatsink diagrams, the nomogram does notgive exact values for Rth h-amb as a function of the dimensionssince the practical conditions always deviate to some extentfrom those under which the nomogram was drawn up. Theactual values for the heatsink thermal resistance may differby up to 10% from the nomogram values. Consequently, itis advisable to take temperature measurements in thefinished equipment, particularly where the thermalconditions are critical.

The conditions to which the nomogram applies are asfollows:

• natural air cooling (unimpeded natural convection with nobuild up of heat);

• ambient temperature about 25˚C, measured about 50mmbelow the lower edge of the heatsink (see Fig. 7);

• atmospheric pressure about 10 N/m2;

• single mounting (that is, not affected by nearby heatsinks);

• distance between the bottom of the heatsink and the baseof a draught-free space about 100mm (see Fig. 7);

• transistor mounted roughly in the centre of the heatsink(this is not so important for finned heatsinks because ofthe good thermal conduction).

The appropriately-sized heatsink is found as follows.

1. Enter the nomogram from the right hand side of section1 at the appropriate Rth h-amb value (see Fig. 8). Movehorizontally to the left, until the appropriate curve fororientation and surface finish is reached.

2. Move vertically upwards to intersect the appropriatepower dissipation curve in section 2.

570


3. Move horizontally to the left into section 3 for the desiredthickness of a flat-plate heatsink, or the type of extrusion.

4. If an extruded heatsink is required, move verticallyupwards to obtain its length (Figs. 9a and 9b give theoutlines of the extrusions).

5. If a flat-plate heatsink is to be used, move verticallydownwards to intersect the appropriate curve forenvelope type in section 4.

6. Move horizontally to the left to obtain heatsink area.

7. The heatsink dimensions should not exceed the ratio of1.25:1.

Fig. 7 Conditions applicable to nomogram in Fig. 6

Fig. 8 Use of the heatsink nomogram

Fig. 9a Outline of Extrusion 30D

Fig. 9b Outline of Extrusion 40D

Thecurves in section 2 take account of the non linear natureof the relationship between the temperature drop acrossthe heatsink and the power dissipation loss. Thus, at aconstant value of the heatsink thermal resistance, thegreater the power dissipation, the smaller is the requiredsize of heatsink. This is illustrated by the following example.

ExampleAn extruded heatsink mounted vertically and with a paintedsurface is required to have a maximum thermal resistanceof Rth h-amb = 2.6 ˚C/W at the following powers:

Enter the nomogram at the appropriate value of the thermalresistance in section 1, and via either the 50W or 5W linein section 2, the appropriate lengths of the extrudedheatsink 30D are found to be:

Case (b) requires a shorter length since the temperaturedifference is ten times greater than in case (a).

As the ambient temperature increases beyond 25˚C, sodoes the temperature of the heatsink and thus the thermalresistance (at constant power) decreases owing to theincreasing role of radiation in the heat removal process.Consequently, a heatsink with dimensions derived fromFig. 6 at Tamb > 25˚C will be more than adequate. If themaximum ambient temperature is less than 25˚C, then thethermal resistance will increase slightly. However, any

Approx

100mm

Approx

50mm

Tamb Tamb

Th

(a)Ptot(av) = 5W (b)Ptot(av) = 50W

(a) length = 110mm and (b) length = 44mm.

571


increase will lie within the limits of accuracy of thenomogram and within the limits set by other uncertaintiesassociated with heatsink calculations.

For heatsinks with relatively small areas, a considerablepart of the heat is dissipated from the transistor case. Thisis why the curves in section 4 tend to flatten out withdecreasing heatsink area. The area of extruded heatsinksis always large with respect to the surface of the transistorcase, even when the length is small.

Fig. 10 Arrangement of two equally loaded transistorsmounted on a common heatsink

If several transistors are mounted on a common heatsink,each transistor should be associated with a particularsection of the heatsink (either an area or length accordingto type) whose maximum thermal resistance is calculatedfrom equations 5 or 6; that is, without taking the heatproduced by nearby transistors into account. From the sum

of these areas or lengths, the size of the common heatsinkcan then be obtained. If a flat heatsink is used, thetransistors are best arranged as shown in Fig. 10. Themaximum mounting base temperatures of transistors insuch a grouping should always be checked once theequipment has been constructed.

Forced air coolingIf the thermal resistance needs to be much less than 1˚C/W,or the heatsink not too large, forced air cooling by meansof fans can be provided. Apart from the size of the heatsink,the thermal resistance now only depends on the speed ofthe cooling air. Provided that the cooling air flows parallelto the fins and with sufficient speed (>0.5m/s), the thermalresistance hardly depends on the power dissipation and theorientation of the heatsink. Note that turbulence in the aircurrent can result in practical values deviating fromtheoretical values.

Fig. 11 shows the form in which the thermal resistances forforced air cooling are given in the case of extrudedheatsinks. It also shows the reduction in thermal resistanceor length of heatsink which may be obtained with forced aircooling.

The effect of forced air cooling in the case of flat heatsinksis seen from Fig. 12. Here, too, the dissipated power andthe orientation of the heatsink have only a slight effect onthe thermal resistance, provided that the air flow issufficiently fast.

Fig. 11 Thermal Resistance of a finned heatsink (type 40D) as a function of the length with natural and forced aircooling

0 50 100 150 200 250 300 3500

0.5

1

1.5

2

2.5

Length (mm)

Rth h-amb (K/W)

P=3W

P=10W

P=30W

P=100W

1m/s2m/s5m/s

Natural

Convection

ForcedCooling

(Vertical)

Blackened

572


Fig. 12 Thermal Resistances of heatsinks (2mm thick copper or 3mm thick aluminium) under natural convection andforced cooling conditions, with a SOT93 envelope.

(a) blackened(b) bright

SummaryThe majority of power transistors require heatsinking, andonce the maximum thermal resistance that will maintain thedevice’s junction temperature below its rating has beencalculated, a heatsink of appropriate type and size can bechosen. The practical conditions under which a transistorwill be operated are likely to differ from the theoretical

considerations used to determine the required heatsink,and thus temperatures should always be checked in thefinished equipment. Finally, some applications require asmall heatsink, or one with a very low thermal resistance,in which case forced air cooling by means of fans shouldbe provided.

573

Lighting Power Semiconductor ApplicationsPhilips Semiconductors

CHAPTER 8

Lighting

8.1 Fluorescent Lamp Control

575


Fluorescent Lamp Control

577


8.1.1 Efficient Fluorescent Lighting using Electronic Ballasts

This section provides a general background to fluorescentlamps and their control requirements, with emphasisplacedon high frequency electronic ballasts and their advantagesover conventional 50/60Hz "magnetic" ballasts. Simplifiedexamples of popular electronic ballast topologies suitablefor low cost / economy applications are introduced.

The fluorescent lamp.

A fluorescent tube is a low pressure mercury vapourdischarge lamp containing an inert gas consisting of argonor krypton at low pressure (below 1 atmosphere) plus asmall measured dose of mercury. There is a filament ateach end which, when hot, emit electrons to sustain thedischarge when the lamp is operating. The mercury vapourdischarge produces ultraviolet light which is converted tovisible light by the phosphors coating the inside of the glasstube. The glass blocks the exit of the ultraviolet radiationbut allows the visible radiation through. See Fig. 1.

Fluorescent tubes exist in many shapes and sizes. Apartfrom the many compact types that have appeared on themarket in recent years as energy efficient replacements forincandescent lamps, the traditional linear tubes range from150mm 4W up to the very high output 2400mm 215W.

Modern fluorescent tubes incorporating the latesttriphosphor technology (i.e. red, green and blue phosphorssimilar to those used in modern high brightness televisionpicture tubes) possess efficacies of around 80 lumens perlamp Watt compared with 68 lumens per lamp Watt for theolder most efficient "white" fluorescent tubes and around12 lumens per Watt for an incandescent bulb. Moreover,the triphosphor lamps reveal colour and skin tones moreaccurately than the standard "white" lamps, which sufferfrom a deficiency in output at the red end of the spectrum.This results in a greenish hue and a suppression of redcolours from anything illuminated by them.

The elimination of the traditional causes of criticism forfluorescent lighting means that this form of lighting isbecoming more acceptable in wider applications than everbefore. Adjustment of the ratios of the three phosphors cancreate colour appearances from a very warm, intimate,incandescent equivalent colour temperature of 2700Kthrough the cool, clean, businesslike 4000K to the very cooldaylight colour temperature of 6500K, all with highefficacies and good colour rendering properties. Before theavailability of triphosphors, these qualities have alwaysbeen mutually exclusive. You could either have highefficacyand poorcolour renderingor poorefficacy andgoodcolour rendering, but not both.

Fig. 1. A fluorescent tube.

A non-operating fluorescent tube will appear as an opencircuit, since there is no electrical connection from one endto the other. In order to "strike the arc", a high voltage mustbe applied across the lamp in order to ionise the gas within.This will instantly "cold start" the lamp and shorten its lifeby sputtering electron-emitting material from its cathodes.

However, if the cathodes (heaters) are first preheated togenerate a space charge of electrons at each end of thelamp, the strike voltage is considerably reduced and lamplife will not be unduly compromised by the start-up.

As soon as arc current flows, the lamp’s electricalimpedance will drop. It now exhibits a negative impedancecharacteristic,where an increase in current is accompaniedby a reduction in lamp voltage. There must therefore be acurrent limiting device in circuit to prevent the rapid onsetof runaway and destruction of the lamp.

The lamp running current should ideally be sinusoidal tominimise the radiation of electromagnetic interference fromthe lamp and its supply wires. Sinusoidal lamp current alsomaximises lamp life. A peak current approaching twice theRMS current will prematurely deplete the electron emittingmaterial from the lamp cathodes. (For a sinewave the peakvalue is only 1.414 times the RMS value.)

There should also be no D.C. component to the lampcurrent; that is, the positive and negative half cycles shouldbe of equal duration. If this is not the case, the resultingpartial rectification will result in premature depletion of theelectron emitter from one of the lamp cathodes.

The ballast.The requirements of a fluorescent lamp ballast are to:(a) Preheat the cathodes to induce electron emission.(b) Provide the starting voltage to initiate the discharge.(c) Limit the running current to the correct value.

There are several types of mains frequency "magnetic"ballast available. By far the most common circuit for 230Vmains supplies has traditionally been the switchstart ballast(seeFig. 2), where lamp ballasting is provided by the choke.Other circuits include, in order of popularity, thesemi-resonant circuit and the quickstart circuit.

CATHODE

LOW PRESSURE ARGONOR KRYPTON FILLING SMALL DOSE OF MERCURY

PHOSPHOR COATING

579


The switchstart circuit has been widely adopted becauseof its simplicity, low cost and improved efficiency whencompared with the alternative options mentioned above.Another reason is that the 230V mains voltage is sufficientlyhigher than the tube running voltage to allow the use of thesimple series impedance ballast in almost all cases. Wherethis is not possible, for example in most 120V suppliedcircuits, the lamp is controlled by a quickstart circuitincorporating voltage step-up.

Fig. 2. Conventional switchstart "magnetic" ballastcircuit.

Switchstart ballast operation.When the voltage is applied to the circuit, the lamp doesnot operate at first, so the full mains voltage appears acrossthe starter via the choke and lamp cathodes.

The starter consists of bi metallic contacts sealed within asmall discharge bulb with an inert gas filling such as argonor neon. The mains voltage causes a glow discharge withinthe starter which heats up the bi metallic contacts, causingthem to close. This completes the circuit and allows preheatcurrent to flow through the choke and both cathodes.

Since the glow discharge within the starter has now ceased,the bi metallic contacts cool down and open. Because theinductance of the choke tries to maintain current flow, thevoltage across the lamp rises rapidly and strikes the lamp.If it does not, the starter’s contacts close again and the cyclerepeats.

Once the lamp has started, the choke controls its currentand voltage to the correct levels. The lamp running currentis enough to keep the cathodes (heaters) hot and emittingelectrons without the need for separate heater supplies,which would otherwise be wasteful of energy. Since thelamp’s running voltage is much lower than the mainsvoltage, there is now not enough voltage to cause a glowdischarge in the starter, so it remains open circuit.

The power factor correction (PFC) capacitor draws leadingcurrent from the mains to compensate for the laggingcurrent drawn by the lamp circuit.

Why electronic ballasts?

Electronic ballasts have been available for well over adecade. Recent leaps in performance, coupled with everincreasing energy costs, the increased awareness of theadvantages they offer, the increasing environmentalawareness of the consumer, and the increasedacceptability of the new fluorescent light sources in existingand new applications, have seen an upsurge in electronicballast use since the beginning of the 1990’s.

Replacing the most efficient low loss mains frequencyswitchstart ballast with an electronic ballast leads toreduced energy consumption and improved performance.The reasons for this are detailed below.

Increased light output.

If the operating frequency is increased from 50Hz to abovethe audible limit of 20kHz, fluorescent lamps can producearound 10% more light for the same input power (seeFig. 3). Alternatively, the input power can be reduced forthe same light output.

Fig. 3. Typical fluorescent lamp efficacy.

Flicker eliminated.

A fluorescent lamp operating at 50/60Hz will extinguishtwice every cycle as the mains sinewave passes throughzero. This produces 100/120Hz flicker which is noticeableor irritating to some people. It will also produce thewell-known and potentially dangerous stroboscopic effectson rotating machinery.

If the lamp is operated at high frequency, however, itproduces continuous light. This is because the timeconstant and hence the response time of the discharge istoo slow for the lamp to have a chance to extinguish duringeach cycle.

PFC

CHOKE

STARTER

L

N

230V

50Hz

50 500 5k 50k 500k

100

102

104

106

108

110

Frequency (Hz)

Lamp efficacy (%)

580


The output waveform of an electronic ballast will usually beslightly modulated by 100/120Hz "ripple". Provided this iskept to a reasonable level by filtering within the ballast, thedrawbacks associated with 100/120Hz flicker areeliminated.

Audible noise eliminated.Since electronic ballasts operate above the audible range,they do not suffer from the audible noise problems that canoccur with mains frequency magnetic ballasts. The familiarbuzzing noise is caused by vibrations in the laminationsand coil of the choke. This can then excite vibrations in thesteel body of the fitting which effectively amplifies theoriginal noise.

Lower ballast power.An electronic ballast will consume less power and thereforedissipate less heat than a mains frequency magneticballast. For example, for two 1500mm 58W energy-savinglamps, the typical ballast power dissipations might be 13Wper ballast for two 50Hz magnetic ballasts compared with9W for a single electronic ballast driving two lamps.

The energy-saving benefits of electronic ballasts havemade it possible to obtain the same light output fromfluorescent lamps as would be obtained using aconventional 50/60Hz magnetic ballast, for a total circuitpower (i.e. lamp and ballast) that is actually less than therated lamp power alone. This is due to two reasons.

Firstly, the lamp can be underrun at high frequency for thesame light output. Secondly, the power consumed by theballast can be so low that the total circuit power is still lessthan the rated power printed on the lamp. Because of this,energy cost reductions of 20 - 25% are achievable.

Extended lamp life.An electronic ballast which "soft starts" the lamp (i.e.provides preheat to the cathodes before applying acontrolled starting pulse) will dislodge a minimum quantityof material from the cathodes during starting. This will givelonger lamp life when compared to the uncontrolledimpulses to which the lamp is subjected in a switchstartcircuit.

Versatile lamp control.Electronic ballasts are available which permit lampdimming. This gives substantial energy savings insituations where the lights are linked to an automatic controlsystem which detects ambient light levels and adjusts lamp

output to maintain a constant level of illumination. Lightsmay also be programmed to dim during intervals whenareas are not in use, for example during lunch breaks.

Electronic ballasts can incorporate feedback to detect theoperating conditions of the lamp(s) so that failed lamps canbe switched off to avoid annoying flicker and possibleballast damage. They can also incorporate regulation,whereby a constant light output is maintained over a rangeof input voltages. Operation can be either from AC or DCsupplies for emergency lighting applications.

Compact and light weight.Owing to the high frequency of operation, the magneticcomponents in an electronic ballast are compact andlightweight with cores of ferrite material, whereas at mainsfrequency the ballast choke must be larger and heavier withbulkier copper windings and a core of laminated steel.

The shape and geometry of a mains frequency choke isdetermined by magnetic efficiency requirements, whereasthe circuitry within an electronic ballast can be arranged toproduce a very slim final package. This permits new levelsof slimness and compactness for the final ballast.

Electronic ballast topologies.The typical building blocks of an electronic ballast areshown in Fig. 4.

An increasing number of electronic ballasts are employingactive power factor correction in the form of a boostconverter between the rectifier and DC filter stages. (Figure5 shows a simplified boost converter arrangement.) Thisobliges the ballast to draw current over most of each mainshalf cycle instead of the usual current spike that a rectifier/ DC filter would demand at each peak of the voltagewaveform. This reduces the harmonic content of the currentand improves the power factor. It will also reduce the sizeof the electromagnetic interference (EMI) filter required,since filtering is now required at the higher harmonicfrequencies of the boost converter switching frequencyinstead of at the mains frequency and harmonics of it.

Electronic ballasts take many forms. The simplest and mosteconomical form might consist of a free-runningself-oscillating circuit using bipolar transistors. This wouldbe an open loop circuit (i.e. no feedback to detect lampoperating conditions).

More expensive options might contain a controlledoscillator in a closed loop circuit using MOSFETs. Here,features could include regulation for varying AC and DCsupply voltages, adjustable lamp brightness, soft startingand a mechanism to detect and shut down failed lamps.

581


Fig. 4. Electronic ballast block diagram.

EMI

FILTERRECTIFIER

BOOST

PFC

DC

FILTER

DC - AC

INVERTERBALLAST TO LAMPSUPPLY

OPTIONAL

POWER FACTOR

CORRECTION

CIRCUIT

OPTIONAL

OPTIONAL FEEDBACK

DIMMING

CONTROL

Fig. 5. A boost converter for active power factorcorrection.

Blocking oscillator.The most basic form of electronic ballast uses a blockingoscillator as shown in Fig. 6. Its use is restricted mainly tolow voltage DC, low power ballasts as used in handlamps,leisure lighting and emergency lighting, where operation isonly for short periods. This is because the lamp has aseverely limited life when it is driven by a spiky waveform,rich in harmonics, such as that produced by this circuit. Thistopology might typically be used to operate tubes of 4W to13W ratings only because of the excessive voltage andcurrent stresses and switching losses that would beexperiencedby the transistor in higher power mains voltageversions.

Voltage step-up to drive the lamp from the low voltagesupply is achieved by the turns ratio of the transformerprimary and secondary, while oscillation is maintained bythe positive feedback supplied by the auxiliary windingconnected to the transistor’s base. The values of R, C,transformer primary inductance LPRI and the transistorparameters set the oscillation frequency and the mark /space ratio of the waveform (which should be 1:1 for thereason given in the first section).

No separate ballast inductor is required, since the onlyenergy delivered to the lamp during the transistor’s OFFtime is what was stored in LPRI during the preceding ONtime. The transistor remains OFF and will not turn ON againuntil all the stored energy has been delivered to the load.Lamp power is therefore controlled by the amount of energystored in the LPRI during each ON period.

Fig. 6. Basic low voltage ballast using a blockingoscillator.

Unlike the blocking oscillator, mains powered electronicballasts usually use two switching power transistors in apush pull or half bridge configuration. This can either be aself oscillating or a driven oscillator circuit. The drivenoscillator option permits easier lamp control and dimming.The self oscillating option has cost advantages where thebenefits of high frequency lighting are required without thenecessity for lamp dimming.

CONTROL

INDUCTOR

FROMEMI

FILTER

TODC - AC

INVERTER

RECTIFIER BOOST CONVERTER DC FILTER

FASTDIODE

+

-

SUPPLY

R

C

12V DC

582


The push pull inverter.A push pull circuit can appear as a voltage fed inverter withseries resonant load or a current fed inverter with parallelresonant load. In both cases a centre tapped transformeris required.

Voltage fed push pull inverter.Figure 7 shows a simplified circuit. This example providesisolation of the output from the mains supply with a separatesecondary winding.

In the voltage fed arrangement, the D.C. rail voltage is fedstraight to the centre tap. Both ends of the winding areconnected to zero volts via transistors, which are alternatelyswitched on during operation. The alternate passage ofcurrent in opposite directions through each half of theprimary winding induces a square wave voltage across thesecondary.

Since the full D.C. rail voltage appears across half theprimary winding at a time, twice this voltage will appearacross the whole primary winding. This means that duringeach transistor’s "off" period, it will experience a maximumtheoretical VCE of 2 x D.C. rail voltage.

Fig. 7. Voltage fed push pull ballast with isolatedoutput.

When power is first applied, the secondary voltage shouldnot be high enough to cold start the lamp, which shouldremain in the high impedance state. The only currentflowing will be through the series resonant combination ofL & C, and both lamp cathodes. This preheat current willbe enough to initiate electron emission from the cathodeswhich will in turn lower the lamp striking voltage to a pointwhere the voltage across the capacitor can then start thelamp (usually within a second).

After starting, the lamp voltage will drop and the current willbe limited and filtered by L. C will help to filter out residualharmonic frequencies and its current will fall to negligibleproportions at the fundamental operating frequency. Theresulting lamp current will closely resemble a sinewave.

The transistor base drives are derived from auxiliarywindings on the transformer which provide the necessarypositive feedback. An advantage with thistransformer-based arrangement is the isolation it providesbetween the lamp and the mains supply.

Current fed parallel resonant push pullinverter.

The main difference with this circuit over the previous oneis that the D.C. rail voltage is fed to the transformer centretap via an inductor which acts as a current source. Acapacitor C across the transformer primary forms a parallelresonant load in combination with the primary windinginductance (see Fig. 8). Instead of a square wave as in thevoltage fed circuit, a full wave rectified sinewave appearsat the centre tap whose theoretical peak amplitude is π/2 xVDC. Twice this amplitudeappears across the whole windingfor the same reason as in the voltage fed push pull circuit.Therefore the maximum theoretical VCE = π x VDC.

Fig. 8. Current fed parallel resonant push pull ballastwith isolated output.

Since each successive half sine produces current flow inopposite directions through the two half windings, asinewave is produced across the whole winding whosepeak to peak amplitude is 2π x VDC.

The additional cost of the inductor might be regarded as adisadvantage. However, the beauty of current fed parallelresonant circuits, of which this is one example, is that theynaturally produce a sinusoidal output, so selection of theballast components for their harmonic filtering properties isno longer so important. This allows the use of a seriesballast capacitor instead of the series L normally required.

Another benefit with this type of circuit is its ability tocontinue normal operation with varying or open circuitloads. This permits independent operation ofparallel-connected lamps across the secondary, each withits own ballast capacitor, where failure of one or more lamps

DRIVE

CIRCUIT

DRIVE

CIRCUIT

+

-

L

T1

T1

T1 C

ADDITIONALLAMPS

TO

Vdc

DRIVE

CIRCUIT

DRIVE

CIRCUIT

+

-

L

C

T1

T1

T1

Vdc

583


will not affect the operation of the remaining lamps. This isunlike series-connected lamps, where the failure of onetube will disable all the tubes on that ballast.

Sinusoidal output topologies are very popular in the selfoscillating low cost ballast market because of theseadvantages and the circuit simplicity.

The half bridge inverter.

The half bridge topology contains two npn transistorsconnected in series across the D.C. rail with the loadconnected to their mid point. The half bridge is so calledbecause the return path for the load current is provided bytwo series-connected capacitors across the D.C. rail. (A fullbridge circuit would have transistors in these positions also,but this arrangement is rarely used in electronic ballasts forfluorescent lamps. Although the required voltage rating ofthe transistors would be halved, this would not compensatefor the increased cost of four power transistors instead oftwo, and the extra complication of controlling the timing ofthe switching of all four transistors.)

The two capacitors, which have a very low reactance andare essentially a short circuit at the ballast operatingfrequency, create a mid-point A.C. reference between theD.C. rails. This blocks the D.C. offset equal to half the railvoltage that would be applied to the lamp if the return pathwere merely taken to one of the rails.

Current fed parallel resonant half bridgeinverter.

Figure 9 shows the simplified circuit. Transformer isolationis provided, and the sinusoidal output permits the use ofballast capacitors as for the current fed push pull topology.The series inductance L in each power supply line acts asthe current source.

Fig. 9. Current fed parallel resonant half bridge ballastwith isolated output.

As each transistor conducts in turn, the current fed resonantload causes alternate polarity half sinewaves with peakvoltages of π/2 x VDC to appear at one end of the transformerprimary. Each half sine appears across the non-conductingtransistor. Therefore the maximum theoretical VCE = π/2 xVDC.

The sum of these half sines produces a full sinewave witha peak to peak amplitude of π x VDC. However, as the returncurrent flows to the A.C. half rail created by the half bridgecapacitors, only half this voltage appears across theprimary, resulting in a peak to peak primary voltage of π/2x VDC.

Voltage fed half bridge inverter.See Fig. 10. This circuit does not employ a transformer sooutput isolation is not provided. Feedback to drive thetransistors is now supplied from two auxiliary windings onthe current transformer CT1 in the lamp current path.

As this is a voltage fed circuit whose output is not naturallysinusoidal, lamp starting, ballasting and waveform shapingare provided by the series L and parallel C as for the voltagefed push pull circuit.

In the voltage fed half bridge circuit, since the transistorsare "firmly anchored" to the supply rails without any currentsource series inductance, they will experience a maximumtheoretical VCE equal to the D.C. rail voltage.

Fig. 10. Voltage fed half bridge ballast.

Variation on the voltage fed half bridgecircuit.A variation on this circuit is shown in Fig. 11, where the twohalf bridge capacitors are replaced by the single D.C.blocking capacitor C2. This enables the load to be returnedto the positive D.C. rail.

The circuit operates as follows:On initial power-up, before the lamp has struck, C1, L andC2 form a series resonant circuit. C2 is larger than C1 soit looks like a short circuit compared to C1. C1 thereforedominates and dictates the resonant frequency in

+

-

CT1

CT1

CT1

L

C

Vdc

+

-

T1

T1

C

TOADDITIONAL

LAMPS

T1

DRIVECIRCUIT

DRIVECIRCUIT

L

LVdc

584


combination with L. A high voltage is developed across C1at resonance which starts the tube. At this point the tubevoltage across C1 collapses and C2 then takes over indictating a lower running frequency in combination with L.

Fig. 11. Variation on voltage fed series resonant halfbridge circuit.

This circuit is the one most commonly used in theelectronically ballasted compact fluorescent lamps and itlends itself to driven as well as self oscillating circuits.

Summary.The circuit examples presented in this Publication all usebipolar transistors, mainly for cost advantage reasons,

especially where high voltage devices up to 1000V ratingand above are required. Ballast manufacturers haveperfected many good, reliable designs using such devicesin circuits based on the simplified topologies shown.

Popular topologies for low cost electronic ballasts haveproved to be the current fed parallel resonant circuits. Tosummarise the reasons for this, they naturally produce theideal sinewave output. This permits the use of simple ballastcapacitors instead of inductors. The circuits also maintainsafe operation with abnormal load conditions. Lamps canbe operated in parallel, where the failure of one or morelamp will not disable the remaining lamps.

The current fed topologies require higher voltagetransistors than the voltage fed topologies. For example,for the current fed half bridge topology, allowing for safetymargins of around 400V for voltage spikes at start-up and110% mains voltage, a 120V ballast would requiretransistors with typical voltage ratings of at least 700V. Theratings for 230V mains would typically be at least 950V, andfor 277V mains typical voltage ratings of at least 1100Vwould be required.

The ratings for a current fed push pull topology would be1000V, 1500V and 1700V respectively.

+

-

CT1

CT1

CT1

L

C1

C2

Vdc

585


8.1.2 Electronic Ballasts - Philips Transistor Selection Guide

Section 8.1.1 provides an introduction to fluorescent lampsand the circuits required to operate them for maximum lifeand efficiency. Several simplified electronic ballasttopologies are introduced.

This section lists those topologies with the theoreticalvoltage demands they place on the transistors, togetherwith a selection table of suitable Philips transistors.

a) Voltage fed push pull inverter.

The D.C. rail voltage appears at the transformer centre tap.

Therefore Vc.t. = VDC.

Half of the transformer’s primary winding is energised withthe full D.C. rail voltage at any one time. Therefore twicethis voltage will appear across the whole winding(autotransformer effect). This voltage appears across eachtransistor in turn when it is non-conducting. So, duringstable circuit operation and neglecting unforeseen voltagespikes:

VCE(max) = 2 x VDC.

b) Current fed push pull inverter.

The transformer centre tap is no longer connected directlyto the D.C. rail. The voltage developed across the seriesinductor L as each transistor conducts results in a positivehalf sinewave at the centre tap whose average voltage isequal to the D.C. rail voltage. A half sine instead of arectangular pulse is produced because of the resonantnature of the load.

Therefore Vc.t.(ave) = VDC.

The peak value of this waveform can be shown byintegration to be π/2 x its average value.

Therefore Vc.t.(pk) = π/2 x Vc.t.(ave) = π/2 x VDC.

Each successive half sine is conducted through alternatehalves of the primary, so twice this amplitude appearsacross the full primary. This gives a peak voltage of twicethe peak centre tap voltage appearing across thenon-conducting transistor (as for the voltage fed push pullcircuit), so:

VCE(pk) = π x VDC.

c) Current fed half bridge inverter.

The transformer primary is driven from one end by thecollector-emitter junction point of the two transistors. If thiswere a voltage fed circuit without any series L, the primarywould be alternately connected to the positive and negativerails by the alternate transistor switching to produce asquare wave with a peak to peak amplitude of VDC.However, because this is a current fed resonant circuit, theconduction of each transistor will produce a half sine whoseaverage voltage is equal to the D.C. rail voltage.

Therefore V(ave) = VDC.

By integrating it can be shown that the half sine will have apeak amplitude of π/2 x its average value.

Therefore V(pk) = π/2 x V(ave) = π/2 x VDC.

DRIVE

CIRCUIT

DRIVE

CIRCUIT

+

-

L

C

T1

T1

T1

Vdc

+

-

T1

T1

C

TOADDITIONAL

LAMPS

T1

DRIVECIRCUIT

DRIVECIRCUIT

L

LVdc

DRIVE

CIRCUIT

DRIVE

CIRCUIT

+

-

L

T1

T1

T1 C

ADDITIONALLAMPS

TO

Vdc

587


This voltage appears across the non-conducting transistor,so:

VCE(pk) = π/2 x VDC.

d) Voltage fed half bridge inverter.

As the transistors are now connected directly to the D.C.rails, their alternate switching will switch the transformerprimary between the D.C. rails only.

Therefore V(max) = VDC.

As this voltage appears across the non-conductingtransistor:

VCE(max) = VDC.

Transistor selection guide.

This guide lists suitable transistors with maximumrecommended output powers for the different topologies. Itassumes that the ballast’s D.C. rail is obtained from rectifiedand smoothed A.C. mains. If boost power factor correctionis included which boosts the D.C. rail voltage to around400V irrespective of mains voltage, the suggestedtransistors for 277V mains should be selected.

+

-

CT1

CT1

CT1

L

C

Vdc

TOPOLOGY: a) V. fed P.P. b) C. fed P.P. c) C. fed H.B. d) V. fed H.B.

120V BUW84/85 35W BUX87P 13W BUW84/85 25W BUW84/85 15WBUX84/85 35W BUX85 55W BUX84/85 25W BUX84/85 15WBUT211 90W BUT11A 140W BUT211 70W BUT211 40WBUT18A 110W BUT18A 170W BUT18A 80W BUT18A 55WBUT12A 140W BUT12A 230W BUT12A 110W BUT12A 70WBUW12A 140W BUW12A 230W BUW12A 110W BUW12A 70W

230V BUX87P 15W BU1706A 230W BUX87P 13W BUW84/85 30WA.C. BUW85 70W BU1706AX 230W BUW85 55W BUX84/85 30W

SUPPLY: BUX85 70W BU508A 360W BUX85 55W BUT211 80WBUT11A 170W BUT11A 140W BUT18A 100WBUT18A 210W BUT18A 160W BUT12A 140WBUT12A 280W BUT12A 220W BUW12A 140WBUW12A 280W BUW12A 220W

277V BU1706A 170W BU1706A 260W BU1706A 130W BUW84/85 40W& most BU1706AX 170W BU1706AX 260W BU1706AX 130W BUX84/85 40Wboosted BU508A 280W BU508A 220W BUT211 100Wdesigns BUT18A 125W

BUT12A 170WBUW12A 170W

588


8.1.3 An Electronic Ballast - Base Drive Optimisation

This section investigates the transistor base drive circuit ina current fed half bridge ballast. (Fig. 1 shows the simplifiedcircuit.) The effect on switching waveforms of progressingfrom a simple base drive circuit to the optimised solutionwill be shown.

Fig. 1. Current fed half bridge ballast.

Base drive requirements.1.Each transistormust not be overdrivenand oversaturatedwhen conducting otherwise excessive base powerdissipation will result. The time will also be increased inbringing the transistor out of saturation during turn-off,leading to increased switching losses.

2. The transistor must not be underdriven because this willresult in excessive collector-to-emitter voltage (VCE) duringconduction, leading to excessive ON-state losses orinability to sustain oscillation. However, because thetransistor is unsaturated, there will be less charge to extractfrom the base, resulting in a shorter storage time and fasterturn-off.

3. Reliable and correct circuit operation should bemaintained for all expected transistor gains, maximum andminimum load, maximum and minimum supply voltage andall component tolerances.

Base drive optimisation.The transformer’s auxiliary windings which provide basedrive might contain just one or two turns each. In order toprovide rapid transistor turn-off, their peak loaded output

voltage would need to be such that the transistor ’sees’ aturn-off voltage of around minus 5V. An approximation tothis drive voltage could be arrived at empirically byincreasing the number of auxiliary turns one by one. Anyfinal voltage adjustment, if necessary, can be achieved byvarying the base drive components.

Simple base drive.In order to meet the requirements of non-saturation andrapid turn-off, the simplest base drive might consist of aresistor to limit the positive base current and a Schottkydiode in parallel with it to discharge the base as quickly aspossible. See Fig. 2.

Fig. 2. Simple base drive.

A Schottky diode is specified for its fast switching and lowforward voltage drop to best meet the rapid turn-offrequirements. A 1A 40V device such as the BYV10-40 isideally suited.

If the resistor is selected empirically so that the transistoris barely saturating, this simple circuit will work, but only fora given load current, supply voltage, transistor gain andbase drive voltage from the transformer auxiliary winding.Altering any of these conditions will either causeunderdriving of the transistor and, ultimately, cessation ofoscillation, or else the transistor will be overdriven, causingincreased collector current fall time and excessiveswitching losses.

For example, the resistor value was optimised fortransistors with low gain limits. Fig. 3 shows the resultingIC fall at transistor turn-off, while Fig. 4 shows the effect ofreplacing the transistor with a high gain limit sample. Theshaded areas bounded by the IC and VCE curves representtransistor power dissipation during switching.

+

-

T1

T1

C

TOADDITIONAL

LAMPS

T1

DRIVECIRCUIT

DRIVECIRCUIT

L

LVdc

R

T1D1

589


Simple base drive.Fig. 3. Low hFE. IC fall with VCE.

Simple base drive.Fig. 4. High hFE. IC fall with VCE.

Improved circuit.What is required is a means of providing enough base driveunder worst case conditions of maximum load current,minimum supply voltage, minimum transistor gain andminimum base drive voltage, while avoiding excessivesaturation in the opposite condition. This can be achievedby diverting excess positive base drive current into thecollector path when the transistor is fully turned on. Thisrequirement is partly met by a Baker Clamp arrangementas shown in Fig. 5.

When the transistor is fully conducting, VCE will be at aminimum. This will bring VC close to VB so that any excessbase drive will then flow through anti saturation diode D2to the collector. As a first approximation, the single resistorR is divided equally into two and D2 taps its voltage fromthe mid point. Figs. 6 and 7 show the resulting IC fallwaveforms. Considerably reduced transistor saturation isevident.

Fig. 5. Improved base drive.

Improved base drive.Fig. 6. Low hFE. IC fall with VCE.

Improved base drive.Fig. 7. High hFE. IC fall with VCE.

With regard to the base waveforms, where the simple circuitproduces more base drive current than is necessary, asshown in Fig. 8, the improved circuit reduces this to thatshown in Fig. 9.

Vce (50V/div)

0

0.5 us/div

Ic (0.2 A/div)

T1D1

D2

R1 R2c

b

e

Vce (50V/div)

0

0.5 us/div

Ic (0.2 A/div)Vce (50V/div)

0

0.5 us/div

Ic (0.2 A/div)

Vce (50V/div)

0

0.5 us/div

Ic (0.2 A/div)

590


Fig. 8. Simple base drive.High hFE. IB.

Fig. 9. Improved base drive.High hFE. IB.

Optimised base drive.

Optimised base drive.Fig. 10. High hFE. VCE, IC and IB.

To ensure correct operation under all conditions, base drivecan be optimised by adjusting the ratio of the two resistorsto vary the amount of tap-off voltage. With the base resistordivided equally into two, this particular circuit suffered froma lack of base drive at low supply voltage. Too much drivehad been diverted away from the base. This was correctedby moving the tap-off point to the right to split the resistortwo thirds to one third to reduce the amount of diverted basedrive. Referring to Fig. 5, R1 becomes 2/3 x R and R2becomes 1/3 x R.

Figs. 11 and 12 show the optimised IC fall waveforms. Afew cycles of the switching waveforms with optimised basedrive are shown in Fig. 10.

Optimised base drive.Fig. 11. Low hFE. IC fall with VCE.

Optimised base drive.Fig. 12. High hFE. IC fall with VCE.

Startup circuit.

The half bridge circuit as described so far cannot start ofits own accord. Both transistors are off and will remain offwhen power is applied until one of them is artificially turnedon to draw current through the transformer primary. Thiswill then induce a voltage in the auxiliary windings whichwill provide the necessary base drive to maintain selfoscillation. Startup is usually achieved using a diac suchas the BR100/03. The circuit is shown in Fig. 13.

Ib (0.1 A/div)

0

10 us/div

Ib (0.1 A/div)

0

10 us/div

Vce (50V/div)

0

0.5 us/div

Ic (0.2 A/div)

Vce (100 V/div)

0

10 us/div

Ic (0.2 A/div)

0

10 us/div

Ib (0.1 A/div)

0

10 us/div

Ic (0.2 A/div)

0

0.5 us/div

Vce (50V/div)

591


When power is first applied, oscillator start-up is achievedas follows:

Transistors Q1 and Q2are initially non conducting. ResistorR4, whose value will be several hundred kilohms, providesa high impedance path between Q2’s collector and thepositive rail to ensure that Q2 has the full D.C. rail voltageacross it prior to start-up.

Capacitor C charges up via R1 until the breakover voltageof the diac D8 is reached. The diac breaks over and dumpsthe capacitor’s charge into the base of Q2 to turn it on. Q2draws current through the transformer primary. From nowon, oscillation is maintained by the voltages induced on theauxiliary base drive windings.

Diode D1 discharges C every time Q2 turns on, therebypreventing the diac’s breakover voltage being reachedduring normal circuit oscillation. This avoids repeatedtriggering of the diac when it is not required, so preventingoversaturation of Q2. (The length of time for C to charge tothe diac’s breakover voltage is much longer than the timebetween ON periods of Q2.)

D4 and D5 provide reverse current protection for Q1 andQ2.

Fig. 13. A classic startup arrangement. (Part of currentfed half bridge circuit.)

TO T1

T1

T1

L

L

R1R4

+

-

D8

R2 R3

R5 R6

D1D2

D3

D4

D5

D7

D6

C

PRIMARY

Q1

Q2

592

Index Power Semiconductor ApplicationsPhilips Semiconductors

Index

Airgap, transformer core, 111, 113Anti saturation diode, 590Asynchronous, 497Automotive

fanssee motor control

IGBT, 481, 483ignition, 479, 481, 483lamps, 435, 455motor control, 425, 457, 459, 471, 475resistive loads, 442reverse battery, 452, 473, 479screen heater, 442seat heater, 442solenoids, 469TOPFET, 473

Avalanche, 61Avalanche breakdown

thyristor, 490Avalanche multiplication, 134

Baker clamp, 138, 187, 190Ballast

electronic, 580fluorescent lamp, 579switchstart, 579

Base drive, 136base inductor, 147base inductor, diode assisted, 148base resistor, 146drive transformer, 145drive transformer leakage inductance, 149electronic ballast, 589forward converter, 187power converters, 141speed-up capacitor, 143

Base inductor, 144, 147Base inductor, diode assisted, 148Boost converter, 109

continuous mode, 109discontinuous mode, 109output ripple, 109

Bootstrap, 303Breakback voltage

diac, 492Breakdown voltage, 70Breakover current

diac, 492Breakover voltage

diac, 492, 592thyristor, 490

Bridge circuitssee Motor Control - AC

Brushless motor, 301, 303Buck-boost converter, 110Buck converter, 108 - 109Burst firing, 537Burst pulses, 564

Capacitancejunction, 29

Capacitormains dropper, 544

CENELEC, 537Charge carriers, 133

triac commutation, 549Choke

fluorescent lamp, 580Choppers, 285Clamp diode, 117Clamp winding, 113Commutation

diode, 164Hi-Com triac, 551thyristor, 492triac, 494, 523, 529

Compact fluorescent lamp, 585Continuous mode

see Switched Mode Power SuppliesContinuous operation, 557Converter (dc-dc)

switched mode power supply, 107Cookers, 537Cooling

forced, 572natural, 570

Crest factor, 529Critical electric field, 134Cross regulation, 114, 117Current fed resonant inverter, 589Current Mode Control, 120Current tail, 138, 143

Damper Diodes, 345, 367forward recovery, 328, 348losses, 347outlines, 345picture distortion, 328, 348selection guide, 345

Darlington, 13Data Sheets

High Voltage Bipolar Transistor, 92,97,331MOSFET, 69

i


dc-dc converter, 119Depletion region, 133Desaturation networks, 86

Baker clamp, 91, 138dI/dt

triac, 531Diac, 492, 500, 527, 530, 591Diode, 6

double diffused, 162epitaxial, 161schottky, 173structure, 161

Diode Modulator, 327, 367Disc drives, 302Discontinuous mode

see Switched Mode Power SuppliesDomestic Appliances, 527Dropper

capacitive, 544resistive, 544, 545

Duty cycle, 561

EFD coresee magnetics

Efficiency Diodessee Damper Diodes

Electric drill, 531Electronic ballast, 580

base drive optimisation, 589current fed half bridge, 584, 587, 589current fed push pull, 583, 587flyback, 582transistor selection guide, 587voltage fed half bridge, 584, 588voltage fed push pull, 583, 587

EMC, 260, 455see RFI, ESDTOPFET, 473

Emitter shortingtriac, 549

Epitaxial diode, 161characteristics, 163dI/dt, 164forward recovery, 168lifetime control, 162operating frequency, 165passivation, 162reverse leakage, 169reverse recovery, 162, 164reverse recovery softness, 167selection guide, 171snap-off, 167softness factor, 167stored charge, 162technology, 162

ESD, 67see Protection, ESDprecautions, 67

ETD coresee magnetics

F-packsee isolated package

Fall time, 143, 144Fast Recovery Epitaxial Diode (FRED)

see epitaxial diodeFBSOA, 134Ferrites

see magneticsFlicker

fluorescent lamp, 580Fluorescent lamp, 579

colour rendering, 579colour temperature, 579efficacy, 579, 580triphosphor, 579

Flyback converter, 110, 111, 113advantages, 114clamp winding, 113continuous mode, 114coupled inductor, 113cross regulation, 114diodes, 115disadvantages, 114discontinuous mode, 114electronic ballast, 582leakage inductance, 113magnetics, 213operation, 113rectifier circuit, 180self oscillating power supply, 199synchronous rectifier, 156, 181transformer core airgap, 111, 113transistors, 115

Flyback converter (two transistor), 111, 114Food mixer, 531Forward converter, 111, 116

advantages, 116clamp diode, 117conduction loss, 197continuous mode, 116core loss, 116core saturation, 117cross regulation, 117diodes, 118disadvantages, 117duty ratio, 117ferrite cores, 116magnetics, 213magnetisation energy, 116, 117

ii


operation, 116output diodes, 117output ripple, 116rectifier circuit, 180reset winding, 117switched mode power supply, 187switching frequency, 195switching losses, 196synchronous rectifier, 157, 181transistors, 118

Forward converter (two transistor), 111, 117Forward recovery, 168FREDFET, 250, 253, 305

bridge circuit, 255charge, 254diode, 254drive, 262loss, 256reverse recovery, 254

FREDFETsmotor control, 259

Full bridge converter, 111, 125advantages, 125diodes, 126disadvantages, 125operation, 125transistors, 126

Gatetriac, 538

Gate driveforward converter, 195

Gold doping, 162, 169GTO, 11Guard ring

schottky diode, 174

Half bridge, 253Half bridge circuits

see also Motor Control - ACHalf bridge converter, 111, 122

advantages, 122clamp diodes, 122cross conduction, 122diodes, 124disadvantages, 122electronic ballast, 584, 587, 589flux symmetry, 122magnetics, 214operation, 122synchronous rectifier, 157transistor voltage, 122transistors, 124voltage doubling, 122

Heat dissipation, 567

Heat sink compound, 567Heater controller, 544Heaters, 537Heatsink, 569Heatsink compound, 514Hi-Com triac, 519, 549, 551

commutation, 551dIcom/dt, 552gate trigger current, 552inductive load control, 551

High side switchMOSFET, 44, 436TOPFET, 430, 473

High Voltage Bipolar Transistor, 8, 79, 91,141, 341

‘bathtub’ curves, 333avalanche breakdown, 131avalanche multiplication, 134Baker clamp, 91, 138base-emitter breakdown, 144base drive, 83, 92, 96, 136, 336, 385base drive circuit, 145base inductor, 138, 144, 147base inductor, diode assisted, 148base resistor, 146breakdown voltage, 79, 86, 92carrier concentration, 151carrier injection, 150conductivity modulation, 135, 150critical electric field, 134current crowding, 135, 136current limiting values, 132current tail, 138, 143current tails, 86, 91d-type, 346data sheet, 92, 97, 331depletion region, 133desaturation, 86, 88, 91device construction, 79dI/dt, 139drive transformer, 145drive transformer leakage inductance, 149dV/dt, 139electric field, 133electronic ballast, 581, 585, 587, 589Fact Sheets, 334fall time, 86, 99, 143, 144FBSOA, 92, 99, 134hard turn-off, 86horizontal deflection, 321, 331, 341leakage current, 98limiting values, 97losses, 92, 333, 342Miller capacitance, 139operation, 150

iii


optimum drive, 88outlines, 332, 346over current, 92, 98over voltage, 92, 97overdrive, 85, 88, 137, 138passivation, 131power limiting value, 132process technology, 80ratings, 97RBSOA, 93, 99, 135, 138, 139RC network, 148reverse recovery, 143, 151safe operating area, 99, 134saturation, 150saturation current, 79, 98, 341secondary breakdown, 92, 133smooth turn-off, 86SMPS, 94, 339, 383snubber, 139space charge, 133speed-up capacitor, 143storage time, 86, 91, 92, 99, 138, 144, 342sub emitter resistance, 135switching, 80, 83, 86, 91, 98, 342technology, 129, 149thermal breakdown, 134thermal runaway, 152turn-off, 91, 92, 138, 142, 146, 151turn-on, 91, 136, 141, 149, 150underdrive, 85, 88voltage limiting values, 130

Horizontal Deflection, 321, 367base drive, 336control ic, 401d-type transistors, 346damper diodes, 345, 367diode modulator, 327, 347, 352, 367drive circuit, 352, 365, 406east-west correction, 325, 352, 367line output transformer, 354linearity correction, 323operating cycle, 321, 332, 347s-correction, 323, 352, 404TDA2595, 364, 368TDA4851, 400TDA8433, 363, 369test circuit, 321transistors, 331, 341, 408waveforms, 322

IGBT, 11, 305automotive, 481, 483clamped, 482, 484ignition, 481, 483

Ignitionautomotive, 479, 481, 483darlington, 483

Induction heating, 53Induction motor

see Motor Control - ACInductive load

see SolenoidInrush current, 528, 530Intrinsic silicon, 133Inverter, 260, 273

see motor control accurrent fed, 52, 53switched mode power supply, 107

Irons, electric, 537Isolated package, 154

stray capacitance, 154, 155thermal resistance, 154

Isolation, 153

J-FET, 9Junction temperature, 470, 557, 561

burst pulses, 564non-rectangular pulse, 565rectangular pulse, composite, 562rectangular pulse, periodic, 561rectangular pulse, single shot, 561

Lamp dimmer, 530Lamps, 435

dI/dt, 438inrush current, 438MOSFET, 435PWM control, 455switch rate, 438TOPFET, 455

Latching currentthyristor, 490

Leakage inductance, 113, 200, 523Lifetime control, 162Lighting

fluorescent, 579phase control, 530

Logic Level FETmotor control, 432

Logic level MOSFET, 436

Magnetics, 207100W 100kHz forward converter, 197100W 50kHz forward converter, 19150W flyback converter, 199core losses, 208core materials, 207EFD core, 210ETD core, 199, 207

iv


flyback converter, 213forward converter, 213half bridge converter, 214power density, 211push-pull converter, 213switched mode power supply, 187switching frequency, 215transformer construction, 215

Mains Flicker, 537Mains pollution, 225

pre-converter, 225Mains transient, 544Mesa glass, 162Metal Oxide Varistor (MOV), 503Miller capacitance, 139Modelling, 236, 265MOS Controlled Thyristor, 13MOSFET, 9, 19, 153, 253

bootstrap, 303breakdown voltage, 22, 70capacitance, 30, 57, 72, 155, 156capacitances, 24characteristics, 23, 70 - 72charge, 32, 57data sheet, 69dI/dt, 36diode, 253drive, 262, 264drive circuit loss, 156driving, 39, 250dV/dt, 36, 39, 264ESD, 67gate-source protection, 264gate charge, 195gate drive, 195gate resistor, 156high side, 436high side drive, 44inductive load, 62lamps, 435leakage current, 71linear mode, parallelling, 52logic level, 37, 57, 305loss, 26, 34maximum current, 69motor control, 259, 429modelling, 265on-resistance, 21, 71package inductance, 49, 73parallel operation, 26, 47, 49, 265parasitic oscillations, 51peak current rating, 251Resonant supply, 53reverse diode, 73ruggedness, 61, 73

safe operating area, 25, 74series operation, 53SMPS, 339, 384solenoid, 62structure, 19switching, 24, 29, 58, 73, 194, 262switching loss, 196synchronous rectifier, 179thermal impedance, 74thermal resistance, 70threshold voltage, 21, 70transconductance, 57, 72turn-off, 34, 36turn-on, 32, 34, 35, 155, 256

Motor, universalback EMF, 531starting, 528

Motor Control - AC, 245, 273anti-parallel diode, 253antiparallel diode, 250carrier frequency, 245control, 248current rating, 262dc link, 249diode, 261diode recovery, 250duty ratio, 246efficiency, 262EMC, 260filter, 250FREDFET, 250, 259, 276gate drives, 249half bridge, 245inverter, 250, 260, 273line voltage, 262loss, 267MOSFET, 259Parallel MOSFETs, 276peak current, 251phase voltage, 262power factor, 262pulse width modulation, 245, 260ripple, 246short circuit, 251signal isolation, 250snubber, 276speed control, 248switching frequency, 246three phase bridge, 246underlap, 248

Motor Control - DC, 285, 293, 425braking, 285, 299brushless, 301control, 290, 295, 303current rating, 288

v


drive, 303duty cycle, 286efficiency, 293FREDFET, 287freewheel diode, 286full bridge, 287half bridge, 287high side switch, 429IGBT, 305inrush, 430inverter, 302linear, 457, 475logic level FET, 432loss, 288MOSFET, 287, 429motor current, 295overload, 430permanent magnet, 293, 301permanent magnet motor, 285PWM, 286, 293, 459, 471servo, 298short circuit, 431stall, 431TOPFET, 430, 457, 459, 475topologies, 286torque, 285, 294triac, 525voltage rating, 288

Motor Control - Stepper, 309bipolar, 310chopper, 314drive, 313hybrid, 312permanent magnet, 309reluctance, 311step angle, 309unipolar, 310

Mounting, transistor, 154Mounting base temperature, 557Mounting torque, 514

Parasitic oscillation, 149Passivation, 131, 162PCB Design, 368, 419Phase angle, 500Phase control, 546

thyristors and triacs, 498triac, 523

Phase voltagesee motor control - ac

Power dissipation, 557see High Voltage Bipolar Transistor loss,MOSFET loss

Power factor correction, 580active, boost converted, 581

Power MOSFETsee MOSFET

Proportional control, 537Protection

ESD, 446, 448, 482overvoltage, 446, 448, 469reverse battery, 452, 473, 479short circuit, 251, 446, 448temperature, 446, 447, 471TOPFET, 445, 447, 451

Pulse operation, 558Pulse Width Modulation (PWM), 108Push-pull converter, 111, 119

advantages, 119clamp diodes, 119cross conduction, 119current mode control, 120diodes, 121disadvantages, 119duty ratio, 119electronic ballast, 582, 587flux symmetry, 119, 120magnetics, 213multiple outputs, 119operation, 119output filter, 119output ripple, 119rectifier circuit, 180switching frequency, 119transformer, 119transistor voltage, 119transistors, 121

Qs (stored charge), 162

RBSOA, 93, 99, 135, 138, 139Rectification, synchronous, 179Reset winding, 117Resistor

mains dropper, 544, 545Resonant power supply, 219, 225

modelling, 236MOSFET, 52, 53pre-converter, 225

Reverse leakage, 169Reverse recovery, 143, 162RFI, 154, 158, 167, 393, 396, 497, 529, 530,537Ruggedness

MOSFET, 62, 73schottky diode, 173

Safe Operating Area (SOA), 25, 74, 134, 557forward biased, 92, 99, 134reverse biased, 93, 99, 135, 138, 139

vi


Saturable choketriac, 523

Schottky diode, 173bulk leakage, 174edge leakage, 174guard ring, 174reverse leakage, 174ruggedness, 173selection guide, 176technology, 173

SCRsee Thyristor

Secondary breakdown, 133Selection Guides

BU25XXA, 331BU25XXD, 331damper diodes, 345EPI diodes, 171horizontal deflection, 343MOSFETs driving heaters, 442MOSFETs driving lamps, 441MOSFETs driving motors, 426Schottky diodes, 176SMPS, 339

Self Oscillating Power Supply (SOPS)50W microcomputer flyback converter, 199ETD transformer, 199

Servo, 298Single ended push-pull

see half bridge converterSnap-off, 167Snubber, 93, 139, 495, 502, 523, 529, 549

active, 279Softness factor, 167Solenoid

TOPFET, 469, 473turn off, 469, 473

Solid state relay, 501SOT186, 154SOT186A, 154SOT199, 154Space charge, 133Speed-up capacitor, 143Speed control

thyristor, 531triac, 527

Starterfluorescent lamp, 580

Startup circuitelectronic ballast, 591self oscillating power supply, 201

Static Induction Thyristor, 11Stepdown converter, 109Stepper motor, 309Stepup converter, 109

Storage time, 144Stored charge, 162Suppression

mains transient, 544Switched Mode Power Supply (SMPS)

see also self oscillating power supply100W 100kHz MOSFET forward converter,192100W 500kHz half bridge converter, 153100W 50kHz bipolar forward converter, 18716 & 32 kHz TV, 389asymmetrical, 111, 113base circuit design, 149boost converter, 109buck-boost converter, 110buck converter, 108ceramic output filter, 153continuous mode, 109, 379control ic, 391control loop, 108core excitation, 113core loss, 167current mode control, 120dc-dc converter, 119diode loss, 166diode reverse recovery effects, 166diode reverse recovery softness, 167diodes, 115, 118, 121, 124, 126discontinuous mode, 109, 379epitaxial diodes, 112, 161flux swing, 111flyback converter, 92, 111, 113, 123forward converter, 111, 116, 379full bridge converter, 111, 125half bridge converter, 111, 122high voltage bipolar transistor, 94, 112, 115,118, 121, 124, 126, 129, 339, 383, 392isolated, 113isolated packages, 153isolation, 108, 111magnetics design, 191, 197magnetisation energy, 113mains filter, 380mains input, 390MOSFET, 112, 153, 33, 384multiple output, 111, 156non-isolated, 108opto-coupler, 392output rectifiers, 163parasitic oscillation, 149power-down, 136power-up, 136, 137, 139power MOSFET, 153, 339, 384pulse width modulation, 108push-pull converter, 111, 119

vii


RBSOA failure, 139rectification, 381, 392rectification efficiency, 163rectifier selection, 112regulation, 108reliability, 139resonant

see resonant power supplyRFI, 154, 158, 167schottky diode, 112, 154, 173snubber, 93, 139, 383soft start, 138standby, 382standby supply, 392start-up, 391stepdown, 109stepup, 109symmetrical, 111, 119, 122synchronisation, 382synchronous rectification, 156, 179TDA8380, 381, 391topologies, 107topology output powers, 111transformer, 111transformer saturation, 138transformers, 391transistor current limiting value, 112transistor mounting, 154transistor selection, 112transistor turn-off, 138transistor turn-on, 136transistor voltage limiting value, 112transistors, 115, 118, 121, 124, 126turns ratio, 111TV & Monitors, 339, 379, 399two transistor flyback, 111, 114two transistor forward, 111, 117

Switching loss, 230Synchronous, 497Synchronous rectification, 156, 179

self driven, 181transformer driven, 180

Temperature control, 537Thermal

continuous operation, 557, 568intermittent operation, 568non-rectangular pulse, 565pulse operation, 558rectangular pulse, composite, 562rectangular pulse, periodic, 561rectangular pulse, single shot, 561single shot operation, 561

Thermal capacity, 558, 568

Thermal characteristicspower semiconductors, 557

Thermal impedance, 74, 568Thermal resistance, 70, 154, 557Thermal time constant, 568Thyristor, 10, 497, 509

’two transistor’ model, 490applications, 527asynchronous control, 497avalanche breakdown, 490breakover voltage, 490, 509cascading, 501commutation, 492control, 497current rating, 511dI/dt, 490dIf/dt, 491dV/dt, 490energy handling, 505external commutation, 493full wave control, 499fusing I2t, 503, 512gate cathode resistor, 500gate circuits, 500gate current, 490gate power, 492gate requirements, 492gate specifications, 512gate triggering, 490half wave control, 499holding current, 490, 509inductive loads, 500inrush current, 503latching current, 490, 509leakage current, 490load line, 492mounting, 514operation, 490overcurrent, 503peak current, 505phase angle, 500phase control, 498, 527pulsed gate, 500resistive loads, 498resonant circuit, 493reverse characteristic, 489reverse recovery, 493RFI, 497self commutation, 493series choke, 502snubber, 502speed controller, 531static switching, 497structure, 489switching, 489

viii


switching characteristics, 517synchronous control, 497temperature rating, 512thermal specifications, 512time proportional control, 497transient protection, 502trigger angle, 500turn-off time, 494turn-on, 490, 509turn-on dI/dt, 502varistor, 503voltage rating, 510

Thyristor data, 509Time proportional control, 537TOPFET

3 pin, 445, 449, 4615 pin, 447, 451, 457, 459, 463driving, 449, 453, 461, 465, 467, 475high side, 473, 475lamps, 455leadforms, 463linear control, 451, 457motor control, 430, 457, 459negative input, 456, 465, 467protection, 445, 447, 451, 469, 473PWM control, 451, 455, 459solenoids, 469

Transformertriac controlled, 523

Transformer core airgap, 111, 113Transformers

see magneticsTransient thermal impedance, 559Transient thermal response, 154Triac, 497, 510, 518

400Hz operation, 489, 518applications, 527, 537asynchronous control, 497breakover voltage, 510charge carriers, 549commutating dI/dt, 494commutating dV/dt, 494commutation, 494, 518, 523, 529, 549control, 497dc inductive load, 523dc motor control, 525dI/dt, 531, 549dIcom/dt, 523dV/dt, 523, 549emitter shorting, 549full wave control, 499fusing I2t, 503, 512gate cathode resistor, 500gate circuits, 500gate current, 491

gate requirements, 492gate resistor, 540, 545gate sensitivity, 491gate triggering, 538holding current, 491, 510Hi-Com, 549, 551inductive loads, 500inrush current, 503isolated trigger, 501latching current, 491, 510operation, 491overcurrent, 503phase angle, 500phase control, 498, 527, 546protection, 544pulse triggering, 492pulsed gate, 500quadrants, 491, 510resistive loads, 498RFI, 497saturable choke, 523series choke, 502snubber, 495, 502, 523, 529, 549speed controller, 527static switching, 497structure, 489switching, 489synchronous control, 497transformer load, 523transient protection, 502trigger angle, 492, 500triggering, 550turn-on dI/dt, 502varistor, 503zero crossing, 537

Trigger angle, 500TV & Monitors

16 kHz black line, 35130-64 kHz autosync, 39932 kHz black line, 361damper diodes, 345, 367diode modulator, 327, 367EHT, 352 - 354, 368, 409, 410high voltage bipolar transistor, 339, 341horizontal deflection, 341picture distortion, 348power MOSFET, 339SMPS, 339, 354, 379, 389, 399vertical deflection, 358, 364, 402

Two transistor flyback converter, 111, 114Two transistor forward converter, 111, 117

Universal motorback EMF, 531

ix


starting, 528

Vacuum cleaner, 527Varistor, 503Vertical Deflection, 358, 364, 402Voltage doubling, 122

Water heaters, 537

Zero crossing, 537Zero voltage switching, 537

x

Power Semiconductor Applications Philips Semiconductors

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