Power FINFET, a Novel Superjunction Power MOSFETngwt/publications/other...Power FINFET CMOSET, June...

CMOSET, June 16, 2011Power FINFET

1University of Toronto

Wai Tung Ng

Smart Power Integration & Semiconductor Devices Research Group

Department of Electrical and Computer EngineeringUniversity of Toronto

Toronto, OntarioCanada, M5S 3G4

E-mail: [email protected]

© 2011

Power FINFET, a Novel Superjunction Power MOSFET



OutlineOverview of Power Semiconductor DevicesDesign issues for Low Voltage Super-Junction

DevicesA Low Voltage Lateral Super-Junction FINFET Basic Idea of SJ-FINFET Structure Device Simulation Works Process Flow and IC Fabrication Experimental Results

Summary



Applications of Smart Power ICs

Supply Voltage (V)

Load

Cur

rent

(A)

100

10

1

0.1

0.01

0.0011 10 100 1000

Telecom

Display

Digital

Bipolarlinear

AC Motors

FluorescentBallast

SwitchingRegulators

LinearRegulator

Automotive



Worldwide Power Semiconductor Market

LV LV LV LV

LV LV

SWR SWR SWR SWR SWR SWR

$16B

Source: M. Vukicevic, Data Processing Market to Dominate Power Semiconductor Market in 2007: Market Tracker, iSuppli Corp., Q1, 2007.



p-substrate

p-wellp+

n-well

drain sourcesource/body drain

HV p-EDMOSHV n-EDMOS

n+SiO2 SiO2 p+ p+n+ p+

SiO2 SiO2 p+ n+

p-wellHV n-well

source source/body drain source/bodysource/body

Floating Source HV n-FSMOS

n+SiO2 n+

SiO2 p+ n+SiO2 SiO2 p+n+ n+

SiO2SiO2

p-substrate

p-well n-well

drain bodysource drain

HV p-EDSMOSHV n-EDSMOS

p+ p+

p-well

body source drain source/bodysource/body

Low Voltage CMOS

p+ n+p+ n+SiO2 SiO2SiO2p+

SiO2SiO2n+SiO2SiO2 n+

SiO2 SiO2 n+ p+ p+SiO2n+

SiO2

n-well

n-drift region n-drift region

n-drift region n-drift region

p-drift region

p-drift region p-drift region

Tox = 780Å

Tox = 120Å

HVNMOS process (cont’d)Another example of CMOS compatible HV-CMOS with

a variety of 40V devices with minimal process changes.



Source

n+

p

n+

p+

Drain

Gate

Oxide

n-

n-

n

pn

np

Source

n+

p

n+

p+

Drain

Gate

Oxide

Lateral Super-Junction Power MOSFETs Super-Junction (SJ) power MOSFET is a promising

device to achieve a low Ron,sp because the drift region iscomposed of heavily doped alternating n/p-pillars. However,conventional SJ structure is not very attractive for lowvoltage MOSFETs (<100V) due to the fact that the channelresistance becomes comparable to the drift regionresistance at low voltage ratings.

Conventional LDMOSFET Superjunction LDMOSFET



y

z

xp

np

np

dd

Vds

Vgs

S

G

D

lz

lx

ly

0.0001

0.001

0.01

0.1

1

10

100

1000

10 100 1000

Breakdown voltage (V)

Spe

cific

on-

resi

stan

ce (m

Ωcm

2)

Fujihira, Fuji, JJAP, 1997

Si-limit

SJ Devices (Lz = 10µm)

Si Majority-Carrier Lateral Devices

Impact of the p/n pillar thickness



Features of Super-Junction MOSFETs Drift region structure: n-drift region replaced by

alternatively stacked, charge-coupled/heavily doped,n- and p- thin layers or pillars.

Low specific on-resistance: Current flow onlythrough the heavily doped parallel n-pillars.

High breakdown voltage: requires full-depletion ofSJ structures (a space-charged region, acting like apure intrinsic layer); simply depends on drift regionlength; independent on dose.

Charge counterbalance condition: controlling thedoping of p- and n-type SJ layers according to theRESURF theory.

Fabrication process: complicated and need preciseprocess controls.



Lateral Power Devices – PerformanceBV vs. Ron-sp

has been a performance matrix that many researchers have been chasing for years.

Ron-sp for power devices in the low voltage range (<100V) depends on many factors. 10 100 1000

10-3

10-2

10-1

100

101

102

103

Thick drift LDMOS

SJ-LDMOS/SOS[13]

d=5μm

Toshiba-0.8μmCMOS/BESOI[4]

Motorola[3]

LUDMOS[10]

BCD5[7]IDLDMOS[14]

Dual path double-resurf LDMOS[11]

Unbalanced SJ-LDMOS[12]

Si_Limit[8],[9] SJVDMOS[9] Cool_MOS[9] SOI Resurf[2]-[6] HexLDMOS Simple Resurf Data Source

Ron

,sp

[ m

Ω−c

m2 ]

BVdss [ V ]



Main Issue: Low Voltage SJ-MOSFETs

Sub-200V

Si-limit

Miura et al , NEC, ISPSD, 2005

Chen et al, NUS, ISPSD, 2007



Reduction of channel resistance Reduction of n-drift resistance E-field relaxation (i.e. higher BV) More efficient use of silicon

SOI substrate

n-drift region

Drain

Source

Gate

SOI substrate

Fill trench with p-pillar to form SJ device

Z

X

Y

Basic Idea of SJ-FINFET Structure



Cross-section: A-A’

SJ unit-cell SJ unit-cell

BOX

p-body

0.3

WtopP

oly-Si

0.6 0.3

1.0

Wside

2 .5

TGox

0.035

Cross-section: B-B’

SJ unit-cell SJ unit-cell

(Sn)(Sp)

BOX

DTI

p-drift

n-drift

Wp0.3 Wn 0.3 0.3 0.3

0.5

0.5

2 .5

Wtop

Wside

C X Y

Z

n

n

Gate

Tepi

p S

BOX

p-substrate

Wp

Drain

B

B’

2·Wn

A’

p-body

Wside

Wtop

p

n

n

p

Lch Ldriftn+n+

Source

p+

Wnn+

DTI

C C’

n+

A

Proposed Lateral SJ-FINFET Structure

Compatibility with modern CMOS process is anessential design consideration



(a) p-body implant (b) SJ-drift trench & implant (c) p-pillar diffusion (d) gate trench

(e) n-doped poly-Si gate (f) n+ source implant (g) p+ contact opening (h) Al metallization

Process Flow for the SJ-FINFET Structure



Parameters for 3D SimulationsThese

parameters were also used in the fabrication of the prototypes.

Parameters ValuesDrift length, Ldrift (µm) 3 to 12n-drift width, Wn (µm) 0.6n-drift doping conc., ND (cm-3) 7.4 × 1016

p-drift width, Wp (µm) 0.3p-drift doping conc., NA (cm-3) 7.4 to 9.8 × 1016

p-body doping conc., Np-body (cm-3) 5.0 × 1017

p-substrate doping conc., Nsub (cm-3) 2.0 × 1014

n+ source/drain contact, Ns/d (cm-3) 1.0 × 1020

p+ contact, Np+(cm-3) 5.0 × 1019

Gate oxide thickness, TGox (nm) 35Top channel width, Wtop (µm) 0.6Side channel width, Wside (µm) 2.0 and 3.0Gate length, Lgate (µm) 1.0Channel length, Lch (µm) 0.5SOI thickness, Tepi (µm) 2.6 and 3.6DTI depth (µm) 2.0 and 3.0Buried oxide thickness, Tbox (µm) 2.0



SJ unit-cell (w/ DTI & Gox)

SJ unit-cell (w/o DTI & Gox)

Drain

Source

SJ drift

DTIGate

Drain

Sourcep-driftchannel

BOXp-sub

p-body

p-body

p-sub

SJ-FINFET — Initial MESH Structure



Formation of the p/n pillars

Phosphorus

Boron

P-pillarN-epi

B, 8e13 cm-2, 45 keV, ± 12°

@ Y = -3Implant After

annealing

N-epi

P-pillar



Formation of the n+ source/drain contacts

N+P-body

N-epi.

Phosphorus

Boron

Arsenic

N+

P-bodyN-epi

P, 5e14 cm-2, 180 keV, ± 45°As, 9e14 cm-2, 200 keV, ± 45°@ Y = -3



1E-09

1E-08

1E-07

1E-06

1E-05

1E-04

0 50 100 150 200

I ds

(A)

Vds (V)

@Ld=3.0μm

@Ld=3.5μm

@Ld=4.0μm

@Ld=4.5μm

@Ld=5.0μm

@Ld=6.0μm

@Ld=8.0μm

@Ld=12.0μm

0

100

200

300

400

0 0.02 0.04 0.06 0.08 0.1

I ds

(A/c

m2

)

Vds (V)

@Ld=3.0μm

@Ld=3.5μm

@Ld=4.0μm

@Ld=4.5μm

@Ld=5.0μm

@Ld=6.0μm

@Ld=8.0μm

@Ld=12.0μm

On-state @ Vg=10V

@ Vds=1V, Ldrift = 3.0µm

Vth ~1.7V

Wn = Wp = 0.3µm

Np-drift = 9.5e16/cm3

Nn-drift = 7.4e16/cm3

@ Ldrift = 3.0µm

Off-state

SJ-FINFT — Device Simulation Results



40

60

80

100

120

-30 -25 -20 -15 -10 -5 0

BV

(V)

Charge imbalance (Nn-Np)/Np (%)

Wside / Ldrift = 2µm / 6µm




Other Published Data

SJ-FINFT — Device Simulation Results (cont’d)

0.1

1

10 100

Spec

ific

on-

resi

stan

ce (m

Ω·c

m2

)


∝BV1.9-2.0

Simulated conventional lateral SJ-LDMOS

Simulated SJ-FINFET

(О: 2µm and ∆: 3µm)

Si-limit: ∝BV2.5

90V 165V



SJ-FINFT: Device Simulation Results

0

0.1

0.2

0.3

0.4

0.5

0.6

0 1 2 3 4 5

R on,

sp(m

Ω·c

m2 )

Y-distance (μm)

@ Lgate=1µm, Lch=0.5µm, Ldrift=3µm

Rch Rn-drift RdrainRsource

Gate

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

0 1 2 3 4 5

E fie

ld(x

105 V

/cm

)

Ldrift (μm)

n-driftsource drain

SJ SOI-LDMOS

SJ-FINFET

Wside = 2µm

Wside= 3µm

Source Gate n-drift Drain

Relaxing the electric field at this point achieves higher breakdown voltage

channel

Ec for Si ~ 5 x 105 V/cm, BV~(Ec·Ldrift) / 2

SJ-FINFT — Device Simulation Results (cont’d)



50000µm (Mask=5cm, Die=1cm)

5000

0µm

(Mas

k=5c

m, D

ie=1

cm)

Total 9 Mask Layers

Final Chip Layout & Die Image



P-pillar Trench

Source Trench

Drain Trench

Poly-Si: Top Gate

Ldrift

Poly-Si: Trench Gate

Drain

Gate

Poly-Si: Top Gate

Poly-Si: Trench Gate P-pillar TrenchSource

Drain

Gate

Poly-Si: Top Gate

Poly-Si: Trench Gate P-pillar Trench

Source

Fabricated SJ-FINFETs: Optical & SEM Images



Ldrift = 3.5µm Ldrift = 6.0µm

Ldrift = 10.0µm Ldrift = 12.0µm

SJ-FINFETs: After Al-Metallization



Measured Data: Transfer I-V CharacteristicsLdrift=3.5µm, W=200µm, Tox = 35nm @ Vds = 0.1V

0E+00

1E-03

2E-03

3E-03

4E-03

5E-03

6E-03

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

I ds

(A)

Vgate (V)

Vth ~ 1.7V

The measured threshold voltage of the SJ-FINFET was approximately 1.7V



The Ron,sp of the SJ-FINFET is approximately 30% smaller than that of the conventional SJ-LDMOSFET.

0.00

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.10

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

I ds(A

)

Vds (V)

Vg= 2V

Vg= 4V

Vg= 6V

Vg= 8V

Vg= 10V

SJ-FINFET: Ldrift=3.5µm, W=200µm

0.00

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.10

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

I ds(A

)

Vds (V)

SJ-LDMOS: Ldrift=3.5µm, W=200µm

Vg= 2V

Vg= 4V

Vg= 6V

Vg= 8V

Vg= 10V

Measured Data: Output I-V Characteristics



The measured data is comparable with other published data and it shows a good agreement in the data trend between the simulation and measurement. For similar BV ratings, about 30% lower Ron,sp was found in the fabricated

0

0.2

0.4

0.6

0.8

1

1.2

1.4

0 20 40 60 80 100 120 140

Spe

cific

on-

resi

stan

ce (m

Ω·c

m2

)


Other published data

Simulated SJ-FINFET

Fabricated SJ-FINFET

Fabricated SJ-LDMOS

Fabricated SJ-LDMOS

Fabricated SJ-FINFET

Simulated SJ-FINFET

Si-limit

Data from [1], [3], [7] are for conventional LDMOSFETs

Data from [2], [4]-[6] are for conventional SJ-LDMOSFETs

[1][2]

[3]

[1][3]

[6]

[4] [5]

[7]

Measured Data: BV versus Ron,sp



Summary Low voltage lateral SJ-FINFET devices with deep

trench p-drift region were proposed and fabricated to improve the electrical characteristics of conventional planar gate SJ-LDMOSFETs.

For the similar BV ratings, the specific on-resistances of the fabricated SJ-FINFET devices were approximately 30% lower than that of the fabricated SJ-LDMOSFETs.

The current work represents the first experimental confirmation that the super-junction concept is advantageous for sub-200V applications.

More details will be presented at IEDM 2010.



Acknowledgements Visiting Scientist: Yasuhiko Onishi, Fuji Electric, JapanProf. Johnny K. O. Sin,

Hong Kong University of Science & TechnologyStaff in Nano-electronic Fabrication Facility (NFF),

Hong Kong University of Science & TechnologyAuto21 Networks of Centres of Excellence of CanadaNatural Sciences and Engineering Research Council of

CanadaU of T Open Fellowship

Power FINFET, a Novel Superjunction Power MOSFETngwt/publications/other...Power FINFET CMOSET, June...

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