Power Electronic Converters for Microgrids (Sharkh/Power Electronic Converters for Microgrids) ||...

2Converter Topologies

This chapter covers the structure, modulation, and modeling in MATLAB®-Simulinkof the conventional two-level (2L), and the three-level (3L) neutral point clamped(NPC) and cascaded H-bridge (CHB) converter topologies.

2.1 Topologies

This section presents the structure of 2L, NPC, and CHB converters, together withtheir switching states and conduction paths.

2.1.1 The Two-Level Converter

The three-phase 2L converter, illustrated in Figure 2.1, consists of three legs (a, b,c), each comprising two switching modules (V1a −V2a, V1b −V2b, V1c −V2c). Themodules are formed by an active switch (e.g. IGBT (insulated gate bipolar transistor),IGCT (insulated gate commutated thyristor), MOSFET (metal oxide semiconductorfield-effect transistor), etc.) and a diode, connected anti-parallel to the switch. Thethree converter legs are connected across a common DC-link capacitor (C), whichprovides a low-inductance path for the rapidly varying currents through the modules.

The active switching of the modules is controlled (i.e., turned on/off) by gating sig-nals given to the module drivers. The gating signals for modules V1x and V2x will besymbolized as g1x and g2x, respectively, where x can be a, b, or c. Each gating signalcan be equal either to 0 (switch is off) or to 1 (switch is on). However, g1x and g2xshould never be made equal to 1 at the same time because this would short-circuit theconverter’s DC-link capacitor. During the converter operation, g1x and g2x for each legare, therefore, complementary (apart from short intervals of dead-time, during whichboth signals are set to 0).

Figure 2.2 illustrates the possible switching states (sx) of each converter leg, definedby the allowed combinations of the gating signals. In the 2L converter, each leg has

Power Electronic Converters for Microgrids, First Edition. Suleiman M. Sharkh, Mohammad A. Abusara,Georgios I. Orfanoudakis and Babar Hussain.© 2014 John Wiley & Sons, Ltd. Published 2014 by John Wiley & Sons, Ltd.Companion Website: www.wiley.com/go/sharkh

14 Power Electronic Converters for Microgrids

VDC

2 V1a

V2a

V1b

V2b

V1c

ia,b,c

V2c

aC b

c

+

VDC

2−

Figure 2.1 Two-level converter topology

V1x

ON

ON

V1x

V2x

Sx = 1 (g1x = 1, g2x = 0)

x x

V2x

VDC

2+

VDC

2+vx =

ix < 0

ix ≥ 0

ix < 0

ix ≥ 0

VDC

2−vx =

VDC

2−

VDC

2+

VDC

2−

Sx = 0 (g1x = 0, g2x = 1)

Figure 2.2 Switching states and conduction paths for a leg of the two-level converter

two possible switching states, sx = 1 or 0, outputting a phase voltage of +VDC/2 and−VDC/2, respectively. For a given state, the conduction path changes according to thedirection of the current. It can be noticed, though, that the phase voltage is solelydependent on the gating signals; it is not affected by the phase current.

2.1.2 The NPC Converter

Each NPC converter comprises four switching modules (V1x −V4x) and two diodes(D5x and D6x), as shown in Figure 2.3. The converter’s DC-link consists of two capac-itors (C1 and C2), connected at the converter’s neutral point (NP). The topology takesits name from the fact that the (clamping) diodes D5x and D6x clamp the voltage of thepoints found between the outer and inner switching modules to the NP voltage. Thisresults in each converter module switching across the voltage of one of the DC-link

Converter Topologies 15

VDC

NP

C2

C1

ab

c

ia,b,c

2

VDC

2+

−

V1a

V2a

V3a

V4a

D6a

D5a

V1b

V2b

V3b

V4b

D6b

D5b

V1c

V2c

V3c

V4c

D6c

D5c

Figure 2.3 NPC converter topology

capacitors. If the capacitors are balanced, the switching voltage of each module istherefore VDC/2.

The gating signals are provided to each leg of the NPC converter to turn on twoadjacent modules at any time. Turning on the upper/lower three adjacent modulesof a leg would short-circuit the upper/lower DC-link capacitor, respectively, whileturning on all four modules, would short-circuit the whole DC-link. Consequently,each leg can only be found at three different switching states, sx = 2, 1, or 0, illustratedin Figure 2.4. The phase voltage is equal to +VDC/2, vNP, and −VDC/2, respectively.Again, the conduction path changes according to the direction of the current but thephase voltage remains unaffected.

2.1.3 The CHB Converter

Unlike the 2L and 3L NPC, the CHB converter is not comprised of three legs con-nected to a common DC-link. Instead, it is based on three H-bridge cells (single-phase,3L converters), each having its own, isolated DC-link. As compared to the 2L andNPC, each cell of the CHB needs to have half the DC-link voltage for the converter tobe able to generate the same (fundamental) output voltage. This has been illustratedin Figure 2.5, by setting the cells’ DC-link voltages to VDC/2 in place of VDC. As forthe case of the NPC converter, the module switching voltage is therefore VDC/2. Thethree cells are connected at a common neutral, n.

Each cell can have four different switching states, resulting from turning on two ofthe cell modules that do not belong to the same leg. Figure 2.6 illustrates the allowed


ix ≥ 0

ix ≥ 0

ix ≥ 0

ON

ON

ON

ON

ON

ON

ix < 0

ix < 0

ix < 0

VDC

NP

C2

C1

x

2

VDC

2 V1x

V2x

V3x

V4x

D6x

D5x

vx =VDC

2+

+

−

+

−

+

−

sx = 2 (g1x = g2x = 1, g3x = g4x = 0)

VDC

NP

C2

C1

x

2

VDC

2 V1x

V2x

V3x

V4x

vx = vNP

sx = 1 (g1x = 0, g2x = g3x = 1, g4x = 0)

VDC

NP

C2

C1

x

2

VDC

2 V1x

V2x

V3x

V4x

D6x

D5x

vx =

sx = 0 (g1x = g2x = 0, g3x = g4x = 1)

VDC

2−

Figure 2.4 Switching states and conduction paths for a leg of the NPC converter

switching states, together with the respective conduction paths. As for the NPC con-verter, states 2 and 0 produce a phase voltage of +VDC/2 and −VDC/2, respectively.Both of the remaining states, 1a and 1b, produce a phase voltage of zero, since theyconnect the cell output (x) to the neutral (n).

2.2 Pulse Width Modulation Strategies

Pulse width modulation (PWM) generates pulsed voltage waveforms whose average(over a switching cycle) is equal to the desired reference signals. Depending on theway they are implemented, PWM strategies can be categorized as carrier-based orspace-vector modulation (SVM) strategies.


Ca

an

ia

V1a V3a

V2a V4a

Cb

bn

ib

V1b V3b

V2b V4b

Cc

cn

ic

V1c V3c

V2c V4c

VDC

2

VDC

2

VDC

2

vn = 0

Figure 2.5 CHB converter topology

2.2.1 Carrier-Based Strategies

Carrier-based strategies utilize a set of reference and carrier waveforms to generate theconverter PWM voltages. Three reference waveforms, one for each converter leg, areused in three-phase converters. A reference waveform provides the desired value ofoutput voltage for the respective phase, normalized with respect to VDC/2. For the caseof sinusoidal pulse width modulation (SPWM), the reference waveforms for phasesa, b, and c, are respectively given by the following equations:

va,ref = M cos(𝜃) (2.1)

vb,ref = M cos(𝜃 − 2π

3

)(2.2)

vc,ref = M cos(𝜃 + 2π

3

)(2.3)

where M is the converter modulation index and 𝜃 is the reference angle.Figure 2.7 illustrates the carrier, reference, and PWM voltage waveforms for phase a,

for a 2L converter modulated using SPWM and unity modulation index. The reference


Cx

x

n

V3x

V2x

VDC

2

ix < 0

ix ≥ 0vx = +

VDC

2

Cx

x

n

V1x

V2x V4x

VDC

2

ix < 0

ix ≥ 0vx = 0

sx = 1a (g1x = g3x = 1, g2x = g4x = 0)

sx = 0 (g2x = g3x = 1, g1x = g4x = 0)

sx = 1b (g2x = g4x = 1, g1x = g3x = 0)

ON ON

ON

Cx

x

n

V1x V3x

VDC

2

ix < 0

ix ≥ 0vx = 0

ON

Cx

x

n

V4x

VDC

2

ix < 0

ix ≥ 0vx = −

VDC

2

ON

ON

ON

ON

V1x

V4x

V3x

V2x V4x

V1x V3x

V2x

sx = 2 (g1x = g4x = 1, g2x = g3x = 0)

Figure 2.6 Switching states and conduction paths for a leg (H-bridge) of the CHB converter

waveforms in a 2L converter are compared with a single, common carrier waveformto determine the width of the generated pulses. The carrier waveform is commonlytriangular. Its peak values are +1 and −1, and its frequency is equal to the switchingfrequency of the converter.

While the value of a reference is higher than that of the carrier waveform, the state,sx, of the respective phase is set to 1, and the phase voltage becomes equal to +VDC/2;otherwise, sx is set to 0 and the phase voltage becomes −VDC/2. The resulting PWMwaveform for phase x has a duty cycle of

𝛿x =1

2(1 + vx,ref) (2.4)


0

0.5

0

Ref

eren

ce/c

arri

er

(a)

(b)

(c)

Ph

ase

vo

ltag

e, v

a (V

)L

ine

vo

ltag

e, v

ab (

V)

−0.5

−1

150

100

50

−100

−50

0

−150

300

200

100

−200

−100

0

−3000 0.005 0.01 0.015 0.02

Time (s)

0.025 0.03 0.035 0.04

Figure 2.7 (a) Reference and carrier waveforms for phase a, (b) phase voltage va, and (c) line

voltage vab for a two-level converter, assuming VDC = 200 V, f= 50 Hz, and fs = 1 kHz

It can be shown that over a period of the carrier, Ts, the area of this waveform,normalized with respect to (w.r.t.) VDC/2, is the same as the area of vx,ref. This ensuresthat the fundamental harmonic component of the PWM waveform is the same as thatof the reference waveform. Filtering of the higher-order harmonics turns the PWMinto the desired sinusoidal voltage waveform.

The carrier-based SPWM strategy for 3L converters uses the three reference wave-forms described by Equations 2.1–2.3, and two carrier waveforms, arranged as shownin Figure 2.8. The carrier waveforms are in phase for the so-called phase disposition(PD) PWM strategies, improving the PWM voltage harmonic spectra [1]. The state ofeach leg or cell of a 3L NPC or CHB converter, respectively, is determined as follows:

• If vx,ref is greater than the upper carrier, sx is set to 2.


• If vx,ref is between the upper and the lower carrier, sx is set to 1.• If vx,ref is lower than the lower carrier, sx is set to 0.

Moreover, in the CHB converter, in order to balance the use of states 1a and 1b,the upper and lower carrier can be used to switch the first (V1x −V2x) and second(V3x −V4x) leg of each cell, respectively (similarly to a 2L converter).

The pulsed phase voltages in 3L converters vary between +VDC/2 and 0 during thepositive reference half cycle, and between 0 and −VDC/2 during the negative one.The duty cycle of the voltage pulses for phase x is now given by

𝛿x = vx,ref (2.5)

Again, it can be shown that the fundamental harmonic of a PWM phase voltage isthe same as that of the respective reference. Furthermore, the generated 3L waveformsrequire less filtering than those of the 2L inverter.

0

0.5

0

Ref

eren

ce/c

arri

er

(a)

(b)

(c)

Ph

ase

vo

ltag

e, v

a (V

)L

ine

vo

ltag

e, v

ab (

V)

−0.5

−1

150

100

50

−100

−50

0

−150

300

200

100

−200

−100

0

−3000 0.005 0.01 0.015 0.02

Time (s)

0.025 0.03 0.035 0.04

Figure 2.8 (a) Reference and carrier waveforms for phase a, (b) phase voltage va, and (c) line

voltage vab for a three-level converter, assuming VDC= 200 V, f= 50 Hz, and fs = 1 kHz


For both 2L and 3L converters, the sinusoidal phase references of the SPWMstrategy result in sinusoidal line voltages, which are supplied to the converter load.Sinusoidal line voltages, however, can also be generated by non-sinusoidal phasereferences if the latter are modified by a common-mode component, cm:

va,ref = M cos(𝜃) + cm (2.6)

vb,ref = M cos(𝜃 − 2π

3

)+ cm (2.7)

vc,ref = M cos(𝜃 + 2π

3

)+ cm (2.8)

The line voltages are accordingly given by:

vab,ref = va,ref − vb,ref = M[cos (𝜃) − cos

(𝜃 − 2π

3

)]=

√3M cos

(𝜃 + π

6

)(2.9)

vbc,ref = vb,ref−vc,ref = M[cos

(𝜃− 2π

3

)−cos

(𝜃+ 2π

3

)]=

√3M cos

(𝜃− 2π

3+π

6

)(2.10)

vca,ref = vc,ref − va,ref = M[cos

(𝜃 + 2π

3

)− cos(𝜃)

]=

√3M cos

(𝜃 + 2π

3+ π

6

)(2.11)

It can be seen that the line voltages are not affected by the insertion of acommon-mode voltage component. The amplitude of the line voltages, however,

(which is equal to√

3M) can be increased by using a common-mode voltage thatallows an increase in the maximum value of M. Namely, the maximum value of M forthe case of SPWM is 1, since higher values lead to over-modulation and introducelow-frequency voltage distortion. An appropriate common-mode signal, on the otherhand, can be added to the reference voltages to keep them in the range of ±1 while Mincreases beyond 1. It can be shown that the maximum value that M can take in thisway is

Mmax = 2√3≈ 1.1547 (2.12)

which leads to a respective maximum line voltage of 2VDC peak-peak.A typical common-mode waveform used for the above purpose is described by

cm3h = −1

6cos(3𝜃) (2.13)

corresponding to a method known as “third harmonic injection” (SPWM+ third har-monic). The waveform of va,ref and the PWM voltages are shown in Figure 2.9 for thisstrategy, at unity modulation index. It can be seen from Figure 2.9a that the modulationindex can now increase further, without leading to over-modulation of the converter.


2.2.2 SVM Strategies

SVM differs from carrier-based implementations of modulation strategies, since theformer (i) is based on numerical calculations instead of waveform intersections and(ii) works directly with line voltages. Starting with the 2L converter, the two statesavailable for each leg lead to the functional diagram shown in Figure 2.10 for theentire three-phase converter.

The converter can therefore have 23 = 8 switching states. Each converter stateis represented by a space vector on the complex plane, given by the followingtransformation:

V = 2√3

(sa + sbej

2π3 + sce−j

2π3

)(2.14)

0

0.5

0

Ref

eren

ce/c

arri

er

(a)

(b)

(c)

Ph

ase

vo

ltag

e, v

a (V

)L

ine

vo

ltag

e, v

ab (

V)

−0.5

−1

150

100

50

−100

−50

0

−150

300

200

100

−200

−100

0

−3000 0.005 0.01 0.015 0.02

Time (s)

0.025 0.03 0.035 0.04

Figure 2.9 (a) Reference and carrier waveforms for phase a, (b) phase voltage va, and

(c) line voltage vab for a three-level converter modulated by SPWM+ third harmonic, assuming

VDC = 200 V, f= 50 Hz, and fs = 1 kHz


VDC

2

1

0

Saa

C

1

0

Sbb 1

0

Scc

+

VDC

2−

Figure 2.10 Functional diagram of the two-level converter

Table 2.1 Space vectors and line voltages for the

two-level converter states

State (sasbsc) Space vector Line voltages (vab, vbc, vca)

000 0 0, 0, 0

100 2∕√

3 ⋅ ej0 VDC, 0, −VDC

110 2∕√

3 ⋅ ej𝜋∕3 0, VDC, −VDC

010 2∕√

3 ⋅ ej2π∕3 −VDC, VDC, 0

011 2∕√

3 ⋅ ej𝜋 −VDC, 0, VDC

001 2∕√

3 ⋅ ej4π∕3 0, −VDC, VDC

101 2∕√

3 ⋅ ej5π∕3 VDC, −VDC, 0

111 0 0, 0, 0

Im

110

m = 1

100

VREF = me jθ

2 Re

√3

θ111000011

010

101001

Figure 2.11 Space vector diagram for the two-level converter


Table 2.1 lists the space vectors corresponding to the different states and relates themto the converter line voltages, while Figure 2.11 illustrates the space vectors on thecomplex plane.

PWM in SVM strategies is realized by activating a number of space vectors, V1,V2, … , Vn, according to respective duty cycles d1, d2, … , dn, to create a voltagereference vector, VREF:

VREF = d1V1 + d2V2 + … + dnVn

with d1 + d2 + … + dn = 1 (2.15)

a

sa 2

0

1

NP

VDC

2+

−

C2

b

sb 2

0

1

c

sc 2

0

1

VDC

2

C1

Figure 2.12 Functional diagram of the NPC converter

120 220

Im

Re

020

102 202002

021

022

200θ

100211

010121

221110

122011

001112

212101

210

m = 1

012 201

2

√3

222

111

000

VREF

Figure 2.13 Space vector diagram for three-level converters


The reference vector represents the three converter line voltages on the SV planeand is defined as follows:

VREF = 1√3

(va,ref + vb,refe

j2π3 + vc,refe

−j2π3

)(2.16)

Assuming that the voltage references are given by Equations 2.6–2.8, VREF can beshown to be equal to

VREF =√

3

2M ⋅ ej𝜃 = m ⋅ ej𝜃 (2.17)

where m will be the symbol for the modulation index for SVM strategies. As shownin Figure 2.11, m is equal to 1 at the limit of the linear (not over-) modulation region,and relates to M as determined by

m =√

3

2M (2.18)

1

2/sqrt(3)

1/6

0

12:34 t

M

refA

Pulses_2L

Carrier-based PWM

thirdH

[v_a]

[v_C]

[v_ab]

[i_abc]

[i_C]

[v_a]

[v_ab]

[i_abc]

A

B

C

A

B

C

v+−

v

g

Two-level inv.

Scope

A

B

C

Mag

Phase

90

Fourier

+−

+−

+ i−

+ i

Mean(discrete)

C

1

−

+ i−

+−

+

i−

[i_C]

[v_C]

DC-link cap VoltageLdc

DC-link cap Current

170

182.8

I_rms

<-

I_mag

phi (deg)

258.5

−29.18

I_dc

RMS(discrete)

1

93.44

I_rms_C

Discrete,Ts = 5.144e−006 s.

Figure 2.14 Simulink model for the two-level converter


SVM strategies can operate with m= 1, or equivalently M=Mmax – seeEquation 2.12 – generating the maximum possible amplitude of line voltage.

Figure 2.12 illustrates the functional diagram of a 3L NPC converter. This convertercan be found at 33 = 27 switching states. The respective space vectors are now derivedby

V = 1√3

(sa + sbej

2π3 + sce−j

2π3

)(2.19)

and are shown in Figure 2.13. The SV diagram is the same for the 3L CHB converter.It can be noticed that there are pairs of small vectors (e.g., 100-211) and a triplet ofzero vectors (000-111-222) that share the same position on the SV plane. The sameis true for the two zero vectors at the middle of the SV diagram for the 2L converter(Figure 2.11). This property of the SV diagrams is essential for creating different SVmodulation strategies, since vectors with the same position on the SV plane can beused alternatively to create the reference vector according to Equation 2.15. The vector

1

2/sqrt(3)

1/6

0

12:34 t

M

refA

Pulses_NPC

Carrier-based PWM

thirdH

[v_a]

[v_C1]

[v_C2]

[i_abc]

[i_ab]

[i_C1]

Scope

+ i

Mean(discrete)

C1

C2

−

Ldc I_dc

171.8

RMS(discrete)

I_rms_C2

94.04

RMS(discrete)

I_rms_C1

94.04

+ i−

[v_a]

[i_C1]

[i_C2]2

DC-link cap Currents

DC-link cap Voltages

+

+

[v_C1]

[v_C2]

[v_ab]

[i_NP]

[i_abc]

A

B

C

A

B

C

v+−

v

g

A

NB

C

Mag

Phase

90

Fourier

+−

+−

+ i−

+ i−

+−

+

i−

184

I_rms

I_mag

phi (deg)

260.2

−28.51


2

<-

Figure 2.15 Simulink model for the NPC converter


selection, on the other hand, determines the common-mode voltage of the converter,correlating SVM to carrier-based strategies, as described in [2–5].

2.3 Modeling

MATLAB®-Simulink SimPowerSystems toolbox is a powerful power electronic sim-ulation tool. It is, however, easier to use Embedded MATLAB® functions to imple-ment (code) modulation strategies. Figures 2.14–2.16 illustrate top level models ofthe 2L, and 3L NPC and CHB converters. In the models are shown:

• The converters and their (carrier-based) modulation functions, which provide thegating signals to the converter modules.

• Manual controls for adjusting the converter modulation index and switchingbetween SPWM and SPWM+ third harmonic.

• The converter load and measurements associated with it.

Additional Simulink models and MATLAB® code are included in Appendix A.

1

2/sqrt(3)1/6

0

12:34 t

M

refA

Pulses_phA

Pulses_phB

Pulses_phC

Carrier-based PWM

thirdH

[v_a]

[v_C1]

[i_abc]

[v_ab]

[i_C1]

Scope

g

A

B−

+

g

A

B−

+

g

A

B−

+

[v_a]

[v_ab]

[i_abc]

A

B

C

A

B

C

v+−

v

Mag

Phase

90

Fourier

+−

+−

+ i−

+ i−

+ i−

183.2

I_rms

I_mag

phi (deg)

259

−27.78


[PWM_a]

[PWM_b]

[PWM_c]

RMS(discrete)

I_rms_C1

119.1

Mean(discrete)

I_dc

106.3

[i_C1]

[i_C3]3

[v_C1]

[v_C3]3

DC-link cap Currents

DC-link cap Voltages

+

+

+

HB Phase a

HB Phase b

HB Phase c

[PWM_a]

[PWM_b]

[PWM_c]

+ i

C1

−

Ldc1

+ i

C2

−

+ i

C3

−

<-

Figure 2.16 Simulink model for the CHB converter


References

1. Holmes, D.G. and Lipo, T.A. (2003) Pulse Width Modulation for Power Converters, IEEE

Press, Piscataway, NJ.

2. Wang, C. and Li, Y. (2010) Analysis and calculation of zero-sequence voltage consider-

ing neutral-point potential balancing in three-level NPC converters. IEEE Transactions onIndustrial Electronics, 57 (7), 2262–2271.

3. Da-peng, C., Wen-xiang, S., Hui, X.I. et al. (2009) Research on zero-sequence signal of

space vector modulation for three-level neutral-point-clamped inverter based on vector dia-

gram partition. IEEE 6th International Power Electronics and Motion Control Conference.

4. Nho, N.V. and Youn, M.-J. (2006) Comprehensive study on space-vector-PWM and

carrier-based-PWM correlation in multilevel invertors. IEEE Proceedings on ElectricPower Applications, 153 (1), 149–158.

5. Pou, J., Zaragoza, J., Ceballos, S. et al. (2012) A carrier-based PWM strategy with

zero-sequence voltage injection for a three-level neutral-point-clamped converter. IEEETransactions on Power Electronics, 27 (2), 642–651.

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