Power Analysis2
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Transcript of Power Analysis2
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Lecture37&38 Power Analysis
Jagannadha Naidu K
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Outline
Power and Energy
Dynamic Power Static Power
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Power and Energy Power is drawn from a voltage source
attached to the VDD
pin(s) of a chip.
Instantaneous Power:
Energy:
Average Power:
( ) ( ) ( )P t I t V t =
0
( )
T
E P t dt=
avg
0
1( )
TEP P t dt
T T= =
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Power in Circuit Elements
( ) ( )VDD DD DDP t I t V =
( ) ( )
( )
2
2R
R R
V t
P t I t RR= =
( ) ( ) ( )
( )
0 0
212
0
C
C
V
C
dVE I t V t dt C V t dt
dt
C V t dV CV
= =
= =
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Charging a Capacitor
When the gate output rises Energy stored in capacitor is
But energy drawn from the supply is
Half the energy from VDD is dissipated in the pMOS transistoras heat, other half stored in capacitor
When the gate output falls Energy in capacitor is dumped to GND
Dissipated as heat in the nMOS transistor
212C L DD
E C V=
( )0 0
2
0
DD
VDD DD L DD
V
L DD L DD
dVE I t V dt C V dt
dt
C V dV C V
= =
= =
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Switching Waveforms
Example: VDD = 1.0 V, CL = 150 fF, f = 1 GHz
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Switching Power
[ ]
switching
0
0
sw
2
sw
1
( )
( )
T
DD DD
T
DDDD
DDDD
DD
P i t V dt T
Vi t dt
TV
Tf CV T
CV f
=
=
=
=
C
fswiDD(t)
VDD
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Activity Factor
Suppose the system clock frequency = f
Let fsw = f, where = activity factor If the signal is a clock, = 1
If the signal switches once per cycle, =
Dynamic power:
2
switching DDP CV f =
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Short Circuit Current
When transistors switch, both nMOS and
pMOS networks may be momentarily ON atonce
Leads to a blip of short circuit current.
< 10% of dynamic power if rise/fall times arecomparable for input and output
We will generally ignore this component
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Power Dissipation Sources
Ptotal = Pdynamic + Pstatic Dynamic power: Pdynamic = Pswitching + Pshortcircuit
Switching load capacitances
Short-circuit current
Static power: Pstatic = (Isub + Igate + Ijunct + Icontention)VDD Subthreshold leakage Gate leakage
Junction leakage
Contention current
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Dynamic Power Example 1 billion transistor chip
50M logic transistors
Average width: 12 Activity factor = 0.1
950M memory transistors Average width: 4
Activity factor = 0.02 1.0 V 65 nm process C = 1 fF/m (gate) + 0.8 fF/m (diffusion)
Estimate dynamic power consumption @ 1 GHz.
Neglect wire capacitance and short-circuit current.
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Solution
( )( ) ( ) ( )
( )( ) ( ) ( )
( ) ( )
6
logic
6mem
2
dynamic logic mem
50 10 12 0.025 / 1.8 / 27 nF
950 10 4 0.025 / 1.8 / 171 nF
0.1 0.02 1.0 1.0 GHz 6.1 W
C m fF m
C m fF m
P C C
= =
= =
= + =
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Dynamic Power Reduction
Try to minimize: Activity factor
Capacitance
Supply voltage
Frequency
2
switching DDP CV f =
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Clock Gating
The best way to reduce the activity is to turnoff the clock to registers in unused blocks Saves clock activity ( = 1) Eliminates all switching activity in the block
Requires determining if block will be used
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Capacitance
Gate capacitance Fewer stages of logic
Small gate sizes
Wire capacitance
Good floorplanning to keep communicating blocksclose to each other
Drive long wires with inverters or buffers ratherthan complex gates
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Static Power
Static power is consumed even when chip is
quiescent. Leakage draws power from nominally OFF
devices
Ratioed circuits burn power in fight between ONtransistors
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Static Power Example
Revisit power estimation for 1 billion
transistor chip Estimate static power consumption
Subthreshold leakage Normal Vt: 100 nA/m High Vt: 10 nA/m High Vt used in all memories and in 95% of logic gates
Gate leakage 5 nA/m Junction leakage negligible
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Solution
( )( ) ( ) ( )
( )( ) ( ) ( )( ) ( )
( )
t
t
t t
t t
6 6
normal-V
6 6 6
high-V
normal-V high-V
normal-V high-V
50 10 12 0.025 m / 0.05 0.75 10 m
50 10 12 0.95 950 10 4 0.025 m / 109.25 10 m
100 nA/ m+ 10 nA/ m / 2 584 mA
5 nA/ m / 2
sub
gate
W
W
I W W
I W W
= =
= + =
= =
= + =
( ) ( )
275 mA
P 584 mA 275 mA 1.0 V 859 mWstatic= + =
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Subthreshold Leakage
For Vds > 50 mV
Ioff= leakage at Vgs = 0, Vds = VDD
( )
10gs ds DD sbV V V k V
Ssub off
I I+
Typical values in 65 nmIoff= 100 nA/m @ Vt = 0.3 VIoff= 10 nA/m @ Vt = 0.4 VIoff= 1 nA/m @ Vt = 0.5 V = 0.1k = 0.1
S = 100 mV/decade
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Leakage Control
Leakage and delay trade off Aim for low leakage in sleep and low delay in
active mode To reduce leakage:
Increase Vt: multiple Vt Use low Vt only in critical circuits
Increase Vs: stack effect Input vector control in sleep
Decrease Vb Reverse body bias in sleep Or forward body bias in active mode
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Gate Leakage
Extremely strong function of tox and Vgs Negligible for older processes Approaches subthreshold leakage at 65 nm and below in
some processes
An order of magnitude less for pMOS than nMOS
Control leakage in the process using tox > 10.5 High-k gate dielectrics help
Some processes provide multiple tox e.g. thicker oxide for 3.3 V I/O transistors
Control leakage in circuits by limiting VDD
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Junction Leakage
From reverse-biased p-n junctions
Between diffusion and substrate or well Ordinary diode leakage is negligible
Band-to-band tunneling (BTBT) can be significant
Especially in high-Vt transistors where other leakage issmall
Worst at Vdb = VDD
Gate-induced drain leakage (GIDL) exacerbates Worst for Vgd = -VDD (or more negative)