pol_dft

LedaDFT Rules GuideVersion J-2014.12December 2014

Comments?E-mail your comments about this manual to [email protected].

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3Contents

Contents

Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7About This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

How Rules Are Organized . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Manual Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Typographical and Symbol Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Getting Leda Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9The Synopsys Web Site . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Chapter 1DFT Coding Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Using the DFT Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Limitations of DFT Policy with Respect to RTL DRC . . . . . . . . . . . . . . . . . . . 13Data Capture Ruleset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

DFT_003 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Message: Avoid using both positive-edge and negative-edge triggered flip-flops in your design

TEST_972 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Message: Clock affects both clock and data inputs of flipflops

TEST_973 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Message: Clock affects both clock and data inputs of latches

TEST_974 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Message: Latch enabled by a clock feeds latches enabled by the same clock

TEST_975 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Message: Latch enabled by a clock affects data input of flipflops clocked by the trailing edge of the same clock

TEST_978 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Message: Latch data gates clocks of flipflops. Combination of latch data and clock signal to clock a flipflop is not allowed

TEST_979 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Message: Latch data gates clocks enabling latches. Combination of latch data and clock signal to clock a latch is not allowed

TEST_980 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Message: Flipflop data gates clocks to flipflops. Combination of flipflop data and clock signal to clock a flipflop is not allowed

4Contents

TEST_981 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Message: Flipflop data gates clocks enabling latches. Combination of flipflop data and clock signal to clock a latch is not allowed

TEST_994 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Message: Clock affects multiple clock or async ports of register

Fault Coverage Ruleset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30DFT_006 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Message: Multiple clocks in the unitDFT_008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Message: Tri-state is detectedDFT_009 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Message: Register all outputs from the block for improved coverage: %sTEST_960 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Message: Avoid asynchronous feedback loopsTEST_970 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Message: Clock affects data inputs of flipflopsTEST_971 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Message: Clock affects data inputs of latchesTEST_976 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Message: Latches capture only when more than one clock is onTEST_977 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Message: Flipflops capture only when more than one clock is onInformational Ruleset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

DFT_017 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Message: Synchronous reset/set/load detected

DFT_019 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Message: Asynchronous reset/set/load detected

DFT_021 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Message: Latch inferred

DFT_022 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Message: Incomplete case statement

Scan Insertion Ruleset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46DFT_002 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Message: Internally generated clock detectedTEST_953 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Message: Flipflops with clocks tied to a signal that is not driven by Test Clock. Flipflops' clock signal is not reached by any Test Clock

TEST_954 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Message: Latches with clocks tied to a signal that is not driven by Test Clock. Latch clock signal is not reached by any Test Clock

TEST_963 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Message: Flipflops have clocks with no off-state controllability. Test Clock reaches flipflops but does not control them at beginning of cycle

5Contents

TEST_964 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Message: Latches have clocks with no off-state controllability. Test Clock reaches latches but does not control them at beginning of cycle

TEST_965 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Message: Latches not holding data in off-state. Test Clock reaches latch but does not hold data in them at beginning of cycle

TEST_966 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Message: Flipflops have no asynch controllability. No Test Asynch reaches flipflop's async control pin

TEST_967 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Message: Latches have no asynch controllability. No Test Asynch reaches latches async control pin

TEST_968 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Message: Flipflops have asynchs that cannot be disabled. Test Asynch reaches flipflops but cannot disable their asynch controls

TEST_969 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Message: Latches have asynchs that cannot be disabled. Test Asynch reaches latches but cannot disable their asynch controls

6Contents

7Preface

Preface

About This ManualThis book contains reference information for prepackaged rules that come with the Leda Checker tool. This information mirrors the information available in the HTML-based help files that you access directly from the Leda Checker tools Error Report. The purpose of this book is to provide a reference that you can view online or print out so that you can review available prepackaged rules and decide which ones you want to use before running the Checker tool on your HDL source files. On the other hand, the HTML-based help system is designed to provide random access to this same information from the Checker Error Report, so that you can quickly access more information about a specific rule that was violated, including in some cases, circuit diagrams and valid and invalid examples of Verilog or VHDL code.

This book is intended for use by hardware design and quality assurance engineers who are already familiar with VHDL or Verilog.

How Rules Are OrganizedRules are organized into major categories called policies, which have multiple rulesets. Each ruleset can contain multiple rules. You use the prepackaged rules to check your VHDL or Verilog source code for compliance with various standards and compatibility with downstream tools in the design and verification flow. Some rules apply just to Verilog or VHDL and some apply to both HDLs. The documentation for each rule, both in the HTML-based help system and in this manual clearly labels which languages each rule applies to.

NoteThere is a separate book for each policy (set of prepackaged rules) that Leda supports.

8Preface

Related DocumentsThis manual is part of the Leda document set. To see a complete listing or to navigate to another online document in the set, refer to the Leda Document Navigator.

Manual OverviewThis manual contains the following chapters and appendixes:

Typographical and Symbol ConventionsThe following conventions are used throughout this document:

Preface Describes the manual and lists the typographical conventions and symbols used in it; explains how to get technical assistance.

Chapter 1DFT Coding Rules

Detailed reference information for all rules in the Leda DFT coding rules policy.

Table 1: Documentation Conventions

Convention Description and Example

% Represents the UNIX prompt.

Bold User input (text entered by the user).% cd $LMC_HOME/hdl

Monospace System-generated text (prompts, messages, files, reports).No Mismatches: 66 Vectors processed: 66 Possible"

Italic or Italic Variables for which you supply a specific value. As a command line example:% setenv LMC_HOME prod_dir

In body text:In the previous example, prod_dir is the directory where your product must be installed.

| (Vertical rule) Choice among alternatives, as in the following syntax example:-effort_level low | medium | high

[ ] (Square brackets) Enclose optional parameters:pin1 [pin2 ... pinN]

In this example, you must enter at least one pin name (pin1), but others are optional ([pin2 pinN]).

9Preface

Getting Leda HelpFor help with Leda, send a detailed explanation of the problem, including contact information, to [email protected].

The Synopsys Web SiteGeneral information about Synopsys and its products is available at this URL:

http://www.synopsys.com

TopMenu > SubMenu Pulldown menu paths, such as:File > Save As

Table 1: Documentation Conventions (Continued)

Convention Description and Example

10

Preface

11

Chapter 1: DFT Coding Rules

1DFT Coding Rules

IntroductionThis chapter provides detailed reference information for the Design For Test (DFT) policy for the Leda Checker tool. This set of rules checks for test design rule violations within your RTL-level design. Most of the DFT rules have both flip-flop versions (check on flip-flop) and latch versions (check on latch). The DFT rules are used to check for design errors that can prevent scan insertion and data capture or reduce fault coverage.

NoteThere are more DFT rules in the DFT ruleset for the Design policy.

Most of the DFT rules are extracted from the set of rules used by the Synopsys RTL DRC tool. Therefore, each DFT rule label in the Leda Checker tool exactly matches the corresponding rule label prefixed with TEST in the RTL DRC tool. If you need more detailed information on these DFT rules, see the RTL DRC help. Run dc_shell, and at the prompt type:

% help TEST-rulenumber

For information about differences between the Leda DFT policy and the RTL DRC checker, see Using the DFT Policy on page 12.

The Leda DFT rules are grouped into the following rulesets, each of which impose constraints on different aspects of the applicable language:

Data Capture Ruleset on page 14

Fault Coverage Ruleset on page 30

Informational Ruleset on page 42

Scan Insertion Ruleset on page 46

12


Using the DFT PolicyBecause the Leda DFT rules are based on RTL DRC checks, you must enter some information about the test clocks when you use some rules of this policy. The Leda Checker prompts for information about test clocks when you select some DFT rules among TEST_953, TEST_954, TEST_966, TEST_967, TEST_970, TEST_971, TEST_972, TEST_973. In batch mode, you must use the following options described in Table 2.

NoteIn Leda, -test_clk_rising and -test_clk_falling are of the same functionality, and will be consolidated into one option -test_clk in the future. Also, -test_asynch and -test_asynch_inverted are the same functionality, and will be consolidated into one option -test_asynch in the future.

Table 2: Leda Batch DFT Options

Batch DFT Options Description

-test_asynch This is the same as set_signal_type test_asynch in the RTL DRC. This command specifies that the signal is active on 1 and has a hold value of 0 during the scan shift phase.

-test_asynch_inverted This is the same as set_signal_type test_asynch_inverted in the RTL DRC This command specifies that the signal is active on 0 and has a hold value of 1 during the scan shift phase.

-test_clk_falling This is the same as create_test_clk -w {N1 N1-N2} in the RTL DRC (where N1 and N2 are positive integers and N 1> N2). This command specifies the test clock signal and states that the first edge is the falling edge

-test_clk_rising This is the same as create_test_clk -w {N1 N1+N2} in the RTL DRC (where N1 and N2 are positive integers). This specifies the test clock signal and states that the first edge is the rising edge.

13


Limitations of DFT Policy with Respect to RTL DRCIn Leda's DFT checks, no delay is taken into account; it is always assumed that the test clock period is 100 ns and the strobe point occurs at 95 ns (default RTL DRC values). Leda also assumes that all test clock events occur before this strobe point.

The following RTL DRC commands (used to define the test protocol) are ignored by the Leda Checker tool, since no signal value propagation is performed.

set_test_hold

set_test_initial

set_test_assume

set_test_isolate The Checker tool also ignores the scan style. Leda only checks rules that are checkable using the LSSD (Level Sensitive Scan Design). This may lead to some differences between the Leda tests and the RTL DRC. In general, Ledas tests are more conservative.

14


Data Capture RulesetThe following rules are from the data capture ruleset:

DFT_003

Message: Avoid using both positive-edge and negative-edge triggered flip-flops in your design

For information on differences between Leda DFT checks and RTL DRC checks, see Using the DFT Policy on page 12.

Description This rule checks whether both rising and falling edge clocks exist within the design.

Policy DFT

Ruleset DATA_CAPTURE

Language VHDL/Verilog

Type Chip-level

Severity Warning

15


ExampleThe following example of invalid Verilog code exhibits this problem:

module DFT_003 (Clk, Reset, Din, Dout); input Clk, Reset, Din; output Dout; reg Dout, Dout_temp;

always @(posedge Clk) // Posedege clockbegin if (!Reset) Dout_temp

16


TEST_972

Message: Clock affects both clock and data inputs of flipflops


module TEST_972 (); reg D, CP , CD, Q; GTECH_FD2 U0 (.D(CP), .CP(CP), .CD(CD), .Q(Q)); // TEST_972 flags hereendmodule

Violations 3: GTECH_FD2 U0 (.D(CP), .CP(CP), .CD(CD), .Q(Q));

^

TEST_972.v:3: DATA_C> [ERROR] TEST_972: Clock affects both clock and data inputs of flipflops

Description This rule checks if a clock signal drives both the data input and the clock pin of a flip-flop.For this rule to work, you must specify a test clock. For more information, see Using the DFT Policy on page 12.

Policy DFT



Type Chip-level

Severity Error

17


The following circuit diagram illustrates the problem:


FFD Q

Clk

TEST-972

Ck

18


TEST_973

Message: Clock affects both clock and data inputs of latches


module TEST_973 (D, CP, CD, Q); input D, CP, CD; output reg Q; GTECH_LD3 U0 (.D(CP), .G(CP), .CD(CD), .Q(Q)); // TEST_973 flags hereendmodule

Violations 4: GTECH_LD3 U0 (.D(CP), .G(CP), .CD(CD), .Q(Q));

^

TEST_973.v:4: DATA_C> [ERROR] TEST_973: Clock affects both clock and data inputs of latches

Description This rule checks if a clock signal drives both the data input and the clock pin of a latch.For this rule to work, you must specify a test clock. For more information, see Using the DFT Policy on page 12.

Policy DFT



Type Chip-level

Severity Error

19




Latch

D Q

Clk

TEST-973

Ck

20


TEST_974

Message: Latch enabled by a clock feeds latches enabled by the same clock


module TEST_974 (D, CP, CD, Q); input D, CP, CD; output reg Q; reg Q_tmp; GTECH_LD3 U0 (.D(D), .G(CP), .CD(CD), .Q(Q_tmp)); GTECH_LD3 U1 (.D(Q_tmp), .G(CP), .CD(CD), .Q(Q)); // TEST_974 flags hereendmodule

Violations 6: GTECH_LD3 U1 (.D(Q_tmp), .G(CP), .CD(CD), .Q(Q));

^

TEST_974.v:6: DATA_C> [ERROR] TEST_974: Latch enabled by a clock feeds latches enabled by the same clock

Description The rule detects if a latch output enabled by a given clock affects the data input of latches using the same clock.

Policy DFT



Type Chip-level

Severity Error

21


ExampleThe following circuit diagram illustrates the problem:


Latch

D Q

Clk

TEST-974

CkLatch

D Q

Ck

22


TEST_975

Message: Latch enabled by a clock affects data input of flipflops clocked by the trailing edge of the same clock


module TEST_975 (D, CP, CD, Q); input D, CP, CD; output reg Q; reg Q_tmp; GTECH_LD3 U0 (.D(D), .G(CP), .CD(CD), .Q(Q_tmp)); always @ (negedge CP) Q

23




FFD Q

Clk

TEST-975

CkLatch

D Q

Ck

24


TEST_978

Message: Latch data gates clocks of flipflops. Combination of latch data and clock signal to clock a flipflop is not allowed



Description This rule detects if a signal used to clock a flip-flop is a combination of a latch output and a given clock where the latch and the flip-flop are within the same clock domain.

Policy DFT



Type Chip-level

Severity Error

FFD Q

Clk

TEST-978

CkLatch

D Q

Ck

25


TEST_979

Message: Latch data gates clocks enabling latches. Combination of latch data and clock signal to clock a latch is not allowed



Description This rule detects if a signal used to enable a latch is a combination of a latch output and a given clock, and the two latches are within the same clock domain.

Policy DFT



Type Chip-level

Severity Error

Latch

D Q

Clk

TEST-979

CkLatch

D Q

Ck

26


TEST_980

Message: Flipflop data gates clocks to flipflops. Combination of flipflop data and clock signal to clock a flipflop is not allowed



Description This rule detects if a signal used to clock a flip-flop is a combination of a flip-flop output and a given clock and the two flip-flops are within the same clock domain.

Policy DFT



Type Chip-level

Severity Error

FFD Q

Clk

TEST-980

Ck

FFD Q

Ck

27


TEST_981

Message: Flipflop data gates clocks enabling latches. Combination of flipflop data and clock signal to clock a latch is not allowed



Description This rule detects if a signal used to enable a latch is a combination of a flip-flop output and a given clock and the latch and flip-flop are within the same clock domain.

Policy DFT



Type Chip-level

Severity Error

Latch

D Q

Clk

TEST-981

Ck

FFD Q

Ck

28


TEST_994

Message: Clock affects multiple clock or async ports of register


module TEST_994 (D, CP, CD, Q); input D, CP, CD; output reg Q; GTECH_FD2 U0 (.D(D), .CP(CP), .CD(CP), .Q(Q)); // TEST_994 flags hereendmodule

Violations 4: GTECH_FD2 U0 (.D(D), .CP(CP), .CD(CP), .Q(Q));

^

TEST_994.v:4: DATA_C> [ERROR] TEST_994: Clock affects multiple clock or async ports of register

Description This rule detects if a clock feeds into a clock pin and a asynchronous control of a given register.

Policy DFT



Type Chip-level

Severity Error

29



FFD Q

Clk

TEST-994

Ck

30


Fault Coverage RulesetThe following rules are from the fault coverage ruleset. For information on differences between Leda DFT checks and RTL DRC checks, see Using the DFT Policy on page 12.

DFT_006

Message: Multiple clocks in the unit


Description None

Policy DFT

Ruleset FAULT_COVERAGE


Type Block-level

Severity Error

31



module DFT_006 (D, CP1, CP2, CD, Q1, Q2); input D, CP1, CP2, CD; output reg Q1, Q2; reg Q_tmp; wire CP_gate; always @ (posedge CP1 or negedge CD) if(CD) Q1

32


DFT_008

Message: Tri-state is detected



module DFT_008 (); wire tristate, En; assign tristate = En ? 0 : 1'bZ; // DFT_008 flags hereendmodule

Violations 3: assign tristate = En ? 0 : 1'bZ;

^

DFT_008.v:3: FAULT_> [ERROR] DFT_008: Tri-state is detected

Description None

Policy DFT



Type Block-level

Severity Error

33


DFT_009

Message: Register all outputs from the block for improved coverage: %s



module DFT_009 (din, dout);input din;output dout; // DFT_009 flags hereassign dout = din;endmodule

Violations 3: output dout;

^

DFT_009.v:3: FAULT_> [ERROR] DFT_009: Register all outputs from the block for improved coverage: DFT_009.dout

Description This rule only checks at the architecture/module level. There is a similar rule in the Leda general coding guidelines policy that you can use to check the entire design.This rule only works if you specify the top level of the design using the -top switch.%s is the name of hierarchical register.

Policy DFT



Type Chip-level

Severity Error

34


TEST_960

Message: Avoid asynchronous feedback loops


Description This rule checks for combinatorial asynchronous path loops.

Policy DFT



Type Chip-level

Severity Error

35



module TEST_960 ( CLK , RST , DATA_IN , AUX , DATA_OUT ); input CLK; input RST; input DATA_IN; input [2:0] AUX;

output DATA_OUT;

reg FF_DATA_IN; reg FF_DATA_OUT;

wire AND1 ,AND2; wire OR1;

always @(posedge CLK or negedge RST) if(!RST) FF_DATA_IN

36


TEST_970

Message: Clock affects data inputs of flipflops


module TEST_970 (D1, D2, CP1, CP2, CD1, CD2, Q1, Q2); input D1, D2, CP1, CP2, CD1, CD2; output reg Q1 , Q2;

GTECH_FD2 U0 (.CP(CP1), .D(D1), .CD(CD1), .Q(Q1)); GTECH_FD2 U1 (.CP(CP2), .D(CP1), .CD(CD2), .Q(Q2));// TEST_970 flags hereendmodule

Violations 6: GTECH_FD2 U1 (.CP(CP2), .D(CP1), .CD(CD2), .Q(Q2));

^

TEST_970.v:6: FAULT_> [ERROR] TEST_970: Clock affects data inputs of flipflops

Description This rule checks if a clock interacts with the data input of a flip-flop.For this rule to work, you must specify a test clock. For more information, see Using the DFT Policy on page 12.

Policy DFT



Type Chip-level

Severity Error

37




FFD QClk2

TEST-970

CkClk1

38


TEST_971

Message: Clock affects data inputs of latches


module TEST_971_fail (D1, D2, CP1, CP2, CD1, CD2, Q1, Q2); input D1, D2, CP1, CP2, CD1, CD2; output reg Q1 , Q2;

GTECH_LD3 U0 (.G(CP1), .D(D1), .CD(CD1), .Q(Q1)); GTECH_LD3 U1 (.G(CP2), .D(CP1), .CD(CD2), .Q(Q2)); // TEST_971 flags hereendmodule

Violations 6: GTECH_LD3 U1 (.G(CP2), .D(CP1), .CD(CD2), .Q(Q2));

^

TEST_971.v:6: FAULT_> [ERROR] TEST_971: Clock affects data inputs of latches

Description This rule checks if a clock interacts with the data input of a latch.For this rule to work, you must specify a test clock. For more information, see Using the DFT Policy on page 12.

Policy DFT



Type Chip-level

Severity Error

39




Latc

h

D QClk2

TEST-971

CkClk1

40


TEST_976

Message: Latches capture only when more than one clock is on



Description This rule checks if a latch can be used as a part of a scan chain. If so, a latch having multiple clocks to enable data must be able to capture data with one clock active and all others off.

Policy DFT



Type Chip-level

Severity Error

Latc

h

D Q

T E S T -9 7 6

C lk 1 C kC lk 2

L o g ic m u st b e a co m b in a tio n o f g a te sre sp ec tin g th e fo llo w in g ru le s :- C lo c k a n d d a ta a re A N D e d- T w o c lo c k s a re O R e d

41


TEST_977

Message: Flipflops capture only when more than one clock is on


Description This rule checks if a flip-flop can be used as a part of a scan chain. If so, a flip-flop having multiple clocks to clock data must be able to capture data with one clock active and all others off.

Policy DFT



Type Chip-level

Severity Error

FFD Q

TEST-977

Clk1 CkClk2

42


Informational RulesetThe following rules are from the informational ruleset:

DFT_017

Message: Synchronous reset/set/load detected



module DFT_017 (SyncRst, B, Clk, C); input SyncRst; input B; input Clk; output C; reg C; always @ (posedge Clk) begin if (SyncRst == 1) // DFT_017 flags here C [WARNING] DFT_017: Synchronous reset/set/load SyncRst detected

Description None

Policy DFT

Ruleset INFORMATIONAL


Type Block-level

Severity Warning

43


DFT_019

Message: Asynchronous reset/set/load detected


Description None.

Policy DFT



Type Block-level

Severity Note

44


DFT_021

Message: Latch inferred



module DFT_021 (B, Clk, C); input B; input Clk; output C; reg C; always @ (Clk) begin if (B) C

45


DFT_022

Message: Incomplete case statement


ExampleThe following examples show valid and invalid coding styles:

module DFT_022 (gate, q);input [1:0] gate;output q;reg q;

always @gate begin // DFT_022:Incomplete case statement case (gate) // DFT_022 flags here 2'b00: q = 1'b0; 2'b10: q = 1'b1; endcaseendendmodule

Violations 7: case (gate)

^^^^

DFT_022.v:7: INFORM> [ERROR] DFT_022: Incomplete case statement

Description This rule fires if all the alternatives of the case statement are not covered and if there is no default clause.

Policy DFT


Language Verilog

Type Block-level

Severity Error

46


Scan Insertion RulesetThe following rules are from the scan insertion ruleset:


DFT_002

Message: Internally generated clock detected



module DFT_002 (); reg Clk, Din, Dout; // DFT_002 flags here always @ (posedge Clk) Dout [ERROR] DFT_002: Internally generated clock detected

Description This rule verifies that all clocks are controllable from the top level of the design and not internally generated via a sequential block.Rationale: internally generated clocks may not be controllable from the boundary of the chip. This reduces test coverage.

Policy DFT

Ruleset SCAN_INSERTION


Type Chip-level

Severity Error

47


TEST_953

Message: Flipflops with clocks tied to a signal that is not driven by Test Clock. Flipflops' clock signal is not reached by any Test Clock


module TEST_953 (TstClk, Din, Dout); input TstClk; input Din; wire Clk; // Not driven by Test Clock output reg Dout; reg Dout1; always @ (posedge Clk) Dout

48




FFD Q

CP

Ck

Test_Ck

TEST-953

49


TEST_954

Message: Latches with clocks tied to a signal that is not driven by Test Clock. Latch clock signal is not reached by any Test Clock


module TEST_954 (TstClk, Din, Dout); input TstClk; input Din; wire Clk; // Not driven by Test Clock output reg Dout; reg Dout1;

GTECH_LD1 U0 (.D(Din), .G(Clk), .Q(Dout)); // TEST_954 flags here GTECH_LD1 U1 (.D(Din), .G(TstClk), .Q(Dout1));endmodule

Violations 8: GTECH_LD1 U0 (.D(Din), .G(Clk), .Q(Dout));

^

TEST_954.v:8: SCAN_I> [ERROR] TEST_954: Latches with clocks tied to a signal that is not driven by Test Clock. Latch clock signal is not reached by any Test Clock

Description This rule checks whether the latch clock is uncontrollable. That case occurs when the test clock does not reach any signal which drives the clock input pins of latches.For this rule to work, you must specify a test clock. For more information, see Using the DFT Policy on page 12.

Policy DFT



Type Chip-level

Severity Error

50




Latch

D Q

EN

Ck

Test_Ck

TEST-954

51


TEST_963

Message: Flipflops have clocks with no off-state controllability. Test Clock reaches flipflops but does not control them at beginning of cycle


module TEST_963 (TstClk, Din, Dout); input TstClk; input Din; wire Clk; output reg Dout; reg Dout1; assign Clk = TstClk | Dout; GTECH_FD1 U0 (.D(Din), .CP(Clk), .Q(Dout)); // TEST_963 flags here GTECH_FD1 U1 (.D(Din), .CP(TstClk), .Q(Dout1));endmodule

Violations

8: GTECH_FD1 U0 (.D(Din), .CP(Clk), .Q(Dout)); ^

TEST_963.v:8: SCAN_I> [ERROR] TEST_963: Flipflops have clocks with no off-state controllability. Test Clock reaches flipflops but does not control them at beginning of cycle

Description This rule detects if the test clock reaches flip-flops but the flip-flop clocks cannot change state as result of test clock toggling.

Policy DFT



Type Chip-level

Severity Error

52




FFD Q

CP

Test_Ck

TEST-963

FFD Q

53


TEST_964

Message: Latches have clocks with no off-state controllability. Test Clock reaches latches but does not control them at beginning of cycle


module TEST_964 (TstClk, Din, Dout); input TstClk; input Din; wire Clk; output reg Dout; reg Dout1; assign Clk = TstClk | Dout; GTECH_LD1 U0 (.D(Din), .G(Clk), .Q(Dout)); // TEST_964 flags here GTECH_LD1 U1 (.D(Din), .G(TstClk), .Q(Dout1));endmodule


^

TEST_964.v:8: SCAN_I> [ERROR] TEST_964: Latches have clocks with no off-state controllability. Test Clock reaches latches but does not control them at beginning of cycle

Description This rule detects if the test clock reaches latches but the latch clocks cannot change state as result of test clock toggling.

Policy DFT



Type Chip-level

Severity Error

54




Latch

D Q

EN

TEST-964

Test_Ck

FFD Q

55


TEST_965

Message: Latches not holding data in off-state. Test Clock reaches latch but does not hold data in them at beginning of cycle


module TEST_965 (TstClk, Din, Dout); input TstClk; input Din; wire Clk; output reg Dout; reg Dout1; assign Clk = ~TstClk; GTECH_LD1 U0 (.D(Din), .G(Clk), .Q(Dout)); // TEST_965 flags here GTECH_LD1 U1 (.D(Din), .G(TstClk), .Q(Dout1));endmodule


^

TEST_965.v:8: SCAN_I> [ERROR] TEST_965: Latches not holding data in off-state. Test Clock reaches latch but does not hold data at beginning of cycle

Description This rule detects if the test clock does not hold data at the beginning of the test clock cycle.

Policy DFT



Type Chip-level

Severity Error

56




Latch

D Q

EN

Test_Ck

TEST-965

Latch

D Q

EN

Test_Ck

TEST-965

57


TEST_966

Message: Flipflops have no asynch controllability. No Test Asynch reaches flipflop's async control pin



Description This rule checks whether the flip-flop asynchronous control signal is uncontrollable. That case occurs when the test asynch does not reach any signal which drives the asynchronous control input pins of flip-flops.For this rule to work, you must specify a test clock. For more information, see Using the DFT Policy on page 12.

Policy DFT



Type Chip-level

Severity Error

FFD Q

Rst

Test_Async

TEST-966

58


TEST_967

Message: Latches have no asynch controllability. No Test Asynch reaches latches async control pin


module TEST_967 (TstClk, Din, Dout, TstRst); input TstClk, TstRst; input Din; wire Clk; output reg Dout; reg Dout1; assign Clk = TstClk | Dout; GTECH_LD3 U0 (.D(Din), .CD(), .G(TstClk), .Q(Dout)); // TEST_967 flags here GTECH_LD3 U1 (.D(Din), .CD(TstRst), .G(TstClk), .Q(Dout1));endmodule

Violations 8: GTECH_LD3 U0 (.D(Din), .CD(), .G(TstClk), .Q(Dout));

^

TEST_967.v:8: SCAN_I> [ERROR] TEST_967: Latches have no asynch controllability. No Test Asynch reaches latches async control pin

Description This rule detects if the latch asynchronous control signal is uncontrollable. That case occurs when the test asynch does not reach any signal which drives the asynchronous control input pins of latches.For this rule to work, you must specify a test clock. For more information, see Using the DFT Policy on page 12.

Policy DFT



Type Chip-level

Severity Error

59




Latch

D Q

Rst

Test_Async

TEST-967

60


TEST_968

Message: Flipflops have asynchs that cannot be disabled. Test Asynch reaches flipflops but cannot disable their asynch controls


module TEST_968 (TstClk, Din, Dout, TstRst); input TstClk, TstRst; input Din; wire Clk; output reg Dout; reg Dout1; wire RstOred, Rst; assign RstOred = TstRst | Rst; GTECH_FD2 U0 (.D(Din), .CD(RstOred), .CP(TstClk), .Q(Dout));

// TEST_968 flags in the above line GTECH_FD2 U1 (.D(Din), .CD(TstRst), .CP(TstClk), .Q(Dout1));endmodule

Violations 9: GTECH_FD2 U0 (.D(Din), .CD(RstOred), .CP(TstClk), .Q(Dout));

^

TEST_968.v:9: SCAN_I> [ERROR] TEST_968: Flipflops have asynchs that cannot be disabled. Test Asynch reaches flipflops but cannot disable their asynch controls

Description This rule detects if the test asynch reaches flip-flops but cannot disable their async controls.

Policy DFT



Type Chip-level

Severity Error

61




FFD Q

Test_Async

TEST-968

Test_Async must disablethe asynchronous pin of theflipflop

62


TEST_969

Message: Latches have asynchs that cannot be disabled. Test Asynch reaches latches but cannot disable their asynch controls


module TEST_969 (TstClk, Din, Dout, TstRst); input TstClk, TstRst; input Din; wire Clk; output reg Dout; reg Dout1; wire RstOred, Rst; assign RstOred = TstRst | Rst; GTECH_LD3 U0 (.D(Din), .CD(RstOred), .G(TstClk), .Q(Dout));

// TEST_969 flags in the above line GTECH_LD3 U1 (.D(Din), .CD(TstRst), .G(TstClk), .Q(Dout1));endmodule

Violations 9: GTECH_LD3 U0 (.D(Din), .CD(RstOred), .G(TstClk), .Q(Dout));

^

TEST_969.v:9: SCAN_I> [ERROR] TEST_969: Latches have asynchs that cannot be disabled. Test Asynch reaches latches but cannot disable their asynch controls

Description This rule detects if the Test_async reaches latches but cannot disable their async controls.

Policy DFT



Type Chip-level

Severity Error

63




Latch

D Q

Test_Async

TEST-969

Test_Async must disablethe asynchronous pin of thelatch

64


Leda Document NavigatorContentsPrefaceAbout This ManualHow Rules Are OrganizedRelated DocumentsManual OverviewTypographical and Symbol Conventions

Getting Leda HelpThe Synopsys Web Site

1 DFT Coding RulesIntroductionUsing the DFT PolicyLimitations of DFT Policy with Respect to RTL DRC

Data Capture RulesetDFT_003TEST_972TEST_973TEST_974TEST_975TEST_978TEST_979TEST_980TEST_981TEST_994

Fault Coverage RulesetDFT_006DFT_008DFT_009TEST_960TEST_970TEST_971TEST_976TEST_977

Informational RulesetDFT_017DFT_019DFT_021DFT_022

Scan Insertion RulesetDFT_002TEST_953TEST_954TEST_963TEST_964TEST_965TEST_966TEST_967TEST_968TEST_969

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