PNP Current Mirror

8/3/2019 PNP Current Mirror

1/27

Unpublished work 2006 by John R Brews 1

PNP current mirror

Schematic

OUT

+

- {V_CC}20.089mA

PARAMETERS:

V_CC = 10V

R_E = 418.85833

R_R = 495.59372

V_SAT = 0.55V

5.7928V

5.0000V

-+

+-

E1

GAIN = 1

M

0

5.0000V

Sweep

+

-

AC

V_ac

1V

0

E

+{R_R}

10.089mA

.model Q_pVAF PNP (Bf={B_F} Is={I_S} Vaf={V_AF}Nf={N_F} Rb={r_X})

5.7928V+

{R_E}

10.044mA

Q_pVAF

Q_Ref

-44.455uA

-10.000mA

DOT-MODEL:

B_F = 224.9477

I_S = .6506fA

V_AF = 115.7V

N_F = 1.0089535

r_X = 10

+

- {V_A}

V_DC

E

+

{R_E}

10.044mA

INPUT SIGNAL

AMPLITUDE = 1V

V_A = 5

FREQUENCY = 1kHz

0

EM

-

+

Transient

Analysis

{AMPLITUDE}

{FREQUENCY}

V_SIN

792.80mV

10.000V

0

5.0000V

MQ_pVAF

Q_Out-44.455uA

-10.000mA5.0000V

Figure 1

Circuit for pnp current mirror using simple device with dot-model statement shown

Figure 1 shows a schematic for a pnp current mirror.1 The purpose of the mirror is to

emulate an ideal current source, that is, to provide the same DC current through the

output node regardless of the voltage applied, DC or transient.

How does it work?

The basic idea behind the circuit is that the left side draws a current through the

reference transistor setting up a corresponding emitter-base voltage. Because the circuit is

1 Also shown in Figure 1 is an evaluator circuit using PSPICE VCVS Part E just to display the value of VEM

on the schematic for easy comparison with the spreadsheet constructed in this chapter.


2/27


symmetric (assuming the output and reference transistors are alike) the same VEB appears

at the output transistor, so the same current flows there (it is mirrored), almost

independent of the voltage VA because VA hardly affects VEB.

Unfortunately, the mirror is not entirely successful, having these limitations:

1. It provides a nearly constant DC current only over a limited range of voltages. This

limitation arises at voltages VA > VM (VM = mid-base voltage), where the output

transistor QOut leaves active mode and goes into saturation.

2. Even in the range of voltages VA < VM where QOut is active, the current is not strictly

constant, but varies somewhat with VA. That is, the circuit resembles a Norton source

with a finite Norton resistance instead of an ideal current source. This limitation is

due to the finite output resistance of transistor QOut.

The above limitations are illustrated in Figure 2.

Figure 2

Circuit output behavior for Figure 1; at the compliance voltage VCV where output resistance beginsa rapid drop to low values, the output transistor is in saturation by VBC = VSAT

The top panel in Figure 2 shows the current-voltage I-Vbehavior of the mirror. Itdelivers a DC current of 10 mA for voltages below approximately 5.55V. The lower

panel shows the resistance of the mirror, determined as the inverse of the derivative of the

current by voltage. It shows that this resistance is high (934 k; at VA = 1 V), but not

quite constant, and drops suddenly just above VA = VM = 5 V. The drop-off voltage is

called the compliance voltage VCV of the mirror, and the voltage range where nearly

VSAT

VCV

Active Mode


3/27


constant DC current is delivered is the compliance range of the mirror. If we choose the

bias at 3 dB roll-off of resistance as the verge of the drop, we find the compliance voltage

is VCV = 5.346 V from Figure 2. At this bias, the output transistor is in saturation by an

amount VBC = VSAT = 0.346 V. At the point where the DC currenthas just begun to

drop (VA = 5.55 V) the output resistance of the mirror already is at a very low value of

only 9.34 k;, showing that the Norton resistance of the mirror is much more sensitive to

saturation of the output transistor than is the DC current itself.

Because the limitations of the mirror depend on the limitations of the transistor, we

need a transistor model that includes the Early voltage of the device. Otherwise, the

mirror would still have a voltage limitation, but would be an ideal current source as long

as QOut was active. Hence, we have the dot-model statement in Figure 1, discussed in

detail shortly.

Design goal

We want to design the circuit of Figure 1 to meet specifications on DC current level

IC at VA = VM (both transistors with VBC = 0 V), on compliance voltage VCV (taken as a

specification on VM because VM is unambiguous and differs from VCV by only the small

voltage VSAT discussed later2), and specifications on output resistance RN (Norton

resistance) of the mirror. The variables at our disposal are the leg resistor value RE andthe reference resistor value RR, so unless we are lucky only two of the three specifications

can be satisfied, and a trade-off will be necessary. For this purpose we will set up a

spreadsheet incorporating the hand analysis below.

AC and DC beta-values

For the dot-model statement of Figure 1, the small-signal ACF-value, which will be

called FAC, is the same as the DC F-value, which is called FDC. However, that is not so formore complex models, so we include this difference in the equations here. EQ. 1 defines

DC F:

2 The value of VSAT is expected to be somewhere around 0.5 V, but its value is unknown without a

simulation. It varies with the type of transistor and with the current and bias conditions.


4/27


EQ. 1

BI

CIDC!F ,

while AC F is defined by:

EQ. 2

CdI

DCd

DC

CI

DC

CdI

DCd

DC

CI

DC

DCCId

CdI

BdI

CdIAC F

F

F

F

FF

FF

!

!!!

12

1

1

/.

According to EQ. 2, FAC is different fromFDC ifFDC depends on IC. For the dot-model

statement of Figure 1 FDC does not depend on IC, but for real transistors it does. So, for

real transistors, FDC and FAC are the same only at the maximum in the FDC vs. IC curve.

An example is shown in Figure 3 below.

I _E

10nA 1. 0uA 100uA 10mA 1. 0A

I ( C) / I ( B) D( I ( C) ) / D( I ( B) )

0

100

200 AC Bet a

DC Be t a

( 1 0 . 0 0 mA, 2 2 4. 9 4 77 )

Figure 3

Comparison of AC and DC F-values as a function of emitter current IE for the Q2N2907A pnp-transistor with VBC = 0 V

Figure 3 shows the current dependence of the two Fs for the Q2N2907A transistorusing the PSPICE dot model statement for this transistor. It can be seen that the two Fs

agree at the maximum inFDC near an emitter current of IE = 10 mA. In addition,FAC >

FDC when FDC has positive derivative, as predicted by EQ. 2.

Figure 3 is generated using the circuit of Figure 4 with a DC SWEEP analysis to

sweep IE. Zero-bias DC voltage sources are inserted in the base and collector leads and

named B and C to indicate that the currents I(B) and I(C) going through them are the base

and collector currents.


5/27


+

-

C

DC = 0V

{I_E}

Q2N2907A

I

B

0

I

PARAMETERS:

I_E = 10m

C

+

-

B

DC = 0V

0

Figure 4

Test circuit for generating AC and DC F-plots of Figure 3

The Q_pVAF dot-model parameters

To allow later comparison with the Q2N2907A, the dot model statement of

Figure 1 is introduced, namely

.model Q_pVAF PNP (Bf={B_F} Is={I_S} Vaf={V_AF} Nf={N_F} Rb={r_X})

which can be compared with the dot-model statement for the Q2N2907A:

.model Q2N2907A PNP (Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829+ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715+ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75+ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10)* National pid=63 case=TO18* 88-09-09 bam creation

provided with PSPICE.

To improve agreement with more realistic dot-model statements like that for the

Q2N2907A, the Q_pVAF dot-model statement includes parameters for Early voltage Vaf,

non-ideal diode-law Nf, and internal series base resistance Rb. This dot-model statement

corresponds in active mode to the I-Vrelation

EQ. 3

-

!

AFV

BCiV

THV

EBiVSICI 11exp

L,

where VEBi, VBCi are the intrinsicemitter-base and base-collector voltages, differing from

the circuit orexternalvalues because of the internal base resistance rX, as discussed

shortly. The parameterL is the ideality factoror, as referred to in the PSPICE

documentation, the forwardcurrent emission coefficient, also discussed shortly.

Notice the intrinsic emitter-base voltage according to EQ. 3 is given by EQ. 4:


6/27


EQ. 4

!

AFV

BCiVSI

CInTHVEBiV

1

1NL

Lets take a closer look at the effects of these parameters.

Early voltage: parameter VAF

The Early voltage enters the current I-Vrelation as shown in EQ. 3. Somewhat less

obvious is the Early voltage influence on the transistorFs. The DC base current of the

transistor, IB, does not depend upon the base-collector voltage, so EQ. 5 gives the DC F

EQ. 5

!!

!

!!AFVBCV

BCVDCBI

AFV

BCVBCVCI

BICI

DC 10

1)0(

FF .

That is, the DC F increases with VBC because of the Early effect. The AC F does the same

thing if the current dependence ofFDC is contained inFDC(VBC=0). That is,

EQ. 6

!!!

AFV

BCVBCVACAC 10FF .

Base resistance: parameter Rb and the intrinsic base resistance rX

The introduction of the base resistance rX introduces some complications into ourequations because the device behavior is governed by the internalVEBi of the transistor,

which differs from the externalVEB of the circuit by the voltage drop across rX. See

Figure 5.

Figure 5

Internal and external voltages related to rX: VEBi < VEB because of drop across rX, while VBCi > VBC

Xr EBiV

EBV

CI

F/CI

BCV BCiV

F

XrCI


7/27


According to Figure 5, the internal and external emitter-base voltages are related as:

EQ. 7

XrDC

CIEBVEBiV

F! .

Combining EQ. 7 with EQ. 4 we find VEB is related to the current by

EQ. 8

XrDC

CI

AFV

BCiVSI

CInTHVEBVF

L

!

1

1N .

In addition to its effect on VEBi, the voltage drop across rX causes a non-zero

internalVBCi of the transistor, even though the external circuit VBC = 0 V. (Consider

Figure 5 for the case where VBC = 0 V.)

A non-zero VBCi means the Early effect comes into play, affecting the current andthe beta values of the transistor, so the transistor betas increase according to

EQ. 9

!!

AFV

BCiVVBCVBCiV 1)0()( FF .

The value of VBCi is given by Ohms law as EQ. 10:

EQ. 10

XrBCiV

CIBCiV )(F

! .

Solving the quadratic found by substituting EQ. 9 into EQ. 10, we find VBCi as shown inEQ. 11 next:

EQ. 11

-

!! 1

2/1

)0(

41

2 AFVBCVXrCIAFV

BCiVF

.

Parameter rX is set using dot-model parameter Rb, namely, rX = Rb.

Current dependence of small-signal parameters; parameterL

You may recall the current and voltage dependence of the transistor small-signalparameters for a simple bipolar exhibiting Early effect. In particular,

EQ. 12

)()0( BCVCIBCVAFV

BCVCI

AFVOr

!

!! ,

CI

THVAC

mg

ACrFF

T }! .


8/27


In EQ. 12, rO = output resistance, rT = base input resistance, gm = small-signal

transconductance, VAF = Early voltage and VTH = thermal voltage (kBT/q 25.864 mV @

27r C). EQ. 12 for rO does not agree with most textbooks, but it does agree with PSPICE

and transistor physics.

In real transistors the ideal diode law is not satisfied. To help match this reality, the

Q_pVAF dot-model statement includes parameter Nf.When this parameter is used, the

transconductance and base resistance are given by the relations:

EQ. 13

THV

CImg

L

1! ,

CI

THVAC

mg

ACrF

LF

T !! ,

where parameterL is the before-mentioned ideality factor also known as the forward

current emission coefficient.

ParameterLis specified by dot-model parameter Nf, namely L = Nf.

SettingL

How can Lbe found? Lets assume we want the value ofL that makes our

Q_pVAF-model fit the Q2N2907A. The same approach works for other models. Figure 5

puts the Q2N2907A and Q_pVAF in identical circuits. These circuits set the external VBC

= 0 V, which is the case for the mirror at the design point. Then we find the externalgm-

values by running a DC sweep of IE and taking derivatives, as shown in Figure 7. We setthe Nfvalue to make the two gm-values the same at the current level of interest, namely

10 mA in this case. We set

EQ. 14

)_(

)29072(

pVAFQmg

ANQmgfN ! = 0.3784089/0.3750509 =1.0089535.

The externalgm-values are related to the internalgm-values by EQ. 15 (using EQ. 7 for

VEBi):

EQ. 15

!

x

x

x

x!

x

x! mig

DC

Xrmig

EBV

EBiV

EBiV

CI

EBV

CIextmgF

1)( ,


9/27


where the internal transconductance gmi = IC/VEBi. EQ. 15 is interesting mainly because

it shows setting the external gm-values equal also makes the internal gm-values equal.3, 4

Q_pVAF

0

PARAMETERS:

I_E = 10mA

0

DOT-MODEL:

B_F = 224.9477

I_S = .6506fA

V_AF = 115.7V

N_F = 1

r_X = 10

{I_E} {I_E}

E_2907A

Q2N2907A

+

-

C_Nf

DC = 0

0

E_VAF 0

+

-

C_2907A

DC = 0

Figure 6

Test circuit for finding value of dot-model parameter Nf; notice that Nf= 1 in this test

I _E

0A 5mA 10mA 15mA 20mA

D( I ( C_Nf ) ) / D( V( E _VAF ) ) D( I ( C_2 907 A) ) / D( V ( E_ 2907 A) )

0

0. 5

1. 0

( Q_pVAF, 10. 0000m, 375. 0509m)

( Q2N2907A, 10. 0000m, 378. 4089m)

Figure 7

Comparison of external gm values when Nf= 1; we want to increase Nfto make these two values thesame

Finding Nf this way makes the simple transistor model Q_pVAF resemble closely

the more realistic model Q2N2907A, and in particular makes sure that the small-signalparameters gm and rT at the design point are the same.

Hand analysis

Q-point analysis

The design is done for the case VA = VM because that makes analysis simpler. If

instead we choose VA < VM, the two transistors have different VBC values and that affects

the currents andF-values because of the Early effect. For VA = VM, applying KVL to the

output side of the circuit of Figure 1, we find a relation for RE given by EQ. 16 below:

EQ. 16

3 Technically there are two values for gmi for each gm, and we want the value very close to gm.4 It is the internalgm-value that is given by EQ. 13 and is listed in the PROBE output file.


10/27


DCCIMVEBVCCV

ERF/11

! .

In EQ. 16 the various symbols are: IC = output (collector) current of QOut, VEB = emitter-

base voltage of QOut, VM = base voltage of both transistors, FDC = DC beta of QOut.

Applying KVL to the left side of the mirror we find RR is given by5EQ. 17

DCCIMV

RRF/21

!

Small-signal analysis

Next we ask just how much the current varies for voltages below the base voltage.

That is, what is the slope of the I-Vcurve for VA < VM. The easiest way to find out is to

bias the mirror at some value of VA below VM and superpose a small-signal AC voltage

Vac. Then the small-signal current Iac that flows is

EQ. 18

acVNR

acVAV

CIacI

1|

x

x! ,

where RN is the Norton resistance of the mirror, and indicates the rate of variation of the

current with applied voltage. The small-signal circuit corresponding to this approach is

shown in Figure 8 below.6 Test current Ix is applied and RN = Vx/Ix.

In Figure 8 the parasitic base resistance rX is included to allow a closer comparison

with the Q2N2907A later on. This resistance is included in Figure 1 by specifying the

dot-model parameter Rb, set in the dot-model PARAMETERbox to Rb = rX.

+

0

+

+

+

0

++

0

+

Figure 8

5 Use KCL at the base of QOut to derive the factor (1+2/FDC).6 The replacement of transistor QRefby the resistor rREF is explained in the Appendix.

xV

ER

ER

REFr

Tr

Or

RR

bIxI

bIACxI F

bI

xI

bIACF

Xr


11/27


Small-signal circuit corresponding to Figure 1

An easy way to solve circuits like this is to determine all the currents and then use

KVL. Taking KVL on the left side of the circuit noting that (rREF + RE) is in parallel with

RRand following Ib through rT and RE we find EQ. 19:

EQ. 19

? A 0// ! ERbIxIXrrRRERREFrbI T ,

which determines Ib in terms of Ix as

EQ. 20

RRERREFrXrrERER

xIbI //!

T.

Then KVL through the right side of the circuit provides

EQ. 21

ERbIxIOrbIACxIxV ! F ,

Collecting terms in Ix and Ib and substituting for Ib from EQ. 20 we find RN as EQ. 22next:

EQ. 22

RRERREFrXrrERrRRERREFr

ERRRERREFrXrrER

ERACOr

xI

xVNR //

//

//1

!!

T

T

TF

.

Notice that for large RE, the leading term in RN approaches (FAC+1) rO, while for

small RE it approaches rO. So RN is a large resistance, and increases with RE. The most

ideal current source from the viewpoint of voltage-independent current occurs at large

RE. Resistance RN has a complex dependence on the specifications for current value and

compliance voltage, and an easy way to see the connections is through graphs generated

using a spreadsheet. (For example, see Figure 19 and Figure 21 later on.)

Transient analysis

When a large-signal sinusoidal AC voltage of amplitude Vac is applied to the mirror

output with DC voltage VA applied, the instantaneous applied voltage is

EQ. 23

)2sin()( tfacVAVtA TY ! .

To avoid driving the output transistor into saturation, where its low resistance will cause

a large AC current spike, the DC bias must be chosen below the compliance voltage VCV

by at least the AC signal amplitude Vac, that is, we require

EQ. 24

acVCVVAV e .


12/27


Spreadsheet

The hand analysis is put into the spreadsheet as shown in Figure 9. The diode-

connected reference transistor resistance is denoted by r_REF, following the analysis in

the appendix. To avoid round-off error, a series expansion is used for V_BCi at smallvalues (an IF STATEMENT represents (1+x)1 by a series for argumentsx < 2 105).7

The numerical values corresponding to Figure 9 are shown in Figure 10.

In Figure 10 the values for the transistor parameters are selected to represent the

QN2907A pnp bipolar transistor parameters included with PSPICE. The values forFDC0

andFAC0 are determined as shown in Figure 3 for the specified current level of

IC = 10 mA at VBC = 0V.

The Norton resistance is found using the AC beta from EQ. 9 and the small-signalcircuit of Figure 8.

Figure 9

Input worksheet for current mirror design project

7 Syntax of the IF STATEMENT is described in Chapter 3, or in EXCEL help. Click on HELP and type if

function in the SEARCH BOX.


13/27


Figure 10

Numerical values for the design in Figure 1

Verification of spreadsheet

Q-point verification

When the spreadsheet values for RE and RRare pasted into PSPICE, the Q-point

results are seen in Figure 1. They agree with the specifications of IC = 10 mA and

VM = 5 V. In addition, we can look at the small-signal results. The PROBE output file is

shown in Figure 11 below. Parameters rO, rT and gm agree with the spreadsheet.

Figure 11

PROBE output file for case of Figure 1; VBC of QOut is not quite zero, indicating some inaccuracy


14/27


Small-signal verification

The Norton resistance is checked using a small-signal ACSWEEP analysis, as shown

in Figure 12. The discrepancy with the spreadsheet is about 2/100 %.

F r equ enc y

1. 0Hz 1. 0KHz 1. 0MHz 1. 0GHz 1. 0THz

1 / I ( V _ a c )

0

1 . 0 M

2 . 0 M

( 1 . 000000000, 888 . 21755144K)

Figure 12

Determination of Norton resistance using small-signal ACSWEEP with a 1 V AC input signal

To check that the discrepancy between PSPICE and the spreadsheet is not some

algebraic problem in our small-signal analysis, we can check the analysis of Figure 8

using PSPICE.We set up the PSPICE circuit shown in Figure 13 below:

0

0

+

{r_PI}

PARAMETERS:

r_REF = 2.5982005

R_E = 418.85833

R_R = 495.59372

r_X = 10r_O = 11570.04445

r_PI = 587.01615

+ {R_E}

0

F1

GAIN = 224.9485643

+{R_E}

+

{r_REF}

+

{R_R}

888.43KV

+

{r_O}

+

{r_X}

I_DC

1A1.0000A

Figure 13

Small-signal circuit corresponding to Figure 8 to check analysis for Norton resistance RN

The circuit of Figure 13 contains no capacitances so a DC analysis is sufficient. The

circuit is linear, so the ratio of the voltage across the test source to the current in the test

source does not depend on the value of the current, which we take as 1 A to make

calculation easy. Then the resistance looking into the circuit is equal numerically to the

voltage at the input.Running the BIAS POINT analysis the results shown in Figure 13 indicate the Norton

resistance is RN = 888.43 k;, compared to 888.43 k; from the spreadsheet. Therefore,

the analysis of the circuit is accurate and the discrepancy in Figure 12 comes from

another source. It does not appear large enough to have practical importance.


15/27


Transient behavior

The spreadsheet has not been extended to treat behavior where the output transistor

is saturated. However, we can make transient analyses to compare with the behavior seen

in Figure 2, providing a check on the concepts behind the mirror design. We set up theDC bias using the parameter V_SAT, as shown in Figure 14. When V_SAT = 0V, the DC

bias is set below VB by the AC amplitude, so EQ. 24 is satisfied and the output transistor

always is active. As V_SAT is increased, the output transistor goes further and further

into saturation, and the mirror resistance falls rapidly.

INPUT SIGNAL

AMPLITUDE = 1V

V_A = {5-AMPLITUDE+V_SAT}

FREQUENCY = 1kHz

DOT-MODEL:

B_F = 224.9477

I_S = .6506fA

V_AF = 115.7V

N_F = 1.0089535r_X = 10

PARAMETERS:

V_CC = 10V

R_E = 418.85833

R_R = 495.59372

V_SAT = 0.346V

Figure 14

Introduction of V_SAT to describe how far into saturation the output transistor is driven at the topof the AC signal

Figure 15

Output current for various values of V_SAT

Figure 15 shows that only slight peaking of output current occurs at V_SAT =

0.346V, the point in Figure 2 where the mirror resistance begins to drop, but becomes

evident as V_SAT is increased to 0.55 V, the point in Figure 2 where the mirror

resistance has dropped substantially. For larger V_SAT, the peak increases very rapidly.

Detection of this peak in AC current is one way to determine the compliance voltage ofthe mirror.

Comparison with a more realistic transistor model


16/27


We replace the simple model of Figure 1 with one of the transistor models provided

with PSPICE, namely the Q2N2907A, as shown in Figure 16.8 The Q-point agrees fairly

closely with the spreadsheet because the dot-model parameters in Figure 1 were chosen

to agree with this transistor. However, the value of VEB =VEM is not the same as with the

simpler model Q_pVAF, VEM = 786 mV compared to 793 mV in Figure 1. The model

Q2N2907A is much more complex than the model Q_pVAF, and parameterL only

approximates its behavior. An investigation of just what leads to the discrepancy could be

a big job. It wont be done here.

0

Q_Out

Q2N2907A

-44.486uA

-10.007mA

+

- {V_CC}20.104mA

0

PARAMETERS:

V_CC = 10VR_E = 418.85833

R_R = 495.59372

V_SAT = 0.346V

5.0037V+

- {V_A}

V_DC

E

0

EM

Sweep

+

-

AC V_AC

1V

5.7897V 786.03mV

+{R_E}

10.052mA

-

+

Transient

Analysis

{AMPLITUDE}

{FREQUENCY}

V_SIN

-+

+

-

E1

GAIN = 1

10.000V

E

Q_Ref

Q2N2907A

-44.488uA

-10.007mA

M

0

+ {R_E}

10.052mA

M

5.7897V

5.0000V

+{R_R}

10.096mA

INPUT SIGNAL

AMPLITUDE = 1V

V_A = 5V

FREQUENCY = 1kHz

Figure 16

The pnp mirror with the dot-model statement for the Q2N2907A provided with PS PICE

The PROBE output file is shown in Figure 17 below. Comparison with Figure 11 shows

the small-signal parameters of the simple model agree, as we intended when setting L.

8 The Q2N2907A is pasted on the schematic by selecting the schematic, opening menu PLACE/PART and

typing Q2N2907A into the PART window. The EVAL library must be enabled.


17/27


Figure 17

PROBE output file for the mirror using Q2N2907A transistors

The small-signal Norton resistance is found in Figure 18. Unlike Figure 12,

Figure 18 shows frequency roll-off due to the parasitic capacitances of the Q2N2907A.

The ideal transistor model Q_pVAF in Figure 1 doesnt include any capacitances.

F r equency

1 . 0Hz 10KHz 100MHz 1. 0THz

1 / I ( V_AC)

0

0. 5M

1. 0M

( 7 . 7 46 K, 6 28 . 4 8K)( 1 Hz , 8 87 . 7 56 7K)

Figure 18

AC Norton resistance vs. frequency for Figure 16The value RN = 887.8 k; in Figure 18 is close to the spreadsheet prediction of RN =

888.4 k;.

Using the spreadsheet as a design tool

The example of Figure 1 satisfies a specification of 10 mA output current for

voltages below VA = 5 V. However, other specifications involving the output resistance

of the mirror could arise. To see what compromises are necessary, trade-off charts areeasily set up as shown in Figure 19 below.


18/27


496

4190

1000

2000

3000

4000

5000

6000

0 2 4 6 8 10 12 14

Output Current I_C (mA)

Leg

R_

E,

RefR_

R

(;

)

R_E

R_R

DESIGN

DESIGN

V_M (V) = 5

8.8843E+05

0.E+00

2.E+06

4.E+06

6.E+06

8.E+06

1.E+07

0 2 4 6 8 10 12 14


Norton

R_

N

(;

)

R_N

Design

V_M (V) = 5

8.8843E+05

9.2, 11570.0

1.E+03

1.E+04

1.E+05

1.E+06

1.E+07

0 2 4 6 8 10

Midbase Voltage V_M (V)

Norton

R_

N

(;

)

R_N

DESIGN

r_O

I_C (mA) = 10

419

496

0

200

400

600

800

1000

0 2 4 6 8 10


Leg

R_

E,

RefR_

R

(;

)

R_E

R_R

DESIGN

DESIGN

I_C (mA) = 10

Figure 19

Trade-off charts based on the spreadsheet of Figure 9

As usual, we first try to understand the trends shown in the charts to gain some

understanding of the circuit behavior. Lets begin by thinking about the downward trends

in RN as either the mid-base voltage VM increases or the output current increases.

Trend of RN with mid-base voltage VM when IC = constant

For VM to increase, the voltage drop across RE must be reduced because VM is

mainly determined by VCC and the drop across RE. At a fixed output current the only way

to reduce this drop is by reduction of RE. EQ. 22 shows that reduction of RE reduces RN

because the contribution to RN from the term

RRERREFrXrrERER

ACOr // TF

drops as RE goes down. For RE = 0 ;, RN = rO, which is as low as it gets.

Trend of RN with output current IC when VM = constant

For IC to increase, the current on the left side of the mirror must increase. One way

this can happen is to reduce RR, because the current basically is determined by VM/RR.

However, such an increase in current will naturally tend to increase the drop across RE,which cannot happen if VM is maintained. Therefore, RE must drop as IC increases, and as

already observed, this causes RN to drop.


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Trend of RR and RE with VM when IC = constant

It already is argued that RE drops as VM increases. Also, as VM increases the current

tends to increase because it is controlled by VM/RR. However, an increase in current is not

allowed if IC is held fixed, so RRmust increase to maintain the current. Thus, RRand REhave opposite trends, as shown in the upper right panel of Figure 19.

Trend of RR and RE with IC when VM = constant

From the above arguments RRand RE both must drop as IC increases to maintain

VM.

This discussion clarifies how RRand RE affect the mirror properties.

Example designAs a different design problem, lets consider a case where we want to specify VM

and RN but dont care much about the current IC, except it should be as large as possible.

To be specific, lets request that VM = 2 V and RN 1 M; for VA VM = 2 V.We

require the amplifier be built with Q2N2907 transistors.

Answer: The design is found using GOAL SEEK.We set VM = 2 V in the input

worksheet, and ask GOAL SEEKto set the output resistance at RN = 1 M; by varying

I_C_mA. See Figure 20.

Figure 20

Using GOAL SEEKto find correct IC for RN = 1 M;

The resulting design curves are shown in Figure 21.


20/27


155

560

0

2000

4000

6000

8000

0 2 4 6 8 10 12 14


Leg

R_

E,

RefR_

R

(;

)

R_E

R_R

DESIGN

DESIGN

V_M (V) = 5

1.0000E+06

0.E+00

5.E+06

1.E+07

2.E+07

0 2 4 6 8 10 12 14


Norton

R_

N

(;

)

R_N

Design

V_M (V) = 5

1.0000E+06

9.2, 9043.5

1.E+03

1.E+04

1.E+05

1.E+06

1.E+07

0 2 4 6 8 10


Norton

R_

N

(;

)

R_N

DESIGN

r_O

I_C (mA) = 12.79

560

1550

200

400

600

800

0 2 4 6 8 10


Leg

R_

E,

RefR_

R

(;

)

R_E

R_R

DESIGN

DESIGN

I_C (mA) = 12.79

Figure 21

Design curves with design point for the requested specs of VM = 2 V and RM = 1 M;

The spreadsheet suggests RE = 560 ; and RR= 155 ;, and that the output current

will be IC = 12.8 mA. This current is larger than the IC = 10 mA used to calibrate our

Q_pVAF model parameters, so our values forFs and L may be off a bit, requiring some

recalibration.We check out the design using PSPICE.

Figure 22

PROBE output file for design

Figure 22 shows the PROBE output file. At this current levelFDC and FAC still are

close to the values used before. The value of rT = 458 ; compares with a spreadsheet

value of rT = 459 ;, so the design shouldnt be too far off.

Figure 23 shows the Q-point at the design condition VA = 2 V = VM. Indeed VM is

very close to the designed-for VM = 2 V.


21/27


Q_Ref

Q2N2907A

-56.941uA

-12.803mA

0

0

E

-

+

Transient

Analysis

{AMPLITUDE}

{FREQUENCY}

V_SIN

M

0

Q_Out

Q2N2907A

-56.940uA

-12.803mA

INPUT SIGNAL

AMPLITUDE = 1V

V_A = 2V

FREQUENCY = 1kHz

E

0

EM

10.000V

M

2.7941V

2.0000V+

- {V_A}

V_DC

2.0015V

+ {R_E}

12.860mA

-+

+

-E1

GAIN = 1

+

- {V_CC}25.720mA

2.7941V

PARAMETERS:

V_CC = 10V

R_E = 560.33533R_R = 154.94888

V_SAT = 0.346V

Sweep

+

-

AC

V_AC1V

792.59mV

+{R_E}

12.860mA

+{R_R}

12.917mA

Figu

re 23

Q-point check on design when VA = VM = specified VM = 2 V

Finally, the real comparison of mirror characteristics is shown in Figure 24.

Figure 24

Mirror properties for example design

Figure 24 shows the mirror RN > 1 M; for VA 1.5 V, while the spec calls for

more room with RN > 1 M; for VA 2 V.We have a couple of choices to improve the

design. The first is simply to use the trade-off curves to pick better values for RE and RR.

The second is to recalibrate the model to see if that makes the spreadsheet design


22/27


adequate. Because the calibration doesnt seem too far off, the first choice looks more

promising.What has to be done to bring the design within specs?

The problem with the design is that VM is too small. So we could try the spreadsheet

again with a larger VM. That tends to lower the RN, so IC has to be adjusted. Iteration is

needed, so we set VM = 2.5 V and use GOAL SEEKto find the design with RN = 1 M;.

For this design the resistance plot is shown in Figure 25. The spreadsheet values are RE =

550 ; and RR= 204.5 ; with IC = 12.12 mA. This design meets the spec with RN 1

M; for VA < 2.3 V, but we are forced to a lower current.

V_A

0V 2V 4V 6V 8V 10V- 1 / D ( I ( V_D C ) )

0

0 . 5 M

1 . 0 M

( 2 . 275, 1 . 0 00M)( 2 . 8 99 , 7 20 . 5 2K)

( 3 . 0 83 , 1 0. 8 0K)

1 . 0 00 , 1 . 0 08M)

Figure 25Mirror resistance for iterated design

Comments

The current mirror, a circuit element ubiquitous in analog design, differs from an

ideal current source strictly because of the limitations of the bipolar transistors used to

build it. For that reason, a somewhat complex model for the transistor is needed tocapture the mirror behavior. Nonetheless, a simple spreadsheet is useful to design a

current mirror to meet specifications on current level, compliance voltage range and

output Norton resistance.

The spreadsheet enables easy exploration of design trade-offs. For example, the

designs presented indicate a trend to lower currents as compliance range is increased at a

fixed Norton resistance. Qualitative design decisions are based upon recognition of these

trade-offs, which can be discovered as well as made quantitative using a spreadsheet to

explore hand analysis. The spreadsheet is also an interface between hand analysis and

PSPICE to aid verification of the assumptions of hand analysis, and to alert us to wrinkles

that must be added to our thinking if we want reasonable designs.

Appendix: the diode-connected transistor


23/27


The small-signal equivalent circuit for QRef, which has the collector shorted to the

base (diode connection), is shown here to be a simple resistor, rREF. This simple resistor

replaces QRef in the small-signal circuit of Figure 8. The small-signal circuit for QRef is

shown in Figure 26.

++

+

Figure 26Small-signal circuit for reference transistor QRef

Because the base and collector are short-circuited, base and collector are the same

node. The voltage between collector and base is VT, so the currents in the various

branches are as shown in Figure 26. Consequently the total current flowing between

collector and emitter is EQ. 25 below:

EQ. 25

T

Frr

V1

r

VI

X

ceAC

O

cec

! .

That is, the transistor behaves like a resistor of value rREF given by EQ. 26:

EQ. 26

!

1

rr//rr

AC

XOREF

F

T

Rewrite this resistance in terms of the current as shown in EQ. 27:

EQ. 27

}

!

T

T F

F

L

F

r

r1

11

V

I

V

I

rr

1

r

1

r

1

XAC

AC

THF

C

AF

C

X

AC

OREF

.

Because VAF >> VTH (for example, for the Q2N2907A in Figure 1 at 27rC, VAF =

115.7 V and VTH 26 mV), the last term dominates the sum, and to a very good

approximation we can take the small-signal equivalent circuit of QRef to be a single

resistor of value rREF given by EQ. 28:

EQ. 28

Xr Tr Or

bACIF

E

C

+

ecV

X

ecb

rr

VI

!

T

cI

O

ec

r

V


24/27


mXTHF

CREF

g

1

r

r1

1

V

Ir }

}

T

L

Exercises

1. Go through the chapter using an n-channel mirror with a simple model Q_nVAF

using dot-model statement:

.model Q_nVAF NPN (Bf={B_F} Is={I_S} Vaf={V_AF} Nf={N_F} Rb={r_X}),

and instead of fitting the pnp Q2N2907A make the Q_nVAF match the

PSPICE-provided npn Q2N2222 transistor.

2. Use the spreadsheet to make trade-off plots using IC as the dependent variable and RN

and VM as independent x-axes. Describe how you obtain these charts. Discuss the

origins of trends in your charts.

3. Make a pnp mirror design using Q2N2907A transistors similar to the one in the

chapter but for specifications of RN 1 M; for VA 8 V.

Answer: Using the spreadsheet calibrated for IC = 10 mA, we find a design using GOAL

SEEKfor RE =306.5 ; and RR= 1.983 k; with IC = 4 mA.We check the F-values as

shown in Figure 27 and the ideality coefficient as shown in Figure 28 and update the

spreadsheet.

I _E

100uA 1. 0mA 10mA

I ( C) / I ( B) D( I ( I _C) ) / D( I ( I _B) )

2 00 . 0

2 12 . 5

2 25 . 0

2 37 . 5( AC Be t a , 4 . 0 00m, 224. 95 )

( DC Be t a , 4 . 0 00m, 223. 86 )

Figure 27

Check ofF-values at initial guessed IC 4 mA


25/27


I _E

0A 5mA 10mA

D( I ( C_Nf ) ) / D( V ( E _VAF ) ) D( I ( C _2 907A) ) / D( V( E _2907A) )

0

200m

400m

( 4. 00000m, 152. 3348m)

( 4. 00000m, 152. 9590m)

Figure 28

External gm-values for use in finding new L = 1.0040976

We then use GOAL SEEKagain to design to specification. See Figure 20. The new

design is RE = 305.7 ;, RR= 1971.8 ;, IC = 4.02 mA. These resistance values are put

into PSPICE to check the design. The PROBE output file is shown in Figure 29, and the Q-

point in Figure 30.

Figure 29

PROBE output file for design


26/27


8.0000V

E

+{R_E}

4.0405mA

0

+{R_R}

4.0585mA

+

- {V_CC}8.0810mA

-

+

Transient

Analysis

{AMPLITUDE}

{FREQUENCY}

V_SIN

M

INPUT SIGNAL

AMPLITUDE = 1V

V_A = 8V

FREQUENCY = 1kHz

EM-+

+

-E1

GAIN = 1

+

- {V_A}

V_DC

E

8.0026V

Q_Ref

Q2N2907A

-17.967uA

-4.0225mA

0

10.000V

0

Sweep

+

-

AC

V_AC1V

PARAMETERS:

V_CC = 10V

R_E = 305.73953R_R = 1971.82545

V_SAT = 0.346V

Q_Out

Q2N2907A

-17.967uA

-4.0225mA

8.7647V

+ {R_E}

4.0405mA

8.7647V

0

762.05mV

M

Figure30

Q-point for VA = 8 V

Figure 29 shows rT = 1.46 k;, compare to the spreadsheet value 1.45 k;, rO =

28.8 k; compared to 28.8 k;, good agreement. Figure 31 shows the mirror

characteristics.

Figure 31

Mirror characteristics for designThe mirror satisfies RN 1 M; for VA 8.2 V, exceeding the 8V specification. The

mirror provides only 4 mA of current however, compared to 12 mA for the design

presented in the chapter.

Software elements presented


27/27

CAPTURE andPSPICE

Finding AC and DC betas (Figure 3)

Introduction to the pnp dot-model statement:

.model Q_pVAF PNP (Bf={B_F} Is={I_S} Vaf={V_AF} Nf={N_F} Rb={r_X})

Introduction to the pnp dot-model statement for the Q2N2907A transistor.

Dealing with base resistance rX

Finding the ideality factorL to match a more realistic bipolar model (Figure 7)

Another example implementing a small-signal circuit (Figure 13)

EXCEL

Another example of implementing a hand analysis in the spreadsheet, verifying it and

using it for design

PNP Current Mirror

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