PN SEQUENCE GENERATER

Tanvir Manhotra ,Amit kulkarni , Rushab Karani

22 October 2012

1 ABSTRACT

Pseudo noise sequence is essentially a randomsequence of binary numbers. So PN sequencegenerator is nothing but random binary numbergenerator. It is random in a sense that the valueof an element of the sequence is independent of thevalues of any of the other elements. It is ’pseudo’because it is deterministic and after N elements itstarts to repeat itself, unlike real random sequences.The implementation of PN sequence generator isbased on the linear feedback shift register (LFSR).The PN sequence generator produces a predefinedsequence of 1’s and 0’s, with 1 and 0 occurring withthe same probability. A sequence of consecutive(2[raised to]n)-1 bits comprise one data pattern, andthis pattern will repeat itself over time. Our projectexplores the PN sequence generator in detail alongwith its applications in spread spectrum

2 INTRODUCTION

The field of wireless communications is currentlygrowing at an unprecedented rate. This growth,prompted in part by the demand for more high-speed, broadband communication systems, hasled to the need for high-resolution, broadbandwireless measurement equipment. The mobilecommunication system is one of the most importantphenomenon in the history of telecommunicationwhich has enriched human civilization and mankindby bringing business and community together.. In

Spread Spectrum CDMA (SS-CDMA) system eachuser is assigned a pseudo noise (PN) sequence forthe purpose of spreading as well as dispreading.Thus PN-sequence generation is considered to bethe heart of SS-CDMA system. The maximal lengthPN-sequence (m-sequence) is the best known PN-sequence whose length is equal to its period. VariousPN-codes can be generated using Linear FeedbackShift Register (LFSR).The generator polynomialprovides the necessary feedback taps for the LFSRcircuit. The implementation of the LFSR circuitwith VLSI technology makes it useful in low-powercommunication system design. LFSR is basically,a shift register configuration that propagates thestored patterns from left to right. The modificationthat provides the PRBS generation is due to theXOR feedback of the selected flip-flop outputs,named taps. When the taps are chosen properly, theLFSR will traverse through all possible states exceptfor the all 0s state and will produce a maximumlength PRBS sequence named M-sequence.

3 PSEUDO NOISE SE-QUENCES

Pseudo noise sequences (PRBSs) are widely used fortesting hardware for digital communication. Testingof hardware for digital communication requirestransmission and reception of a signal that subjectsthe transmission channel to the characteristics ofrandom digital signal. A PN sequence is a randombit sequence that repeats itself, thus not truly

1

random, as the name implies. A truly randomsequence never repeats itself, but truly randomsequences are difficult to generate, and would havevery little use in practical systems. However PNsequence with long sequence lengths (several billionbits) show close resemblance to truly random signals,and are sufficient for test purposes. PN sequencehave well known properties, and the generationand acquisition of them are simple. Knowing howa PRBS is generated makes it possible to predictthe sequence. This is a very desirable feature whentesting hardware for digital communication, as itallows you to predict how an incoming sequenceis supposed to look. This makes it possible toregister and count any errors that might occur in thesequence. PN sequence can be generated by shiftingbits through a number (N) of cascaded registers,where some of the register outputs (referred to astap sets) are added modulo-2 and fed back to theinput of the first register. The maximal length of thesequence is determined by the number of possiblestates that the shift register can assume, and theproperties of the sequence is determined by whichtap sets that are modulo-2 added and feed back tothe first register. This type of PRBS generator iscalled a linear feedback shift.

4 MAXIMUM LENGTH SE-QUENCES

LFSR’s can have multiple maximal length tap se-quences. A maximal length tap sequence also de-scribes the exponents in what is known as a primi-tive polynomial mod 2. Example, a tap sequence of4, 1 describes the primitive polynomial x4 + x1 +1. Finding a primitive polynomial mod 2 of degreen (the largest exponent in the polynomial) will yielda maximal length tap sequence for an LFSR that isn bits long. There is no quick way to determine if atap sequence is maximal length. However, there aresome ways to tell if one is not maximal length:

1. Maximal length tap sequences always have aneven number of taps

2. The tap values in a maximal length tap sequenceare all relativelyprime.

A tap sequence like 12, 9, 6, 3 will not be maximallength because the tap values are all divisible by 3.Discovering one maximal length tap sequence leadsautomatically to another. If a maximal length tapsequence is described by [n, A, B, C], another maxi-mal length tap sequence will be described by [n, n-C,n-B, n-A]. Thus, if [32, 3, 2, 1] is a maximal lengthtap sequence, [32, 31, 30, 29] will also be a maximallength tap sequence. An interesting behaviour of twosuch tap sequences is that the output bit streams aremirror images in time.CHARACTERISTICS OF OUTPUT STREAM: Bydefinition, the period of an LFSR is the length ofthe output stream before it repeats. Besides beingnon-repetitive, a period of a maximal length streamhas other features that are characteristic of randomstreams.

• Sums of ones and zeroes: In one period of a maxi-mal length stream, the sum of all ones will be onegreater than the sum of all zeroes. In a randomstream, the difference between the two sums willtend to grow progressively smaller in proportionto the length of the stream as the stream getslonger. In an infinite random stream, the sumswill be equal.

• Runs of ones and zeroes: A run is a pattern ofequal values in the bit stream. A bit stream like10110100 has six runs of the following lengths inorder: 1, 1, 2, 1, 1, 2. One period of an n-bitLFSR with a maximal length tap sequence willhave 2[raised to](n-1) runs (e.g., a 5 bit deviceyields 16 runs in one period). 1/2 the runs willbe one bit long, 1/4 the runs will be 2 bits long,1/8 the runs will be 3 bits long, etc., up to a sin-gle run of zeroes that is n-1 bits long and a singlerun of ones that is n bits long. A random streamof sufficient length shows similar behaviour sta-tistically.

2

• Shifted stream: Take the stream of bits in oneperiod of an LFSR with a maximal length tapsequence and circularly shift it any number ofbits less than the total length. Do a bitwise XORwith the original stream. A random stream alsoshows this behaviour. One characteristic of theLFSR output not shared with a random streamis that the LFSR stream is deterministic. Givenknowledge of the present state of the LFSR, thenext state can always be predicted.

5 WORKING

Our project comprises of VHDL modelling of fourdifferent PN sequence generators. We have depictedthe simulation of Maximal length sequences. Hence,the sequence repeats after 2[raised to]n-1 bits, wheren is the number of LFSR. The different PN generatorsare as follows:

1. For 3 LFSR- [2,0]: In this case, LFSR(2) receivesinput which is the result of XOR of output ofLFSR(2) and LFSR(0)

In this PN sequence, the sequence repeats after(2[raised to]3-1)=7 bits. The number of ones areone greater than the number of zeroes. Four runscan be observed: 00,111,0,1If this sequence is used in direct sequence spreadspectrum then at the transmitter side we have:Let the modulated data be: 1100101

The encoded data is then transmitted over thechannel and at receiver end we decode the datausing a locally generated synchronised PN se-quence:

2. 5-LFSR[4,3,1,0]: In this PN sequence generator,5 LFSR are used. The random sequence repeatsafter (2[raised to]5)-1= 31 bits.

The above sequence generator can be used fordata transmission and reception in the sameway as 3-LFSR sequence generator.

3. GOLD SEQUENCE:The Gold Sequence Gener-ator block generates a Gold sequence. Gold se-quences form a large class of sequences that havegood periodic cross-correlation properties. TheGold sequences are defined using a specified pairof sequences u and v, of period N = 2n - 1, calleda preferred pair, as defined in the following sec-tion, Preferred Pairs of Sequences. The set G(u,v) of Gold sequences is defined by

3

where T represents the operator that shiftsvectors cyclically to the left by one place. Notethat G(u,v) contains N + 2 sequences of periodN. The Gold Sequence Generator block outputsone of these sequences according to the block’sparameters. Gold sequences have the propertythat the cross-correlation between any two, orbetween shifted versions of them, takes on oneof three values: -t(n), -1, or t(n) - 2, where

The Gold Sequence Generator block uses twoPN Sequence Generator blocks to generate thepreferred pair of sequences, and then XORsthese sequences to produce the output sequence,as shown in the following diagram:

We have used two 6-LFSR PN sequence genera-tors[5,0] and [5,4,1,0]:

4. 8-LFSR-[8,7,6,5,2,1]: In this case, the 8 linearfeedback shift registers are used. The sequencerepeats after (2[raised to])8-1=255 bits

The above sequence generator can be used fordata transmission and reception in the sameway as 3-LFSR sequence generator

6 APPLICATIONS

1. Direct sequence spread spectrum: Direct-sequence spread-spectrum transmissions multi-ply the data being transmitted by a ”noise” sig-nal. This noise signal is a pseudorandom se-quence of 1 and 1 values, at a frequency muchhigher than that of the original signal.

The resulting signal resembles white noise, likean audio recording of ”static”. However, this

4

noise-like signal can be used to exactly recon-struct the original data at the receiving end, bymultiplying it by the same pseudorandom se-quence (because 1 1 = 1, and 1 1 = 1). Thisprocess, known as ”de-spreading”, mathemati-cally constitutes a correlation of the transmittedPN sequence with the PN sequence that the re-ceiver believes the transmitter is using. The re-sulting effect of enhancing signal to noise ratioon the channel is called process gain. This ef-fect can be made larger by employing a longerPN sequence and more chips per bit, but phys-ical devices used to generate the PN sequenceimpose practical limits on attainable processinggain.If an undesired transmitter transmits on thesame channel but with a different PN sequence(or no sequence at all), the de-spreading processresults in no processing gain for that signal. Thiseffect is the basis for the code division multipleaccess (CDMA) property of DSSS, which allowsmultiple transmitters to share the same channelwithin the limits of the cross-correlation proper-ties of their PN sequences.

2. Use as Built in self tester (BIST): At the heartof this BIST approach, lie a pseudo-random bi-nary sequence (PRBS) generator and a signatureregister. The PRBS generator is most easily im-plemented using a linear feedback shift register(LFSR). A PRBS generator allows us to gener-ate all (well, almost all) of the required binarypatterns for the circuit under test. The LFSRcan be used to both generate the test sequencefor the design that is to incorporate BIST andwith slight modification can be used to capturethe response of the design and generate a signa-ture (the bit pattern held in the signature reg-ister). The signature in the signature registercan be compared to a known good signature.Within certain realms of mathematical probabil-ity, if the signature for the circuit being testedis the same as the known good signature, thenthe tested circuit is deemed as being function-ally correct. There is a little maths involved indiscovering the known good value for the signa-ture of the circuit being tested but more on that

in Part Two. This month we are going to con-centrate on the design of an LFSR and one kindof signature register. The maximal length LFSRgenerates data that is almost random (hence theterm pseudorandom’). The output of the LFSRcan be taken in parallel-out form or as a serialbit stream. The serial bit stream is usually takenfrom the MSB of the LFSR. Given taps 6 and 9,it turns out that the only pattern not generatedis all zeroes. It is a fairly simple task to adda little extra circuitry to generate this pattern,but we won’t tackle this just yet. Naturally thiswould give us a RBS generator, not a pseudo tobe seen.

7 ABOUT XILINX

Xilinx designs, develops and markets programmablelogic products including integrated circuits (ICs),software design tools, predefined system functions de-livered as intellectual property (IP) cores, design ser-vices, customer training, field engineering and tech-nical support. Xilinx sells both FPGAs and CPLDsprogrammable logic devices for electronic equipmentmanufacturers in end markets such as communica-tions, industrial, consumer, automotive and data pro-cessing. Xilinx FPGAs can run a regular embed-ded OS (such as Linux or vxWorks) and can imple-ment processor peripherals in programmable logic.Xilinx delivers programmable platforms to help de-sign engineers make their vision a reality. Xilinxprogrammable chips are the innovation platform ofchoice for today’s leading companies for the designof tens of thousands of products that improve thequality of our everyday lives. Xilinx designs, devel-ops and markets programmable logic products includ-ing integrated circuits (ICs), software design tools,predefined system functions delivered as intellectualproperty (IP) cores, design services, customer train-ing,engineering and technical support.

5

8 CPLD

The design of a digital system using PLD oftenrequires the connection of several devices to pro-duce the complete specification. For these type ofapplications, Complex Programmable Logic Devices(CPLD) are more suitable. A CPLD is a collectionof individual PLDs on a single integrated circuit. Aprogrammable interconnection structure allows thePLDs to be connected to each other in the same waythat can be done with the individual PLDs. Now,the switch matrix receives inputs from the I/O blockand directs it to the individual macrocells. Similarly,selected outputs from macrocells are sent to the out-puts as needed. Each PLD typically contains from 8to 16 macrocells. The macrocells within each PLDare usually fully connected. If a macrocell has un-used product terms they can be used by other nearbymacrocells. Different manufacturers use different ap-proaches to make individual PLDs, the type of macro-cells, I/O blocks and the programmable interconnec-tion structure. The basic component used in PLD isthe gate array. A gate array consists of pattern ofgates fabricated in an area of silicon that is repeatedthousands of times until the entire chip is coveredwith the gates.

9 Features of CPLD

• High performance -5 ns pin to pin logic delay-Counter frequency 125 MHz

• Large density range -36-288 macrocells withupto 6000 usable gates.

• Enhanced pin locking architecture.

• Programmable power reduction mode in eachmacrocell.

• Slew rate control.

• High drive 24 mA output.

• Advanced CMOS 5v fast Flash technology.

• Flexible 36V 18 function block-90 product termsdrive any or all of 18 macro cells within functionblock-global and product term clocks, output en-ables, set and reset signals.

• Extensive IEEE std 1149.1 boundaryscan(JTAG) support.

• Programmable power reduction mode in eachmacrocell.

• Skew rate controlled on individual outputs.

• User programmable ground pin capability.

10 Conclusion

This report discussed the concept of pseudo ran-dom sequences as applicable to spread spectrumcommunications. Maximal length sequences wereintroduced, and used as an introduction to morecomplicated methods of PN code generation withthe help of LFSRS. The linear feedback shift register(LFSR) is a shift register which, using feedback,modifies itself on each rising edge of the clock. Thecode for implementing the required PN sequenceswas realized by writing VHDL program and thesubsequently, the simulation was observed.

6

11 References

1. Bookname: Digital Design Principles andPractices.Author: John K.Wakerley.Publication: Pearson Education.

2. Bookname: Communication Systems.Author: Simon Haykin.Publication: John Wiley and Sons.

3. Bookname: Designing cdma2000 Systems.Author: Leonhard Korowajczuk, Bruno deSouza Abreu Xavier.Publication: John Wiley and Sons.

4. Bookname: WCDMA Design Handbook.Author: Andrew Richardson.Publication: Cambridge university press.

5. Website: xilinx.com

6. Website: en.wikipedia.org

7