PMU-Based Real-Time Damping Control System Software and Hardware Architecture Synthesis and...
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Transcript of PMU-Based Real-Time Damping Control System Software and Hardware Architecture Synthesis and...
PMU-based Real-Time Damping Control System Software and Hardware Architecture Synthesis and Evaluation
Eldrich Rebello*, Dr. Luigi Vanfretti*~ and M. Shoaib Almas**Electric Power Systems Division, KTH Royal Institute of Technology, Stockholm, Sweden
~R&D Department, Statnett SF, Oslo, Norway, Email: [email protected]
· Low-frequency, electromechanically induced, interarea oscillations are of concern in the continued stability of interconnected power systems.
· Wide Area Monitoring, Protection and Control (WAMPAC) systems based on wide-area measurements such as synchrophasor (C37.118) data can be exploited to address the inter-area oscillation problem.
· This work develops a hardware prototype of a synchrophasor-based oscillation damping control system. · A Compact Reconfigurable Input Output (cRIO) controller from National Instruments is used to implement the realtime hardware prototype of wide-area oscillation damper.
Abstract
Data-Flow Path for Developed Hardware Prototype of Damping Control System
Real-Time Hardware-in-the-Loop Setup for Performance Assessment of Prototype Challenges and Conclusion
WAPOD Prototype Architecture Refinement
2: Opal-RT
3A: Amplifier
3B: PMUs
4: PDC6: NI-cRIO (WAPOD)
1: MATLAB model development and Opal-RT software interface
6: BabelFish receives PDC streams and unwraps it to
provide raw phasor, analog, digitals to NI-cRIO
Power system model being loaded in Opal-RT for real-time execution
PDC stream being received by BabelFish
Raw values of phasor, analog, digital being sent to NI-cRIO based WAPOD
Three stage architecture refinement process. Distributing tasks among host computer, RT-Layer of NI-cRIO and FPGA-Layer of NI-cRIO
Iterative architecture development is based on 1) Initial Investigation2)Requirements Definition3) Architecture Design4)Coding and Implementation5) Experimental Testing to validate requirements
Challenges· Analogue signal magnitude limits· Different Data/Loop rates : PMU data rate, RT Simulation step size, FPGA Execution time
· FPGA Resource Limitations : Finite FPGA resources, code must be optimised
· FPGA function limitations : Functions like multiplication, Trigonometric consume large amount of FPGA resources
· PMU Data extraction performed on Remote Computer: Developed controller not Stand-Alone
· Other Challenges: Signal to Noise Ratio, Communication network delay and scaling issues
Conclusion· A hardware prototype of a real-time power oscillation damping control system was developed and tested.
· The developed prototype uses a real-time implementation of a wide-area control system.
· The success of the tests performed indicates that PMU-based wide area controllers can be exploited for multiple control applications in power system control and monitoring.
Final architecture as implemented in the NI-cRIO (model 9081)
· Klein-Rogers-Kundur Power System model executed in real-time using eMEGASIM real-time simulator from OPAL-RT.
· Voltage and current signals were fed to the commercial PMUs.
· Synchrophasors from PMUs were received inside NI-cRIO to execute phasor-POD algorithm to generate damping signals.
Prot
otyp
e us
ing
NI-c
RIO
(908
1) RT-Module1.06 GHz dual-core Intel Celeron processor, 16 GB nonvolatile storage, 2 GB DDR3 800 MHz RAM
FPGA ModuleFPGA type : Spartan-6 LX75Number of flip-flops: 93,296Number of 6-input LUTs: 46,648Number of DSP: 48As 1 slices(18 x 18 multipliers) ....................... 132Embedded block RAM ................... 3,096 kbits
Ethernet PortConnected to the local network and communicating
with remote VI (Host VI) using network published shared variables
Analog Output Module (Damping Signal Output)16 channels, 25 kS/s per channel simultaneous analog output, ±10 V output range , 16-bit
resolution. Each channel can update at up to 25 kS/s because each channel has its own digital -to-analog converter